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Advances in Chemical Mechanical Planarization (CMP)

Advances in Chemical Mechanical Planarization (CMP)

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Advances in Chemical Mechanical Planarization (CMP)

Comprimento:
1,026 página
Lançado em:
Jan 9, 2016
ISBN:
9780081002186
Formato:
Livro

Descrição

Advances in Chemical Mechanical Planarization (CMP) provides the latest information on a mainstream process that is critical for high-volume, high-yield semiconductor manufacturing, and even more so as device dimensions continue to shrink. The technology has grown to encompass the removal and planarization of multiple metal and dielectric materials and layers both at the device and the metallization levels, using different tools and parameters, requiring improvements in the control of topography and defects.

This important book offers a systematic review of fundamentals and advances in the area. Part One covers CMP of dielectric and metal films, with chapters focusing on the use of particular techniques and processes, and on CMP of particular various materials, including ultra low-k materials and high-mobility channel materials, and ending with a chapter reviewing the environmental impacts of CMP processes.

Part Two addresses consumables and process control for improved CMP, and includes chapters on the preparation and characterization of slurry, diamond disc pad conditioning, the use of FTIR spectroscopy for characterization of surface processes, and approaches for defection characterization, mitigation, and reduction.

  • Considers techniques and processes for CMP of dielectric and metal films
  • Includes chapters devoted to CMP for particular materials
  • Addresses consumables and process control for improved CMP
Lançado em:
Jan 9, 2016
ISBN:
9780081002186
Formato:
Livro

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Advances in Chemical Mechanical Planarization (CMP) - Elsevier Science

Advances in Chemical Mechanical Planarization (CMP)

Editor

Suryadevara Babu

Table of Contents

Cover image

Title page

Related titles

Copyright

List of contributors

Woodhead Publishing Series in Electronic and Optical Materials

Introduction

Part One. CMP of dielectric and metal films

1. Chemical and physical mechanisms of dielectric chemical mechanical polishing (CMP)

1.1. Introduction

1.2. History of dielectric CMP

1.3. Material removal mechanism of dielectric CMP

1.4. Defectivity of dielectric CMP

1.5. Major applications of dielectric CMP

1.6. Future of dielectric CMP

2. Copper chemical mechanical planarization (Cu CMP) challenges in 22nm back-end-of-line (BEOL) and beyond

2.1. Introduction

2.2. Factors that affect Cu CMP at the 22nm node and beyond

2.3. Conclusions

3. Electrochemical techniques and their applications for chemical mechanical planarization (CMP) of metal films

3.1. Introduction

3.2. Chemical component of metal CMP

3.3. Electrochemical basis of metal CMP

3.4. Experimental considerations

3.5. Illustrative applications

3.6. Conclusions

4. Ultra low-k materials and chemical mechanical planarization (CMP)

4.1. Integration of ultra-low-k materials in semiconductor devices

4.2. CMP of ULK materials

4.3. ULK CMP in integrated dual-damascene structures

4.4. Current trends in ULK dielectrics

5. CMP processing of high mobility channel materials: Alternatives to Si

5.1. Introduction

5.2. Ge/SiGe as high mobility channel materials

5.3. III–V materials as high mobility channel materials

5.4. Conclusions and future trends

6. Multiscale modeling of chemical mechanical planarization (CMP)

6.1. Introduction

6.2. CMP models of material removal mechanisms

6.3. CMP models for planarization processes

6.4. Applying CMP models for process characterization

6.5. Future trends

7. Polishing of SiC films

7.1. Introduction

7.2. Crystalline SiC

7.3. Amorphous SiC (a-SiC) films

7.4. Summary

8. Chemical and physical mechanisms of CMP of gallium nitride

8.1. Introduction

8.2. Process development history of GaN final treatment

8.3. CMP technology as the substrate final finishing process and its application to GaN substrate

8.4. Colloidal silica CMP of GaN and evaluation of the residual damaged layer

8.5. Preparation for shortening CMP process time

8.6. Superiority of CMP for final processing of GaN (comparison with dry etching)

8.7. Nonequivalent crystallographic planes of GaN and related front/back processing properties: control of substrate warp

8.8. Conclusions

9. Abrasive-free and ultra-low abrasive chemical mechanical polishing (CMP) processes

9.1. Introduction

9.2. Abrasive-free slurries for poly-Si CMP

9.3. Abrasive-free processes for the Cu damascene CMP process

9.4. Abrasive-free formulations and role of abrasives for barrier CMP

9.5. Future trends

10. Environmental aspects of planarization processes

10.1. Introduction

10.2. Wastewater generation and characterization

10.3. Water quality criteria

10.4. Particle stability and destabilization

10.5. Particle destabilization

10.6. Physicochemical characteristics and behavior of alumina, ceria, and silica particles

10.7. CMP wastewater treatment

10.8. Sedimentation

10.9. Coagulation and flotation

10.10. Summary

Part Two. Consumables and process control for improved CMP

11. Preparation and characterization of slurry for chemical mechanical planarization (CMP)

11.1. Introduction

11.2. Preparation of slurry for CMP

11.3. Characterizations of slurry for CMP

11.4. Conclusion

12. Chemical metrology methods for CMP quality

12.1. Introduction

12.2. Particle size distribution

12.3. Density

12.4. Large particle counting

12.5. Zeta potential

12.6. Conductivity

12.7. Titration

12.8. pH

12.9. Viscosity

12.10. Temperature

12.11. Metrology statistical capability

12.12. Bench-top versus in-line measurement

13. Diamond disc pad conditioning in chemical mechanical polishing

13.1. Introduction

13.2. Design and manufacture of diamond disc conditioner

13.3. Diamond disc pad conditioning process control

13.4. Diamond disc pad conditioning modeling and simulation

13.5. Conclusions

14. Characterization of surface processes during oxide CMP by in situ FTIR spectroscopy

14.1. Introduction

14.2. Silicon dioxide CMP as a topic of fundamental research

14.3. Infrared spectroscopy

14.4. ATR FTIR spectroscopy

14.5. Si-based reflection elements for ATR-FTIR investigations

14.6. In situ applications of ATR-FTIR spectroscopy using mSREs

14.7. Conclusions

15. A novel slurry injection system for CMP

15.1. Introduction

15.2. Pad rinsing and slurry response to rinsing

15.3. A novel slurry injection system

15.4. Performance of the Araca SIS

15.5. Why does the Araca SIS work?

15.6. Summary and conclusions

16. Chemical mechanical polishing (CMP) removal rate uniformity and role of carrier parameters

16.1. Rotary table method in several CMP methods

16.2. CMP removal rate uniformity

16.3. Carrier and the roles of carrier parameters

16.4. Profile control

17. Approaches to defect characterization, mitigation, and reduction

17.1. CMP defects: their source and characterization

17.2. Defect mitigation and reduction

17.3. Conclusion

18. Applications of chemical mechanical planarization (CMP) to More than Moore devices

18.1. Introduction: More Moore versus More than Moore

18.2. CMP for More than Moore devices

18.3. Specific CMP process requirements

18.4. Specific CMP consumables requirements

18.5. Applications

18.6. Conclusions

19. CMP for phase change materials

19.1. Introduction

19.2. Requirements for GST CMP

19.3. GST CMP issues

19.4. GST polishing mechanism

Index

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Copyright

Woodhead Publishing is an imprint of Elsevier

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This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein).

Notices

Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary.

Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility.

To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein.

ISBN: 978-0-08-100165-3 (print)

ISBN: 978-0-08-100218-6 (online)

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For information on all Woodhead Publishing publications visit our website at http://store.elsevier.com/

List of contributors

H. Aida

Namiki Precision Jewel Co. Ltd., Shinden, Tokyo, Japan

Kyushu University Art, Science and Technology Center for Cooperative Research (KASTEC), Kasuga-city, Fukuoka, Japan

E.A. Baisie,     Cabot Microelectronics Corp., Aurora, IL, USA

D. Boning,     Massachusetts Institute of Technology, Cambridge, MA, USA

L. Borucki,     Araca Inc., Tucson, AZ, USA

W. Fan,     Cabot Microelectronics Corporation, Aurora, IL, USA

M. Krishnan,     Colloid & Interface Science—Advanced Planarization Group, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA

U. Künzelmann,     Dresden University of Technology, Dresden, Germany

U.R.K. Lagudu,     Micron Technology, Inc., Boise, ID, USA

Z.C. Li,     North Carolina Agricultural & Technical State University, Greensboro, NC, USA

M.F. Lofaro,     Colloid & Interface Science—Advanced Planarization Group, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA

Y. Moon,     Advanced Technology Development (ATD), GLOBALFOUNDRIES, Malta, NY, USA

J. Nalaskowski,     SUNY Poly SEMATECH, Albany, NY, USA

P. Ong,     IMEC, Heverlee, Belgium

U. Paik,     Hanyang University, Seoul, South Korea

S.S. Papa Rao,     SUNY Poly SEMATECH, Albany, NY, USA

K. Pate,     Intel Corporation, Hillsboro, OR, USA

N.K. Penta,     Dow Electronic Materials, Delaware, USA

D. Roy,     Clarkson University, Potsdam, NY, USA

P. Safier,     Intel Corporation, Hillsboro, OR, USA

H. Schumacher,     GLOBALFOUNDRIES, Dresden, Germany

J. Seo,     Hanyang University, Seoul, South Korea

Z. Song,     Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China

D.E. Speed,     IBM Corporation, Hopewell Junction, NY, USA

L. Teugels,     IMEC, Heverlee, Belgium

W.-T. Tseng

IBM Semiconductor Research & Development Center, NY, USA

Now at Advanced Technology Development, GLOBALFOUNDRIES, NY, USA

M. Tsujimura,     Ebara Corporation, Tokyo, Japan

L. Wang,     Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China

X.H. Zhang,     Seagate Technology LLC, Minneapolis, MN, USA

Q. Zhang,     School of Mechanical Engineering, Yangzhou University, Yangzhou, Jiangsu, China

G. Zwicker,     Fraunhofer Institute for Silicon Technology ISIT, Fraunhoferstrasse 1, Itzehoe, Germany

Woodhead Publishing Series in Electronic and Optical Materials

1 Circuit analysis

J. E. Whitehouse

2 Signal processing in electronic communications: For engineers and mathematicians

M. J. Chapman, D. P. Goodall and N. C. Steele

3 Pattern recognition and image processing

D. Luo

4 Digital filters and signal processing in electronic engineering: Theory, applications, architecture, code

S. M. Bozic and R. J. Chance

5 Cable engineering for local area networks

B. J. Elliott

6 Designing a structured cabling system to ISO 11801: Cross-referenced to European CENELEC and American Standards

Second edition

B. J. Elliott

7 Microscopy techniques for materials science

A. Clarke and C. Eberhardt

8 Materials for energy conversion devices

Edited by C. C. Sorrell, J. Nowotny and S. Sugihara

9 Digital image processing: Mathematical and computational methods

Second edition

J. M. Blackledge

10 Nanolithography and patterning techniques in microelectronics

Edited by D. Bucknall

11 Digital signal processing: Mathematical and computational methods, software development and applications

Second edition

J. M. Blackledge

12 Handbook of advanced dielectric, piezoelectric and ferroelectric materials: Synthesis, properties and applications

Edited by Z.-G. Ye

13 Materials for fuel cells

Edited by M. Gasik

14 Solid-state hydrogen storage: Materials and chemistry

Edited by G. Walker

15 Laser cooling of solids

S. V. Petrushkin and V. V. Samartsev

16 Polymer electrolytes: Fundamentals and applications

Edited by C. A. C. Sequeira and D. A. F. Santos

17 Advanced piezoelectric materials: Science and technology

Edited by K. Uchino

18 Optical switches: Materials and design

Edited by S. J. Chua and B. Li

19 Advanced adhesives in electronics: Materials, properties and applications

Edited by M. O. Alam and C. Bailey

20 Thin film growth: Physics, materials science and applications

Edited by Z. Cao

21 Electromigration in thin films and electronic devices: Materials and reliability

Edited by C.-U. Kim

22 In situ characterization of thin film growth

Edited by G. Koster and G. Rijnders

23 Silicon-germanium (SiGe) nanostructures: Production, properties and applications in electronics

Edited by Y. Shiraki and N. Usami

24 High-temperature superconductors

Edited by X. G. Qiu

25 Introduction to the physics of nanoelectronics

S. G. Tan and M. B. A. Jalil

26 Printed films: Materials science and applications in sensors, electronics and photonics

Edited by M. Prudenziati and J. Hormadaly

27 Laser growth and processing of photonic devices

Edited by N. A. Vainos

28 Quantum optics with semiconductor nanostructures

Edited by F. Jahnke

29 Ultrasonic transducers: Materials and design for sensors, actuators and medical applications

Edited by K. Nakamura

30 Waste electrical and electronic equipment (WEEE) handbook

Edited by V. Goodship and A. Stevels

31 Applications of ATILA FEM software to smart materials: Case studies in designing devices

Edited by K. Uchino and J.-C. Debus

32 MEMS for automotive and aerospace applications

Edited by M. Kraft and N. M. White

33 Semiconductor lasers: Fundamentals and applications

Edited by A. Baranov and E. Tournie

34 Handbook of terahertz technology for imaging, sensing and communications

Edited by D. Saeedkia

35 Handbook of solid-state lasers: Materials, systems and applications

Edited by B. Denker and E. Shklovsky

36 Organic light-emitting diodes (OLEDs): Materials, devices and applications

Edited by A. Buckley

37 Lasers for medical applications: Diagnostics, therapy and surgery

Edited by H. Jelínková

38 Semiconductor gas sensors

Edited by R. Jaaniso and O. K. Tan

39 Handbook of organic materials for optical and (opto)electronic devices: Properties and applications

Edited by O. Ostroverkhova

40 Metallic films for electronic, optical and magnetic applications: Structure, processing and properties

Edited by K. Barmak and K. Coffey

41 Handbook of laser welding technologies

Edited by S. Katayama

42 Nanolithography: The art of fabricating nanoelectronic and nanophotonic devices and systems

Edited by M. Feldman

43 Laser spectroscopy for sensing: Fundamentals, techniques and applications

Edited by M. Baudelet

44 Chalcogenide glasses: Preparation, properties and applications

Edited by J.-L. Adam and X. Zhang

45 Handbook of MEMS for wireless and mobile applications

Edited by D. Uttamchandani

46 Subsea optics and imaging

Edited by J. Watson and O. Zielinski

47 Carbon nanotubes and graphene for photonic applications

Edited by S. Yamashita, Y. Saito and J. H. Choi

48 Optical biomimetics: Materials and applications

Edited by M. Large

49 Optical thin films and coatings

Edited by A. Piegari and F. Flory

50 Computer design of diffractive optics

Edited by V. A. Soifer

51 Smart sensors and MEMS: Intelligent devices and microsystems for

industrial applications

Edited by S. Nihtianov and A. Luque

52 Fundamentals of femtosecond optics

S. A. Kozlov and V. V. Samartsev

53 Nanostructured semiconductor oxides for the next generation of electronics and functional devices: Properties and applications

S. Zhuiykov

54 Nitride semiconductor light-emitting diodes (LEDs): Materials, technologies and applications

Edited by J. J. Huang, H. C. Kuo and S. C. Shen

55 Sensor technologies for civil infrastructures

Volume 1: Sensing hardware and data collection methods for performance assessment

Edited by M. Wang, J. Lynch and H. Sohn

56 Sensor technologies for civil infrastructures

Volume 2: Applications in structural health monitoring

Edited by M. Wang, J. Lynch and H. Sohn

57 Graphene: Properties, preparation, characterisation and devices

Edited by V. Skákalová and A. B. Kaiser

58 Silicon-on-insulator (SOI) technology

Edited by O. Kononchuk and B.-Y. Nguyen

59 Biological identification: DNA amplification and sequencing, optical sensing, lab-on-chip and portable systems

Edited by R. P. Schaudies

60 High performance silicon imaging: Fundamentals and applications of CMOS and CCD sensors

Edited by D. Durini

61 Nanosensors for chemical and biological applications: Sensing with

nanotubes, nanowires and nanoparticles

Edited by K. C. Honeychurch

62 Composite magnetoelectrics: Materials, structures, and applications

G. Srinivasan, S. Priya and N. Sun

63 Quantum information processing with diamond: Principles and applications

Edited by S. Prawer and I. Aharonovich

64 Advances in non-volatile memory and storage technology

Edited by Y. Nishi

65 Laser surface engineering: Processes and applications

Edited by J. Lawrence, C. Dowding, D. Waugh and J. Griffiths

66 Power ultrasonics: Applications of high-intensity ultrasound

Edited by J. A. Gallego-Juárez and K. F. Graff

67 Advances in delay-tolerant networks (DTNs): Architectures, routing and challenges

Edited by J. J. P. C. Rodrigues

68 Handbook of flexible organic electronics: Materials, manufacturing and applications

Edited by S. Logothetidis

69 Machine-to-machine (M2M) communications: Architecture, performance and applications

Edited by C. Anton-Haro and M. Dohler

70 Ecological design of smart home networks: Technologies, social impact and sustainability

Edited by N. Saito and D. Menga

71 Industrial tomography: Systems and applications

Edited by M. Wang

72 Vehicular communications and networks: Architectures, protocols, operation and deployment

Edited by W. Chen

73 Modeling, characterization and production of nanomaterials: Electronics, photonics and energy applications

Edited by V. Tewary and Y. Zhang

74 Reliability characterisation of electrical and electronic systems

Edited by J. Swingler

75 Industrial wireless sensor networks: Monitoring, control and automation

Edited by R. Budampati and S. Kolavennu

76 Epitaxial growth of complex metal oxides

Edited by G. Koster, M. Huijben and G. Rijnders

77 Semiconductor nanowires: Materials, synthesis, characterization and applications

Edited by J. Arbiol and Q. Xiong

78 Superconductors in the power grid

Edited by C. Rey

79 Optofluidics, sensors and actuators in microstructured optical fibres

Edited by S. Pissadakis

80 Magnetic nano- and microwires: Design, synthesis, properties and applications

Edited by M. Vázquez

81 Robust design of microelectronic assemblies against mechanical shock, temperature and moisture

E.-H. Wong and Y.-W. Mai

82 Biomimetic technologies: Principles and applications

Edited by T. D. Ngo

83 Directed self-assembly of block co-polymers for nano-manufacturing

Edited by R. Gronheid and P. Nealey

84 Photodetectors

Edited by B. Nabet

85 Fundamentals and applications of nanophotonics

Edited by J. Haus

86 Advances in chemical mechanical planarization (CMP)

Edited by S. V. Babu

Introduction

The high volume fabrication of the billion or more active devices in each microprocessor chip in a silicon substrate is achieved through several evolving and continuing material and technology advances. From a manufacturing perspective, these can be best described by dividing the fabrication sequence into two segments that are commonly labeled front-end-of-the-line (FEOL) and the back-end-of-the-line (BEOL) process steps. Typically, FEOL processes include all the process steps necessary to build the device architecture in the substrate, including, in the case of CMOS devices, the structures for the electrical isolation of the devices, the source and drain of the transistors, and the gate that controls the performance characteristics of the channel between them. Of course, all these multitude of devices once fabricated need to be interconnected to form the necessary logic and memory circuits; they also need to be connected to a power source and then finally packaged. These later operations can be conveniently lumped and labeled as the BEOL process steps. Chemical mechanical planarization (CMP) has been an enabling technology in the realization of both FEOL and BEOL process steps with excellent reproducibility and acceptable product yields.

This book covers a range of topics in the rapidly advancing science and technology of CMP as it is practiced in' both FEOL and BEOL processes. The P in CMP is sometimes used to denote polishing, which may imply only material removal as in the case of a featureless blanket film. In contrast, planarization explicitly refers to the ultimate role of CMP in achieving the wafer- and die-level surface planarity across widely varying pattern sizes and densities. The other two words in CMP, chemical and mechanical, are the essence of the process, since a synergistic interplay between what at first glance may appear to be discrete processes that are essentially chemical and mechanical in nature, is crucial to the overall success of the CMP process. The nanoscale surface topographic uniformity that is essential to overcome the depth-of-focus limitations of the lithography techniques used to pattern the device structures can only be achieved by the CMP process.

Nevertheless, since it relies on the abrasive properties of metal oxide particles suspended in a colloidal dispersion, the activity of the chemical reagents, a relatively softer polymeric pad, and a wafer carrier to hold the wafer face down to achieve the nanolevel wafer and die scale planarity, it is truly counterintuitive in its scope. The side containing the active elements of each and every wafer, always processed in an ultraclean and extremely low particle environment, is exposed to billions of abrasive particles multiple times, and after each pass all the particles and the chemical agents in the dispersion need to be completely removed from the wafer surface during post-CMP processing to prevent surface contamination and degradation. In spite of this, CMP has proven to be the only viable technique that can achieve nanolevel uniformity over many generations of rapidly diminishing feature sizes.

Innovative engineering coupled with a solid scientific underpinning and creativity have led to immeasurable progress in the functionality of these integrated logic and memory devices while simultaneously lowering their ultimate cost by orders of magnitude over the last 25–30  years. Now silicon-based microelectronic devices contain over a billion active devices, a number that continues to increase, and continue to be sold at ever dropping prices. This unparalleled combination has made these devices ubiquitous in our daily life, e.g., in automobiles, smartphones and communications, video streaming, and medical diagnostics, just to name a few. In the process, they are creating an extraordinary impact on society and in some cases in unforeseen ways. Indeed, it is commonplace now to see 3- or 4-year-old children who have become proficient in manipulating screen images created by these devices to entertain themselves as well as learning from them.

Such an extraordinary functionality coupled with the necessary speedy response are achieved by continuously shrinking the feature sizes over time, planned and driven by the International Technology Roadmap for Semiconductors (ITRS), a roadmap that is updated every 2 years or so (the latest is available at http://www.itrs.net/) and keeping up with the dictates of the so-called Moore's law. Now devices containing functioning elements with a nominal size of 14  nm are in high volume production with even smaller sizes on the horizon.

The recent and successful emergence of three-dimensional finFET gate structures has led to a dramatic improvement in the performance of the logic devices but also necessitated more stringent removal rate and planarization challenges for the CMP FEOL operations. Various dielectric materials are essential components in these devices, providing electrical insulation, masking, etch and polish stops, etc., as well as playing an active role in the formation of the gate. Planarization of these dielectric films on each wafer is carried out multiple times in the process sequence and is discussed in the chapter authored by Yongsik Moon. Polishing of a-SiC, another potential stop layer in the film stack, is discussed in the chapter by Uma Lagudu.

In situ accessing of the surface of the oxide films being polished can provide very useful information. In spite of the strongly optically absorbing nature of the polishing slurries, Henrik Schumacher and Ulrich Künzelmann describe in their chapter how Fourier transform infrared spectroscopy and attenuated total reflection spectroscopy can be used to investigate the surface states as well as the chemical, mechanical, and colloidal interactions at the oxide surfaces during polishing. Additionally, planarizing SiGe and several III–V candidate materials for faster electron and hole transport across the channel in any transistor is gaining considerable attention, especially for the next generation nodes. Along with the CMP challenges, serious environmental concerns for safe handling of these materials and post-CMP disposal have emerged. These concerns are being exacerbated by the potential for various health hazards of the smaller sized abrasive particles alone or in combination with the chemical reagents present in the colloidal dispersions. These newer classes of materials and the environmental challenges posed by them are discussed in this book in the chapters authored by Patrick Ong and Lieve Teugels and by David Speed, respectively.

The immensity of the number of devices to be interconnected in the BEOL requires a complex nonplanar multilevel wiring scheme that physically towers over the silicon substrate, quite analogous to a multistory apartment complex, except that the feature sizes are at the nanolevel. Indeed, the minimum interconnect pitch, which is the sum of the wiring thickness and space between a pair of wires, is only ∼52  nm and dropping, while the number of wiring levels, analogous to the number of floors in the complex, is over 14 in some current devices.

A rough metric for the signal speed in the wiring of the interconnect structures is the inverse of product of the resistance of the conductive wires and the capacitance of the dielectric insulators separating them—the lower the product, the higher the speed. Hence, in simple terms, the metals with a high conductivity and the dielectrics with a low capacitance are preferred during design and fabrication. However, the conductivity of metallic nanowires starts decreasing with decreasing line width while lower capacitance materials are prone to mechanical and electrical reliability concerns due to their fragile nature and inherent porosity, complicating this simple criterion. In any case, Cu is the current metal of choice for the electrical wiring while a variety of so-called low-k dielectrics are available as alternatives to silicon dioxide to insulate them electrically from each other. However, Cu can diffuse through various oxide dielectrics even at relatively low temperatures and hence requires a diffusion barrier layer that also enhances adhesion between it and the dielectric layer. Until recently a thin layer of Ta/TaN has been preferred for such a barrier layer. However, due its relatively low electrical conductivity and the diminishing width of the Cu lines, thinner and more conductive metallic films like Co, Ru, Mn, etc. and their alloys are being tested. In principle, these are all very good candidates but still face several challenges that need to be overcome. In this book, these concerns regarding the use of Cu for 22  nm and future smaller nodes and ultra-low-k dielectric materials are addressed in the chapters authored by Mahadevaiyer Krishnan and Michael Lofaro and by Jakub Nalaskowski and Satyavolu Papa Rao, respectively.

The differential chemical reactivity of the Cu and barrier films when exposed to the slurry chemicals in the polishing environment can lead to the desired selective material removal but can also generate a variety of defects—corrosion pits, fangs due to galvanic corrosion, etc., and the underlying processes can be best investigated using a variety of electrochemical techniques, as described in the chapter authored by Dipankar Roy.

An importance reason for the widespread use of CMP in device fabrication, whether FEOL or BEOL, is the ability to maintain the all-important process yields by minimizing various types of defects both in dielectric and metal films through a combination of an increased understanding of the formation and characterization of various types of defects and by time-consuming and rather expensive process optimization through trial and error. CMP may even eliminate some of the preformed defects in the incoming wafers, even though it is commonly felt that CMP is the root cause of most of the defects. Since abrasives by design have to dig, scratch, and remove material from the film surface that is being planarized, they also leave defects and particle/pad residue behind. These topics are discussed in the chapter authored by Wei-Tsu Tseng. Potentially, most of these defects can be eliminated if abrasive-free solutions or dispersions with ultra-low abrasive loading can be utilized without any detrimental effects on removal rate and selectivity. Some available formulations are discussed in the chapter authored by Naresh Penta.

Another type of related, and just as important, challenge is the minimization of the within-wafer and within-die removal rate nonuniformity. The inherent complexity and dynamics of the three body interactions occurring in the wafer/abrasive/pad contact region modulated by the chemical reagents and the inability to probe this region experimentally compound and complicate the necessary process optimization. Many factors including various components in the polishing tool like the wafer carrier, pressure distribution across the wafer, retaining ring and the backing film, and the polishing pad along with the slurry flow rate and its distribution along the pad–wafer interface impact the optimization process. In spite of these difficulties, process improvements that lead to defect minimization and high product yields are being made. Slurry characteristics themselves, for example, large particles, play a crucial role in many of the polishing performance metrics. All these are discussed in the chapters authored by Manabu Tsujimura, Kevin Pate and Paul Safier, and Jihoon Seo and Ungyu Paik. Pad conditioning to maintain its surface activity is crucial and is discussed in the chapter authored by Z. Li, E. Baisie, X. Zhang, and Q. Zhang, while a novel slurry injection system that can help achieve better slurry distribution and utilization is discussed in the chapter by Len Borucki.

Since direct experimental probing of this three body contact region has not been practical, significant resources are allocated to model the interactions occurring in this region. Remarkably, the length scales involved range from hundreds of millimeters at the pad and wafer level down to nanometers at the device level, meaning a 10⁷-fold variation. The advances being made in this multilength scale arena are described in the chapter authored by Wei Fan and Duane Boning.

Novel Ge-Sb-Te-based chalcogenide phase change materials have displayed immense potential for flash memory storage but require various planarization steps for resolving some of the manufacturing challenges as discussed in the chapter authored by Zhitang Song and Liangyong Wang.

Silicon-based semiconductor processing technologies are also widely used to manufacture a variety of analog/RF devices, passive components, high voltage and power transistors, sensors and actuators commonly known as MEMS (microelectromechanical systems) and MOEMS (microoptoelectromechanical systems), and biochips. Even though the feature sizes in these devices differ widely from each other and are much larger than those in Si-based devices, they pose their own processing peculiarities. Gerfried Zwicker has authored a chapter describing the remarkable applications of CMP for these diverse applications that he aptly labeled More than Moore Devices. Next generation optoelectronic devices, a rapidly growing technology segment, require mirror-smooth GaN substrates. In spite of GaN's very high hardness and chemical inertness, CMP offers uniquely a way of achieving the desired surface finish as described in the chapter authored by Hideo Aida.

The collection of chapters that constitute this book is wide ranging but obviously does not cover the entire gamut. In particular, while immense progress has been made in understanding the fundamental science and technology of the planarization process, practice of CMP maintains a lengthy lead. The evolution of high volume production planarization processes has its own market-driven schedules and cannot wait until the first principles-based science/technology investigations provide even most, if not all, of the answers. This is probably valid for most technologies and CMP is no exception.

I wish to acknowledge each of the authors, who in spite of more pressing primary job responsibilities, dedicated vast amounts of time and effort that are required to write the texts that make up this collection. I must also acknowledge the persistence, patience, and dedication of the four individuals from the publisher that made this book a reality: Laura Pugh, who first approached and convinced me to edit this book, followed by Lucy Beg, Anneka Hess, and Christina Cameron—all accomplished professionals.

Finally, I am grateful to my large number of talented ex- and current PhD students and research associates for their hard work and dedication as well as the multitude of corporate and other partners that over the years sponsored our research activities and also collaborated with us.

S.V. Babu,     Clarkson University, Potsdam, NY, USA

Part One

CMP of dielectric and metal films

Outline

1. Chemical and physical mechanisms of dielectric chemical mechanical polishing (CMP)

2. Copper chemical mechanical planarization (Cu CMP) challenges in 22 nm back-end-of-line (BEOL) and beyond

3. Electrochemical techniques and their applications for chemical mechanical planarization (CMP) of metal films

4. Ultra low-k materials and chemical mechanical planarization (CMP)

5. CMP processing of high mobility channel materials: alternatives to Si

6. Multiscale modeling of chemical mechanical planarization (CMP)

7. Polishing of SiC films

8. Chemical and physical mechanisms of CMP of gallium nitride

9. Abrasive-free and ultra-low abrasive chemical mechanical polishing (CMP) processes

10. Environmental aspects of planarization processes

1

Chemical and physical mechanisms of dielectric chemical mechanical polishing (CMP)

Y. Moon     Advanced Technology Development (ATD), GLOBALFOUNDRIES, Malta, NY, USA

Abstract

Dielectric chemical mechanical polishing (CMP) was implemented in semiconductor fabrication as a simple alternative planarization process for the interlevel dielectrics surface instead of the reactive ion etching process of the 1980s. Since then, there have been a growing number of applications of the dielectric CMP process in advanced semiconductor fabrication because of multiple new integration schemes (such as replacement metal gate (RMG), or self-aligned contact), which require advanced planarization technology. It is important to understand its history, material removal mechanism, defect formation, and present and future applications to comprehend why dielectric CMP has to be used, how the material is removed, and how the defect is created. By understanding what has been studied on the current dielectric CMP process, future applications of dielectric CMP can be further improved for better process performance and, therefore, for better device performance and yield.

Keywords

Chemical mechanical planarization; Chemical mechanical polishing (CMP); Interlevel dielectrics (ILD); Oxide CMP; Semiconductor fabrication

1.1. Introduction

A dielectric material is an electrical insulator (such as silicon dioxide), which is widely used in semiconductor fabrication. In shallow trench isolation (STI), dielectric material separates the two transistors by being located between two devices. In the interlevel dielectric (ILD) layer, a dielectric separates the whole device region from the metallization layer as an independent layer located between the front-end-of-line (FEOL) and back-end-of-line (BEOL). Dielectric chemical mechanical polishing (CMP) is the CMP process that will polish and planarize dielectrics. Dielectric CMP is the first CMP process used in modern microdevice fabrication and the most widely used among all the CMP processes in memory devices as well as in logic devices in semiconductor manufacturing. In this chapter, the dielectric CMP is reviewed from its material removal mechanisms to its applications in semiconductor fabrication. It is important to understand its history, its motivation to use, and its future application in advanced semiconductor technology.

1.2. History of dielectric CMP

CMP or planarization is a relatively new fabrication technology in semiconductor manufacturing, compared to lithography, etching, or thin film deposition technology. The concept of polishing has been used for centuries for optics fabrication. In the early 1950s, polishing was implemented in preparing silicon wafer substrate to minimize any surface damage [1,2]. In the 1980s, polishing was used as part of the integrated circuit fabrication process to planarize the ILD surface instead of reactive ion etching (RIE) technology [3], and the first technical paper on CMP was published in the late 1980s [4]. Since then, ILD CMP has become the process of choice for ILD planarization and the role of the CMP process has expanded to other applications such as STI, tungsten contact formation, or copper metallization by damascene technology.

In the advanced semiconductor technology node, dielectric CMP is no longer a simple dielectric planarization process. The applications of dielectric CMP technology further extended to multiple modules to enable critical integration schemes such as replacement metal gate (RMG), multigate transistor, or self-aligned contact (SAC) modules. In particular, since CMP's use in gate formation, the technological requirement from the dielectric CMP process went beyond what the conventional dielectric CMP process was able to deliver. The number of CMP processes in advanced semiconductor manufacturing has also expanded up to 20–30 steps because of RMG and fin formation (Figure 1.1).

Figure 1.1  CMP applications in advanced logic technology [ 5 , 13 ].

In order to meet this stringent process requirement, technological innovation is needed in various CMP consumables, process parameters, or process control, such as extreme selectivity slurry, self-stopping-on-planarization slurry, solid polishing pad with extended planarization length capability, or real-time automatic process/profile control.

1.3. Material removal mechanism of dielectric CMP

The material removal rate (MRR) of CMP is explained by the Preston equation, which was developed in the glass polishing application [6]. It simply indicates that the MRR is proportional to the pressure applied on the wafer and the relative velocity of the wafer.

The Preston equation is a very simple equation to explain the major process parameters in predicting the MRR of glass polishing. In the modern CMP process, which is used in advanced semiconductor fabrication, it is almost impossible to predict the accurate MRR from a certain process condition by knowing only pressure and velocity of the wafer being polished. This is because there are quite a few process parameters in addition to pressure and velocity, which can greatly impact on the MRR and mechanism. There are numerous process models that can predict the MRR at given process conditions, but none of them is able to provide a precise MRR because of the complexity of the process.

The material removal mechanism of the CMP process was relatively well explained by the previous scientists. The material removal mechanism of dielectric CMP is further well explained by Cook in his paper published in 1990 Si) and the diffusion rate is controlled by multiple process conditions such as pressure or temperature. This hydrated oxide surface is removed by an abrasion process. The indentation process by each abrasive was modeled by Hertzian contact and their contact stress was calculated from the theory of elasticity.

The mechanical component of the material removal mechanism in the CMP process has been explained from previous literature [7,8].

First of all, the mechanical behavior of the CMP process needs to be understood in order to explain the mechanical component of the material removal mechanism. At the experimental set-up to measure the friction force on the wafer surface, the polishing platen was connected to a load cell while it is at a fixed position (Figure 1.2). The load cell enabled the measurement of the friction between the wafer and the polishing pad. The friction signal from the load cell was amplified and collected using a PC-based data collection system.

The wafer did not rotate to its own center, but made a rotation against the center of the polishing pad with or without the presence of the polishing slurry. The downforce on the wafer and the rotational speed of the wafer were changed and the friction applied on the wafer surface was monitored.

It was shown that the friction force applied on the wafer was directly proportional to the downforce. In a dry pad condition without any slurry, the friction on the wafer was relatively constant with the wafer velocity. However, in the presence of polishing slurry on the pad, the friction force decreased with the wafer velocity (Figure 1.3). This phenomenon can be well explained by the Stribeck curve from tribology (Figure 1.4).

The Stribeck curve explains the relationship between the coefficient of friction and the lubrication thickness with a certain constant called Hersey number. Hersey number is the multiplication of the viscosity of the lubricant and the velocity of the moving object divided by the pressure applied on the object.

The Stribeck curve shows that the friction force applied on the moving surface decreases with the relative velocity of the moving object in the presence of lubrication. This is because the thickness of the lubrication film between two objects increases with the relative velocity. In the presence of the abrasive slurry, the friction between the wafer and the pad decreased with the wafer velocity. It is believed that this is caused by increased slurry thickness between the wafer and the pad from higher wafer velocity. In the dry pad condition, however, the friction force remained constant with the wafer velocity since there is no lubrication film under the wafer surface. This can be illustrated in terms of interaction with pad and abrasives (Figure 1.5). In the condition of high downforce or low wafer velocity, the wafer moves on the pad with thinner slurry film. This can cause increased interaction between the wafer surface and the abrasives supported by the polishing pad. In the condition of low downforce or high wafer velocity, wafer behavior can be the opposite. Wafer can slide on the pad with thicker slurry film. This can result in less interaction between the wafer and the abrasives.

Figure 1.2  Friction force measurement during the CMP process [8] .

Figure 1.3  Friction force measurement during the CMP process [8] . (a) Without polishing slurry and (b) with polishing slurry.

Figure 1.4  Stribeck curve [ 8 , 9 ].

Figure 1.5  Illustration of CMP with different slurry film thickness [8] . (a) CMP with thinner slurry film and (b) CMP with thicker slurry film.

Figure 1.6  Amount of material removal per sliding distance during CMP [8] .

In order to understand the kinetics of the material removal mechanism in CMP, the amount of material removal per sliding distance needs to be measured and understood (Figure 1.6). By using the same test set-up shown previously, the amount of oxide removal per sliding distance was measured with different wafer velocity and downforce. The amount of oxide removal per sliding distance was at the maximum at the lower wafer velocity. As the wafer velocity increased, material removal per sliding distance decreased. This phenomenon can explain how material removal is made in different vertical positions of the wafer.

At the higher wafer velocity, the slurry film between the wafer surface and the polishing pad becomes thicker and there is less chance of the polishing pad asperity being in contact with the wafer surface. This means there will be fewer abrasives in contact with the wafer surface and, thus, the material removal per sliding distance is minimized. At the lower wafer velocity, the slurry film becomes thinner and more pad asperity is in contact with the wafer surface. In this case, material removal per sliding distance is maximized.

Abrasives in the polishing slurry are trapped between the wafer surface and the polishing pad asperity during the polishing process. This phenomenon enables the abrasion action on the wafer surface caused by the relative motion between the pad and the wafer. Therefore, the more pad asperity in contact with the wafer surface, the more material removal per sliding distance can be expected. In both cases, the wafer traveled the same distance. However, material removal during the identical distance changes depending on how fast the wafer travels the distance. As indicated in the Stribeck curve, the wafer with high velocity will interact less with the pad and the abrasive due to thicker slurry film. This results in lower material removal. The wafer with low velocity, however, will interact more with the pad and the abrasive due to thinner slurry film. This results in higher material removal. This phenomenon is very important to understand the material removal mechanism in dielectric CMP and is illustrated in Figure 1.7.

Figure 1.7  Illustration of the material removal per sliding distance with two different slurry films during CMP [8] . (a) CMP with thinner slurry film and (b) CMP with thicker slurry film.

From a simple experiment, the mechanical portion and the chemical portion in the MRR can be explained. The abrasives in the polishing slurry were separated by using a centrifuge process and were mixed with deionized (DI) water to create a chemical-less polishing slurry (Figure 1.8). The abrasives in DI water are dispersed using an agitator to remove any abrasive agglomeration. The chemical that was separated from the original polishing slurry became the abrasive-less polishing slurry. Both slurries were used in the polishing test using the oxide wafer and material removal per sliding distance was measured (Figure 1.9). The polishing process with chemical-less slurry is called mechanical polishing and the one with abrasive-less slurry is called chemical polishing. Material removal per sliding distance using the regular polishing slurry was corrected for comparison.

Material removal per sliding distance in chemical polishing was simply zero. This indicates the material cannot be removed without abrasives since they activate the abrasion action in the oxide CMP. Previous literature also showed that the MRR is simply zero without abrasive particles inside the slurry [7]. This indicates that material removal cannot be made only by the chemical reaction between the dielectric surface and the chemicals in the polishing slurry. The mechanical portion of the material removal mechanism is crucial in obtaining the MRR in the CMP process.

Figure 1.8  Illustration of preparation of chemical-less and abrasive-less polishing slurry [8] .

Figure 1.9  Material removal per sliding distance from mechanical polishing and chemical polishing [8] .

Figure 1.10  Material removal mechanism in the CMP process [8] .

In the case of the mechanical polishing that uses chemical-less slurry, the material removal per sliding distance was relatively consistent with velocity and only 40–60% of material removal from the regular CMP process. The material removal per sliding distance from mechanical polishing is suppressed because of insufficient chemically activated layers, which assist in the molecular-scale abrasion action. These phenomena indicate that material removal from the polishing process can be maximized only when there is a synergy effect between the mechanical and the chemical action during the polishing process.

In summary, the material removal mechanism during dielectric CMP can be defined as the abrasives that are trapped between the wafer surface and the polishing pad asperity make an abrasion action against the wafer surface that was chemically modified. The key mechanism to determine overall MRR from the wafer surface is how many abrasives are engaged with the wafer surface in the presence of force applied on the abrasives. The number of the active abrasives depends on the actual gap, or the slurry film thickness between the polishing pad and the wafer surface. The slurry film thickness can be controlled by the downforce applied on the wafer, the relative velocity between the wafer and the polishing pad, and the viscosity of the polishing slurry. The slurry film thickness or gap can determine the contact area of the pad asperity where the active abrasives are trapped and engaged for the abrasion process. This material removal mechanism is illustrated in Figure 1.10.

1.4. Defectivity of dielectric CMP

The major defectivity mode from the dielectric CMP process is polishing scratches (Figure 1.11). A polishing scratch at the STI CMP process is used as an example in this chapter since a scratch can be more visible at the STI CMP due to additional chemical etching process steps. At the STI CMP, oxide is polished away until silicon nitride (SiN) is fully exposed. After STI CMP, additional oxide is chemically etched out to eliminate any residual oxide on the top of SiN. The nitride is etched out to expose the active silicon surface (Figure 1.12).

Figure 1.11  SEM images of micro-scratch at post-STI CMP process [10] .

As observed in the scanning electron microscope (SEM) image, any macro-scratch can be observed right after the STI CMP step, but most of the polishing scratches can be seen after the oxide deglazing step since the wet etch step can make any tiny micro-scratch more visible by isotropic etching (Figure 1.13). A very tiny micro-scratch can be observed on the nitride surface, but the scratch on the oxide surface is expanded due to the additional wet etch step.

This phenomenon has been shown in the optics polishing study [11] (Figure 1.14). In the case of loose abrasive grinding/polishing using diamond abrasives, only the straight line of a micro-scratch can be observed right after the polishing process. After oxide etching by 20% hydrogen fluoride for 60  s, the circular shape chatter-mark polishing scratch can be clearly seen.

The mechanism of the chatter-mark scratch has been explained from optics polishing [7] (Figure 1.15). It was shown that as a grinding particle travels across a glass surface, the tensile stress from the frictional pull of the particle results in chatter-mark flaws. The area in front of the abrasive particle will be under compressive stress and the area after abrasives have passed will be under tensile stress. The reason for the round shape chatter-mark was explained using maximum shear stress formation [12] (Figure 1.16). When an object is under normal stress and shear stress at the same time, the resultant stress field due to the inclined loading on a surface will show both compressive and tensile stresses. Because of the circular shape maximum shear stress in the tensile region from the side view, the round shape chatter-mark is created behind the point of contact body. From a study of the grinding and lapping process, it was shown that the circular shape lateral crack can be created under normal pressure indentation on a brittle surface because of the maximum shear stress around the indented spot [13] (Figure 1.17).

Figure 1.12  STI CMP process [10] . (a) Pre-CMP, (b) STI CMP, (c) oxide deglazing, and (d) nitride strip.

Figure 1.13  SEM images of micro-scratch at post-STI CMP process [10] .

Figure 1.14  Images of polished glass surface after polishing (before etch) and after etching. Reproduced with permission Ref. [11], © 1991 Optical Society of America.

Figure 1.15  Stress created in glass surface due to bonding between polishing particle and glass surface.

Figure 1.16  Resultant stress field due to inclined loading of a surface [12] .

Figure 1.17  Circular-shape lateral crack under normal pressure indentation on a brittle surface [13] .

Figure 1.18  Polishing scratch mechanism in dielectric CMP [10] .

The polishing scratch mechanism in dielectric CMP is illustrated in Figure 1.18. From the top view, an arc shaped chatter-mark is created behind the abrasive contact region because of the maximum shear stress in the tensile region. In this case, the concave side of the arc shape of the micro-scratch will face the direction of travel of the abrasive against the wafer surface. From

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