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Plasma Etching Processes for CMOS Devices Realization

Plasma Etching Processes for CMOS Devices Realization

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Plasma Etching Processes for CMOS Devices Realization

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191 página
1 hora
Lançado em:
Jan 25, 2017
ISBN:
9780081011966
Formato:
Livro

Descrição

Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent. Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography. This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.

  • Helps readers discover the master technology used to pattern complex structures involving various materials
  • Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials
  • Teaches users how etch compensation helps to create devices that are smaller than 20 nm
Lançado em:
Jan 25, 2017
ISBN:
9780081011966
Formato:
Livro

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Plasma Etching Processes for CMOS Devices Realization - Elsevier Science

Plasma Etching Processes for CMOS Device Realization

Nicolas Posseme

Series Editor

Robert Baptist

Table of Contents

Cover image

Title page

Copyright

Preface

1: CMOS Devices Through the Years

Abstract

1.1 Scaling law by Dennard

1.2 CMOS device improvement through the years

1.3 Summary

1.4 What is coming next?

2: Plasma Etching in Microelectronics

Abstract

2.1 Overview of plasmas and plasma etch tools

2.2 Plasma surface interactions during plasma etching

2.3 Patterns transfer by plasma etching

2.4 Conclusion

3: Patterning Challenges in Microelectronics

Abstract

3.1 Optical immersion lithography

3.2 Next-generation lithography

3.3 Conclusion

4: Plasma Etch Challenges for Gate Patterning

Abstract

4.1 pSi gate etching

4.2 Metal gate etching

4.3 Stopping on the gate oxide

4.4 High-k dielectric etching

4.5 Line width roughness transfer during gate patterning

4.6 Chamber wall consideration after gate patterning

4.7 Summary

List of Acronyms

List of Authors

Index

Copyright

First published 2017 in Great Britain and the United States by ISTE Press Ltd and Elsevier Ltd

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

ISTE Press Ltd

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London SW19 4EU

UK

www.iste.co.uk

Elsevier Ltd

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Kidlington, Oxford, OX5 1GB

UK

www.elsevier.com

Notices

Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary.

Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility.

To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein.

For information on all our publications visit our website at http://store.elsevier.com/

© ISTE Press Ltd 2017

The rights of Nicolas Posseme to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

British Library Cataloguing-in-Publication Data

A CIP record for this book is available from the British Library

Library of Congress Cataloging in Publication Data

A catalog record for this book is available from the Library of Congress

ISBN 978-1-78548-096-6

Printed and bound in the UK and US

Preface

Nicolas Posseme October 2016

Plasma etching is the main technology used to pattern complex structures involving various materials (from metals to semiconductors and oxides to polymers) in domains such as microelectronics, bio-technology, photonics and microsensors. The ability of cold plasmas, including mainly inductively coupled plasmas (ICP) and capacitively coupled plasmas (CCP), to generate well-controlled etched profiles (anisotropic (vertical) etching) and high etch selectivities (selected material is etched at the much higher rate than others) between materials involved in complex stacks of materials has made this technology successful. The most famous field in which plasma technology has played a key role for the last 40 years is the semiconductor industry.

Plasma etching (using an ionized gas to carve tiny components on silicon wafers) has long enabled the perpetuation of Moore’s law (the observation that the number of transistors that can be squeezed into an integrated circuit doubles about every 2 years). Today, etch compensation helps to create devices that are smaller than 20 nm.

Plasma technologies have been critical not only to assist the miniaturization capabilities of lithography with specific processes such as resist trimming processes (lateral erosion of the photoresist mask in order to decrease its critical dimension defined by the lithography) and double patterning (a method of overlaying two patterns to achieve the original design) technologies, but also to pattern complex structures with the appropriate level of dimension control. However, with the constant scaling down in device dimensions and the emergence of planar fully depleted silicon on insulator (FDSOI) or complex 3D structures (like FinFET sub-20 nm devices, nanowires and stacked nanowires at long term), plasma etching requirements have become more and more stringent with critical dimension control, profile control and film damage at the atomic scale to reach zero variability (precise control of the gate transistor dimension with no damage) required at the horizon of 2020 according to the ITRS.

Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvements in plasma technology (plasma sources, chamber design, etc.), new chemistry methods (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, direct self-assembly (DSA), e-beam lithography or nanoimprint lithography.

The goal of this book is to present these etch challenges and associated solutions encountered through the years for transistor realization.

After an introduction to the evolution of CMOS devices through the years in Chapter 1, we will define in Chapter 2 the plasma etching in microelectronics. Then, in Chapter 3, we will present patterning challenges in microelectronics and how plasma etch technology becomes a key solution. Finally, in Chapter 4, we will present the challenges and constraints associated with transistor manufacturing.

1

CMOS Devices Through the Years

Maud Vinet; Nicolas Posseme

Abstract

The CMOS transistor is the fundamental building block of modern electronic devices and is ubiquitous in modern electronic systems. Its dimension is typically around 20 nm and the unit cost of the device is around a few nano dollars.

Keywords

CMOS Devices; FDSOI; FinFET; Gate-last approach; Leakage current reduction; Mobility; Patterning; Scaling law

The CMOS transistor is the fundamental building block of modern electronic devices and is ubiquitous in modern electronic systems. Its dimension is typically around 20 nm and the unit cost of the device is around a few nano dollars.

The basic principle of the solid state transistor was stated by Julius Edgar Lilienfeld in 1925 who patented "a method and apparatus for controlling the flow of an electric current between two terminals of an electrically conducting solid by establishing a third potential between said terminals" (Figure 1.1) [LIL 25].

Figure 1.1 Schematics of Lilienfeld’s original patented transistor (from E.J. Lilienfeld [LIL 25])

The experimental demonstration began in 1947 with American physicists John Bardeen, Walter Brattain and William Shockley who made the first point contact transistor (Figure 1.2). Working at Bell Labs, they were looking for a solution to replace the vacuum tubes which were not very reliable, consumed too much power and produced too much heat to be practical for AT&T’s markets. They were jointly awarded the Nobel Prize in Physics in 1956 for their achievement [NOB 47].

Figure 1.2 Artifact of the first point contact transistor fabricated by Bardeen, Shockley and Brattain in 1947 in Bells Labs

The first demonstration of a semiconductor-based amplifying device was the point contact transistor made out of a germanium crystal lying on a metal plate. The crystal was contacted by a gold strip cut into two pieces which were a hair apart, and covered a triangle which was held in contact by a spring.

To improve the point contact transistor, Shockley conceived the possibility of minority carrier injection and invented an entirely new, considerably more robust, type of transistor with a layered or sandwich structure. This structure went on to be used for the vast majority of all transistors in the 1960s, and evolved into the bipolar junction transistor. At that time, though, the junction-based transistors were limited in performance, since they were not able to carry voice signals due to frequency limitations.

The man who paved the way for the improvement was Gordon Teal, who suspected that better grown materials of better quality could lead to better performance. Teal thought transistors should be built from a single crystal, as opposed to cutting a sliver from a larger ingot of many crystals. His method was to take a tiny seed crystal and dip it into the melted germanium then pull slowly as a crystal formed like an icicle below the seed.

In 1959, Dawon Kahng and Martin M. (John) Atalla at Bell Labs invented the metal–oxide–semiconductor field-effect transistor (MOSFET). Operationally and structurally, it was different from the bipolar junction transistor. The MOSFET was made by putting an insulating layer on the surface of the semiconductor and then placing a metallic gate electrode on that. It used crystalline silicon for the semiconductor and a thermally oxidized layer of silicon dioxide for the insulator. The silicon MOSFET did not generate localized electron traps at the interface between the silicon and its native oxide layer, and thus was inherently free from the trapping and scattering of carriers that had impeded the performance of the earlier field-effect transistors.

As the industry expanded, the fundamental fabrication operations (photolithography, etching, deposition and thermal treatment) became more and more specialized and intertwined. Relying on several suppliers, this specialization led the industry to advance at a fast pace. The need for a technology roadmap arose in order to coordinate the industry, so that each supplier could target an appropriate date for their part of the work [GAR 00].

For several years, the Semiconductor Industry Association (SIA) gave the responsibility of coordination to the United States, which led to the creation of an American style roadmap, called the National Technology

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