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Three-Dimensional Integrated Circuit Design

Three-Dimensional Integrated Circuit Design

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Three-Dimensional Integrated Circuit Design

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Jul 4, 2017


Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.

Expanded with new chapters and updates throughout based on the latest research in 3-D integration:

  • Manufacturing techniques for 3-D ICs with TSVs
  • Electrical modeling and closed-form expressions of through silicon vias
  • Substrate noise coupling in heterogeneous 3-D ICs
  • Design of 3-D ICs with inductive links
  • Synchronization in 3-D ICs
  • Variation effects on 3-D ICs
  • Correlation of WID variations for intra-tier buffers and wires
  • Offers practical guidance on designing 3-D heterogeneous systems
  • Provides power delivery of 3-D ICs
  • Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more
  • Provides experimental case studies in power delivery, synchronization, and thermal characterization
Lançado em:
Jul 4, 2017

Sobre o autor

Vasilis F. Pavlidis received the B.Sc. and M.Eng. degrees in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2003 and 2008, respectively. He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer. Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative.

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Amostra do Livro

Three-Dimensional Integrated Circuit Design - Vasilis F. Pavlidis

Three-Dimensional Integrated Circuit Design

Second Edition

Vasilis F. Pavlidis

Ioannis Savidis

Eby G. Friedman

Table of Contents

Cover image

Title page



List of Figures

About the Authors

Preface to the Second Edition

Preface to the First Edition


Organization of the Book

Chapter 1. Introduction


1.1 Interconnect Issues in Integrated Systems

1.2 Three-Dimensional or Vertical Integration

1.3 Book Organization

Chapter 2. Manufacturing of Three-Dimensional Packaged Systems


2.1 Stacking Methods for Transistors, Circuits, and Dies

2.2 System-on-Package

2.3 Technologies for System-in-Package

2.4 Technologies for 2.5-D Integration

2.5 Summary

Chapter 3. Manufacturing Technologies for Three-Dimensional Integrated Circuits


3.1 Monolithic Three-Dimensional ICs

3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via

3.3 Contactless Three-Dimensional ICs

3.4 Vertical Interconnects for Three-Dimensional ICs

3.5 Summary

Chapter 4. Electrical Properties of Through Silicon Vias


4.1 Physical Characteristics of a Through Silicon Via

4.2 Electrical Model of Through Silicon Via

4.3 Modeling a Three-Dimensional Via as a Cylinder

4.4 Compact Models

4.5 Through Silicon Via Impedance Models

4.6 Electrical Characterization Through Numerical Simulation

4.7 Case Study—Through Silicon Via Characterization of the MITLL TSV process

4.8 Summary

Chapter 5. Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs


5.1 Heterogeneous Substrate Coupling

5.2 Frequency Response

5.3 Techniques to Improve Noise Isolation

5.4 Summary

Chapter 6. Three-Dimensional ICs with Inductive Links


6.1 Wireless On-Chip Communication Interfaces

6.2 On-Chip Inductors for Intertier Links

6.3 Transmitter and Receiver Circuits

6.4 Challenges for Wireless On-Chip Communication

6.5 Intertier Power Transfer

6.6 Summary

Chapter 7. Interconnect Prediction Models


7.1 Interconnect Prediction Models for Two-Dimensional Circuits

7.2 Interconnect Prediction Models for Three-Dimensional ICs

7.3 Projections for Three-Dimensional ICs

7.4 Summary

Chapter 8. Cost Considerations for Three-Dimensional Integration


8.1 Through Silicon Via Processing Options

8.2 Interposer-Based Systems Integration

8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration

8.4 Summary

Chapter 9. Physical Design Techniques for Three-Dimensional ICs


9.1 Floorplanning Techniques

9.2 Floorplanning Three-Dimensional ICs

9.3 Placement Techniques

9.4 Placement in Three-Dimensional ICs

9.5 Routing Techniques

9.6 Layout Tools

9.7 Summary

Chapter 10. Timing Optimization for Two-Terminal Interconnects


10.1 Intertier Interconnect Models

10.2 Two-Terminal Nets With a Single Intertier Via

10.3 Two Terminal Interconnects With Multiple Intertier Vias

10.4 Summary

Chapter 11. Timing Optimization for Multiterminal Interconnects


11.1 Timing Driven Via Placement for Intertier Interconnect Trees

11.2 Multiterminal Interconnect Via Placement Heuristics

11.3 Via Placement Algorithms for Interconnect Trees

11.4 Discussion of Via Placement Results

11.5 Summary

Chapter 12. Thermal Modeling and Analysis


12.1 Heat Transfer in Three-Dimensional ICs

12.2 Closed-Form Temperature Models

12.3 Mesh-Based Thermal Models

12.4 Thermal Analysis Techniques

12.5 Summary

Chapter 13. Thermal Management Strategies for Three-Dimensional ICs


13.1 Thermal Management Through Power Density Reduction

13.2 Thermal Management Through Enhanced Thermal Conductivity

13.3 Hybrid Methodologies for Thermal Management

13.4 Summary

Chapter 14. Case Study: Thermal Coupling in 3-D Integrated Circuits


14.1 Thermal Propagation Test Circuit

14.2 Setup and Experiments

14.3 Design Considerations Based on Experimental Results

14.4 Verification of Experimental Results with Simulations

14.5 Summary

Chapter 15. Synchronization in Three-Dimensional ICs


15.1 Synthesis Techniques for Planar Clock Distribution Networks

15.2 Global Three-Dimensional Clock Distribution Networks

15.3 Synthesis of Three-Dimensional Clock Distribution Networks

15.4 Practical Considerations of Three-Dimensional Clock Tree Synthesis

15.5 Summary

Chapter 16. Case Study: Clock Distribution Networks for Three-Dimensional ICs


16.1 MIT Lincoln Laboratories Three-Dimensional IC Fabrication Technology

16.2 Three-Dimensional Test Circuit Architecture

16.3 Clock Distribution Network Structures Within the Test Circuit

16.4 Models of the Clock Distribution Network Topologies Incorporating Three-Dimensional Via Impedance

16.5 Experimental Results

16.6 Summary

Chapter 17. Variability Issues in Three-Dimensional ICs


17.1 Process Variations in Data paths Within Three-Dimensional ICs

17.2 Effects of Process Variations on Clock Paths

17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks

17.4 Summary

Chapter 18. Power Delivery for Three-Dimensional ICs


18.1 The Power Delivery Challenge

18.2 Models for Three-Dimensional Power Distribution Networks

18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise

18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks

18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks

18.6 Summary

Chapter 19. Case Study: 3-D Power Distribution Topologies and Models


19.1 3-D Power Distribution Network Test Circuit

19.2 Experimental Results

19.3 Characteristics of 3-D Power Distribution Topologies

19.4 Summary

Chapter 20. 3-D Circuit Architectures


20.1 Classification of Wire Limited 3-D Circuits

20.2 3-D Microprocessors and Memories

20.3 3-D Networks-on-Chip

20.4 3-D FPGAs

20.5 Summary

Chapter 21. Conclusions

Appendix A. Enumeration of Gate Pairs in a 3-D IC

Appendix B. Formal Proof of Optimum Single Via Placement

Appendix C. Proof of the Two-Terminal Via Placement Heuristic

Appendix D. Proof of Condition for Via Placement of Multi-terminal Nets

Appendix E. Correlation of WID Variations for Intratier Buffers

Appendix F. Extension of the Proposed Model to Include Variations of Wires

Glossary of Terms




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To Stella for her disarming criticism.


To my wife, Ana Lucia, my son, Ioannis Alexander, and to the rest of my family for their endless love and support.


To Laurie, my companion in life.


List of Figures

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