COMPUTER ARCHITECTURE CS 1251 VI SEMESTER CHAPTER - 1 UNIT 1 --------BASIC STRUCTURE OF COMPUTERS PART A 1.

.Write the basic functional units of computer ? The basic functional units of a computer are input unit ,output unit ,memory unit , ALU unit and control unit. 2.Define ALU. What are the various operations performed in ALU? ALU is a part of computer that performs all arithmetic and logical operations. It is a component of central processing unit. Arithmetic operations: Addition, subtraction, multiplication, division, increment and decrement; Logical operations: AND, OR, XOR, NOT, compare, shift, rotate.3. Compute the effective CPI for a processor, for the following instruction mix: Instruction type Clock cycle count Frequency ALU operations 1 40 Loads 3 20 Stores 2 10 Branches taken 3 20 Branches untaken 2 10 An enhancement to the processor is made by adding a branch prediction unit. This decreases the number of cycles taken to execute a branch from 3 to 2. What is the improvement in performance ? Speed up =execution time old /execution time new Execution time old or CPU time=I.C.* Clk Cycles * cycle time Execution time old =[40*1+20*3+10*2+20*2+10*2] Cycles*cycles time The enhancement decreases the number of cycles taken for branch instruction from 3 to 2. Execution time new =[40*1+20*3+10*2+20*2+10*2] =180 cycles *cycle time Speed up = (200*cycles time)/(180 cycles *cycles time) =1.1 4.What is a bus? What are the different buses in a CPU? A group of lines that serve as a connecting path for several devices is called bus . The different buses in a CPU are 1] Data bus 2] Address bus 3] Control bus 5. Why data bus is bidirectional and address bus is unidirectional in most microprocessor? Data bus:

The data bus consists of 8, 16, 32 or more parallel signal lines. These lines are used to send data to memory and output ports ,and to receive data from memory and input port. Therefore, data bus lines are bidirectional. This means that CPU can read data on these lines from memory or from a port, as well as send data out of these lines to a memory location or to a port. The data bus is connected in parallel to all peripherals. The communication between peripherals and CPU is activated by giving output enable pulse to the peripherals. Outputs of peripherals are floated when they are not in use. Address bus: It is a unidirectional bus. The address bus consists of 16, 20, 24 or more parallel signal lines. On these lines the CPU sends out the address of the memory location or IO port that is to be written to or read from. Here, the communication is one-way, the address is send from CPU to memory and IO port and hence these lines are unidirectional. 6. What is meant by stored program concepts? Discuss. Stored program concept is an idea of storing the program and data in the memory. 7. Define multiprogramming? Multiprogramming is a technique in several jobs are in main memory at once and the processor is switched from job as needed to keep several jobs advancing while keeping the peripheral devices in use. 8. Define multiprocessing? Multiprocessing is the ability of an operating system to support more than one process at the same time. 9. Define time sharing? Time sharing is the process in which the system is designed to allow many users to use the CPU simultaneously. 10. What is a super computer? A computer with high computational speed, very large memory and expansive parallel structured hardware is known as a super computer. EX: CDC 6600 11. What is meant by VLSI technology? VLSI is the abbreviation for Very Large Scale Integration. In this technology millions of transistors are put inside a single chip as tiny components. The VLSI chips do the function of millions of transistors. These are used to implement parallel algorithms directly in hardware. 12. What are the characteristics of Von Neumann computers?

* The program can data were represented in digital form and stored in the memory. * The architecture has 5 basic parts -> the memory, the ALU, Control Unit, Input unit and output unit. * It uses binary arithmetic. * There were only fixed point arithmetic and no floating point arithmetic. * used a special general purpose register called Accumulator. * The first general purpose machine. 13. Define parallel processing. It is an efficient form of information processing to exploit the concurrent events in the computing process. 14. Define pipelining. Pipelining is technique of decomposing a sequential process in to number of sub operations and each of these sub operations are carried out independently in dedicated segments concurrently. 15. Mention some applications of parallel processing. * In simulation and Modeling -> weather forecasting, oceanography, socio economy * Engineering design and automation -> Aerodynamics, finite element analysis AI * Medical, military and research -> computer assisted topography genetic engineering etc * Energy resource explosion. 16. In what way hardware and software are equivalent? Not equivalent. Software and hardware are logically equivalent. Any operation done by software could be done by hardware. Any instruction executed by hardware can be simulated by software. They are not equivalent in the sense that, minimum hardware required to execute software cannot be simulated by software. In other words with out the hardware software cannot function, whereas with NIL software the hardware function perfectly. 17. Distinguish between hardware and firmware. The hardware deals with all electronics and electrical components of a computer. EX: ICs, diodes, resistors, power supplies, tapes etc The firmware is embedded software of certain electronic circuits. EX: ROMBIOS. 18. What is an operating system? A System software which acts as an interface between the user and the machine. 19. Define system throughput. It is defined as the number of instructions executed per unit time (sec). 20. What is mainframe computer?

It is the large computer system containing thousands of ICs. It is a room- sized machine placed in special computer centers and not directly accessible to average users. It serves as a central computing facility for an organization such as university, factory or bank. 21. What is mini computer? Minicomputers are small and low cost computers are characterized by Short word size i.e. CPU word sizes of 8 or 16 bits. Limited hardware and software facilities. Physically smaller in size. 2. Define micro computer. Microcomputer is a smaller, slower and cheaper computer packing all the electronics of the computer in to a handful of ICs, including the CPU and memory and IO chips. 25. What is workstation? The more powerful desktop computers intended for scientific and engineering applications are referred as workstations. 26. Write the features of the third generation computers? Pipelining concept was introduced. Cache memory concept was introduced to close the speed gap between the CPU and main memory Multiprogramming was introduced. Time sharing concept was introduced. Virtual memory concept was introduced to close the speed gap between the CPU and main memory. Multiprogramming was introduced. Time sharing concept was introduced. Virtual memory concept was introduced. Ex: IBM 360/370, CDC 6600/7600, Texas Instruments ASC (Advanced Scientific Computer), Digital Equipments PDP-8. CHAPTER-2 UNIT 1 ----------MACHINE INSTRUCTIONS AND ADDRESSING MODES PART-A 1. What is load store architecture? In a load / store architecture, operands must be in registers before they can be processed. The instructions that refer to memory Locations are load, store and jump / branch .It supports limited set of addressing modes and use hardware to execute instructions. 2. Explain the absolute and auto increment addressing modes with an example instruction.

Absolute or direct addressing: To fetch an operand, the address of the operand in the memory is given in the instruction. This form is called direct addressing. This type of addressing mode is used for handling STATIC data Add B=> A = A + M [B] Auto-increment addressing mode: It is similar to register indirect mode except that register is incremented after its value is used to access memory. Add R1, (R2) +; R1 <- R1 + M [R2] R2 <- R2 +d This type of addressing mode is useful for stepping through arrays in a loop. R2 start of array d size of an element 3. List out the different computer instruction formats. 4 address instruction Opcode Source opera address 1 Source opera address 2 Destination opera address Next instructi address 3 address instruction Opcode Source operand address Source operand address Destination opera address 2 address instruction Opcode Source destination opera address Source operand address 2 1 address instruction Opcode Source operand address 0 address instruction Opcode 4. Explain the following addressing modes with an example: a) Register indirect addressing b) Relative addressing Register indirect addressing: The effective address of the operand is the contents of the register or memory location, whose address appears in the instruction. Add R1, R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3. Application: 1. used in pointers

R3 Memory Relative addressing: The effective address is obtained by adding contents of program counter with displacement. Effective address = [PC] + displacement Ex: near, far, short, jump instructions 1. mem address instruction displacement 1000 near 10 EA for next instruction = [PC] + 10 = 1001 + 10 = 1011 2. mem address instruction displacement 4000 JC 50 EA = 4001 + 50 = 4051 5. Define index mode. In this mode the contents of the index register is added to the address part of the instruction to get the EA of the operand. The index register is a special purpose CPU register that contains the index value. The address part of the instruction determines the starting address of the data array in the memory. Each operand in the array is stored in the memory relative to the starting address of the array. The distance between the starting address of the array and the location of the operand in the array is the index value present in the index register. Any operand in the array can be accessed with the same instruction provided that the index register contains the correct index value. The index register can be incremented to facilitate access to the consecutive operands. Some computers dictate one CPU register to function as index register. This register is involved implicitly when the index mode instruction is used. USE: The indexed mode is used to access the array type data structure. 6.What is the role of program counter in addressing? In this addressing mode the contents of program counter is added to the address part of the instruction in order to obtain the EA. When the address part of the instruction is added to the contents of the PC the result produces the EA whose position is relative to the next instruction. 7.What are the different addressing modes? Direct addressing, indirect addressing, immediate addressing, base addressing, Index addressing,

based index addressing, based indexed with displacement addressing, relative addressing. 8.Compare the stack based architecture with GPR based architecture. Stack based Vs GPR based Reading a register in GPR architecture does not affect its contents but reading in stack architecture removes the data form top of the stack. Lot of over head involved in maintaining temporary variables in the stack. In stack based architecture the register file stack is invisible to the programmer. Only the top of the stack is visible. Hence easier to maintain compatibility with future versions. Instruction lengths are smaller in stack based because the source and destination specifies are not required. Hence the code length may be smaller Add R1, R2, [R3] Operand 9.Consider a two level indirection instruction such as Mov A, [ind], where ind points to the memory location that contains the address of the operand that needs to be moved to register A. give an application of such two level indirection. Pointer implementation is made easy with indirection. With two level indirection it is easier to handle pointer of pointer. 10.What are condition codes? Can a processor be designed without any condition codes? Condition codes are 1- bit flag that store information regarding the result of various operations. These are used in conditional branch instructions. They give elegant way of handling the conditional control flow. A processor may be designed without condition codes, but it must have some other means of handling change in flow control may be instructions like compare and branch if equal to zero. 11. Which data structures can be best supported using (a) indirect addressing mode (b) indexed addressing mode? (a) indirect addressing mode pointer data structure. (b) indexed addressing mode array data structure. 12. What are the four basic types of operations that need to be supported by an instruction set? Data transfer between memory and the processor register.

 Arithmetic and logic operations on data. Program sequencing and control. i/o transfer 13. What are the limitations of assembly languages? Limitations of assembly language: 1. Assembly language is processor dependent hence requires knowledge of internal details of processor to write a program. 2. It is less user friendly than higher level languages. 3. program development is slower than the program development using high level languages. 14. The memory unit of a computer has 256 K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a memory address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word. Total memory size = 256 K * 32 bits = 1024 Kbytes Address bits = 20 Mode field = 3 bit 2^3 = 8 >7 Register address field = 6 bits 2^6 = 64> 60 Opcode field = 32 - 20 3 6=3 bits. 15. List the steps involved in the instruction execution. Fetch the instruction from the memory. Decode the instruction. Fetch the operands from the memory for executing the instruction/ Execute the instruction. Store the results. 16. Explain the various instruction types? Instructions are of many types Data movement instruction Dyadic operations Monadic operations Comparisons and conditional jumps Procedure call instruction Loop control Input / output 17. Explain the various addressing modes. The general subject of specifying where the operands are is called addressing. Immediate addressing Direct addressing Register addressing Relative addressing

 Indirect addressing Register indirect mode Multilevel indirect addressing Indexed address mode Base register addressing mode Auto increment or auto decrement mode Implied addressing Stack addressing CHAPTER 3 UNIT 2 ---ARITHMETIC UNIT 1. Discuss the IEEE format used for representing singleprecision floating point numbers IEEE standard signal precision floating point number: Signal Precision: 32 bit 32 bit S E M Sign of 8 bit signed 23 bit mantissa/fraction Number exponent 0-signifies + excess 127 1-signifies - representation Value represented = 1.M X 2E 127 2. Discuss the principle of operation of a carry save adder. Principle of Carry save Adder Multiplication requires addition of several summands. Carry-save adder (CSA) speeds up the addition of summands. Here instead of carry rippling along the rows, they are saved and introduced into next row in correct weight position For Example 101101 (45) M x 111111 (63) Q 101101 A 101101 B 101101 C 101101 D 101101 E 101101 F 10110001011 Product(2835) 3. Define Bit slice Processor. Bit Slice ALU: It is a technique for construction an ALU from modules, each of which processes 1 bit data or slice of an operand. For Eg. Two 4 bit ALU could be arranged side by side to form an 8 bit ALU. 4. State the principles of operation of a carry look ahead adder Principles of Carry look ahead adder

Carry look ahead adder is a method for speeding up the addition process. It is done by eliminating carry delay rippling through stages. For Example Full adder Si = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi Ci+1 = YiCi + XiCi + XiYi = XiYi + (Xi+Yi)Ci = Gi + PiCi Gi = XiYi Generate function Pi = Xi + Yi Propagate functions 5. Write IEEE standard for Floating point format The IEEE standard describes the floating point representations and the way in which the four basic arithmetic operations are to be performed on these floating point operands. There are two types of representations for floating point numbers. 1. Single precision 2. Double precision 32 bit S E M Sign of 8 bit signed 23 bit mantissa/fraction Number exponent 0-signifies + excess - 127 1-signifies - representation Single precision (32 bit) Value represented = 1.M X 2E 127 Double precision Double precision representation contains 11 bits excess -1023 exponent E which has the range 1 E 2046 for normal values. This means that the actual exponent E is in range -1022 E 1023. The 53 bit mantissa provides a precision equivalent to about 16 decimal digits. 64 bit S E M Sign bit 11 Bit excess -1023 52 bit mantissa fraction Exponent 6. Define overflow Overflow: If the result of an arithmetic operation is outside the representable range, then overflow is said to occur. 7. Define Underflow If the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bits, underflow is said to occur. 8. What is the principle of Booths multiplication technique?

Skipping over of 1s Recording of multipliers such that a whenever a series of 1s occur the multiplication operation corresponding to it can be replaced by an addition of two numbers. 9. What is the purpose of guard bits used in floating point operations? The guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy in the final results. Example: In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bit including leading 1. some operations which results in extra bits are called guard bits. 10. Give the Booths recording and bit pair recording of the number. 1000111101000101. 1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0] -1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1 Bit pair recoding 1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0] -2 -1 0 -1 1 0 +1 +1 11. Draw the symbolic representation of the full adder and gibe the expression for the sum. Xi Yi Ci+1 Ci Si 12. In conforming to the IEEE standard mention any four situations under which a process sets exception flag. 1. Under flow 2. Over flow 3. Divide by Zero 4. Invalid. 13. Why floating point number is more difficult to represent and process than integer? In floating point numbers we have to represent any number in three fields sign, exponent and mantissa. The IEEE 754 standard gibes the format for these fields and according to format the numbers are to be represented. In case of any process we have to consider mantissa and exponent separately. Therefore, floating point numbers are more difficult to represent and process than integer. 14. Draw a full adder circuit and give the truth table. Inputs Outputs A B Cin Carry Sum 00000

00101 01001 01110 10001 10110 11010 11111 Truth table for full adder Cin A Sum B Block schematic of full adder 15. Give any 2 complement multiplier algorithm Robertsons algorithm Booths algorithm 16. What is spatial expansion in ALU? In this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form a single ALU capable of processing Km bit words directly. 17. What is temporal expansion in ALU? In this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform an operation on Km-bit words in K consecutive steps. In each step the ALU processes a separate m-bit slice of each operand. This processing is also called multi cycle or multi precision processing. 18. When a ALU is said to be bit sliced. An ALU is said to be bit sliced if each component ALU concurrently process a separate Slice of m bits from each Km bit operand. 19. Give the advanced features of ALU Floating point arithmetic circuit Pipelined circuit Co-processor.

Full Adder
20. What is a co-processor? A co-processor a separate instruction set processor that is closely coupled to CPU and whose instructions and registers are direct extensions of CPU. 21. What is a co-processor trap? Even if no coprocessor is present, Co-processor instructions can be included in CPU programs, because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memory location where a software routine implementing the desired coprocessor instruction is stored. This CPU generated interrupt is called a Co-processor trap. 22. Define Micro operation? A micro operation is an elementary operation performed with data stored in the register. 23. What are the types of micro operations? There are four types of micro operations. Arithmetic micro operation: performs arithmetic operations on the data stored in the register Logical micro operation: performs bit manipulation operations on the data stored in the register. Register transfer micro operation: transfers binary information from one register to another register Shift micro operation: performs shift operations on the data stored in the register CHAPTER 4 UNIT 3 ---BASIC PROCESSING UNIT 1. What are the advantages and disadvantages of hardwired and micro-programmed control? Hardwired control Advantages It is implemented using the gates, Flip Flops and hardware circuits. High speed operation and hence execution is faster Smaller implementation (component counts) Favored approach in RISC style designs. Disadvantages Complex sequencing and micro operation logic. Difficult to design and test Inflexible design Difficult to add new instructions Micro-programmed control Advantages It stores the control signals in the sequence in control memory. Modification is simple by modifying the micro program in the control memory. Just read from the control memory every clock cycle Favored approach in CISC style designs. Disadvantages Execution is slow Separate Control memory is used 2. Define hard-wired control?

Hard Wired control is a implemented with gates, f-flips decoders and other digital circuits. The goal in hard-wired design control is to minimize the number of components and maximize the speed of operation. 3. What are the relative advantages and disadvantages of micro-programmed control over hardwired control? Advantages of micro programmed control over hardware control It provides considerable flexibility in implementing instruction sets. It facilitates adding new instructions. Disadvantages Execution is slower Control memory is needed 4. Define Microinstruction The individual control words in the micro program are usually referred to as microinstruction 5. Faster operations can be achieved by pre-fetching the next micro-instruction, while the current one being executed. What are the complexities involved in perfetching the micro instruction. Whenever the status flags need to e checked to determine the next address of the micro instruction. Complex hardware is needed to handle such cases. 6. State the differences between hardwired and microprogrammed control unit. Hardwired control Micro programmed control It is implemented using the gates, Flip Flop and hardwired circuits. No control memory is used. Execution is faster. Modification is difficult. RISC Machines. It will be implemented using the micro program stored in the control memory. Control memory is used. Execution is slower. Modification is simple by modifying the micro program in the control memory. CISC Machines. 7. Why is the Wait-For-memory-Function-Completed step needed when reading from or writing to the main memory? WMFC (Wait-For-memory-Function-Completed) step is required for the write control signal/read

control single cause the memory bus interface hardware to issue a write command / read command on the memory bus. The processor wait in this process until the memory operation is completed and an WMFC response is received. 8. What are the address sequencing capabilities required in a control memory? Incrementing of the control address register. Unconditional branch as specified by address field of the microinstruction. Conditional branch depending on status bits in register of computer. A facility for sub-routines calls and returns. 9. Discuss the principle of operation of a micro programmed control unit? Microprogramming is a second alternative for designing the control unit of a digital computer. The principle of microprogramming is an elegant and systematic method for controlling the micro-operation sequences in a digital computer. 10. What are the types of control organizations we have? There are two types of control organizations Hardwired control organizations Micro programmed control organization. 11. What is a control word? A control variable which can be represented by a string of 1s and 0s is called a control word. 12. What is micro programmed control unit? A control unit whose binary control variables are stored in the memory is called a micro programmed control unit. 13. What is a micro instruction? A set of micro operations constitute a micro instruction, 14. What is a micro program? A set of micro instructions constitute a micro program. 15. What are the differences between the main memory and control memory? Main Memory Control Memory It is used storing OS routine and user Program. Ordinary user can access the main memory do modifications. This is larger in size. It is used to store the micro program. Ordinary user can not access the control memory. Only the designers can do the same.

This is smaller in size. 16. What is micro program sequencer? The next address generator is also called the micro program sequencer. This will generate the address of the next microinstruction in the sequence. 17. What is meant by mapping process? The transformation from the instruction code bits to an address in the control memory where the routine is located is referenced to as a mapping process. 18. Give the micro instruction format. F1 F2 F3 CD BR AD Where F1, F2, F3 Micro operation fields (3 bits each) CD Condition for branching (2 bits) BR Branch field (2 bits) AD Address field (7 bits). 19. What is a hard wired logic? If a computer is designed to operate based on the control gates, and other hard ware circuitry then it is called hard wired control logic. 20. What is micro programming? A technique for implementing the control function of the processor in a systematic and a flexible manner is called as micro programming. 21. What are the advantages and disadvantages of the microprogramming? Advantages An instruction set can be changed by changing the micro program. Any up gradation to the existing system require only to modify the micro programs. Less costly compared to hard wired logic. Disadvantages Comparatively slow. CHAPTER 5 UNIT 3------PIPLINING 1. What is the ideal up expected in a pipelined architecture with n stages? Justify your answer. Ideal Speedup Pipelining No. of segments k Clock cycle time tp Tasks n First task T1 requires ktp to complete its operations. (n-1) tasks (n-1) tp Total time = [k + (n-1)] tp Speedup S = ntn /(k + (n-1))tp

If n is large, k + (n-1) becomes n. Therefore S = ntn/ntp = tn/tp = k = No. of Stages (Since) 2. What is parallel processing? Parallel processing refers to the concept of speeding-up the execution of a program, by dividing the program into multiple fragments that can execute simultaneously, each on its own processor. A program being executed across n-processor might execute n-times faster than it would be using a single processor. 3. State the different types of hazard that can occur in a pipeline. Types of hazards in pipeline Structural hazards It arises from resource conflicts when the hardware cannot support all possible combination of instructions in simultaneous overlapped execution. Data hazards It arises when an instruction depends on the result of a previous instruction. Control hazards It arises from pipelining of branches and other instructions that change the program counter. 4. Define nanoprogramming. Micro instructions are stored in the micro memory (control memory). There is a chance that a group of micro instructions may occur several times in a micro program. As a result the more memory space is needed. By making use of the nano memory we can have significant saving in the memory when a group of micro operations occur several times in a micro program. These n micro instructions can be held in a separate memory called the nano memory of size nB bits. Each of these n bits occurs once in the nano memory. Each micro instruction in the original micro program is replaced by the address that specifies the location of the nano memory in which the original B bit wide micro instructions are held. The micro program control unit reads an address from the micro program. The contents of this address in the nano memory are the desired control word. The bits in the control word are used by the control unit to accomplish the desired operation. The control unit employing the nano memory (two level) is slower than the one using a conventional

control memory (single memory). This is because the nano memory requires two memory reads (one for the control memory the other for the nano memory). 5. What is pipelining? Pipelining is a technique of decomposing a sequential process in to sub processes with each sub process being executed in a special dedicated segment that operates concurrently with all other programs. 6. How do control instructions like branch, cause problems in a pipelined processor? Pipelined processor gives the best throughput for sequenced line instruction. In branch instruction, as it has to calculate the target address, whether the instruction jump from one memory location to other. In the meantime, before calculating the larger, the next sequence instructions are got into the pipelines, which are rolled back, when target is calculated. 7. What is meant by super scalar processor? Super scalar processors are designed to exploit more instruction level parallelism in user programs. This means that multiple functional units are used. With such an arrangement it is possible to start the execution of several instructions in every clock cycle. This mode of operation is called super scalar execution. 8. Define pipeline speedup. Speed up is the ratio of the average instruction time without pipelining to the average instruction time with pipelining. Average instruction time without pipelining Speedup= Average instruction time with pipelining 9. What is pipelined computer? When a hardware is divided in to a number of sub units so as to perform the sub operations in an overlapped fashion is called as a pipelined computer. 10. List the various pipelined processors. 8086, 8088, 80286, 80386. STAR 100, CRAY 1 and CYBER 205 etc. 11. Classify the pipeline computers. Based on level of processing processor pipeline, instruction pipeline, arithmetic pipelines Based on number of functions Uni-functional and multi functional pipelines. Based on the configuration Static and Dynamic pipelines and linear and non linear pipelines

 Based on type of input Scalar and vector pipelines. 12. Give the basic structure of the pipeline processor. 13. Define efficiency of a linear pipeline? Efficiency of a linear pipeline can be defined as percentage of busy time space plan over the total time space span. This is equal to sum of all busy and idle time-space spans. N = [bkT/K[kn + (n-1) T] = n/K + (n-1) Where N number of tasks. K number of pipeline stages. T clock period of linear pipeline. 14. Define reservation table of a pipeline processor. Reservation table represents the flow of data through pipeline for one complete evaluation of a given function. 15. Explain the need of an instruction buffer in a pipelined CPU.
R 1

S1 R 2 S2 R3 Sn RN In order to increase the computational speed of the pipeline processor the instructions are fetched in advance and will be placed in the instruction buffer. 16. Define arithmetic pipeline? Where it is used? A pipeline processor which is designed to perform arithmetic operations (fixed point or floating point arithmetic pipeline) is called arithmetic pipeline. An arithmetic pipeline receives multiple data as inputs and performs the designated operation on the data. Arithmetic pipelines are used in the high-speed computers where a same type of operation has to be performed repeatedly on a set of data items. 17. What is Vectorizer? The process to replace a block of sequential code by vector instructions is called vectorization. The system software, which generates parallelism, is called as vectorizing compiler. 18. Write down the expression for speedup factor in a pipelined architecture. The speedup for a pipeline computer is S = (k + n -1) tp

Where K number of segments in a pipeline N number of instructions to be executed. Tp cycle time 19. Explain the delayed branch concept. When a branch instruction is encountered it delays the pipeline operation until the instruction at the branch address is fetched. The method used in most RISC processors is to rely on the compilers to redefine the branches so that they take at proper time in the pipeline. This method is called delayed branch. 20. What are the problems faced in instruction pipeline. Resource conflicts Caused by access to the memory by two at the same time. Most of the conflicts can be resolved by using separate instruction and data memories. Data dependency Arises when an instruction depends on the results of the previous instruction but this result is not yet available. Branch difficulties Arises from branch and other instruction that change the value of PC (Program Counter). CHAPTER 6 UNIT 4 ---MEMORY SYSTEM 1. Distinguish between the write-through and write-back policies pointing out their merits and demerits. When the CPU finds a word in the cache during a read operation the main memory is not involved in the transfer however if the operation is a write, there are two ways that the system can proceed. The simplest and most commonly used procedure is to update main memory with every memory write operation with cache memory being updated in parallel if it contains the word at the specified address. This is called write-through method. This method has an advantage that main memory always contains the same data as the cache. This care is important in systems with DMA transfers. This method is simple to implement. This disadvantage is that it requires time to write data in main memory resulting in traffic. The 2nd procedure is called write-back method. In this method only the cache location is updated during a write operation. The location is then marked by a flag so that later when the block is removed from the cache, the changes are copied in to main memory. The disadvantage is that main memory may contain

inconsistent data. 2. What is the necessary of virtual memory? Virtual memory is an important concept related to memory management. It is used to increase the apparent size of main memory at a very low cost. Data are addressed in a virtual address space that can be as large as the addressing capability of CPU. 3. Define hit ratio. When a processor refers a data item from a cache, if the referenced item is in the cache, then such a reference is called Hit. If the referenced data is not in the cache, then it is called miss Hit ratio is defined as the ratio of number of Hits to number of references. Number of Hits Hit ratio = Total Number of references Number of Hits = Hits + Misses 4. What is meant by memory interleaving? Show the distribution of addresses for a memory system consisting of two banks of four 1k memory modules to form an 8k memory system. Give the man memory address format. The memory interleaving is a more effective way to address memory modules. The low order k bits of the memory address select a module, and high order m bits name a location within module. Here consecutive addresses are located in consecutive modules. M bits K bits MM Address Total memory = 8k No. of address lines = 13 Memory Bank 0 Memory Bank 1 (Capacity 1K) (Capacity 1K) Since we have 2 banks K bit = 1 (To differentiate bank 0 and bank 1) k bits For bank selection Address in Module 5. What is TLB? What is its significance? Translation look aside buffer is a small cache incorporated in memory management unit. It consists of page table entries that correspond to most recently accessed pages. Significance

The TLB enables faster address computing It contains 64 to 256 entries 6. What is virtual memory? Virtual memory is an important concept related to memory management. It is used to increase the apparent size of main memory at a very low cost. Data are addressed in a virtual address space that can be as large as the addressing capability of CPU. 7. What is the necessary for memory hierarchy? Memory hierarchy The major objective of designing memory hierarchy system is to provide adequate storage capacity with acceptable level of performance at a reasonable cost. Address in Module Module Module 1
ABR Module 0

Module 2k - 1 1k 1k 1k 1k 1k 1k 1k 1k 12 bits 1 bit 8. How cache memory is used to reduce the execution time. If active portions of the program and data are placed in a fast small memory, the average memory access time can be reduced, thus reducing the total execution time of the program. Such a fast small memory is called as cache memory. 9. Define memory interleaving. In order to carry out two or more simultaneous access to memory, the memory must be partitioned in to separate modules. The advantage of a modular memory is that it allows the interleaving i.e consecutive addresses are assigned to different memory module. 10. In many computers the cache block size is in the range 32 to 128 bytes. What would be the main advantages and disadvantages of making the size of the cache blocks larger or smaller?

Larger the size of the cache fewer be the cache misses if most of the data in the block are actually used. It will be wasteful if much of the data are not used before the cache block is moved from cache. Smaller size means more misses. 11. What is the function of a TLB? (Translation Look-aside Buffer) A small cache, called the Translation Look aside Buffer (TLB) is interporated into the memory management unit, which consists of the page table entries that corresponding to the most recently accessed paper. 12. An eight-way set-associative cache consists of a total of 256 blocks. The main memory contains 8192 blocks, each consisting of 128 words. 1. How many bits are there in the main memory address? 2. How many bits are there in the TAG, SET and WORD fields? The main memory contains of 256 blocks, and each block consists of 128 words. Total words in MM = 8192 X 128 = 1048576 To address 32768 words we required (220 = 1048576) 20 bits 13. What do you understand by Hit ratio? Hit ratio is a concept defined for any two adjacent level of a memory hierarchy. When information is found in cache we call it a hit, otherwise miss. This hit and miss ratio is used to measure the performance of cache. 14. Define locality of reference. What are its types? During the course of execution of a program memory references by the processor for both the instruction and the data tends to cluster. There are two types: 1. Spatial Locality 2. Temporal Locality 15. List the factors that determine the storage device performance. The storage device performance based on the following factors: Address reference statistics Access time storage capacity Block size Allocation algorithm 16. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? 2 (128 x 8) RAM Chips 17. What is memory system? Every computer contains several types of devices to store the instructions and data required for its

operation. These storage devices plus the algorithm-implemented by hardware and/or software-needed to manage the stored information form the memory system of computer. 18. Give the classification of memory. They can be placed into 4 groups. CPU registers Main memory Secondary memory Cache 19. Define CPU register, Main memory, Secondary memory, Cache. CPU registers: These high speed registers in the CPU serve as the working memory for temporary storage of instruction and data. Main memory: This large, fairly fast external memory stores programs and data that are in active use. Storage locations in main memory are addressed directly by CPUs load and store instruction. Secondary memory: This is larger in capacity but much slower than main memory. Secondary memory stores systems programs, larger data files that are not continuously required by CPU. Cache: Most computers have another level of IC memory-sometimes several such levels called cache memory, which is positioned logically between the CPU registers and main memory. 20. Give the multilevel hierarchy of storage devices. The goal of every memory system is to provide adequate storage capacity with an acceptable level of performance and cost. We can achieve these goals by employing several memory types with different cost/performance ratios-that are organized to provide a high average performance at a low average cost per bit. The individual memory units form a multilevel hierarchy of storage devices. 21. What is Read Access Time? A basic performance measure is the average time to read a fixed amount of information, for instance, one word, from the memory. This parameter is called the read access time. 22. Define Random Access Memory. It storage locations can be accessed in any order and access time is

independent of the location being accessed, the memory is termed a random-access memory. 23. What is Serial Access Memory? Memories whose storage locations can be accessed only in a certain predetermined sequence called serial access time. 24. What is Semi Random Access? Memory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks. If each track has its own read write head, the tracks can be accessed randomly, but access within each track is serial. In such cases the access mode is semi random. 25. What is ROM? Memories whose contents cannot be altered online if they can be altered at all are read only memories. 26. What are PROMs? Semi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs. 27. What is destructive readout? In some memories the method of reading the memories destroys the stored information, this phenomenon is called destructive read out memory. 28. What do you mean by NDRO. Memories in which reading does not affect the stored data have non destructive read out data. 29. Define memory refreshing. Memory refreshing is defined as the process of regaining the lost charge for this continuous refreshing is needed. 30. What is SRAM and DRAM? SRAM Static random access memory. It tends to be faster. They require no refreshing. DRAM Dynamic random access memory. Data is stored in the form of charges. So continuous refreshing is needed. 31. What is volatile memory? A memory is volatile if the loss of power destroys the stored information. Information can be stored indefinitely in a volatile memory by providing battery backup or other means to maintain a continuous supply of power. 32. What is cycle time of memory? The minimum time that must elapse between the start of two consecutive access operations can be

greater than Ta. this elapsed time is called the cycle time. 33. What is MTBF? Mean Time Before Failure. It is used to measure reliability. Memories with no moving parts have much higher reliability than memories such as magnetic disks. 34. Give the categories of semiconductor memories. The semi conductor memories fall into two categories. They are 1. SRAM 2. DRAM 35. What is flash memory? A recent semiconductor technology called flash memory of a same nonvolatility as a PROM, but it can be done a bit at a time. 36. Mention the causes of access a block of data in serial access memory. Long access time is due to several factors. The read-write head positioning time. The relatively slow speed at which the tracks move. The fact that the data transfer to and from the memory is serial rather than parallel. 37. How will you calculate time Tb to access a block of data in serial access memory? The time Tb taken to access the block of data is Tb = Ts + 1/2r + n/rN 38. What is a multilevel memory? A computers memory unit form a hierarchy of different memory type in which each member is in some sense subordinate to next highest member of hierarchy. 39. What is split cache? A cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is called split cache. 40. Give the basic structure of cache and what is its use? Cache and main memory form a district sub hierarchy whose design objective is to support CPU access with a minimum of delay. Hence hardware controllers that are transparent to both user and system programs usually manage this sub hierarchy. 41. What is cache data memory? Memory words are stored in cache data memory and are grouped into small pages called cache blocks or lines. The contents of the caches data memory are thus copies of a set of main memory blocks. 42. Mention two system organizations for caches. Two system organization for caches are Look aside

 Look through 43. What is associate memory? In associative memory each unit of stored information is fixed length word. Any sub field of the word can be chosen as the key. The desired key is specified by a mask register, whose contents identify the bit positions that define the key. It has a select circuit which enables the data field to be accessed. 44. Define seek time and latency time. The average time to move a head from one track is seek time (Ts) of the memory. Once the head is in position, the desired cell may be in the wrong part of the moving track. Some time is required for the cell to reach the read/write head so that data transfer can begin. The average time for this movement to take place is the latency time (T1). 45. Mention two kinds of address locality to achieve their goal. Two kinds address locality to achieve their goals are Associative addressing or content addressing. Direct mapping. 46. What is the use of magnetic tape memories in todays usage? The magnetic tape unit is one of the oldest and cheapest forms of mass memory. Its main use today is to provide backup storage for a computer system in the event of failure of its hard disk sub system. 47. What is DVD? A much denser type of CD digital video has recently been introduced in both read-only and read-write forms. With two recording surfaces and two storage layers per surface, a DVD can have a capacity as high as 16GB. 48. Define magneto optical disk. A magneto-optical disk memory uses rotating disks that store information in magnetic form but are accessed by a laser beam similar to that in a CD-ROM drive. Like a magnetic disk, a magneto optical disk has a magnetizable surface coating whose direction of magnetization can be polarized. CHAPTER 7 UNIT 5-----INPUT OUTPUT ORGANIZATION 1. Distinguish between memory mapped I/O and I/O mapped I/O. Memory mapped I/O: When I/O devices and the memory share the same address space, the arrangement is called memorymapped

I/O. The machine instructions that can access memory is used to transfer data to or from an I/O device. Bus Single-Bus Structure: For example, if DATAIN is the address of the input buffer of keyboard, the instruction. MOVE DATAIN, R0 Reads the data from DATAIN and stores them into processor register R0. Similarly if DATAOUT is the address of the output buffer of a display unit or printer, the instruction. MOVE R0, DATAOUT sends the data from R0 to location DATAOUT. I/O mapped I/O: Here the I/O devices the memories have different address space. It has special I/O instructions. The advantage of a separate I/O address space is that I/O devices deals with fewer address lines. 2. Consider a computer in which several devices are to be serviced interrupts. How do you handle this it the processor has only one request line? Daisy Chain: Consider the problem of simultaneous request from two or more devices. The processor has to decide which request to be serviced first. Polling the status register of the I/O devices is the simplest scheme. Priority is determined by the order in which devices are polled. In daisy chain scheme, interrupt request line INTR is common to all devices. The interrupt acknowledgement INTA, propagates serially through the devices. When several devices raise an interrupt request, the processor responds by setting INTA line to 1. The signal is received by device 1. Device 1 passes the signal on to device 2 only if it does not require any service. If device 1 has a pending request for interrupt, it blocks the INTA signal and proceeds to put its device identifying code on the data lines. Therefore, in daisy chain arrangement, the device that is closest to the processor has the highest priority. INTR INTA DAISY CHAIN Processor I/O Device1
Memory

I/O Device n

Processor

Device 1 Device 2 Device n

3. What is DMA? DMA (Direct Memory Access) provides I/O transfer of data directly to and from the memory unit and the peripheral. 4. Define Peripherals? Peripheral refers to any external devices connected to a computer. Computer peripherals can be divided into two categories according to their functions. I/O peripherals: Keyboard, Mouse, Video Display Unit, Printer. Storage Function: Secondary Memories, Mass Storage Device. Eg: CD, Hard disk, Magnetic disk, Magnetic tape. 5. Distinguish between a synchronous bus and an asynchronous bus. In synchronous bus both the transmitting and receiving devices use same clock for interpretation of individual bits. Synchronous buses can operate with lower latency and higher bandwith. In an asynchronous bus, the sender and the receiver generate their clock signals independently. It uses start stop bit for data transmission 1 0 Start bit 1 bit 1 or 2 Time stop bit 6. How does a processor handle an interrupt? Main program Interrupt service routine (ISR) 1. ______________________ 2. ______________________ i. ______________________ i+1 _____________________ _______________________ m______________________ Assume that an interrupt request arises during execution of instruction i. steps to handle interrupt by the processor is as follow: 1. Processor completes execution of instruction i 2. Processor saves the PC value, program status on to stack. 3. It loads the PC with starting address of ISR 4. After ISR is executed, the processor resumes the main program execution by reloading PC with (i+1)th instruction address. 7. Define dumb terminal
0

LSB

1234567 Early CRT terminals were relatively simple in their functional capability, being able to perform primitive I/O operations. Such terminals are some times called dumb terminals. 8. Why are interrupt masks provided in any processor? Interrupt masks enable the higher priority devices come first and there for lower priority devices come last. This interrupt enable bits as a bit vector is called as interrupt mark which enables/disables the devices according to the correct configuration of the mask. 9. How does bus arbitration typically work? 1. A bus master waiting to use the bus asserts the bus request 2. A bus master cannot the bus until its request is granted. 3. A bus master must signal to the arbiter the end of the bus utilization. 10. How is DMA operation? State its advantages. DMA stands for Direct Memory Access. In order to transfer bulk amount of data between memory and I/O device without involvement of CPU, this technique is used. The advantage is fast data transfer. 11. What is the necessity of an interface? Any device that has to be connected to a CPU requires an interface, which takes care of the mismatch in speed, data and electrical characteristics between the CPU to the device. 12. Why does DMA have priority over the CPU when both request a memory transfer? Since the data transfer rate using DMA is quite higher than the CPU and memory transfer rate, the DMA have priority over the CPU when both request a memory transfer. 13. Define intra segment and inter segment communication. Intra segment communication: Communication through a single computer. It can communicate through a distance of a meter only. Inter segment communication: Communication through long distance. A set of computers and connections called buses are involved. 14. Mention the group of lines in the system bus. 1. Address lines. 2. Data lines. 3. Control lines. 15. What is bus master and slave master? Input output operations involve data transfers between IO device and Memory. In all the preceding

operations Memory is passive or slave device with respect to system bus transactions. Where as the CPU can control the system bus, i.e serve as a bus master. 16. What is the use of IO controller? The magnetic disks and other secondary memory need to be connected to the system bus via interface circuits called Io controllers. That performs series to parallel and parallel to series format conversions and other control functions. It can interface many IO devices to system bus. 17. Differentiate synchronous and asynchronous communication In synchronous communication each item is transferred during the time slot know to both the source and destination. Data transfer is slow. In asynchronous communication data transfer is faster and can be used for long distance communication. Each item being transferred is accompanied by the control signals. 18. What is strobe signal? The data ready / request signals are used to load data from the source unit to the bus of from the bus to the destination unit. Such control signals are called strobe signals. 19. What is bus arbitration? The possibility exists that several master or slave units connected to a shared bus will request access to the bus at the same time. A selection mechanism called bus arbitration is therefore required to enable the current master, which we still refer to as bus controller to decide among such competing requests. 20. Mention the types of bus arbitration. Daisy chaining, Polling and Independent requesting 21. What is IO control method? It refers the data transfer between the IO device and the memory or between the IO device and the CPU. Ex: Testing the status of the device and to determine if they require service by the CPU. 22. What is DMA? The CPU and IO controller interact only when the CPU yield the control of the memory bus to the IO controller in response to the request from the latter. This level of IO control is called direct memory access and the IO device interface control circuit is called as DMA controller. 23. Why the DMA does gets priority over CPU when both request memory transfer. The CPU can wait to fetch instruction and data from the memory with out any damage occurring except that the loss of time. DMA usually transfers data from a device that cant be stopped since information

continues to flow so loss of data may occur.