Code No: B5506, B5703 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.

Tech II Semester Examinations, March/April 2011 LOW POWER VLSI DESIGN (COMMON TO EMBEDDED SYSTEMS, VLSI SYSTEM DESIGN) Time: 3hours Max. Marks: 60 Answer any five questions All questions carry equal marks --1. a) Discuss about the following issues pertaining to Low Power VLSI Design. i) Power Supply Voltage. ii)Threshold Voltage. iii) Scaling. iv) Interconnect wires. What are the advantages of SOI Technology? Explain. [8+4] Draw the structure for standard buried collector (SBC) BICMOS incorporating a buried n+ layer and a deep n+ sinker for the reduction of collector series resistance and explain the same. Draw the sketch for double diffused drain and explain about the same. [6+6] Draw the sketches to illustrate poly ridge emitter transistor (PRET), low capacitance Bipolar/ Bi CMOS process and explain about the salient features of the same. Explain about copper interconnects for deep-submicron CMOS/BI CMOS structures. [6+6] Draw the sketches and explain about the salient features of Low-Voltage/ Low-Power lateral BJT on SOI. Explain about high performance LVLP CMOS transistor structure via Poly Profile Engineering. [6+6] Explain about: i) Secondary MOSFET Behavior. ii) Threshold Variations. iii) Source/ Drain Resistances. iv) Sub-Threshold Conduction.

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Draw two input NAND gate, Full-Swing Complementary MOS/Bipolar logic gate circuits and explain their working. With the help of a schematic diagram explain about the working of an FS-M BI CMOS logic gate. [6+6] Contd..2

::2:: 7. Explain about the following themes in the evolution of latches and Flip-Flops. a) The Functionality Theme. b) The Synchronous Theme. c) The Optimization Theme. d) The Performance Theme. e) The Pipelining Theme. [12] Write notes on any TWO: a) ESD-Free BI CMOS digital circuit. b) Full-Swing Multi drain/ Multi collector complimentary Bi CMOS buffers. c) Modified Gummel Poon model. [12]

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