LB# 820-2347 Schematic Diagram (Project K50)

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
SCHEMATIC,GINSU_A(K50)
10
643852
ENGINEERING RELEASED
DATE
10/30/08 ?
D
(.csa)
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
Contents
Sync
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
(.csa)
Page
03/06/2008
Table of Contents
TABLE_TABLEOFCONTENTS_HEAD
K50
System Block Diagram
K50
Power Block Diagram
K50
3
4
BOM Configuration
10/30/2008
10/30/2008
10/30/2008
04/08/2008
10/30/2008
04/07/2008
10/30/2008
K50
Power Conn / Alias
K51
Functional / ICT Test
K50
UNUSED SIGNAL ALIAS/STAND OFF
K51
SIGNAL & GND ALIASES
K50
9
10
CPU FSB
10/30/2008
10/30/2008
10/30/2008
K50
11
CPU Power & Ground
K50
12
CPU Decoupling & VID
K50
eXtended Debug Port (XDP)
K50
13
14
MCP CPU Interface
10/30/2008
10/30/2008
10/30/2008
10/30/2008
K50
15
MCP Memory Interface
K50
MCP Memory Misc
K50
16
17
MCP PCIe Interfaces
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
K50
18
MCP Ethernet & Graphics
K50
19
MCP PCI & LPC
K50
20
MCP SATA & USB
K50
21
MCP HDA & MISC
K50
22
MCP Power & Ground
K50
Debug: CPU
K50
23
25
10/30/2008
MCP Standard Decoupling
K50
26
MCP Graphics Support

SB Misc
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
K50
29
FSB/DDR3 Vref Margining
K50
30
MEMORY COUPLING CAPS
K50
31
DDR3 SO-DIMM Connector A
K50
32
DDR3 SO-DIMM CONNECTOR B
K50
33
DDR3 Support
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
10/30/2008
K50
34
PCI-E MiniCard Connector
K50
37
Ethernet PHY (RTL8211CL)
K50
38
Ethernet & AirPort Support

39
ETHERNET CONNECTOR
K50
K50
41
FireWire LLC/PHY (FW643)
K50
42
FW: 1394B MISC
K50
43
FIREWIRE CONNECTOR
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
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Contents
54
Sync
10/30/2008
MCP CURRENT AND VOLTAGE SENSE

55
K50
10/15/2008
Thermal Sensors
56
DEREK
10/30/2008
HD AND OD FAN
57
K50
10/30/2008
CPU FAN
K50
61
10/30/2008
SPI ROM
K50
69
10/30/2008
POWER SEQUENCING BLOCK DIAGRAM
K50
70
10/30/2008
PGOOD and Power Sequencing
K50
IMVP6 CPU VCore Regulator
K50
IMVP6 3RD PHASE
K50
71
10/30/2008
72
10/30/2008
73
10/30/2008
5V_S3 REGULATOR
74
K50
10/30/2008
MCP CORE REGULATOR

75
K50
10/30/2008
1.5V DDR SUPPLY

76
K50
10/30/2008
1.05VS0/3.3V S5 SUPPLIES
K50
S3 & S0 FETs
K50
78
10/30/2008
79
10/30/2008
1V05 S5 POWER SUPPLY

80
K50
10/30/2008
1V8 POWER SUPPLY

84
K50
10/30/2008
MXM PCIe, DP & Power

85
K50
10/30/2008
MXM I/O
K50
86
10/30/2008
MXM PCIE CAPS

87
K50
10/30/2008
MXM ALIASES
89
K50
10/15/2008
LVDS MUX RESISTORS

90
SIJI
10/15/2008
INTERNAL DISPLAY CONNS

91
SIJI
10/30/2008
DP MUX SUPPORT
i
l
e
r
P
10/30/2008
K50
28
Date
93
DISPLAYPORT SUPPORT
94
DisplayPort Connector
98
MLB: AUDIO CONNECTOR
100
CPU/FSB Constraints
101
Memory Constraints
102
MCP Constraints 1
103
MCP Constraints 2
104
Ethernet Constraints
105
FireWire Constraints
106
SMC Constraints
107
GRAPHICS CONSTRAINTS
108
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
10/30/2008
K50
09/03/2008
K50
10/30/2008
K50/K51 SPECIFIC CONSTRAINTS
K50
K50/K51 RULE DEFINITIONS
K50
109
10/30/2008
K50
45
10/30/2008
SATA Connectors
K50
46
10/30/2008
EXTERNAL USB CONNECTORS
K50
47
07/09/2008
Internal USB Connections
K51
49
10/30/2008
SMC
K50
50
10/30/2008
SMC Support
K50
51
10/30/2008
LPC+SPI Debug Connector
K50
52
10/15/2008
SMBUS CONNECTIONS
DEREK
53
10/30/2008
Current & Voltage Sensing
LAST_MODIFIED=Thu Oct 30 17:51:22 2008
K50
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
X.XXX
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
TITLE
DO NOT SCALE DRAWING
SCH,K50,MLB
NONE
DRAWING
SIZE
TITLE=K51
ABBREV=DRAWING
THIRD ANGLE PROJECTION
LAST_MODIFIED=Thu Oct 30 17:51:22 2008
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-7840
DRAWING
10
SHT
OF
109
U1000
INTEL CPU
2.X OR 3.X GHZ
PENRYN
PG 10,11
U1300
PG 10
XDP CONN
PG 13
FSB
D
PG 13
y
r
a
n
i
m
il
J3100, J3200
MAIN
MEMORY
FSB INTERFACE
GPIOs
2 UDIMMs
DDR3-1067MHZ
DIMM
PG 15
PG 31,32
POWER SUPPLY
PG 55
Misc
CLK
TEMP SENSORS
MXM - GPU DIE
CPU HEATSINK
GPU HEATSINK
AMBIENT INTAKE
CPU DIE
HARD DRIVE
OPTICAL DRIVE
MCP DIE
MCP HEATSINK
LCD TEMP
64-Bit
1067 MHZ
PG 24
U6100
SYNTH
J4510
SPI
NVIDIA
J4520
PG 45
U4900
MCP79
SATA
LPC
PG 20
CTRL
DVI OUT
DP OUT
HDMI OUT
PG 18
USB
J8400
MXM CONNECTOR
X16 PCI-E
PG 84
PG 17
e
r
PCI-E
UP TO 20 LANES3
PG 90
RGMII
PCI
(UP TO FOUR PORTS)
PG 18
PG 19
FW643
PG 41
LPC+SPI CONN
Port80,serial
J4720
J4780
J4610,4620,4630,4640
J4700
Bluetooth
IR
CAMERA
PG 47
PG 47
PG 47
EXTERNAL
USB
Connectors
RGB OUT
U4100
PG 49
PWR
LVDS OUT
INTERNAL
DISP
J5100
PG 51
J9410
J9002
Fan Ser
Prt
PG 19
TMDS OUT
PG 94
ADC
B,0 BSB
SMC
U1400
DISPLAY
PORT
CONN
PG 56,57
PG 47
0 1 2 3 4 5 6 7 8 9 10 11
1.05V/3GHZ.
SATA-A1
SATA
Conn
ODD
FAN CONN AND CONTROL
PG 61
PG 20
PG 45
J5600, J5601, J5700
PG 21
(UP TO 12 DEVICES)
1.05V/3GHZ.
SATA-A0
SATA
Conn
HD
POWER PGSENSE
53
SPI
Boot ROM
SMB
DIMMs
PG 21
HDA
PG 21
INTERCONNECT PAGE 98
AUDIO BOARD
U6200
Audio
Codec
U3700
GB
E-NET
RTL8211CLGR
PG 37
U6301
U6400
U6500
System Block Diagram
U6600,6605,6610,6620
T3900
SYNC_MASTER=K50
MAGNETICS
Line In
Amp
HEADPHONE
Amp
Line Out
Amp
Speaker
Amps
SYNC_DATE=10/30/2008

PG 39

J4300
J3400
U3900
FireWire
Conn
Mini PCI-E
AirPort
PG 43
PG 34

J6800,6801,6802,6803
E-NET
Conn
SIZE
Audio
Conns
DRAWING NUMBER
PG 39
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
y
r
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il
AC/DC POWER SUPPLY
ACDC_TEMP
TEMP SENSOR
CONTROL
DCM/FCM
12V_S5
PAGE 6
PM_SLP_S3_OD
24V_S0
PP24_S0_INV
24" ONLY
PP12V_S0_HDD
PP12V_S0_INV
PP12V_S5
PP12V_S0
24" PANEL
20" PANEL
HARD DRIVE
FANS
MXM
20" INVERTER
AUDIO
FIREWIRE PORTS
PPVCORE_CPU
.95-1.25V @ 68A
PAGE 71-72
DDR3 MAIN MEMORY
PP5V_S3_REG
FET (10.3A)
PAGE 74
USB
CAMERA
IR
PPDDR_S3_REG
13A (S3 & S0)
PAGE 75
PP5V_S0
FET (6.9A)
PAGE 78
PP0V75_S0
0.75V @ 0.6A
PAGE 75
P3V3S3_EN
e
r
PP3V3_S3
3.3V @ 2.8A
PAGE 76
ETHERNET
BT
AP
FW
P3V3S0_EN
PP3V3_S0
FET (2.8A)
PAGE 78
PP1V5_S0
1.5V @ 4.9A
PAGE 78
PP1V8_S0_REG
SW (300MA)
PAGE 80
AUDIO
20" PANEL
OPTICAL
MXM
HDD
BOOT ROM
MCP
SMC
PP1V05_S0
1.05V @ 6.8A
PAGE 76
MCP_FSB (VTT)
CPU_VCCP
MCP_PLL
PM_SLP_S3
P5VS0_EN
PP3V3_S5_REG
3.3V @ 6.2A
PAGE 76
MAIN MEMORY
CPU_CORE
PP1V05_S5
1.0V @ 0.4A
PAGE 79
AUDIO
MXM
CLOCK
MCP
PP1V_S5
1.0V @ 0.08A
PAGE 42
PP1V2_S3
1.2V @ 0.2A
PAGE 38
FW
CPU_AVDD
AP PCIE
MCP79 MEM
MEM_VTT
ENET
MCP_ENET
MCP_VDD_AUXC
PPMCPCORE_S0_REG MCP_CORE
1.0-1.2V @ 17A
PAGE 74
Power Block Diagram

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
COMMON
BOM Variants
(DELETED HDCP ROM)

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
U1400
CRITICAL
MCP_B02
U4100
CRITICAL
TABLE_5_ITEM
338S0636
338S0654
IC,FW643-06,1394B, REV-E
820-2404
PCB,FAB,IO ALIGNMENT,K50/K51
IO1
CRITICAL
825-7122
MLB LABEL,48.0X4.8
X14
CRITICAL
341T0135
EFI ROM,K50/K51
U6100
CRITICAL
511S0038
CONN,INTEL SKT-P, BGA,26X26-479
U1000
CRITICAL
IC_GMCP_MCP79-B02,35X35MM, BGA1437, DT
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
630-9501
PCBA,MLB,K50,GOOD
20_INCH_LCD,2P66GHZ_CPU,BASIC,IG
630-9500
PCBA,MLB,K50,CTO
20_INCH_LCD,2P66GHZ_CPU,BASIC,MXM,MXM_PWR_SENSE,K50_BETTER,12V_PWR_SENSE
607-2695
K50 MLB DEVELOPMENT
DEVELOPMENT,XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
y
r
a
n
i
m
TABLE_5_ITEM
338S0570
U3700
CRITICAL
CRITICAL
IC,RTL8211CL,GIGE TRANSCEIVER, 48P TQFP
K50 PARTS
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
TABLE_5_ITEM
051-7577
PCB,SCHEM,MLB,K50
SCH1
20_INCH_LCD
820-2347
PCB,FAB,MLB,K50,HF
MLB1
20_INCH_LCD
(338S0563 - BLNK) 341T0132
IC,SMC,K50
U4900
114S0305
RES,7.87K,0402,1%,1/16W,LF
R7117
20_INCH_LCD
132S0205
CAP,CER,270PF,10%,50V,0402
C7113
20_INCH_LCD
132S0178
CAP,CER,0.47UF,10%,6.3V,0402
C7128
20_INCH_LCD
TABLE_5_ITEM
TABLE_5_ITEM
BOM GROUPS
CRITICAL
20_INCH_LCD
TABLE_5_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
BASIC
COMMON,ALTERNATE,MCP_TDIODE,MCP79,CPUV_PHASE3,XDP,CPU_TDIODE,MCP_B02
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
MCP79
BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCP
TABLE_5_ITEM
132S0082
C
CPUS
TABLE_5_HEAD
PART#
QTY
CRITICAL
BOM OPTION
IC,PDC,QJTC,QS,2.66,55W,1066,E0,6M,PGA
CPU
CRITICAL
2P66GHZ_CPU
DESCRIPTION
IC,PDC,QJEX,QS,2.8,55W,1066,E0,6M,PGA
CPU
CRITICAL
2P8GHZ_CPU
IC,PDC,QJTF,QS,2.93,55W,1066,E0,6M,PGA
CPU
CRITICAL
2P93GHZ_CPU
IC,PDC,QJTJ,QS,3.06,55W,1066,E0,6M,PGA
CPU
CRITICAL
3P06GHZ_CPU
TABLE_5_ITEM
337S3698
337S3699
337S3700
337S3701
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
i
l
e
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P
BOARD STACK-UP
B
TOP
2
3
4
5
6
7
BOTTOM
SIGNAL
GROUND
SIGNAL
POWER
POWER
SIGNAL
GROUND
SIGNAL
CAP,CER,0.068UF,10%,10V,0402
C7134
20_INCH_LCD
ALTERNATES
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
516S0657
988-2127
BOM OPTION
REF DES
COMMENTS:
J3100,J3200
CONN,RCPT,SO-DIMM,DDR3,R/A,204P,LF (NON-HF)
TABLE_ALT_ITEM
BOM Configuration
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
"S0" RAILS
1
PP3V3_S0
ON IN RUN AND SLEEP
APN: 518-0338
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
90D1
53B5
LCD_PWM
PP12V_S0_INPUT
C627
0.001UF
10%
50V
2 X7R
402
1%
1/16W
MF-LF
2 402
M-RT-TH
1
10
11
12
C623
10UF
10%
16V
2 X5R-CERM
1210
20%
10V
2 X5R
805
C629
0.001UF
87D5 8D3 90A3 90C4
10%
50V
2 X7R
402
2N7002
PM_SLPS3_BUF2_L
SOT23-HF1
PP1V05_S0_REG
MAKE_BASE=TRUE
VOLTAGE=1.05V
C630
10%
50V
X7R
402
54D6 54C5 7D3 70A8
=PP1V05_S0_MCP_FSB
=PP1V05_S0_CPU
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_HDMI_VDD_R
PP1V5_S0
=PP1V5_S0_CPU
=PP1V5_S0_MINI
=PP1V8R1V5_S0_MCP_MEM
MAKE_BASE=TRUE
VOLTAGE=1.5V
C
7D3 6D4 6B7 78D1
PP3V3_S3
DEVELOPMENT
1
R600
1K
80C3 7D3
5%
1/16W
MF-LF
2 402
PP1V8_S0_REG
=PP3V3R1V8_S0_MCP_IFP_VDD_R
=PP1V8_S0_PGCMP
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=GND
MAX_NECK_LENGTH=4.1 MM
ITS_ALIVE
1 DEVELOPMENT
LED605
GREEN-3.6MCD
2.0X1.25MM-SM
7D3 6D7 6B8 78C1 53C3
38C8 7C3 6D2 76C1 38B7
7D3 6D4 6C8 78D1
PP3V3_S5_REG
R602
R601
1K
1K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
CORE_VOLTAGES_ON_R
ITS_PLUGGED_IN
1
1
LED602
LED601
2
GREEN-3.6MCD
2.0X1.25MM-SM
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:2
CORE_VOLTAGES_ON
SILKSCREEN:1
Q602
2N7002
7C4 7C3 7B4 70D3 70B1
IN
ALL_SYS_PWRGD_R 1
SOT23-HF1
P
2
PP3V3_S0
7D3 6D7 6B6 78C1 53C3
MXM
1
R604
1K
5%
1/16W
MF-LF
2 402
90C5 90A8 90A6
GPU_PRESENT_R
1
R603
3.3K
5%
1/10W
MF-LF
2 603
GREEN-3.6MCD
2.0X1.25MM-SM
9D6
IN
Q604
SOT23-HF1
PP5V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
LED603
2N7002
MXM_GOOD
7D3 78D5 70A8
3 MXM
e
r
LCD_SHOULD_ON
SILKSCREEN:3
GPU_PRESENT_DRAIN
PPV_LCD_CONN
MXM
LED604
2
PP3V3_S0
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S3
GREEN-3.6MCD
2.0X1.25MM-SM
MAKE_BASE=TRUE
VOLTAGE=1.5V
NET_SPACING_TYPE=PPDDR_MEM
78A4
53D8 11B5 11D6 12D7 53B6
PPVTT_S3_DDR_BUF
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET
=PPDDR_S3_S0FET
=PPDDR_S3_PGCMP
=PPVTT_S3_DDR_BUF
108D3 31A5 31D7

79C3 7C3 38C6
PP1V05_S5_REG
=PP1V05_S5_MCP_VDD_AUXC
=PP3V3_S0_FAN
=PP3V3_S0_MCP
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_MCP_GPIO
=PP3V3R1V5_S0_MCP_HDA
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_IMVP
=PP3V3_S0_AUDIO
=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS
=PP3V3_S0_SMC_LS
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_MGMT
=PP3V3_S0_DPCONN
=PP3V3_S0_TSENS
=PP3V3_S0_MXM
=PP3V3_S0_XDP
=PP3V3_S0_ODD
=PP3V3_S0_SATALED
=PP3V3_S0_SMC
=PP3V3_S0_PWRCTL
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_VIDEO
=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO
=PP5V_S0_SATA
=PP5V_S0_MXM
=PP5V_S0_IMVP
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_1V8
7D3 6C8 6B7 78D1
PP3V3_S3
33C6
78B6
70B8
29D3
38C8 7C3 6B8 76C1 38B7
MAKE_BASE=TRUE
VOLTAGE=3.3V
22D5 25D8
14A2 14B7 22D3 23C3 25C8
10D5 11C6 12B3 13D6 50C2
=PP3V3_S3_MINI
=PP3V3_S3_BT
=PP3V3_S3_VREFMRGN
=PP3V3_FW_FWPHY
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_SMC
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_MCPREG
PP3V3_S5_REG
=PP3V3_S5_MCP
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_SMC
=PP3V3_S5_ROM
=PP3V3_S5_RTC_D
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMBUS_SMC_BSA
=PP3V3_S5_FAN
=PP3V3_S5_SMCUSBMUX
=PP3V3_S5_MEMRESET
=PP3V3_S5_P1V05S5
=PP3V3_S5_PWRCTL
=PP3V3_S5_S3FET
=PP3V3_S5_S0FET
MAKE_BASE=TRUE
VOLTAGE=3.3V
34D2
47D4
29D8
42C8 41B1 41D2 42B7 43A5 43B8

21A3
50B5
52D3
74D7
25D4
25D8 28D4
7D3 73C1
PP5V_S3_REG
MAKE_BASE=TRUE
VOLTAGE=5V
25C4
28C2 20B6
26D8
=PP5V_S3_BNDI
=PP5V_S3_DDRREG
=PP5V_S3_USB
=PP5V_S3_VTTCLAMP
=PP5V_S3_PWRCTL
=PP5V_S3_S0FET
=PP5V_S3_MCPREG
47B4 47D8
51C8 61C6
28D7
7D4 51C3 51C8 51D5
52D3
56B7 56D7 57D7
46D6
33C6
79C6
70A3 70B1 70B3 70C1 70D8
78D4
78C4
70D8 78B7
78D7
7C3 76C4
PP5V_S5_LDO
=PP5V_S5_AVREF
50B8
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
74D7
PP12V_S5
=PP12V_S5_FW
=PPVIN_S5_DDRREG
=PPVIN_S5_P3V3S5
=PPVIN_S5_P5VS3
=PP12V_S5_REG
=PP12V_S5_PWRCTL
MAKE_BASE=TRUE
VOLTAGE=12V
43D8
75C4
76D4
73D4 73D5
76D5
70B8
26D8
70A8
56B7 56C7 57C7
21C2 22B3 25B8

26C7
18C1 19D1 21A4
25B6
21D3 21D8 25A8

31A8
32A8
71D8
98C4 98C6
51C3
52C8 52D8
50A8 50B4 50C2

52D5
52C5
52C3
94A6 94B8 94C4 94D7
55A5 55B8 55D4
85A6 84D2 84D8 85C2

13D6
45C5
45D3
50C1 53D5 54D6
70B4
55C4
90D6
7D4 51D5
98C4 98C6
6D6 45C6
84D5
71D8 72D7
Power Conn / Alias
93C5 93C7
80C5
SYNC_MASTER=K51

53B4 53B3 7D3 70B8
PP12V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
=PP12V_S0_FAN
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_CPU
=PPV_S0_MXM_PWR
=PPVIN_S0_P1V05S0
=PPV_S0_LCD_24INCH
=PPVIN_S0_MCPCORE

56C6 56D7 57D6
98C6
53B8 71D8 72D7
53D4
76C8
SIZE
90C8
DRAWING NUMBER
74D4
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
49D4 50D1 50D7
78A4
SILKSCREEN:4
18C7 20C1
46C8 46D8
53C4 53B5 7C3
34C2
22B3 25B8
75C7
11B6 12B3
16C3 16C7 25C8 30B7 30C7
22A3 25D8
MAKE_BASE=TRUE
VOLTAGE=1.05V
108D3 32A5 32D7
y
r
a
n
i
m
il
=PPVCORE_S0_MCP
EMC: C600,C626,C627,C628,C629,C630,C631
PLACE AT J600.
PPDDR_S3_REG
32A4
MAKE_BASE=TRUE
VOLTAGE=0.75V
MAKE_BASE=TRUE
VOLTAGE=1.05V
C631
7D3 75C1
31A4
7D3 75C8
74B8 PPMCPCORE_S0_REG
10%
50V
2 X7R
402
0.001UF
=PPVCORE_S0_CPU
6A4 45C6
0.001UF
C600
Q610
IN
50C3
PM_SLP_S3_OD
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
MAKE_BASE=TRUE
VOLTAGE=1.25V
7D3 76C8
PPVCORE_CPU
0.001UF
10%
50V
2 X7R
402
70C8 50C3 49C5 9D6
7D3 72C1 71D1
74C7 54B5 7D3 74D1
10UF
PPVTT_S0_DDR_LDO
MAKE_BASE=TRUE
VOLTAGE=0.75V
VOLTAGE=12V
PP12V_S5_INPUT 53C5
ACDC_TEMP
LVDS_BKL_ON
=PP5V_S0_SATA
C624
VOLTAGE=0V
7D3 75C8
1.5K
76755-0012
0.001UF
R610
J600
C626
10%
50V
2 X7R
402
10%
50V
2 X7R
402
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
C628
0.001UF
PP12V_S0_INPUT PROPERTIES
1
"S5" RAILS
"S3" RAILS
ONLY ON IN RUN
7D3 6B8 6B6 78C1 53C3
10
OF
109
FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

LAYOUT NOTE: PLACE NEAR J1000
FSB_A_L<6>
FSB_ADSTB_L<0>
FSB_A_L<27>
FSB_ADSTB_L<1>
FSB_D_L<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
FSB_D_L<16>
FSB_DSTB_L_P<1>
FSB_D_L<41>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
FSB_D_L<59>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
CPU_INIT_L
CPU_A20M_L
CPU_IGNNE_L
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_CLK_CPU_P
FSB_CLK_CPU_N
100C3 14D6 10D8 7D7

100C3 14B6 10D8 7D7
100C3 14C6 10C8 7D7
100C3 14B6 10C8 7D7
100D3 14D3 10C4 7D7
100D3 14D6 10C4 7D7
100D3 14D6 10C4 7D7
100D3 14D3 10C4 7D7
100D3 14D6 10B4 7D7

100D3 14C3 10C2 7D7
100D3 14D6 10C2 7D7
100D3 14D6 10C2 7D7
100D3 14B3 10B2 7D7
100D3 14D6 10B2 7D7
100D3 14D6 10B2 7D7
10D6 100B3 14A3
10C8 100C3 14A3
10C8 100B3 14A3
10C8 100B3 14A3
10C8 100B3 14A3
10B8 100B3 14A3
10B8 100B3 14A3
100C3 14B6 10D8 7C7
100C3 14B6 10D8 7C7
100C3 14B6 10D8 7C7
100C3 14B6 10D8 7C7
100C3 14B6 10D8 7C7
10B6 100B3 14B3
10B6 7B3 100B3 14B3
1
PP1000 SM
PP
1
PP1001 SM
PP
1
PP1002 SM
PP
1
PP1003 SM
PP
1
PP1004 SM
PP
1
PP1006 SM
PP
1
SM
PP1007 PP
1
PP1008 SM
PP
1
PP1010 SM
PP
1
PP1012 SM
PP
1
PP1013 SM
PP
1
PP1015 SM
PP
1
PP1016 SM
PP
1
SM
PP1017 PP
1
PP1019 SM
PP
1
PP1022 SM
PP
1
PP1023 SM
PP
1
PP1024 SM
PP
1
PP1025 SM
PP
1
PP1026 SM
PP
1
SM
PP1027 PP
1
PP1028 SM
PP
1
PP1029 SM
PP
1
PP1030 SM
PP
1
PP1031 SM
PP
1
PP1032 SM
PP
1
PP1033 SM
PP
1
PP1034 SM
PP
1
PP1035 SM
PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
LAYOUT NOTE: PLACE NEAR U1400

100C3 14D6 10D8 7D8
100C3 14B6 10D8 7D8
100C3 14C6 10C8 7D8
100C3 14B6 10C8 7D8
100D3 14D3 10C4 7D8
100D3 14D6 10C4 7D8
100D3 14D6 10C4 7D8
100D3 14D3 10C4 7D8
100D3 14D6 10B4 7D8
100D3 14C3 10C2 7D8
100D3 14D6 10C2 7D8
100D3 14D6 10C2 7D8
100D3 14B3 10B2 7D8
100D3 14D6 10B2 7D8
100D3 14D6 10B2 7D8
14B6 100C3 10D6
100C3 14B6 10D6
100C3 14B6 10D6
100C3 14B6 10D6
100C3 23C3 14B6 10D6
100C3 14B6 10D6
10B2 100B3 14A3
100C3 14B6 10D8 7C8
100C3 14B6 10D8 7C8
100C3 14B6 10D8 7C8
100C3 14B6 10D8 7C8
100C3 14B6 10D8 7C8
70A3 7C4 71C7
FSB_A_L<6>
FSB_ADSTB_L<0>
FSB_A_L<27>
FSB_ADSTB_L<1>
FSB_D_L<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
FSB_D_L<16>
FSB_DSTB_L_P<1>
FSB_D_L<41>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
FSB_D_L<59>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
FSB_LOCK_L
FSB_HIT_L
FSB_HITM_L
FSB_BNR_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DPWR_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
VR_PWRGOOD_DELAY
1
PP1400 SM
1
PP1401 SM
1
PP1402 SM
1
PP1403 SM
1
PP1404 SM
1
PP1406 SM
SM
PP1407 1
1
PP1408 SM
1
PP1410 SM
1
PP1412 SM
1
PP1413 SM
1
PP1415 SM
1
PP1416 SM
SM
PP1417 1
1
PP1419 SM
1
PP1420 SM
1
PP1421 SM
1
PP1422 SM
1
PP1423 SM
1
PP1424 SM
SM
PP1425 1
1
PP1426 SM
1
PP1427 SM
1
PP1428 SM
1
PP1429 SM
1
PP1430 SM
1
PP1431 SM
1
PP1434 SM
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
37B7 18C3
1
PP3704 SM
PP
ENET_RESET_L
41C2 102C3 17C3

41C2 102C3 17C3
41C3 102D3
41C3 102D3
41A2 7B3 9C2
101D3 31B4 15B7
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
101D3 31C4 15C7

101C3 31B7 15D7
101C3 31A7 15D7
101C3 31C4 15D5
101C3 31B2 15D5
101C3 31C4 15D5
101C3 31B7 15D5
101C3 31B5 15D5
101B3 31B7 15D5
101B3 32C4 15B3
101B3 32C4 15B3
101B3 32B4 15C3
101B3 32C4 15C3
101A3 32B7 15C3
101A3 32A5 15D3
101D1 32B2 15D1
P4MM
101D1 32C4 15D1

101D1 32B7 15D1
101D1 32B5 15D1
101D1 32B5 15D1

101D1 32B7 15D1
101D1 32A5 15D1
9C6 102D3 86C1
9C6 102D3 86C1
MEM_A_DQ<7>
MEM_A_DQ<14>
MEM_A_DQ<16>
MEM_A_DQ<25>
MEM_A_DQ<47>
MEM_A_DQ<59>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<6>
MEM_B_DQ<6>
MEM_B_DQ<8>
MEM_B_DQ<23>
MEM_B_DQ<25>
MEM_B_DQ<38>
MEM_B_DQ<62>
MEM_B_DQS_P<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<7>
PEG_D2R_P<7>
PEG_D2R_N<7>
SC0700
EMI-SPRING
SC0701
EMI-SPRING
CLIP-SM1
103D3 51D5 49C8 19B3
IN
P4MM
103D3 51D5 49C8 19B3 7D6 7B8
IN
OMIT
P4MM
OMIT
103D3 51D4 49C8 19B3
IN
103D3 51D4 49C8 19B3
IN
FW_RESET_L
1
PP4004 SM
PP
OMIT
51D5 49C8 103D3 19C3
IN
19B7 51D5 49C5 7C8
IN
50D3 49B5 51D5
IN
51D5 9D2
IN
51C5 49C1
IN
50D3 51D5 49B5
IN
49C1 51C5
IN
51C5 50D3 49C5 49B8 46D5
IN
51D4 49C8 19B7
IN
7D4 103D3 51D5 49C8 19B3 7B8
SDF0727
NUT-6.5OD1.8H-1.56-3.8-TH
1
PP1442 SM
1
PP1443 SM
1
PP1444 SM
1
PP1445 SM
1
PP1447 SM
1
PP1449 SM
SM
PP1452 1
1
PP1454 SM
1
PP1456 SM
1
PP1458 SM
1
PP1460 SM
1
PP1463 SM
1
PP1466 SM
SM
PP1467 1
1
PP1468 SM
1
PP1469 SM
1
PP1470 SM
1
PP1473 SM
1
PP1478 SM
1
PP1481 SM
SM
PP1483 1
1
PP1484 SM
1
PP1485 SM
1
PP1486 SM
1
PP1489 SM
1
PP1490 SM
1
PP1491 SM
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
OMIT
P4MM
e
r
ZH0711
5R3P5-6B
1
ZH0712
4P25R3P5
1
OMIT
OMIT
ZH0713
4P25R3P5
1
OMIT
OMIT
OMIT
ZH0730
ZH0700
ZH0701
ZH0702
ZH0703
4R3P25
4R3P25
4R3P25
4R3P25
4P75R4
4P75R4
4P75R4
4P75R4
ZH0714
4P25R3P5
1
OMIT
ZH0715
4P25R3P5
1
FUNC_TEST=TRUE
6D6 72C1 71D1
IN
FUNC_TEST=TRUE
74C7 54B5 6D6 74D1 74B8
IN
FUNC_TEST=TRUE
6D6 76C8
IN
FUNC_TEST=TRUE
54D6 54C5 6C6 70A8
IN
FUNC_TEST=TRUE
80C3 6C6
IN
6D7 6B8 6B6 78C1 53C3
IN
FUNC_TEST=TRUE
6A6 78D5 70A8
IN
FUNC_TEST=TRUE
53B4 53B3 6A6 70B8
IN
PPVTT_S0_DDR_LDO
PPVCORE_CPU
PPMCPCORE_S0_REG
PP1V05_S0_REG
PP1V5_S0
PP1V8_S0_REG
FUNC_TEST=TRUE
PP3V3_S0
PP5V_S0
PP12V_S0
FUNC_TEST=TRUE
50D3 49B5 51D4
IN
50D3 49B5 51D4
IN
49C3 51C4 50D6 7D6
IN
IN
50D3 49C5 49B8 51C4 46D5
IN
51D4 49C5 19C3
IN
51C4 18B7
IN
51D4 51A8
IN
51D4 51C8
IN
51D5 51A8
IN
51A8 51D5
IN
IN
7C3 7B4 6B7 70D3 70B1
IN
71C7 49D8
IN
70A3 71C7 7C7
IN
ZH520
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH501
FUNC_TEST=TRUE
HOLE-VIA
ZH511
ZH521
HOLE-VIA
FUNC_TEST=TRUE
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH502
HOLE-VIA
ZH512
ZH522
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
"S3" RAILS
4 TPS
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
6D4 75C1
IN
FUNC_TEST=TRUE
6D4 75C8
IN
6D4 6C8 6B7 78D1
IN
6C4 73C1
IN
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PPDDR_S3_REG
PPVTT_S3_DDR_BUF
PP3V3_S3
PP5V_S3_REG
ZH503
HOLE-VIA
ZH513
ZH523
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH504
HOLE-VIA
ZH514
ZH524
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
"S5" RAILS
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
79C3 6D2 38C6
IN
FUNC_TEST=TRUE
38C8 6D2 6B8 76C1 38B7
IN
FUNC_TEST=TRUE
6C2 76C4
IN
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=16
53C4 53B5 6C2
IN
28B8 49B8 7C8
IN
50D7
IN
7C4 7B4 6B7 70D3 70B1
IN
3 TPS
PP1V05_S5_REG
PP3V3_S5_REG
PP5V_S5_LDO
PP12V_S5
PM_SYSRST_L
SMC_MANUAL_RST_L
ALL_SYS_PWRGD_R
ZH505
HOLE-VIA
ZH515
ZH525
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH506
HOLE-VIA
1
ZH516
FUNC_TEST=TRUE
ZH526
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
ZH507
HOLE-VIA
ZH517
ZH527
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PWROK SEQUENCING
ALL_SYS_PWRGD_R
FUNC_TEST=TRUE
IMVP_VR_ON
VR_PWRGOOD_DELAY
ZH510
HOLE-VIA
FUNC_TEST=TRUE
ZH508
HOLE-VIA
ZH518
ZH528
HOLE-VIA
HOLE-VIA
ZH509
HOLE-VIA
ZH519
ZH529
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
102C3 87C5 9C6
IN
10B6 100B3 14B3 7C8
IN
19D7 19D2 103D3
IN
19D7 19D2 103D3
IN
860-0895
SDF0717
STDOFF-7P0OD15P0H-TH
998-0847
OMIT
ZH0718
4P25R3P5
1
9D7 102B3 21C3
IN
70D8 50C3 49C5 38D7 102B3 21C3
IN
7C4 7C3 6B7 70D3 70B1
IN
13C7 10B2 100B3 14A3
IN
PM_SLP_S3_L
PM_SLP_S4_L
ALL_SYS_PWRGD_R
CPU_PWRGD
FUNC_TEST=TRUE
41B2
IN
FUNC_TEST=TRUE
41B2
IN
FUNC_TEST=TRUE
41B2
IN
FUNC_TEST=TRUE
41B2
IN
41B6
IN
41B6
IN
41B6
IN
41A6
IN
IN
GPU_CLK100M_PCIE_N
FSB_CLK_CPU_N
FUNC_TEST=TRUE
PCI_REQ0_L
PCI_REQ1_L
FUNC_TEST=TRUE
TP_FW643_TCK
TP_FW643_TMS
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_SM
TP_FW643_SE
TP_FW643_NAND_TREE
TP_FW643_CE
FUNC_TEST=TRUE
FW_RESET_L
FUNC_TEST=TRUE
ZH536
FUNC_TEST=TRUE
HOLE-VIA
1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH531
HOLE-VIA
ZH534
ZH537
HOLE-VIA
HOLE-VIA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
ZH532
HOLE-VIA
ZH535
HOLE-VIA
FUNC_TEST=TRUE
XDP CONNECTOR
ZH0725
OMIT
IN
41A2 9C2 7D6
998-0850
OMIT
6D6 75C8
SHUTDOWN/SLEEP TIMING
CRITICAL
998-0847
P4MM
ZH0723
A
OMIT
OMIT
P4MM
OMIT
P4MM
OMIT
ZH0722
HOLE-VIA
FUNC_TEST=TRUE
FOR ICT
P
OMIT
ZH500
FUNC_TEST=TRUE
STARTUP (BOOT/WAKE) TIMING
998-0846 FOR MCP HEATSINK

OMIT
OMIT
P4MM
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_CLK33M_LPCPLUS
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
LPC_SERIRQ
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPC_PWRDWN_L
LPCPLUS_GPIO
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MOSI
SPI_ALT_MISO
SPIROM_USE_MLB
GND
16 TPS
y
r
a
n
i
m
il
1
PP4901 SM
PP
1
PP4902 SM
PP
1
PP4903 SM
PP
SMC_LRESET_L
SMC_RESET_L
LPC_AD<1>
P4MM
CLIP-SM-K2
CRITICAL
SDF0726
P4MM
49C1 51C4
SC0702
835-0266
NUT-6.5OD1.8H-1.56-3.8-TH
IN
1
PP4002 SM
PP
1
PP4003 SM
PP
EMI-SPRING
CLIP-SM1
CRITICAL
51D4 103D3 9B2
PCIE_FW_R2D_P
PCIE_FW_R2D_N
49C8 9D2
CRITICAL
BTW DIMMS
CRITICAL
IN
51D4 51C7
101D3 31C2 15B7
1
PP2105 SM
PP
1
PP2106 SM
PP
1
PP2132 SM
PP
1
PP2133 SM
PP
1
PP2113 SM
PP
1
PP2114 SM
PP
1
PP4904 SM
PP
1
SM
PP4905 PP
1
PP2119 SM
PP
1
PP2120 SM
PP
1
PP2121 SM
PP
1
PP2122 SM
PP
1
PP2123 SM
PP
1
PP2126 SM
PP
1
SM
PP2127 PP
1
PP2128 SM
PP
1
PP2129 SM
PP
IN
51D5 6A4
OMIT
P4MM
OMIT
P4MM
101D3 31C4 15B7
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
17B6 102C3 41C1 PCIE_FW_D2R_P
17B6 102C3 41C1 PCIE_FW_D2R_N
28B8 7C3 49B8 PM_SYSRST_L
19B7 7D4 51D5 49C5 PM_CLKRUN_L
SATA_ODD_D2R_P
20D6 102B3 45C5
SATA_ODD_D2R_N
20D6 102B3 45C5
20D6 102C3 45C5 SATA_HDD_D2R_P
20D6 102C3 45D5 SATA_HDD_D2R_N
51D5 49C8 19B3 7D6 LPC_AD<1>
7D4 103D3
103C3 47B7 20D3 USB_CAMERA_P
103C3 47B7 20D3 USB_CAMERA_N
47D4 103C3 20D3 USB_BT_P
47D4 103C3 20C3 USB_BT_N
61C6 51A6 103B3 21B3 SPI_CLK_R
21B3 103B3 61B2 51A6 SPI_MISO
51D5 51C8 51C3 6D1
1
PP4000 SM
PP
1
PP4001 SM
PP
17B6 102D3 34C8
10 TPS
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
49C3 7D4 51C4 50D6
MISC GROUND VIAS
"S0" RAILS
P4MM
17B6 102D3 34C8
LPC CONNECTOR
OMIT
OMIT
ZH0720
4P25R3P5
1
100A3 13C6 10C6 10C5
IN
13C6
IN
13C6
IN
13C6
IN
13C6
IN
13C6
IN
13C6
IN
13C6
IN
13C6 19C4
IN
52D8 106D3 21C3 13B6
IN
52D8 106D3 21C3 13B6
IN
19D7 13C3
IN
13C3 100B3 14B3
IN
13C3 100B3 14B3
IN
13C4 100A3
IN
28B8 13B3 10C6
IN
10C6 10A6 100A3 13B3
IN
10C6 10B6 100A3 13B3
IN
10C6 10B6 100A3 13B3
IN
13B3 10B6 100A3 10C6
IN
10C6 10A6 100A3 13B6
IN
21B7 13C3
IN
21B7 13C3
IN
21B7 13B6
IN
13C3 21B7
IN
21B7 13C3
IN
XDP_BPM_L<5..0>
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP_PWRGD
PM_LATRIGGER_L
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
MCP_DEBUG<0..7>
FSB_CLK_ITP_P
FSB_CLK_ITP_N
XDP_CPURST_L
XDP_DBRESET_L
XDP_TRST_L
XDP_TDI
XDP_TMS
XDP_TDO
XDP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TCK
JTAG_MCP_TDO
JTAG_MCP_TRST_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
Functional / ICT Test
FUNC_TEST=TRUE
FUNC_TEST=TRUE
SYNC_MASTER=K50
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
998-1608

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
18C6
MCP_TV_DAC_RSET
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
NO_TEST=TRUE
18C6
MCP_TV_DAC_VREF
NC_MCP_TV_DAC_VREF
18C6
MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
18C6
MCP_CLK27M_XTALOUT
18C3
CRT_IG_R_C_PR
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE
NO_TEST=TRUE
18C3
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
18C3
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB
18C3
CRT_IG_HSYNC
NC_CRT_IG_HSYNC
18C3
CRT_IG_VSYNC
18C3
TP_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
18C3
NO_TEST=TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_VSYNC
19C7
TP_PCI_AD<31..15>
NC_PCI_AD<31..15>
19D4
TP_PCI_IRDY_L
NC_PCI_IRDY_L
19D4
TP_PCI_C_BE_L<1..0>
NC_PCI_C_BE_L<1..0>
19D4
TP_PCI_SERR_L
NC_PCI_SERR_L
19D4
TP_PCI_DEVSEL_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_DEVSEL_L
MAKE_BASE=TRUE
19D4
TP_PCI_PERR_L
19B7
TP_LPC_DRQ0_L
NO_TEST=TRUE
NC_PCI_PERR_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LPC_DRQ0_L
MAKE_BASE=TRUE
TP_MCP_BUF_SIO_CLK
NC_MCP_BUF_SIO_CLK
16D6
TP_MEM_A_ODT<3..2>
NC_MEM_A_ODT<3..2>
16D6 16C6
TP_MEM_A_CKE<3..2>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_CKE<3..2>
MAKE_BASE=TRUE
TP_MEM_A_CS_L<3..2>
NO_TEST=TRUE
NC_MEM_A_CS_L<3..2>
MAKE_BASE=TRUE
15B5
TP_MEM_A_CLK2P
NC_MEM_A_CLK2P
15B5
TP_MEM_A_CLK2N
NC_MEM_A_CLK2N
16D6
TP_MEM_A_CLK3P
NC_MEM_A_CLK3P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_MEM_A_CLK3N
NC_MEM_A_CLK3N
TP_MEM_A_CLK4P
NC_MEM_A_CLK4P
16D6
TP_MEM_A_CLK4N
16D6
TP_MEM_A_CLK5P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_CLK4N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_CLK5P
MAKE_BASE=TRUE
NC_MEM_A_CLK5N
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_MEM_B_CS_L<3..2>
NC_MEM_B_CS_L<3..2>
16D3
TP_MEM_B_ODT<3..2>
16D3 16C3
TP_MEM_B_CKE<3..2>
NC_MEM_B_CKE<3..2>
MAKE_BASE=TRUE
NO_TEST=TRUE
15B1
TP_MEM_B_CLK2P
NC_MEM_B_CLK2P
NO_TEST=TRUE
15B1
TP_MEM_B_CLK2N
NC_MEM_B_CLK2N
16D3
TP_MEM_B_CLK3P
NC_MEM_B_CLK3P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_ODT<3..2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
16D3
16D3
MAKE_BASE=TRUE
NC_MEM_B_CLK3N
MAKE_BASE=TRUE
TP_MEM_B_CLK4P
NC_MEM_B_CLK4P
MAKE_BASE=TRUE
TP_MEM_B_CLK4N
NC_MEM_B_CLK4N
MAKE_BASE=TRUE
16D3
16D3
TP_MEM_B_CLK5P
NC_MEM_B_CLK5P
MAKE_BASE=TRUE
TP_MEM_B_CLK5N
21D7
TP_MLB_RAM_SIZE
NC_MEM_B_CLK5N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_GPIO_18
MAKE_BASE=TRUE
TP_PCI_C_BE_L<3>
NC_PCI_C_BE_L<3>
19C4
TP_PCI_CLK0
NC_PCI_CLK0
19C4
TP_PCI_CLK1
NC_PCI_CLK1
19D4
TP_PCI_FRAME_L
19D4
TP_PCI_GNT0_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_PCI_GNT1_L
NC_PCI_GNT1_L
19C7
TP_PCI_INTW_L
NC_PCI_INTW_L
19C7
TP_PCI_INTX_L
NC_PCI_INTX_L
19C7
TP_PCI_INTY_L
NC_PCI_INTY_L
19C7
TP_PCI_INTZ_L
NC_PCI_INTZ_L
19D4
TP_PCI_PAR
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
TP_USB_TPAD_N
MAKE_BASE=TRUE
TP_USB_TPAD_P
MAKE_BASE=TRUE
MCP HAS INTERNAL 15K PULL-DOWNS
20D3
USB_TPAD_N
20D3
USB_TPAD_P
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
UNUSED MEMORY SIGNALS
NO_TEST=TRUE
NO_TEST=TRUE
31D5
MEM_A_A<15>
TP_MEM_A_A<15>
32D5
MEM_B_A<15>
TP_MEM_B_A_<15>
NO_TEST=TRUE
NC_PCI_TRDY_L
17C3
TP_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4N
17C3
TP_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
TESTPOINT FOR OPTIONAL GMUX JTAG FROM MCP
NC_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE5N
MAKE_BASE=TRUE
17B3
17B3
17C6
PCIE_EXCARD_PRSNT_L
NC_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
e
r
MAKE_BASE=TRUE
17C6
TP_PE4_CLKREQ_L
NC_PE4_CLKREQ_L
17C6
TP_PE4_PRSNT_L
NC_PE4_PRSNT_L
21C7
TP_SB_A20GATE
20C3
TP_USB_10N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SB_A20GATE
MAKE_BASE=TRUE
NC_USB_10N
MAKE_BASE=TRUE
NC_USB_10P
MAKE_BASE=TRUE
NC_USB_11N
MAKE_BASE=TRUE
20C3
TP_USB_11P
NC_USB_11P
20C3
USB_EXCARD_N
NC_USB_EXCARD_N
20C3
USB_EXCARD_P
NC_USB_EXCARD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17B6
GMUX_JTAG_TCK_L
17B6
GMUX_JTAG_TDO
19D4
GMUX_JTAG_TDI
19D4
GMUX_JTAG_TMS
NC_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GMUX_JTAG_TDO
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_GMUX_JTAG_TDI
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_GMUX_JTAG_TMS
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
K51 ONLY STANDOFFS
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
CRITICAL
CRITICAL
860-0895
860-0895
SDF0800
SDF0801
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_ODD_PWR_EN_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_P
17C3
PCIE_CLK100M_EXCARD_N
17C6
EXCARD_CLKREQ_L
NC_EXCARD_CLKREQ_L
19D7
TP_PCI_AD<12..10>
NC_PCI_AD<12..10>
19D7
TP_PCI_AD<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
UNUSED SIGNAL ALIAS/STAND OFF
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
17C3
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCI_TRDY_L
NO_TEST=TRUE
MAKE_BASE=TRUE
UNUSED INTERNAL USB PORTS
NO_TEST=TRUE
19C7
NO_TEST=TRUE
IN
NO_TEST=TRUE
NC_PCI_STOP_L
ODD_PWR_EN_L
LVDS_BKL_ON
NO_TEST=TRUE
TP_PCI_STOP_L
21B3
TP_VR_PWRGD_CLKEN_L
MAKE_BASE=TRUE
90C4 90A3 6D6 87D5
19D4
NO_TEST=TRUE
VR_PWRGD_CLKEN_L
71C7
NC_PCI_RESET1_L
MAKE_BASE=TRUE
TP_USB_11N
TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_PCI_RESET1_L
20C3
TP_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
NO_TEST=TRUE
19C4
TP_USB_10P
PCIE_EXCARD_R2D_C_N
NO_TEST=TRUE
NC_MCP_PCI_GNT0_L
19D4
20C3
PCIE_EXCARD_R2D_C_P
17B3
TP_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
NC_PCI_FRAME_L
MAKE_BASE=TRUE
17B3
TP_PCIE_EXCARD_D2R_P
y
r
a
n
i
m
il
19D4
MAKE_BASE=TRUE
17B6
PCIE_EXCARD_D2R_N
NO_TEST=TRUE
NC_MLB_RAM_SIZE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_MEM_B_CLK3N
TP_MCP_GPIO_18
NO_TEST=TRUE
16D3
16D3
17B6
PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
NC_MCP_KBDRSTIN_L
MAKE_BASE=TRUE
17B6
NO_TEST=TRUE
NC_ENET_PWDWN_L
MAKE_BASE=TRUE
NO_TEST=TRUE
16D6
TP_MEM_A_CLK5N
TP_MCP_KBDRSTIN_L
17B3
NO_TEST=TRUE
16D6
16D6
21C7
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_ENET_PWRDWN_L
NO_TEST=TRUE
21B3
16D6
18C3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_ENET_INTR_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_ENET_INTR_L
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_MCP_RGB_VSYNC
18C6
NO_TEST=TRUE
MAKE_BASE=TRUE
TESTPOINT ALIAS FOR UNUSED NETS
NC ON UNUSED ALIASES
MAKE_BASE=TRUE
NO_TEST=TRUE
SYNC_MASTER=K51
NC_PCI_AD<8>
MAKE_BASE=TRUE
NO_TEST=TRUE

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
SIGNAL ALIAS
CPU_PSI_L
21D7
TP_MLB_RAM_VENDOR
71C7
MAKE_BASE=TRUE
LPC Reset (Unbuffered)
MXM_GOOD
6A8
MAKE_BASE=TRUE
R981
103D3 19C3
R910
7B4 102B3 21C3
PM_SLP_S3_L
15
PM_SLPS3_BUF2_L
6C8 49C5 50C3 70C8
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
15
5%
1/16W
MF-LF
402
IN
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
33
1
PM_SLPS3_BUF1_L
73A6 94D7
MAKE_BASE=TRUE
1
R912
100K
5%
1/16W
MF-LF
OUT
7D4 51D5
SMC_LRESET_L
OUT
7D6 49C8
FW_RESET_L
OUT
7D6 7B3 41A2
MINI_RESET_L
OUT
34C3
PEG_RESET_L
OUT
87C5 90D4
PCA9557D_RESET_L
OUT
29A5
y
r
a
n
i
m
il
R983
33
DEBUG_RESET_L
2
5%
1/16W
MF-LF
402
(P50 HAS A 100K TO GROUND)
R911
1
Platform Reset Connections
IMVP6_PSI_L
10B2
5%
1/16W
MF-LF
402
PCIE Reset (Unbuffered)
2 402
R992
17B3
PEG Slot Support
IN
PCIE_RESET_L
R991
0
17C3
IN
GPU_CLK100M_PCIE_P
MAKE_BASE=TRUE
17C3
IN
PEG_CLK100M_N
17D3 17C3
IN
=PEG_R2D_C_P<0..15>
IN
=PEG_R2D_C_N<0..15>
17D6 17C6
OUT
=PEG_D2R_P<0..15>
17D6 17C6
OUT
=PEG_D2R_N<0..15>
17C6
IN
PEG_PRSNT_L
18B6
IN
=MCP_HDMI_TXC_P
18B6
IN
=MCP_HDMI_TXC_N
18B6
IN
=MCP_HDMI_TXD_P<0..2>
18B6
IN
=MCP_HDMI_TXD_N<0..2>
18A3
IN
=MCP_HDMI_DDC_CLK
BI
=MCP_HDMI_DDC_DATA
OUT
=MCP_HDMI_HPD
17D3 17C3
PEG_CLK100M_P
GPU_CLK100M_PCIE_N
MAKE_BASE=TRUE
PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
PEG_D2R_P<0..15>
MAKE_BASE=TRUE
PEG_D2R_N<0..15>
MAKE_BASE=TRUE
MXM_DETECT_L
MAKE_BASE=TRUE
OUT
87C5 102C3
OUT
87C5 102C3 7C3
OUT
102D3 86A7 86B7 86C7 86D7
OUT
102D3 86A7 86B7 86C7 86D7
7B7 86A1 86B1 86C1 86D1 102D3
IN
7B7 86A1 86B1 86C1 86D1 102D3
OUT
85B6 85B3
OUT
107D2 91C4
OUT
107D2 91D4
OUT
107D2 91B7 91B8 91C8
DisplayPort / TMDS Support
18A3
18B6
DP_IG_ML_P<3>
MAKE_BASE=TRUE
DP_IG_ML_N<3>
MAKE_BASE=TRUE
DP_IG_ML_P<2..0>
MAKE_BASE=TRUE
DP_IG_ML_N<2..0>
MAKE_BASE=TRUE
DP_IG_DDC_CLK
MAKE_BASE=TRUE
DP_IG_DDC_DATA
DP_IG_HPD
MAKE_BASE=TRUE
R972
107D2 91B8 91C8 91D8
OUT
93C8
IN
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
19C4
OUT
BI
MAKE_BASE=TRUE
R990
5%
1/16W
MF-LF
402
R971
IN
5%
1/16W
MF-LF
402
93D8
91B4
33
MEM_VTT_EN_R
IN
DDRVTT_EN
OUT
75C8 78A4
5%
1/16W
MF-LF
402
NO STUFF
C973
0.47UF
R900
18B6
=DVI_HPD_GMUX_INT
HPLUG_DET2
MAKE_BASE=TRUE
20K
5%
1/16W
MF-LF
402
e
r
MCP79 PCIe PRSNT# Straps
PCIE_FW_PRSNT_L
PCIE_MINI_PRSNT_L
OUT
17C6
OUT
17C6
USB ALIAS
70D8
IN
PGOOD_5V_S3
PM_EN_USB_PWR
OUT
R925
103D3 19B3
IN
LPC_CLK33M_SMC_R
33
LPC_CLK33M_SMC
OUT
103D3 49C8
LPC_CLK33M_LPCPLUS
OUT
103D3 7D4 51D4
PM_CLK32K_SUSCLK
OUT
103D3 49C5
R926
33
5%
1/16W
MF-LF
402
R929
103D3 21B3
IN
22
PM_CLK32K_SUSCLK_R
1
2
5%
1/16W
MF-LF
402
MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP

R930
21B3
IN
22
MCP_CPUVDD_EN
1
MCP_CPU_VLD
OUT
21B7
5%
1/16W
MF-LF
402
SIGNAL & GND ALIASES
46C8
18D6
=MCP_MII_RXER
18D6
=MCP_MII_COL
MCP_MII_NU
SYNC_MASTER=K50
MAKE_BASE=TRUE
18D6
=MCP_MII_CRS
GND RAILS
GND_AUDIO_SPKRAMP
5%
1/16W
MF-LF
402
GROUND ALIAS
98D6
10%
6.3V
CERM-X5R
402

1
R955

47K
5%
1/16W
MF-LF
2 402

GND
VOLTAGE=0V
SIZE
MAKE_BASE=TRUE
MAX_NECK_LENGTH=4.1 MM
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
OMIT
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14B6 7D8 7D7
BI
100C3 14B6 7C8 7C7
BI
100C3 14B6 7C8 7C7
BI
100C3 14B6 7C8 7C7
BI
100C3 14B6 7C8 7C7
BI
100C3 14B6 7C8 7C7
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
100C3 14C6
BI
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6 7D8 7D7
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14C6
BI
100C3 14B6 7D8 7D7
BI
100C3 14A3 7D8

14B7 100B3
100B3 14A3 7D8
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
CPU_A20M_L
OUT CPU_FERR_L
IN CPU_IGNNE_L
IN
100B3 14A3 7D8
IN
100B3 14A3 7D8
IN
100B3 14A3 7D8
IN
100B3 14A3 7C8
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
23B7 TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
BGA-SKT-P
1 OF 4
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
G5
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
DEFER*
DRDY*
DBSY*
H5
E1
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
BR0*
F1
FSB_BREQ0_L
F21
BI
7D7 14B6 100C3
BI
14B3 100C3
BI
14B3 100C3
BI
14B6 100C3
BI
7D7 14B6 100C3
BI
7D7 14B6 23C3 100C3
D20 100A3 CPU_IERR_L

B3
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
HIT*
HITM*
G6
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
F4
G3
G2
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
=PP1V05_S0_CPU
R1000 1
54.9
1%
1/16W
MF-LF
402
7D8 14A3 100B3
14A3 23C3 100C3 13C2
IN
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
7D7 100C3 14B6
IN
14A6 100C3
IN
14A6 100C3
IN
14A6 100C3
IN
14B6 100C3
BI
7D7 14B6 100C3
BI
7D7 14B6 100C3
BI
100A3 7B4 13C6
BI
100A3 7B4 13C6
BI
100A3 7B4 13C6
BI
13C6 100A3 7B4
BI
R1001 1
1%
1/16W
MF-LF
402
13C6 100A3 7B4
BI
IN
IN
13B3 100A3 7A4 10B6
OUT
100A3 7A4 10B6 13B3
IN
13B3 100A3 7A4 10B6
IN
13B3 100A3 7A4 10A6
OUT
13B3 7A4 28B8
R1002 1
THERMTRIP*
55D4 108D3
OUT
55D4 108D3
C7
PM_THRMTRIP_L
OUT
50B1 100B3 14B7
A24
100D3 14D3
BI
OUT
BI
100D3 14D3
BI
100D3 14D3
BI
100D3 14D3
14B6 50B3 100B3
A21
FSB_CLK_CPU_P
FSB_CLK_CPU_N
7C8 14B3 100B3
IN
7C8 14B3 100B3 7B3
IN
BI
100D3 14D3
BI
BI
100D3 14D3
BI
100D3 14D3
BI
e
r
1K
CPU JTAG Support
R1090
10C6 7A4 100A3 13B3
XDP_TMS
10C6 7A4 100A3 13B3
XDP_TDI
XDP_TDO
P
13B3 7A4 100A3 10C6
10C6 7A4 100A3 13B3
XDP_TCK
XDP_TRST_L
R1006
2.0K
R1092
54.9
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
10C6 7A4 100A3 13B6
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R1091
54.9
54.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
BI
100D3 14D3
BI
100D3 14D6
BI
100D3 14D6 7D8 7D7
BI
100D3 14D6 7D8 7D7
BI
100D3 14D3 7D8 7D7
BI
100D3 14D3
BI
R1094
649
54.9
1%
1/16W
MF-LF
402
BI
100D3 14D3
BI
100D3 14D3
BI
100D3 14C3
BI
BI
100D3 14C3
BI
100D3 14C3
BI
BI
100D3 14C3
BI
100D3 14C3
BI
100D3 14C3
BI
100D3 14C3
BI
100D3 14C3
BI
100D3 14C3
BI
100D3 14D6
BI
100D3 14D6 7D8 7D7
BI
100D3 14D6
BI
NO STUFF
C1014
NO STUFF
10%
16V
X5R
402
R1010
1
0
5%
1/16W
MF-LF
402
R1011 1
1K
NO STUFF
1
23C7
23C7
23B7
E22
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
BGA-SKT-P
2 OF 4
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
7D7 7D8 14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14C3 100D3
BI
14B3 100D3
BI
7D7 7D8 14D6 100D3
BI
14D6 100D3
BI
7D7 7D8 14D6 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
7D7 7D8 14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
14B3 100D3
BI
7D7 7D8 14D6 100D3
BI
14D6 100D3
BI
7D7 7D8 14D6 100D3
R26 100A3 CPU_COMP<0>

U26 100A3 CPU_COMP<1>
AA1 100A3 CPU_COMP<2>
Y1
E5
B5
D24
D6
D7
AE6
100A3
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
IN
14A3 100B3 71C7
IN
14A3 100B3
IN
7C7 14A3 100B3
IN
14A3 100B3 7B4 13C7
IN
OUT
R1023 1
R1021 1
54.9
1%
1/16W
MF-LF
402
54.9
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
14A3 100B3
9D7
R1022
R1020
27.4
R1012
1K
5%
1/16W
MF-LF
402 2
0.1uF
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
OUT CPU_BSEL<0>
OUT CPU_BSEL<1>
OUT CPU_BSEL<2>
100A3 29B2
NO STUFF
R1093
BI
100D3 14D3
100D3 14C3
R1005
BI
100D3 14D3
100D3 14C3
BI
100D3 14D3
100D3 14D3
A22
BI
100D3 14D3
100D3 14D3
H CLK
BCLK0
BCLK1
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
OUT
B25
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
BI
100D3 14D3
5%
1/16W
MF-LF
402
D21
100D3 14D3 7D8 7D7
100D3 14D3
54.9
13C6 100A3 7B4
13B6 100A3 7A4 10A6
y
r
a
n
i
m
il
OMIT
THERMAL
PROCHOT*
THERMDA
THERMDC
6D4 11C6 12B3 13D6 50C2
IERR*
INIT*
F3
14B6 100C3
BI
68
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
H1
E2
DATA GRP 2
BI
ADS*
BNR*
BPRI*
PENRYN
DATA GRP 3
BI
100C3 14C6
M3
U1000
DATA GRP 0
100C3 14D6
K5
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
DATA GRP 1
BI
L4
CONTROL
100C3 14D6
L5
XDP/ITP SIGNALS
BI
J4
ADDR GROUP0
BI
100C3 14D6 7D8 7D7
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
100C3 14D6
ICH
BI
100C3 14D6
RESERVED
100C3 14D6
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
27.4
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
PLACEMENT_NOTE (all 4 resistors):
1%
1/16W
MF-LF
402
Place within 12.7mm of CPU
CPU FSB
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
10
109
A4
P6
A8
(CPU CORE POWER)
P21
OMIT
A11
=PPVCORE_S0_CPU
A7
AB20
A9
OMIT
AB7
U1000
AC7
A10
A12
3 OF 4
AC15
A18
AC17
A20
AC18
B7
AD7
B9
AD9
B10
AD10
B12
AD12
B14
AD14
B15
AD15
B17
AD17
B18
AD18
VCC
AE10
AE12
C12
AE13
C13
AE15
C15
AE17
C17
AE18
C18
AE20
AF10
D12
AF12
D14
AF14
D15
AF15
VCC
D17
AF17
D18
AF18
E7
AF20
E12
V6
E13
J6
E15
K6
E17
M6
E18
J21
E20
K21
F7
M21
VCCP
F12
R21
F14
R6
F15
T21
F17
T6
F18
V21
F20
W21
4500 mA (before VCC stable)

2500 mA (after VCC stable)
VCCA
C26
6C4 12B3
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
130 mA
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
VCCSENSE
AB15
AB17
AB18
VSSSENSE
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
AE7
CPU_VCCSENSE_P
CPU_VCCSENSE_N
12C2
OUT
12C2
OUT
12C2
OUT
12C2
OUT
12C2
OUT
12C2
OUT
12C2
P
AF7
e
r
(CPU INTERNAL PLL POWER 1.5V)
B26
AA10
R5
BGA-SKT-P
A19
R22
4 OF 4
A23
R25
AF2
T1
=PPVCORE_S0_CPU
R1100
100
1%
1/16W
MF-LF
402
OUT
y
r
a
n
i
m
il
B8
T23
T26
B13
U3
B16
U6
B19
U21
B21
U24
B24
V2
C5
V5
C8
V22
C11
V25
C14
W1
C16
W4
C19
W23
C2
W26
Y3
Y6
D1
Y21
D4
Y24
D8
AA2
AA5
D13
AA8
D16
AA11
D19
AA14
D23
AA16
D26
AA19
E3
AA22
E6
AA25
E8
AB1
E11
AB4
VSS
AB11
AB13
E21
AB16
E24
AB19
F5
AB23
F8
AB26
F11
AC3
F13
AC6
F16
AC8
F19
AC11
F2
AC14
F22
AC16
F25
AC19
G4
AC21
G1
AC24
AD2
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
J2
AD19
J5
AD22
J22
AD25
J25
AE1
K1
100A3 71A3
AE8
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
R1101
M22
AF8
100
M25
AF11
N1
AF13
1%
1/16W
MF-LF
402
N4
AF16
N23
AF19
N26
AF21
P3
B1
AE4
K4
100A3 71A3
AB8
E19
G26
6D4 53D8 11D6 12D7 53B6
VSS
E16
G23
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
OUT
T4
B11
E14
6D4 10D5 12B3 13D6 50C2
=PP1V5_S0_CPU
(BR1#)
AA9
(CPU IO POWER 1.05V)
N6
F10
P24
R2
D11
N21
F9
PENRYN
C25
G21
E10
A16
C22
=PP1V05_S0_CPU
E9
A14
U1000
B6
AF9
D10
AA7
Design Target)
HFM)
LFM)
Design Target)
AE9
C9
C10
D9
(SV
(SV
(SV
(LV
AC13
A17
B20
A
A
A
A
AC12
BGA-SKT-P
A15
44
41
30.4
23
AC9
PENRYN
A13
6D4 53D8 11B5 12D7 53B6
A25
(Socket-P KEY)
AF25
CPU Power & Ground

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
REV.
051-7840
10
OF
11
109
CPU VCORE HF AND BULK DECOUPLING

6X 220UF. 32X 22UF 0805
53B6 11D6 11B5 53D8 6D4
=PPVCORE_S0_CPU
y
r
a
n
i
m
il
NOTE: CHANGED TO X5R CAPS TO MATCH PREVIOUS IMACS AND FOR C4
LAYOUT NOTE:
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
NOSTUFF
C1200
C1201
C1202
C1203
C1204
C1205
22UF
22UF
22UF
22UF
22UF
22UF
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
LAYOUT NOTE:
1
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
C1210
C1211
C1212
C1213
C1214
C1215
22UF
22UF
22UF
22UF
22UF
22UF
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
C
LAYOUT NOTE:
1
PLACE NEAR SOCKET NORTH SIDE (ON TOPSIDE)
C1220
C1221
NOSTUFF
C1222
NOSTUFF
C1223
NOSTUFF
C1224
C1206
C1207
C1208
22UF
22UF
22UF
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
C1216
C1217
C1218
C1219
22UF
22UF
22UF
22UF
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
CPU VCORE VID CONNECTIONS
C1209
22UF
11B6
CPU_VID<0>
IMVP6_VID<0>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<1>
IMVP6_VID<1>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<2>
IMVP6_VID<2>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<3>
IMVP6_VID<3>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<4>
IMVP6_VID<4>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<5>
IMVP6_VID<5>
MAKE_BASE=TRUE
100A3 71C7
11B6
CPU_VID<6>
IMVP6_VID<6>
MAKE_BASE=TRUE
100A3 71C7
NOSTUFF
C1225
22UF
22UF
22UF
22UF
22UF
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
22UF
20%
6.3V
CERM-X5R
805
C1226
C1227
C1228
C1229
C1230
C1231
VCCA (CPU AVdd) DECOUPLING
LAYOUT NOTE:
PLACE NEAR SOCKET SOUTH SIDE (ON TOPSIDE)
22UF
2
NOSTUFF
22UF
20%
6.3V
CERM-X5R
805
22UF
20%
6.3V
CERM-X5R
805
22UF
20%
6.3V
CERM-X5R
805
B
LAYOUT NOTE:
CRITICAL
1 NOSTUFF
CRITICAL
1
C1250
PLACE ON BOTTOMSIDE
2
LAYOUT NOTE:
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1254
C1255
CRITICAL
C1252
220UF-0.007OHM
220UF-0.007OHM
20%
2V
POLY
CASE-D2-SM
20%
2V
POLY
CASE-D2-SM
20%
2V
POLY
CASE-D2-SM
P
C1260
C1261
C1262
C1263
10%
16V
CERM
402
LAYOUT NOTE:
PLACE C1281 NEAR PIN B26 OF U1000
C1253
220UF-0.007OHM
C1281
LAYOUT NOTE:
20%
2V
POLY
CASE-D2-SM
PLACE ON BOTTOMSIDE
=PP1V05_S0_CPU
1X 330UF, 6X 0.1UF 0402

C1235
330UF
C1264
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
6.3V
ELEC
6.3X8-SM-HF
C1265
20%
10V
CERM
402
CRITICAL 1
0.1UF
CRITICAL
50C2 13D6 11C6 10D5 6D4
20%
10V
CERM
402
VCCP (CPU I/O) DECOUPLING
0.1UF
0.01UF
20%
6.3V
X5R
603
220UF-0.007OHM
10uF
20%
2V
POLY
CASE-D2-SM
1x 10uF, 1x 0.01uF
C1280
220UF-0.007OHM
2
=PP1V5_S0_CPU
20%
6.3V
CERM-X5R
805
e
r
CRITICAL
C1251
22UF
20%
6.3V
CERM-X5R
805
11B6 6C4
20%
2V
POLY
CASE-D2-SM
NOSTUFF
220UF-0.007OHM
PLACE NEAR MCP
NOSTUFF
C1236
C1237
C1238
C1239
C1240
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C1241
0.1UF
20%
10V
CERM
402
LAYOUT NOTE:
PLACE C1235 CLOSE TO CPU
CPU Decoupling & VID

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
12
109
y
r
a
n
i
m
il
MCP79-specific pinout
6B4
50C2 12B3 11C6 10D5 6D4
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP_CONN
XDP
R1315 1
CRITICAL
J1300
54.9
1%
1/16W
MF-LF
402 2
7B4 100A3 10C5
BI
7B4 100A3 10C6
BI
F-ST-SM
XDP_BPM_L<5>
XDP_BPM_L<4>
BI
7B4 100A3 10C6
LTH-030-01-G-D-A-TR
2
OBSFN_A0
OBSFN_A1
OBSDATA_A0
OBSDATA_A1
10
12
11
14
13
16
15
7B4 100A3 10C6
IN
7B4 100A3 10C6
IN
7B4 100A3 10C6
IN
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
7B4
7B4
7B4
7B4
7B4
XDP
7B4
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
OBSDATA_B3
R1399
10B2 7B4 100B3 14A3
IN
CPU_PWRGD
1K
7B4
XDP_PWRGD
XDP_OBS20
5%
1/16W
MF-LF
402
7A4 19C4
IN
21B7 7A4
OUT
52D8 7A4 106D3 21C3
BI
52D8 7A4 106D3 21C3
BI
10C6 10A6 7A4 100A3
OUT
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
XDP_TCK
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
NC
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
e
r
OBSDATA_C0
OBSDATA_C1
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
19D7 7A4
BI
19D7 7A4
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
19D7 7A4
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
7A4 21B7
OUT
7A4 21B7
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
19D7 7A4
BI
19D7 7A4
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
19D7 7A4
BI
19D7 7A4
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
7A4 100A3 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
IN
21B7 7A4
OUT
7A4 21B7
BI
19D7 7A4
IN
14B3 100B3 7A4
IN
14B3 100B3 7A4
XDP
R1303
OUT
10C6 7A4 28B8
IN
10C6 100A3 7A4 10B6
OUT
100A3 7A4 10A6 10C6
OUT
100A3 7A4 10B6 10C6
OUT
100A3 7A4 10B6 10C6
1K
5%
1/16W
MF-LF
402
FSB_CPURST_L
IN
14A3 23C3 100C3 10D6
PLACEMENT_NOTE=Place close to CPU to minimize stub.
XDP_PRESENT#
XDP
0.1uF
10%
16V
X5R
402
JTAG_MCP_TDO
JTAG_MCP_TRST_L
XDP
C1300
OBSFN_C0
OBSFN_C1
C1301
0.1uF
10%
16V
X5R
402
eXtended Debug Port (XDP)

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
13
109
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
BI
100D3 10C4
BI
100D3 10C4 7D8 7D7
BI
100D3 10B4 7D8 7D7
BI
100D3 10B4
BI
100D3 10B4
BI
100D3 10C2
BI
100D3 10C2 7D8 7D7
BI
100D3 10C2 7D8 7D7
BI
100D3 10B2
BI
100D3 10B2 7D8 7D7
BI
100D3 10B2 7D8 7D7
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8 7D8 7D7
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10D8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8 7D8 7D7

100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
BI
100C3 10C8
100C3 10C8
100C3 10D8 7D8 7D7

100C3 10C8 7D8 7D7
100C3 10D8 7C8 7C7
25C8 23C3 22D3 14A2 6D4
=PP1V05_S0_MCP_FSB
R1410 1
B
100B3 50B1 10C6
IN
100B3 10C8
IN
R1415 1
54.9
62
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BI
100C3 10D8 7C8 7C7
R1416
5%
1/16W
MF-LF
402
100C3 10D6 7D7
100C3 23C3 10D6 7D7
100C3 10D6 7D7
10D6 100C3
23B5
IN
23C5
IN
23C5
IN
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NO STUFF
P
1
R1422
1K
5%
1/16W
MF-LF
402
R1430
R1435
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
N37
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_ADS_L
FSB_BNR_L
BI
FSB_BREQ0_L
BI
100C3 FSB_BREQ1_L
FSB_DBSY_L
BI
FSB_DRDY_L
BI
FSB_HIT_L
BI
FSB_HITM_L
BI
FSB_LOCK_L
IN
FSB_TRDY_L
OUT
23B5
OUT
100B3 50B3 10C5
OUT
CPU_PECI_MCP
CPU_PROCHOT_L
V41
W37
V35
L36
N35
10D6 100C3
OUT
10D6 100C3
OUT
10D6 100C3
OUT
25C2
M41
J41
AC34
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35
AE36
AK35
AC38
AA33
AC39
AC33
AC35
AD42
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
E41
AJ41
AG43
AH40
F42
100B3
D42
F41
49.9
1%
1/16W
MF-LF
402
CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
BI
7D7 7D8 10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
CPU_ADSTB0#
CPU_ADSTB1#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_BPRI#
CPU_DEFER#
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
AA41
AA40
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
G42
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
AL43
BCLK_OUT_NB_P
BCLK_OUT_NB_N
AL41
100B3
AK42
100B3
BCLK_IN_N
BCLK_IN_P
AK41
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
AF41
CPU_PWRGD
CPU_RESET#
AH43
G41
AL42
BI
7D7 7D8 10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10C4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10B4 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
7D7 7D8 10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10C2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
7D7 7D8 10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
BI
10B2 100D3
FSB_BPRI_L
FSB_DEFER_L
OUT
10D6 100C3
OUT
10D6 100C3
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
7C8 100B3 10B6
OUT
7C8 100B3 7B3 10B6
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
100B3 7A4 13C3
OUT
100B3 7A4 13C3
FSB_CLK_MCP_P
FSB_CLK_MCP_N
Loop-back clock for delay matching.
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
AC41
AB41
AC42
CPU_RS0#
CPU_RS1#
CPU_RS2#
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
100B3
CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#
y
r
a
n
i
m
il
M39
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
100B3
1%
1/16W
MF-LF
402
W39
U40
206
20
29
15
mA
mA
mA
mA
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AG27
AH27
AG28
AH28
AM39
AM40
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AM43
AM42
R1436
49.9
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
BI
100B3
R1431 1
T40
e
r
100C3 10D6
100C3 10D6 7D7
R1421 1
BI
100C3 10D8 7C8 7C7
100C3 10D6 7D7
NO STUFF
BI
BI
100C3 10D6
1K
BI
BI
100C3 10D6 7D7
R1420 1
BI
100C3 10D8 7C8 7C7
PM_THRMTRIP_L
CPU_FERR_L
NO STUFF
BI
100C3 10D8 7C8 7C7
62
BI
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
FSB
100D3 10C4 7D8 7D7
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AJ40
AH39
AH42
AF42
AG41
AH41
H38
AM33
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
7D8 100C3 10C8
OUT
7D8 100B3 10C8
OUT
7D8 100B3 10D6
OUT
7D8 100B3 10C8
OUT
7D8 100B3 10B8
OUT
7C8 100B3 10B8
=PP1V05_S0_MCP_FSB
R1440
150
OUT
MCP CPU Interface
5%
1/16W
MF-LF
402
OUT
OUT
6D4 14B7 22D3 23C3 25C8
NO STUFF
1
SYNC_MASTER=K50
100B3 7B4 10B2 13C7
23C3 100C3 10D6 13C2

100B3 10B2
OUT
100B3 10B2
OUT
7C7 100B3 10B2
OUT
7D8 100B3 10C8
OUT
100B3 10B2 71C7

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
REV.
051-7840
10
OF
14
109
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
101C3 31A5
BI
101C3 31B7
BI
101C3 31A7 7C7
BI
101C3 31A7
BI
101C3 31B5
BI
101C3 31B5
BI
101C3 31B5
BI
101C3 31B7
BI
101C3 31B5
BI
101C3 31B7
BI
101C3 31B7
BI
101C3 31B5
BI
101C3 31B7
BI
101C3 31B5
BI
101C3 31B7 7C7
BI
101C3 31B7
BI
101C3 31B7
BI
101C3 31B7
BI
101C3 31B5
BI
101C3 31B5
BI
101C3 31B5
BI
BI
101C3 31B7
BI
101C3 31C5
BI
101C3 31B5
BI
101C3 31B5
BI
101C3 31B7
BI
101C3 31B7
BI
101C3 31C7
BI
101D3 31C2
BI
101D3 31C4
BI
101D3 31C2
BI
101D3 31C2
BI
101D3 31C2
BI
101D3 31C4
101D3 31C4 7C7
101D3 31C4
BI
BI
BI
101D3 31B4
BI
101D3 31B2
BI
101D3 31C4
BI
101D3 31C4
BI
101D3 31B2
BI
101D3 31C2
BI
101D3 31C2
BI
101D3 31B4 7C7
BI
101D3 31C4
BI
101D3 31C2 7C7
BI
101D3 31C2
BI
101C3 31B5
101C3 31B5
BI
101C3 31A7
BI
101D3 31C4
BI
101D3 31C2
BI
101D3 31C4
BI
101D3 31C2
BI
101D3 31C4
BI
101D3 31C4 7C7
BI
101D3 31C4
BI
101D3 31D2
BI
101D3 31D2
BI
101D3 31C2
BI
101D3 31C2
BI
101D3 31D4
BI
101D3 31D4
BI
31A7 101C3
OUT
31B5 101C3
OUT
31B7 101C3
OUT
31B5 101C3
OUT
31C2 101C3
OUT
31B4 101C3
OUT
31C2 101C3
OUT
31C4 101C3
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
101C3 31A5
OMIT
U1400
MRAS0#
MCAS0#
MWE0#
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
AV17
AP17
AR17
BI
31A5 101B3
101A3 32A5
BI
BI
31A5 101B3
101A3 32A5 7B7
BI
BI
31B7 101B3
101A3 32B7
BI
7B7 31B7 101B3
101A3 32A7
BI
BI
7B7 31B5 101C3
101A3 32A7
BI
BI
31B5 101C3
101A3 32A7
BI
BI
7B7 31B7 101C3
BI
31B7 101C3
BI
7C7 31C4 101C3
BI
31C4 101C3
BI
7C7 31B2 101C3
BI
31C2 101C3
BI
7C7 31C4 101C3
BI
31C4 101C3
BI
31C2 101C3
BI
31D2 101C3
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C7
101A3 32B5
BI
101A3 32B5
BI
101A3 32B5
BI
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
AP23
AP19
AW17
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
AV33
MCLK0A_1_P
MCLK0A_1_N
BA24
MCLK0A_0_P
MCLK0A_0_N
BB20
MCS0A_1#
MCS0A_0#
AY24
BC20
AT15
P
MODT0A_1
MODT0A_0
MCKE0A_1
MCKE0A_0
AR18
AP15
AV15
AU23
AT23
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C7
OUT
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C5
OUT
101D3 31C7
OUT
101D3 31C5
e
r
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
AW33
OUT
8B8
8B8
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
101D3 31C5
OUT
101D3 31C5
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
OUT
101D3 31C7
OUT
101D3 31C7
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
OUT
101D3 31C7
OUT
101D3 31C5
AT4
AT3
AV2
AV3
AR4
AR3
AU2
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
y
r
a
n
i
m
il
101A3 32B7
BI
101A3 32B5
BI
101A3 32B7
BI
101A3 32B7
BI
101A3 32B5
BI
101A3 32B7
BI
101A3 32B5
BI
101A3 32B7
BI
101A3 32B7
BI
101A3 32B7
BI
101A3 32B7
BI
101A3 32B5
BI
101A3 32B5
BI
101A3 32B5
BI
101A3 32B5
BI
101A3 32B5
MBA0_2
MBA0_1
MBA0_0
BI
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
BI
101A3 32B7 7B7
BI
101B3 32C5
BI
101B3 32B5
BI
101B3 32B5
BI
101B3 32B7
BI
101B3 32B7
BI
101B3 32C7
BI
101B3 32C2
BI
101B3 32C4
BI
101B3 32C2
BI
101B3 32C2
BI
101B3 32C2
BI
101B3 32C4
BI
101B3 32C4 7B7
BI
101B3 32C4
BI
101B3 32B4 7B7
BI
101B3 32B2
BI
101B3 32C4
BI
101B3 32C4
BI
101B3 32B2
BI
101B3 32C2
BI
101B3 32C2
BI
101B3 32B4
BI
101B3 32C4
BI
101B3 32C2
BI
101B3 32C2
BI
101B3 32C4
BI
101B3 32C2
BI
101B3 32C4
BI
101B3 32C2
BI
101B3 32C4 7B7
BI
101B3 32C4
BI
101B3 32C4 7B7
BI
101B3 32D2
BI
101B3 32D2
BI
101B3 32C2
BI
101B3 32C2
BI
101B3 32D4
BI
101B3 32D4
BI
32A7 101A3
OUT
32B5 101A3
OUT
32B7 101A3
OUT
OUT
101D3 31C5
32B5 101A3
OUT
OUT
101D3 31C5
32C2 101A3
OUT
32B4 101A3
OUT
OUT
101D3 31D5
32C2 101A3
OUT
OUT
101D3 31D7
32C4 101A3
OUT
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MEMORY PARTITION 1
MRAS1#
MCAS1#
MWE1#
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
AW16
BA15
BA16
MBA1_2
MBA1_1
MBA1_0
BB29
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BA29
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BB18
BB17
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
BI
BI
32A5 101D1
7B7 32A5 101D1
BI
7B7 32B7 101D1
BI
32B7 101D1
BI
7B7 32B5 101D1
BI
7B7 32B5 101D1
BI
32B7 101D1
BI
7B7 32B7 101D1
BI
32C4 101D1
BI
7B7 32C4 101D1
BI
7B7 32B2 101D1
BI
32C2 101D1
BI
32C4 101D1
BI
32C4 101D1
BI
32C2 101D1
BI
32D2 101D1
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C7
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C7
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C5
OUT
101B3 32C7
OUT
101B3 32C5
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
MCLK1A_1_P
MCLK1A_1_N
BB22
MCLK1A_0_P
MCLK1A_0_N
BA19
MCS1A_1#
MCS1A_0#
BB14
MODT1A_1
MODT1A_0
BB13
MCKE1A_1
MCKE1A_0
AY31
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
BB42
BA22
AY19
BB16
AY15
BB30
8A8
8A8
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
101B3 32C5
OUT
101B3 32C5
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
101B3 32C7
OUT
101B3 32C7
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
101B3 32C7
OUT
101B3 32C5
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
101B3 32C5
OUT
101B3 32C5
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
101B3 32D5
OUT
101B3 32D7
MCP Memory Interface

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
15
109
OMIT
U1400
MCP79-TOPO-B
BGA
8B8
8B8
8B8
8B8
8B8
8B8
8C8
8C8
8B8
8B8
30C7 30B7 25C8 16C3 6C4
25B2
AU33
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
R1610 1
40.2
1%
1/16W
MF-LF
402
2
101D1
101D1
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
R1611 1
40.2
1%
1/16W
MF-LF
402
AU34
BA21
BB21
AU17
AR15
AN17
AN15
AV23
AN25
17
12
19
39
mA
mA
mA
mA
T27
U28
U27
T28
AN41
AM41
AP12
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
e
r
MCLK0B_1_P
MCLK0B_1_N
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
MCLK1B_2_P
MCLK1B_2_N
BA41
MCLK1B_1_P
MCLK1B_1_N
AY23
MCLK1B_0_P
MCLK1B_0_N
BA20
MCS1B_0#
MCS1B_1#
BC16
MODT1B_0
MODT1B_1
AY16
MCKE1B_0
MCKE1B_1
BA30
BA31
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MRESET0#
AY32
MCP_MEM_RESET_L
BB41
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
8A8
8A8
8A8
y
r
a
n
i
m
il
BC24
AA22
MCLK0B_2_P
MCLK0B_2_N
MEMORY CONTROL 1B
8B8
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
MEMORY CONTROL 0B
(4 OF 11)
8B8
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26
MCLK0B_0_P
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MODT0B_0
MODT0B_1
MCKE0B_0
MCKE0B_1
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
BA23
AY20
BA13
BC13
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
8A8
8A8
8B8
8B8
8B8
8B8
8B8
8B8
OUT
33B6
TP or NC for DDR2.
MEM_COMP_VDD
MEM_COMP_GND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
8A8
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AM17
6C4 16C7 25C8 30B7 30C7
4771 mA (A01, DDR3)
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
MCP Memory Misc
T9
U18
SYNC_MASTER=K50
U20
U22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
16
109
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
IN
9C7
9C7
IN
9C7
9C7
9C7
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
IN
IN
PEG_PRSNT_L
IN
34C6
IN
9B6
IN
41B2
IN
9B6
IN
8A6
IN
8B6
IN
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
FW_CLKREQ_L
PCIE_FW_PRSNT_L
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L
8B6
8B6
98B7
IN
8B4
OUT
AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L
TP_MCP_GPIO_18
GMUX_JTAG_TDO
8D6
8B4
34C6
IN
PCIE_WAKE_L
IN
e
r
102D3 34C8 7C8
IN
102D3 34C8 7C8
IN
102C3 41C1 7C8
IN
102C3 41C1 7C8
IN
8D4
IN
8D4
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
IN
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
=PP1V05_S0_MCP_PEX_DVDD0
25D7 28C1
57 mA (A01, DVDD0 & 1)
F7
E7
D7
C7
E6
F6
E5
F5
E4
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
C9
Int PU
PE0_PRSNT_16#
Int PU
D5
PEB_CLKREQ#/GPIO_49
D9
PEB_PRSNT# Int PU
E8
PEC_CLKREQ#/GPIO_50
Int PU
C10
PEC_PRSNT# Int PU
M15
PED_CLKREQ#/GPIO_51
B10
PED_PRSNT# Int PU
L16
PEE_CLKREQ#/GPIO_16
L18
PEE_PRSNT#/GPIO_46
M16
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
M18
M17
Int PU
Int PU
Int PU
Int PU
C4
B4
A4
A3
B3
B2
C1
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
PEG_CLK100M_P
PEG_CLK100M_N
OUT
9C7
OUT
9C7
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
102C3 34C6
OUT
102C3 34C6
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
7D6 102C3 41C2
OUT
7D6 102C3 41C2
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
OUT
8A6
OUT
8A6
F9
E9
H7
G7
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
PE0_REFCLK_P
PE0_REFCLK_N
E11
PE1_REFCLK_P
PE1_REFCLK_N
G11
PE2_REFCLK_P
PE2_REFCLK_N
J11
PE3_REFCLK_P
PE3_REFCLK_N
G13
PE4_REFCLK_P
PE4_REFCLK_N
J13
PE5_REFCLK_P
PE5_REFCLK_N
L14
PE6_REFCLK_P
PE6_REFCLK_N
N14
D11
F11
J10
F13
H13
K14
W19
U17
V19
W16
W17
W18
U16
T19
MCP_PEX_CLK_COMP
8B6
8B6
K11
PCIE_RESET_L
OUT
9C4
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
OUT
102D3 34B8
OUT
102D3 34C8
PE1_RX1_P
PE1_RX1_N
PE1_TX1_P
PE1_TX1_N
B8
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
102D3 41C1
OUT
102C3 41C1
PE1_RX2_P
PE1_RX2_N
PE1_TX2_P
PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
OUT
8D4
OUT
8D4
PE1_RX3_P
PE1_RX3_N
PE1_TX3_P
PE1_TX3_N
B6
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
U19
+DVDD1_PEX1
+DVDD1_PEX2
T16
+V_PLL_PEX
A11
8C6
D8
C8
A8
B7
PEX_CLK_COMP
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
C6
Y12
28D1 25D1
206 mA (A01, AVDD0 & 1)
AB12
Minimum 1.025V for Gen2 support
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
28D2
M13
N13
MCP PCIe Interfaces
P13
NO STUFF
1
SYNC_MASTER=K50
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K
AA12
=PP1V05_S0_MCP_PEX_AVDD1
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
8B6
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
T17
8B6
PE1_TX0_P
PE1_TX0_N
PE1_RX0_P
PE1_RX0_N
G9
E1
PEX_RST0#
F17
Int PU
PE_WAKE# Int PU (S5)
H9
D2
M14
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
J9
D1
84 mA (A01)
102C3
D4
Int PU
M19
K9
PP1V05_S0_MCP_PLL_PEX
25C2
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
C5
Int PU
28D2
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
y
r
a
n
i
m
il
E3
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
PCI EXPRESS
9C7
1%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place within 12.7mm of U1400

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
17
109
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
IN
104D3 37C1
IN
104D3 37C1
IN
104D3 37C1
IN
104D3 37B1
IN
9A4
IN
9A4
IN
9A4
IN
R1810 1
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
E24
A24
5 mA (A01)
2
MCP_MII_COMP_VDD
104D3 MCP_MII_COMP_GND
47K
7C4 51C4
8D8
OUT
8D8
OUT
8D8
IN
8D8
OUT
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
NOTE: HDMI port requires level-shifting. IFP interface can

be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
+V_DUAL_MACPLL
C27
MII_COMP_VDD
MII_COMP_GND
E36
A35
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
C38
D38
LPCPLUS_GPIO
DP_IG_CA_DET
BI
IN
90D6
OUT
90A5
OUT
90A5
OUT
9C7
OUT
9C7
OUT
9C7
9C7
OUT
OUT
9C7
OUT
9C7
OUT
9C7
OUT
9C7
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
MCP_MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
B24
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
RGMII_TXC/MII_TXCLK
D24
RGMII_TXCTL/MII_TXEN
C26
RGMII_MDC
RGMII_MDIO
D21
RGMII_PWRDWN/GPIO_37
RGMII_INTR/GPIO_35
T23
B38
93B5
Interface Mode
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
C39
=PP3V3_S5_MCP_GPIO
5%
1/16W
MF-LF
402
E28
107D2 93C8
107D2 93C8
9B7
OUT
OUT
OUT
IN
P
9B7
IN
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
e
r
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
GPIO_6/FERR*/IGPU_GPIO_6
GPIO_7/NFERR*/IGPU_GPIO_7
G39
D35
E35
G35
F35
F33
G33
J33
H33
D43
C43
C31
F31
LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET2/GPIO_22
HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V)
M27
M26
PP3V3_S0_MCP_VPLL
26C5
16 mA (A01)
26D6
26C7 102C3
(See below)
XTALIN_TV
XTALOUT_TV
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
8 mA
8 mA
TV
C
Y
Comp
B15
F40
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
TV_DAC_RSET
TV_DAC_VREF
E16
E37
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
26D6
26C7 102C3
(See below)
RGB_DAC_RSET
RGB_DAC_VREF
104D3 37C6
104D3 37C6
OUT
104D3 37C6
OUT
104D3 37C6
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
104D3 37C7
OUT
104D3 37B6
OUT
104D3 37B6
C21
ENET_MDC
ENET_MDIO
G23
TP_ENET_PWRDWN_L
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
C25
D25
M28
M29
+VDD_IFPA
+VDD_IFPB
+V_PLL_IFPAB
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
HDMI_VPROBE
J30
J32
103 mA
103 mA
K32
B31
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
B39
RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE
A40
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
D36
IFPA_TXC_P
IFPA_TXC_N
B35
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
B32
IFPB_TXC_P
IFPB_TXC_N
L31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J29
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
C30
DDC_CLK3
DDC_DATA3
D31
IFPAB_RSET
IFPAB_VPROBE
E32
37B6 104D3
104D3 38B3
OUT
7D6 37B7
206 mA (A01)
MII
=PP3V3_S0_MCP_GPIO
R1860 1
26C4
ENET_TXD<0>
RGMII
NOTE: All Apple products set strap to

MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
8D6
OUT
Interface
100K
5%
1/16W
MF-LF
402
6B4 19D1 21A4
R1861
100K
5%
1/16W
MF-LF
402
MCP_DDC_CLK0
MCP_DDC_DATA0
A31
B40
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
A41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
A36
B36
C36
C37
C35
A32
D32
C32
D33
C33
B34
C34
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.
8C8
8C8
TV DAC Disable:
OUT
8D8
OUT
8D8
OUT
8D8
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
8C8
OUT
8C8
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
107D2 89B8
OUT
107D2 89B8
OUT
107D2 89D8
OUT
107C2 89D8
OUT
107D2 89D8
OUT
107C2 89D8
OUT
107D2 89C8
OUT
107C2 89C8
OUT
107D2 89B8
OUT
107C2 89B8
OUT
107C2 89C5
OUT
107C2 89C5
OUT
107C2 89A8
OUT
107C2 89A8
OUT
107C2 89D5
OUT
107C2 89D5
OUT
107C2 89D5
OUT
107C2 89D5
OUT
107C2 89C5
OUT
107C2 89C5
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
89B5
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
102C3 26C6
OUT
102C3 26C6
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
RGB DAC Disable:
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
A39
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
K31
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
H29
L29
K29
L30
K30
N30
M30
B30
E31
G31
BI
BI
89A5
9B7
9B7
R1850
10K
GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal

pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
BI
Network Interface Select
25A4
OUT
C24
DDC_CLK0
DDC_DATA0
/
/
/
/
IN
OUT
+V_RGB_DAC
+V_TV_DAC
RGB ONLY
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
R1820
MII_VREF
38D2 25D6
131 mA (A01)
V23
PP3V3_S0_MCP_DAC
49.9
F23
B27
R1811 1
20C1 6D1
RGMII_RXCTL/MII_RXDV
J22
104D3
1%
1/16W
MF-LF
402
RGMII_RXC/MII_RXCLK
C22
B22
PP1V05_ENET_MCP_PLL_MAC
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
A23
B26
TP_ENET_INTR_L
8D6
25A6
U23
y
r
a
n
i
m
il
B23
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
49.9
1%
1/16W
MF-LF
402
C23
ENET_CLK125M_RXCLK
ENET_RX_CTRL
+V_DUAL_RMGT1
+V_DUAL_RMGT2
38D2 18D7 25A5 25B6
83 mA (A01)
=PP1V05_ENET_MCP_RMGT
DACS
IN
104D3 37C1
K24
FLAT PANEL
25B6 25A5 18D3 38D2
104D3 37C1
J24
+3.3V_DUAL_RMGT2
LAN
+3.3V_DUAL_RMGT1
5%
1/16W
MF-LF
402
MCP Ethernet & Graphics

SYNC_MASTER=K50

=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
18
109
OMIT
U1400
21A4 18C1 6B4
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
19D2
98C7
OUT
OUT
19D2
IN
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
7A4 13C3
BI
8A6
8A6
8A6
8A6
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C6
8C6
8C6
8C6
8C6
7D4 51D5 49C5 7C8
41B2
IN
IN
8C8
7D4 51D4 49C8
BI
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_TRDY_L
PM_CLKRUN_L
T2
V9
T3
U9
T4
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
P2
N3
N2
N1
Y3
AD11
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AE2
AE1
AE6
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
Int PU
LPC_DRQ0#
LPC_SERIRQ Int PU
PCI_PME#/GPIO_30
Int PU (S5)
PCI_RESET0#
PCI_RESET1#
PCI_CLK0
PCI_CLK1
PCI_CLK2
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R3
U10
R4
U11
P3
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AA3
AA6
AA11
W10
Y4
AA10
Y1
AB9
AA7
Y2
PM_LATRIGGER_L
T1
MEM_VTT_EN_R
TP_PCI_RESET1_L
R10
R11
R6
R7
R8
103D3
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
19D7 7B3 103D3
OUT
8B4
OUT
8B4
OUT
19D2
19D7
19D7
R1989
8.2K
R1990
R1991
R1992
R1994
8.2K
8.2K
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8C8
8C8
TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R
8D6
8C8
8C6
8C8
8C6
8C8
8C8
8C6
OUT
7A4 13C6
OUT
9C4
8C6
8D6
8C6
PCI_CLKIN
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
R9
103D3
R1910
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
103D3
AD2
103D3
AD1
103D3
AD5
103D3
AE9
Y26
e
r
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to pin R8
R1960
22
LPC_FRAME_L
5%
1/16W
MF-LF
OUT
402
LPC_RESET_L
AE5
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
PCI_CLK33M_MCP
LPC_FRAME_R_L
LPC_PWRDWN_L
AD4
AE12
LPC_RESET0#
LPC_CLK0
GND
U26
8C6
MCP_RS232_SOUT_L
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
MCP_RS232_SIN_L
22
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
R1950
R1951
R1952
R1953
22
22
22
22
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
103D3 7D4 49C8 51D5
OUT
7C4 49C5 51D4
OUT
103D3 9D4
BI
49C8 51D5 103D3 7D4
BI
7B8 7D6 49C8 51D5 103D3 7D4
BI
49C8 51D4 103D3 7D4
BI
LPC_CLK33M_SMC_R
U24
19D7 7B3 103D3
y
r
a
n
i
m
il
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L
AA9
8C6
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_TRDY#
19D4
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI
19D2 7B3 103D3
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
LPC
19D2 7B3 103D3
OUT
49C8 51D4 103D3 7D4
103D3 9B4
R1961
10K
5%
1/16W
MF-LF
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
MCP PCI & LPC
AD28
AD33
SYNC_MASTER=K50
AD34

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
19
109
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
45D5 102C3
45D5 102C3
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
OUT
OUT
102C3 45D5 7B8
IN
102C3 45C5 7B8
IN
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ7
AJ6
AJ5
AJ4
SATA_A0_TX_P
SATA_A0_TX_N
USB0_P
USB0_N
SATA_A0_RX_N
SATA_A0_RX_P
USB1_P
USB1_N
USB2_P
USB2_N
OUT
45C5 102C3
OUT
102B3 45C5 7B8
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
102B3 45C5 7B8
IN
AK9
TP_SATA_C_D2RN
TP_SATA_C_D2RP
AK2
AJ3
AJ2
AJ1
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
AM4
AL3
AL4
AK3
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
AJ10
AJ9
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AN1
AM1
AM2
AM3
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_SATA_F_D2RN
TP_SATA_F_D2RP
D29
C28
D28
A28
B28
External A
USB_EXTA_P
USB_EXTA_N
BI
46A7 103D3
BI
46A7 103D3
AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N
BI
34B3 103C3
BI
34B3 103C3
External D
USB_EXTD_P
USB_EXTD_N
BI
46D5 103C3
BI
46D5 103C3
BI
7B8 47B7 103C3
y
r
a
n
i
m
il
AJ11
AP3
AP2
AN3
AN2
SATA_A1_TX_P
SATA_A1_TX_N
Camera
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_C0_TX_P
SATA_C0_TX_N
USB3_P
USB3_N
F29
USB4_P
USB4_N
K27
USB_CAMERA_P
USB_CAMERA_N
G29
BI
7B8 47B7 103C3
USB_IR_P
USB_IR_N
BI
47B4 103C3
BI
47B4 103C3
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
8C4
BI
8C4
Bluetooth
USB_BT_P
USB_BT_N
BI
7B8 103C3 47D4
BI
7B8 103C3 47D4
External B
USB_EXTB_P
USB_EXTB_N
BI
46B6 103C3
BI
46B6 103C3
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
BI
8A6
BI
8B6
External C
USB_EXTC_P
USB_EXTC_N
BI
46B3 103C3
BI
46B3 103C3
IR
SATA
USB
45C5 102C3
C29
L27
USB5_P
USB5_N
J26
USB6_P
USB6_N
F27
USB7_P
USB7_N
USB8_P
USB8_N
USB9_P
USB9_N
J27
G27
D27
E27
K25
L25
H25
J25
USB10_P
USB10_N
F25
USB11_P
USB11_N
K23
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
L21
+V_PLL_USB
L28
TP_USB_10P
TP_USB_10N
G25
SATA_C1_RX_N
SATA_C1_RX_P
R2051
8.2K
6D1 18C7
R2053
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8B6
R2050
8B6
8B6
SATA_C0_RX_N
SATA_C0_RX_P
SATA_C1_TX_P
SATA_C1_TX_N
8B6
TP_USB_11P
TP_USB_11N
L23
=PP3V3_S5_MCP_GPIO
R2052
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
K21
J21
H21
PP3V3_S0_MCP_PLL_USB
IN
46C8
IN
46C8
IN
46D7
IN
25B4
19 mA (A01)
USB_RBIAS_GND
A27
103D3
MCP_USB_RBIAS_GND
R2060 1
TP_MCP_SATALED_L
45C3
PP1V05_S0_MCP_PLL_SATA
25B2
28C2
84 mA (A01)
6C4 =PP1V05_S0_MCP_SATA_DVDD0
43 mA (A01, DVDD0 & 1)
e
r
28B3
=PP1V05_S0_MCP_SATA_AVDD0
28C2
127 mA (A01, AVDD0 & 1)
P
28B3
102B3
E12
AE16
AF19
AG16
AG17
AG19
AH17
AH19
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
SATA_LED#
+V_PLL_SATA
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
+DVDD1_SATA1
+DVDD1_SATA2
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
MCP_SATA_TERMP
AN14
AL14
AM13
AM14
AE3
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AD35
AD37
AD38
806
1%
1/16W
MF-LF
402
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
R2010
2.49K
1%
1/16W
MF-LF
402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
20
109
OMIT
U1400
MCP79-TOPO-B
6B4 21D8 25A8
7 mA (A01)
BGA
(9 OF 11)
HDA
+V_DUAL_HDA1
+V_DUAL_HDA2
D
98C6
IN
8D6
25A8 21D3 6B4
9D7
HDA_SDIN0
G15
TP_MLB_RAM_SIZE
J14
TP_MLB_RAM_VENDOR
J15
(MXM_OK for MXM systems)

1
HDA_SDATA_IN0
Int PD
51B1
50D3 49D5
49.9K
1%
1/16W
MF-LF
402
R2121
OUT
IN
8B6
49.9K
5%
1/16W
MF-LF
402
R2170
21A7
103B3
F15
HDA_SDOUT_R
22
HDA_SDOUT
A15
1%
1/16W
MF-LF
402
8D6
49C5
IN
49B8
IN
HDA_PULLDN_COMP
PP1V05_S0_MCP_PLL_NV
20 mA
17 mA
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
AE18
AE17
+V_PLL_NV_H
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12/SUS_STAT#/ACCLMTR
K13
C18
Int PU
A20GATE
KBRDRSTIN# Int PU
SIO_PME#
Int PU (S5)
EXT_SMI/GPIO_32# Int PU (S5)
B20
INTRUDER#
L13
C19
5%
1/16W
MF-LF
402
21A7 103B3
22
HDA_BIT_CLK_R
HDA_BIT_CLK
5%
1/16W
MF-LF
402
HDA_RESET#
K15
21A7 103B3
L15
21A7 103B3
22
HDA_RST_R_L
HDA_SYNC_R
22
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK
HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA
K17
SLP_S3#
SLP_RMGT#
SLP_S5#
G17
THERM_DIODE_P
THERM_DIODE_N
B11
IN
71C8 100A3
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
49C8
IN
C16
28B5
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN# Int PU (S5)

RSTBTN# Int PU
RTC_RST_L
C20
RTC_RST#
HDA_RST_L
OUT
103B3 98C6
HDA_SYNC
OUT
103B3 98C6
5%
1/16W
MF-LF
402
H17
IN
OUT
MCP_THMDIODE_P
MCP_THMDIODE_N
C11
IN
MCP_CPU_VLD
C17
CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST#
JTAG_TCK
7A4 13C3
IN
13C3 7A4
OUT
7A4 13C3
IN
7A4 13C3
IN
7A4 13B6
IN
28C8
IN
OUT
IN
OUT
G19
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16
B16
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19
B19
C2170
C2172
10PF
10PF
5%
50V
CERM
402
5%
50V
CERM
402
C2171
XTALIN
XTALOUT
XTALIN_RTC
XTALOUT_RTC
R2151
100K
P
2
5%
1/16W
MF-LF
402
R2140
R2141
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
L20
M21
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
SPKR
C13
MCP_SPKR
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
L19
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
B12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
CPUVDD_EN
D17
MCP_CPUVDD_EN
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
C14
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
SUS_CLK/GPIO_34
BUF_SIO_CLK
B18
TEST_MODE_EN
PKG_TEST
K22
M20
10PF
5%
50V
CERM
402
5%
50V
CERM
402
G21
F21
M23
A12
D12
D13
C15
B14
102B3 7B4 9D7

38D7
OUT
102B3 7B4 38D7 49C5 50C3 70D8
SPI0
SPI1
OUT
55C4 108C3
OUT
55C4 108C3
OUT
21A3 74D7
OUT
21A3 74C7
OUT
21A3 74C7
NOTE: MCP79 does not support FWH, only

LPC ROMs. So Apple designs will
not use LPC for BootROM override.
=PP3V3_S0_MCP
NOTE: MCP79 rev A01 does not support

SPI1 option. Rev B01 will.
6B4 22B3 25B8
R2180
10K
OUT
BI
OUT
BI
OUT
IN
OUT
IN
=PP3V3_S0_MCP_GPIO
13B6 106D3 7A4 52D8
Frequency
50B3
52C8
R2142
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
ARB_DETECT
14.31818 MHz
Connects to SMC for

automatic recovery.
SPI Frequency Select

Frequency
SPI_DO
SPI_CLK
31 MHz
42 MHz
25 MHz
1 MHz
31A5 32A5 49B8 21A4 55C1

8A6
21A4 50B3
9A4
OUT
103B3 51C6
OUT
7B8 103B3 51A6 61C6
IN
7B8 51A6 61B2 103B3
OUT
103B3 51A6 61C2
OUT
103D3 9B4
NOTE: Straps not provided on this page.
8C8
MCP_TEST_MODE_EN
L22
R2163
R2190
1K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
6B4 18C1 19D1
6D3
R2154
100K
5%
1/16W
MF-LF
402
AP_PWR_EN
21C3
21C3
21C3 98C7
MCP HDA & MISC
31A5 32A5 49B8 21B3 55C1
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
21B3 50B3
21B3
R2147
R2155
R2156
100K
22K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
21C3 74D7
SYNC_MASTER=K50
21C3 74C7

R2157
22K
21C3 74C7
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
HDA_SYNC
24 MHz
USER mode: Normal

SAFE mode: For ROMSIP
recovery
21A4
OUT
R2143
10K
5%
1/16W
MF-LF
402
21A3
=PP3V3_S3_MCP_GPIO
1
R2181
10K
13B6 106D3 7A4 52D8
52C8
BUF_SIO_CLK Frequency
5%
1/16W
MF-LF
402
OUT
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
AE7
C2173
10PF
PCI
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
21A4 98C7
OUT
10K
5%
1/16W
MF-LF
402
K19
(MGPIO2)
10K
LPC_FRAME#
BOOT_MODE_USER
e
r
J18
5%
1/16W
MF-LF
402
21D4 103B3
PWRGD_SB
PS_PWRGD
J19
10K
21D4 103B3
E20
F19
R2150 1
21D4 103B3
D20
HDA_SDOUT
LPC
21A4
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
J17
I/F
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
MCP_GPIO_4
AUD_I2C_INT_L
L17
(MGPIO3)
IN
28C8
21D4 103B3
LID# Int PU (S5)

LLB# Int PU (S5)
9A2
28C8
For EMI Reduction on HDA interface
M24
70A2
28C8
HDA Output Caps
M25
PM_RSMRST_L
MCP_PS_PWRGD
IN
103B3 98C6
BIOS Boot Select
BOOT_MODE_SAFE
MISC
49B8
TP_MCP_LID_L
PM_BATLOW_L
49D8
HDA_RST_R_L
HDA_SYNC_R
OUT
R2172
SM_INTRUDER_L
HDA_SDOUT_R
HDA_BIT_CLK_R
103B3 98C6
y
r
a
n
i
m
il
HDA_BITCLK
E15
OUT
5%
1/16W
MF-LF
402
PP3V3_G3_RTC
8.2K
R2173
37 mA (A01)
R2160
R2171
HDA_SYNC
1%
1/16W
MF-LF
402
25A2
R2120 1
HDA_SDATA_OUT
HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
Int PD
R2110
MCP_HDA_PULLDN_COMP
28D5 22A5
K16
HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
Int PD
49.9
J16
10
OF
21
109
MCP79-TOPO-B
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
25D8 6D4
AV40
BGA
(10 OF 11)
=PPVCORE_S0_MCP
AA25
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
BA1
AC23
BA4
U25
AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
AC19
D18
AC20
D19
AC21
D22
D23
AA17
D26
AC24
D30
AC25
D37
AC26
AC27
D6
E13
AC28
E17
AD21
E21
AD23
W27
E25
V25
E29
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
AE26
G10
AE27
G12
AE28
G14
AF10
G16
AF11
BC12
AA19
G22
G24
AF2
AW20
AF21
AF23
G34
G4
AF25
AF3
G43
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
AG11
H23
AG12
AN8
AG21
G40
AG23
J12
J8
AG25
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
e
r
AG3
AG4
AA21
AG6
AG7
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
W25
AF12
28D5 21C8
=PP1V05_S0_MCP_FSB
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
R32
1139 mA
6D4 14A2 14B7 23C3 25C8
1182 mA (A01)
AC32
E40
J36
N32
T32
U32
V32
y
r
a
n
i
m
il
AA16
BC41
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)
A20
+VBAT
POWER
AH34
GND
BGA
(11 OF 11)
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
U1400
MCP79-TOPO-B
AH33
OMIT
OMIT
U1400
AH26
+VTT_CPUCLK
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
AG32
43 mA
=PP3V3_S0_MCP
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
G36
AD10
6B4 21C2 25B8
450 mA (A01)
AE8
AB10
AD9
Y10
AB11
AA8
Y9
=PP3V3_S5_MCP
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3
T21
16 mA
6D1 25B8
266 mA (A01)
H19
J20
K20
250 mA
H27
J28
K28
6D1 25D8
105 mA (A01)
MCP Power & Ground
U21
V21
SYNC_MASTER=K50

Y11
AH16
T22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
22
109
y
r
a
n
i
Extra FSB Pull-ups
CPU FSB Frequency Straps
Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa
25C8 22D3 14B7 14A2 6D4
=PP1V05_S0_MCP_FSB
NO STUFF
R23961
10B4
10B4
10B4
IN
IN
IN
CPU_BSEL<0>
MCP_BSEL<0>
100B3
=MCP_BSEL<0>
MAKE_BASE=TRUE
CPU_BSEL<1>
MCP_BSEL<1>
100B3
MCP_BSEL<2>
100B3
OUT
14A7
BSEL<2..0>
FSB MHz
000
266
001
133
010
200
011
(166)
=MCP_BSEL<2>
MAKE_BASE=TRUE
OUT
OUT
14A7
14A7
100
333
101
100
110
(400)
111
(RSVD)
NOTE: () values not supported by MCP79.
5%
1/16W
MF-LF
402 2
100C3 14B6 10D6 7D7
OUT
13C2 10D6 100C3 14A3
OUT
NO STUFF
R2397
51
5%
1/16W
MF-LF
2 402
FSB_BREQ0_L
FSB_CPURST_L
m
il
=MCP_BSEL<1>
MAKE_BASE=TRUE
CPU_BSEL<2>
62
e
r
Merom/Penryn do not officially support PECI, but its not clear

whether PECI interface is present or not. T12 used pin F6.
R2390
10B8
BI
TP_CPU_RSVD_F6
CPU_PECI
MAKE_BASE=TRUE
20
5%
1/16W
MF-LF
402
CPU_PECI_MCP
BI
14B6
Debug: CPU
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
23
109
8
MCP Core Power
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)
=PPVCORE_S0_MCP
22D5 6D4
TABLE_5_HEAD
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
(No IG vs. EG data)
PART#
28D4
MCP PCIE (DVDD) Power

DIFFERENT THAN ON T18
6C4 =PP1V05_S0_MCP_PEX_DVDD
C2501
4.7UF
C2502
4.7UF
20%
4V
X5R
402
C2503
4.7UF
20%
4V
X5R
402
20%
4V
X5R
402
C2504
4.7UF
1UF
2
1UF
10%
10V
X5R
402-1
C2505
NV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)

K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)
28C1 =PP1V05_S0_MCP_PEX_DVDD0
C2506
1UF
10%
10V
X5R
402-1
C2507
1UF
10%
10V
X5R
402-1
57 mA (A01)
MXM
PEX_DVDD RAIL SPLIT BASED

ON IG VS. EG. 8 OUT OF 10
BALLS FOR DVDD0 SO 80% OF
CAPACITANCE ON DVDD0
C2515
C2516
1UF
2.2UF
20%
6.3V
CERM
402-LF
10%
10V
X5R
402-1
MXM
C2517
1UF
2
10%
10V
X5R
402-1
C2509
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
C2510
0.1UF
C2511
0.1UF
20%
10V
CERM
402
C2512
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
C2513
116S0004
6D4
43 mA (A01)
MXM
RES,0,5%,0402
C2574,C2518
C2520
20%
6.3V
CERM
402-LF
4.7UF
20%
4V
X5R
402
y
r
a
n
i
m
il
1
18D3 38D2
105 mA (A01)
C2521
2.2UF
20%
10V
CERM
402
20%
6.3V
CERM
402-LF
C2525
C2526
0.1uF
2
MCP FSB (VTT) Power
C2528
0.1uF
20%
10V
CERM
402
4.7uF
20%
10V
CERM
402
20%
4V
X5R
402
C2529
C2531
C2532
C2533
C2534
C2535
C2536
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
4.7UF
20%
4V
X5R
402
C2541
C2542
C2543
C2544
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C2550
C2551
C2552
C2553
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
e
r
83 mA (A01)
20%
6.3V
CERM
402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
7 mA (A01)
1
C2562
2.2UF
20%
6.3V
CERM
402-LF
L2595
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
1
PP1V05_ENET_MCP_PLL_MAC
VOLTAGE=1.05V
2
0402
C2595
4.7UF
20%
4V
X5R
402
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
6.3V
CERM
402-LF
C2576
20%
6.3V
CERM
402-LF
14A6
270 mA (A01)
C2581
20%
4V
X5R
402
PP1V05_S0_MCP_PLL_PEX
C2582
20%
4V
X5R
402
VOLTAGE=3.3V
0402
C2583
2.2UF
20%
4V
X5R
402
PP1V05_S0_MCP_PLL_SATA
0402
C2584
C2555
4.7UF
20%
4V
X5R
402
20%
6.3V
CERM
402-LF
2.2UF
20%
4V
X5R
402
PP1V05_S0_MCP_PLL_CORE
VOLTAGE=1.05V
C2564
C2586
C2597
4.7UF
4.7UF
20%
4V
X5R
402
20%
4V
X5R
402
20%
6.3V
CERM
402-LF
16C6
87 mA (A01)
C2587
2.2UF
20%
4V
X5R
402
L2588
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
C2588
4.7UF
20%
4V
X5R
402
21C7
VOLTAGE=1.05V
2
0402
C2589
2.2UF
2
20%
4V
X5R
402
37 mA (A01)
C2590
2.2UF
20%
4V
X5R
402
MCP Standard Decoupling
R2591 1
1.47K
1%
1/16W
MF-LF
402
SYNC_MASTER=K50
2
MCP_MII_VREF
OUT
18D3

5 mA (A01)
R2590 1
1.47K
1%
1/16W
MF-LF
402 2
20%
10V
CERM
402
18C6
C2596
L2586
30-OHM-1.7A
2.2UF
84 mA (A01)
C2585
0402
20B6
VOLTAGE=1.05V
19 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
17A6
84 mA (A01)
L2584
MCP79 Ethernet VRef
25B6 18D7 18D3 38D2
30-OHM-1.7A
2.2UF
4.7UF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
20C3
0.1UF
2
MCP 3.3V Ethernet Power
C2560
2.2UF
5 mA (A01)
20%
6.3V
CERM
402-LF
C2591
0.1UF
2
20%
10V
CERM
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
PEX_AVDD RAIL SPLIT BASED

ON IG VS. EG. 12 OUT OF 15
BALLS FOR AVDD0 SO 80% OF
CAPACITANCE ON AVDD0
127 mA (A01)
VOLTAGE=1.05V
C2549
0.1UF
30-OHM-1.7A
25A5 18D7 18D3 38D2
38D2
19 mA (A01)
266 mA (A01)
C2548
L2555
21D8 21D3 6B4
C2547
0.1UF
20%
10V
CERM
402
6B4
MCP 3.3V/1.5V HDA Power
C2546
0.1UF
20%
10V
CERM
402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)
=PP3V3_S5_MCP
C2545
0.1UF
450 mA (A01)
22B3 6D1
2.2UF
L2582
30-OHM-1.7A
C2540
MCP 3.3V AUX/USB Power
28D1 17B3
C2574
2.2UF
0402
=PP3V3_S0_MCP
2.2UF
20%
6.3V
CERM
402-LF
PP1V05_S0_MCP_PLL_FSB
20%
4V
X5R
402
MCP 3.3V Power
MXM
C2573
2.2UF
20%
6.3V
CERM
402-LF
4.7UF
4771 mA (A01, DDR3)
22B3 21C2 6B4
VOLTAGE=1.05V
C2580
MCP Memory Power

30B7 16C7 16C3 6C4
30C7
2.2UF
L2580
0402
C2530
C2575
30-OHM-1.7A
562 mA (A01)
2.2UF
20%
10V
CERM
402
6C4
1182 mA (A01)
20%
6.3V
CERM
402-LF
MXM
C2572
VOLTAGE=1.05V
0.1uF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
2.2UF
0603
MXM
C2571
206 mA (A01)
MXM
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
28C3
L2575
131 mA (A01)
C2570
0.1uF
28D4
VOLTAGE=1.05V
30-OHM-5A
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
0603
MCP 1.05V RMGT Power
IG
20%
10V
CERM
402
333 mA (A01)
C2518
L2570
=PP1V05_S0_MCP_SATA_DVDD
MCP 1.05V AUX Power
22D3 14B7 14A2 6D4

23C3
BOM OPTION
0.1UF
MCP SATA (DVDD) Power

28C3
2.2UF
10%
10V
X5R
402-1
C2508
0.1UF
17B6
22A3 6D1
DESCRIPTION
TABLE_5_ITEM
C2500
20%
4V
X5R
402
QTY
10
OF
25
109
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

IG
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
R2680
6C4
=PP3V3R1V8_S0_MCP_IFP_VDD_R 1
PP3V3R1V8_S0_MCP_IFP_VDD
5%
1/16W
MF-LF
402
IG
1
C2610
=PP3V3R1V8_S0_MCP_IFP_VDD
18B6
MAKE_BASE=TRUE
190 mA (A01, 1.8V)

TABLE_5_HEAD
2.2UF
2
PART#
20%
6.3V
CERM
402-LF
QTY
DESCRIPTION
CRITICAL
TABLE_5_ITEM
116S0004
RES,0,5%,402
C2610
MXM
=PP1V05_S0_MCP_HDMI_VDD_R
y
r
IG
R2690
6C4
BOM OPTION
TABLE_5_HEAD
PP1V05_S0_MCP_HDMI_VDD
5%
1/16W
MF-LF
402
IG
C2615
IG
1
4.7UF
20%
4V
X5R
402
=PP1V05_S0_MCP_HDMI_VDD
PART#
QTY
DESCRIPTION
RES,0,5%,402
C2616
0.1UF
20%
10V
CERM
402
95 mA (A01)
MCP_HDMI_RSET
MCP_HDMI_VPROBE
102C3 18A3
102C3 18A3
NO STUFF
C2620
20%
10V
CERM
402
6B4
C2630
1K
1%
1/16W
MF-LF
402
=PP3V3_S0_MCP_VPLL_UF
20%
10V
CERM
402
2
0402
IG
1
4.7UF
20%
6.3V
CERM
603
DESCRIPTION
POWER_MCP_DAC
16 mA (A01)
C2641
20%
10V
CERM
402
e
r
RES,0,5%,402
C2641
CRITICAL
BOM OPTION
MXM
5%
1/16W
MF-LF
402
m
il
VOLTAGE=3.3V
0.1uF
1%
1/16W
MF-LF
402
IG
C2640
116S0004
R2630
1K
0.1UF
QTY
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

IG
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
18B6
16 mA (A01)
PART#
NO STUFF
NO STUFF
R2620
0.1UF
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MXM
a
n
i
R2650
PP3V3_S0_MCP_DAC
MAKE_BASE=TRUE
102C3 18A6
BOM OPTION
TABLE_5_ITEM
116S0004
C2616
18C3
102C3 18A6
CRITICAL
18A6
MAKE_BASE=TRUE
TABLE_5_HEAD
TABLE_5_ITEM
MCP Graphics Support

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
26
109
RTC Power Sources

PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN
D2800
BAT54DW-X-G
SOT-363
6D1
IMAC
Coin-Cell Holder
PPVBATT_G3_RTC
1K
VOLTAGE=3.3V
PP3V3_G3_RTC
PPVBATT_G3_RTC_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
CRITICAL
1
=PP3V3_S5_RTC_D
1
NC
NC
NC
21C8 22A5
VOLTAGE=3.3V
R2800
C2800
NC
J2800
C2801
C2802
1UF
0.1UF
0.1UF
10%
6.3V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
25D1
PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
R2880
0
1
SM
PLACE AT LEAST 1 CAP NEAR MCP PIN A20
511S0054
y
r
MXM
BB10201-C1403-7H
2
PP1V05_S0_MCP_PEX_AVDD0
UNPOWER PEG INTERFACE WHEN IG IS USED
25D8 6C4
32.768K
SM-2
5%
50V
CERM
402
Y2810
CRITICAL
NC
NC
5%
1/16W
MF-LF
402
10M
5%
1/16W
MF-LF
402
OUT
R2882
R2811
21B7
RTC_CLK32K_XTALOUT_R
C2811
12pF
1
RTC_CLK32K_XTALIN
MCP 25MHz Crystal
C2815
R2815
CRITICAL
Y2815
25.0000M
10M
5%
1/16W
MF-LF
402 2
21B7
OUT
SM-3.2X2.5MM
NC
NC
2
5%
50V
CERM
402
R2816
12pF
5%
1/16W
MF-LF
402
NO STUFF
MCP_CLK25M_XTALOUT_R
IN
MCP_CLK25M_XTALOUT
m
il
12pF
2
5%
50V
CERM
402
Reset Button
7C3 49B8 7C8
IN
PM_SYSRST_L
e
r
XDP
R2896
7A4 13B3 10C6
IN
XDP_DBRESET_L
R2899
0
1
10K pull-up to 3.3V S0 inside MCP
33
2
5%
1/16W
MF-LF
402
PM_SYSRST_DEBOUNCE_L
2
5%
1/16W
MF-LF
402
NO STUFF
1
R2898
C2899
1UF
NO STUFF
2
10%
10V
X5R
402
5%
1/10W
MF-LF
603 2
SILK_PART=RESET_BTN
17A6
PP1V05_S0_MCP_PEX_DVDD0
17B6 25D7
MAKE_BASE=TRUE
VOLTAGE=1.05V
UNPOWER PEG INTERFACE WHEN IG IS USED
SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1
C2816
1
MCP_CLK25M_XTALIN
5%
1/16W
MF-LF
402
5%
50V
CERM
402
21B7
MXM
12pF
RTC_CLK32K_XTALOUT
=PP1V05_S0_MCP_PEX_DVDD
a
n
i
C2810
R2810
IN
17B3 25D1
RTC Crystal
21B7
MAKE_BASE=TRUE
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
NOTE: R2800 and D2800 form the doublefault protection for RTC battery.
17A3
OUT
21C7
AVDD IS FILTERED ON P25
25D2
PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
20B6
25D6
=PP1V05_S0_MCP_SATA_DVDD
6C4 20B6
DVDD DOES NOT NEED FILTER
20B6
20B6
SB Misc
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
28
109
Page Notes
MEM A VREF DQ
Power aliases required by this page:

- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
DAC channel
Min DAC code
Max DAC code
Max sink I
Max source I
Nominal Vref
Min Vref
Max Vref
Vref Stepping
(per DAC LSB)
Signal aliases required by this page:

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:

VREFMRGN
NO_VREFMRGN
MEM A VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF DQ
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
CPU FSB VREF

C
0x00
0x55
-0.91 mA
0.52 mA
0.70 V
0.091 V
1.044 V
11.2 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
6D3
10mA max load
y
r
a
n
i
m
il
R2903
1
A2
V+
UCSP
A1
VREFMRGN
0.1UF
20%
10V
2 CERM
402
=PP3V3_S3_VREFMRGN
6D3
A3
VREFMRGN
R2901
C2901
0.1UF
20%
2 10V
CERM
402
U2902
B1
C2
V+
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
10 A1
VOUTB 2
VREFMRGN_CA_SODIMM
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
TP_DAC5574_VOUTD
R2902
100K
GND
3
A2
C2904
V+
20%
10V
2 CERM
402
A3
R2907
C2
V+
100K
0.1UF
20%
2 10V
CERM
402
P
U2901
PCA9557
QFN
ADDR=0x30(WR)/0x31(RD)
52B1
IN
BI
A0
4 A1
5 A2
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
SCL
2 SDA
THRM
17
PAD
P0
P1
P2
P3
P4
P5
P6
P7
6
7
9
10
11
12
13
14
RESET* 15
GND
e
r
Place close to J3200.126
UCSP
A1
NC
A4
V-
B4
U2904
B1
C2
V+
TP_PCA9557_P0
VREFMRGN_CPUFSB_EN
R2914
MAX4253
VREFMRGN
UCSP
C1
VREFMRGN_CPUFSB_BUF
29A4
VREFMRGN_CA_SODIMMA_EN
C3
29C3
VREFMRGN_DQ_SODIMMA_EN
B4
29D3
VREFMRGN
29B5 VREFMRGN_CPUFSB_EN
CPU_GTLREF
1%
1/16W
MF-LF
402
C4
V-
100
OUT
100A3 10B4
Place close to U1000.AD26
VREFMRGN_CA_SODIMMB_EN
29B3
R2913
VREFMRGN_DQ_SODIMMB_EN
29C3
100K
TP_PCA9557_P6
TP_PCA9557_P7
5%
1/16W
MF-LF
402
PCA9557D_RESET_L
IN
VREFMRGN
9C2
52B1
VREFMRGN
VCC
A3
1%
1/16W
MF-LF
402
32B3
MAX4253
VREFMRGN
20%
10V
2 CERM
402
100
16
C2902
V+
0.1UF
PP0V75_S3_MEM_VREFCA_B
VREFMRGN
VREFMRGN
1
A2
C2905
OMIT
VREFMRGN
5%
1/16W
MF-LF
402
U2904
B1
VREFMRGN
R2908
VREFMRGN_CA_SODIMMB_BUF
29A5 VREFMRGN_CA_SODIMMB_EN
B4
200
31B3
R2912
C4
V-
100
PP0V75_S3_MEM_VREFCA_A
VREFMRGN
1%
1/16W
MF-LF
402
MAX4253
UCSP
C1
VREFMRGN
OMIT
R2911
VREFMRGN
5%
1/16W
MF-LF
402
U2903
B1
1%
1/16W
MF-LF
402
100K
C3
VREFMRGN_CA_SODIMMA_BUF
29B5 VREFMRGN_CA_SODIMMA_EN
B4
200
32D5
R2910
A4
V-
100
VREFMRGN
1%
1/16W
MF-LF
402
MAX4253
UCSP
A1
VREFMRGN
0.1UF
U2903
B1
VREFMRGN
PP0V75_S3_MEM_VREFDQ_B
R2909
VREFMRGN
5%
1/16W
MF-LF
402
OMIT
1%
1/16W
MF-LF
402
29A5 VREFMRGN_DQ_SODIMMB_EN
B4
VREFMRGN_DQ_SODIMM
VREFMRGN_DQ_SODIMMB_BUF
C4
V-
200
R2906
52C1
IN
DAC5574
52C1
C3
1%
1/16W
MF-LF
402
MAX4253
UCSP
C1
VREFMRGN
VREFMRGN
8 U2900
VDD
1
MSOP VOUTA
5%
1/16W
MF-LF
402
20%
6.3V
CERM
402-LF
VREFMRGN
31D5
VREFMRGN
R2905
1
100K
2.2UF
C2900
100
1%
1/16W
MF-LF
402
29A5 VREFMRGN_DQ_SODIMMA_EN
B4
VREFMRGN
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
C2903
1%
1/16W
MF-LF
402
U2902
B1
VREFMRGN
200
OMIT
FSB/DDR3 Vref Margining
Required zero ohm resistors when no VREF margining circuit stuffed

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
SYNC_MASTER=K50
BOM OPTION
TABLE_5_ITEM
114S0149
RES,402,1/16W,200 OHM,1%
R2903
VREFMRGN
116S0004
RES,402,1/16W,0 OHM,5%
R2903
PRODUCTION
114S0149
RES,402,1/16W,200 OHM,1%
R2905
VREFMRGN
116S0004
RES,402,1/16W,0 OHM,5%
R2905
PRODUCTION

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM
114S0149
RES,402,1/16W,200 OHM,1%
R2909
VREFMRGN
116S0004
RES,402,1/16W,0 OHM,5%
R2909
PRODUCTION
114S0149
RES,402,1/16W,200 OHM,1%
R2911
VREFMRGN
SIZE
TABLE_5_ITEM
TABLE_5_ITEM
116S0004
RES,402,1/16W,0 OHM,5%
R2911
DRAWING NUMBER
TABLE_5_ITEM
APPLE INC.
SCALE
SHT
PRODUCTION
NONE
REV.
051-7840
10
OF
29
109
y
r
CAPS TO COUPLE MCP 1V5_S0_MEM AND DIMMS 1V5_S3
a
n
i
CAPS TO COUPLE MCP 1V5_S0_MEM ON DIMM A (FURTHER FROM MCP)

30C7 30B7 25C8 16C7 16C3 6C4
C3016
0.1UF
20%
10V
2 CERM
402
C3017
0.1UF
20%
10V
2 CERM
402
C3018
0.1UF
20%
10V
2 CERM
402
C3019
0.1UF
20%
10V
2 CERM
402
C3010
0.1UF
20%
10V
2 CERM
402
CAPS TO COUPLE MCP 1V5_S0_MEM ON DIMM B (CLOSER TO MCP)

30C7 30B7 25C8 16C7 16C3 6C4
C3025
0.1UF
20%
2 10V
CERM
402
C3026
0.1UF
20%
2 10V
CERM
402
C3027
0.1UF
20%
2 10V
CERM
402
C3028
0.1UF
20%
2 10V
CERM
402
C3029
0.1UF
20%
2 10V
CERM
402
EXTRA DECOUPLING CAPS FOR MCP MEM RAIL
4771 mA (A01, DDR3)
1
C3041
0.1UF
20%
10V
CERM
402
P
1
C3042
C3044
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
C3020
0.1UF
20%
2 10V
CERM
402
C3021
0.1UF
20%
2 10V
CERM
402
C3022
0.1UF
20%
2 10V
CERM
402
C3023
0.1UF
20%
2 10V
CERM
402
C3014
0.1UF
20%
2 10V
CERM
402
C3030
0.1UF
20%
2 10V
CERM
402
C3031
0.1UF
20%
2 10V
CERM
402
C3032
0.1UF
20%
2 10V
CERM
402
C3033
0.1UF
20%
2 10V
CERM
402
C3034
0.1UF
20%
2 10V
CERM
402
C3035
0.1UF
20%
2 10V
CERM
402
e
r
30C7 25C8 16C7 16C3 6C4
m
il
C3046
0.1UF
20%
10V
CERM
402
MEMORY COUPLING CAPS

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
30
109
Page Notes
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

31A5 108D3 6D3
=PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
C3100
C3101
- =PP0V75_S0_MEM_VTT_A
10UF
10UF
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
20%
6.3V
X5R
603
20%
6.3V
X5R
603
C3110
C3111
1UF
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3112
1UF
C3113
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3114
C3115
C3116
C3117
1UF
1UF
1UF
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3118
1UF
10%
2 6.3V
CERM
402
C3119
1UF
10%
2 6.3V
CERM
402
C3120
C3121
C3122
1UF
1UF
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3123
1UF
10%
2 6.3V
CERM
402
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
29D1
PP0V75_S3_MEM_VREFDQ_A
(NONE)
y
r
a
n
i
m
il
C3130
C3131
2.2UF
73
203
CKE0
CKE1
VDD
VDD
A15
NC
A14
BA2
VDD
VDD
F-RT-SM
A12/BC*
A11
A7
A9
VDD
VDD
A6
A8
A4
A5
VDD
VDD
A2
A3
A0
A1
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ61
DQ56
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
205
206
MTG PIN
MTG PIN
75
NC 77
101D3 15C5
101D3 15C5
IN
101D3 15C5
IN
101D3 15C5
IN
IN
101D3 15B5
IN
101D3 15B5
IN
101D3 15B5
IN
101D3 15B5
IN
101D3 15B5
IN
101D3 15C5
IN
101D3 15C5
IN
101D3 15C5
IN
101D3 15C5
IN
101D3 15C5
IN
101D3 15B5
IN
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
79
81
83
85
87
89
91
93
95
97
99
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
101
MEM_A_A<10>
MEM_A_BA<0>
107
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
103
105
109
111
113
115
117
119
121
123
NC 125
127
101C3 15C7
BI
101C3 15C7
BI
101C3 15D5
BI
101C3 15D5 7B7
BI
101C3 15C7
BI
101C3 15C7
BI
MEM_A_DQ<32>
MEM_A_DQ<33>
129
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
135
MEM_A_DQ<34>
MEM_A_DQ<38>
131
133
137
139
141
143
145
101C3 15C7
BI
101C3 15C7
BI
MEM_A_DQ<44>
MEM_A_DQ<45>
147
149
151
101C3 15B7
IN
MEM_A_DM<5>
153
155
101C3 15D7 7C7
BI
BI
MEM_A_DQ<47>
MEM_A_DQ<46>
157
101C3 15D7
101C3 15D7
BI
101C3 15D7
BI
MEM_A_DQ<49>
MEM_A_DQ<52>
163
165
159
161
167
101B3 15D5 7B7
BI
101B3 15D5
BI
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
169
171
173
101C3 15D7
BI
101C3 15D7
BI
MEM_A_DQ<54>
MEM_A_DQ<51>
P
175
177
179
101C3 15D7
BI
101C3 15D7
BI
MEM_A_DQ<61>
MEM_A_DQ<60>
101C3 15B7
IN
MEM_A_DM<7>
101C3 15D7
BI
101C3 15D7 7C7
BI
MEM_A_DQ<58>
MEM_A_DQ<59>
181
183
185
187
189
191
193
195
MEM_A_SA<0>
6B4
=PPSPD_S0_MEM_A
MEM_A_SA<1>
1
1
C3140
2.2UF
20%
6.3V
CERM
402-LF
R3140
R3141
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
J3100
DDR3-SODIMM
MEM_A_CKE<0>
KEY
(SYMBOL 2 OF 2)
IN
197
199
201
209
20%
10V
CERM
402
CRITICAL
101D3 15A5
0.1UF
20%
6.3V
CERM
402-LF
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
MEM_A_CKE<1>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_ODT<1>
136
138
140
142
144
146
148
150
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DM<4>
MEM_A_DQ<35>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
e
r
MTG PIN
MTG PIN
MTG PIN
152
154
156
158
160
162
164
166
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<53>
MEM_A_DQ<48>
168
170
172
MEM_A_DM<6>
174
MEM_A_DQ<50>
MEM_A_DQ<55>
176
178
180
182
184
186
188
101D3 15B7
IN
8C4
IN
15C5 101D3
101C3 15A7
BI
BI
IN
IN
15C5 101D3
101D3 15B7
BI
IN
15C5 101D3
101D3 15B7 7C7
BI
IN
15B5 101D3
101D3 15B7
BI
IN
15B5 101D3
101D3 15B7
BI
IN
15B5 101D3
101C3 15D5
BI
IN
15B5 101D3
101C3 15D5 7C7
BI
IN
15B5 101D3
101D3 15B7
BI
IN
15B5 101D3
101D3 15B7
BI
IN
15C5 101D3
101D3 15C7 7C7
BI
IN
15C5 101D3
101D3 15C7
BI
IN
15B5 101D3
101C3 15D5
BI
IN
15B5 101D3
101C3 15D5 7C7
BI
IN
15B5 101D3
101D3 15C7
BI
101D3 15C7
BI
MEM_A_DQ<0>
MEM_A_DQ<1>
7
9
11
MEM_A_DM<0>
13
15
MEM_A_DQ<6>
MEM_A_DQ<7>
17
19
21
MEM_A_DQ<8>
MEM_A_DQ<12>
23
25
27
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
29
31
MEM_A_DQ<10>
MEM_A_DQ<15>
33
MEM_A_DQ<25>
MEM_A_DQ<24>
39
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
45
MEM_A_DQ<26>
MEM_A_DQ<30>
51
53
35
37
41
43
47
49
55
126
128
132
134
15A5 101D3
101D3 15B7
MEM_A_A<15>
MEM_A_A<14>
124
130
IN
3
5
MEM_A_DQ<57>
MEM_A_DQ<56>
BI
15C7 101C3
BI
15C7 101C3
IN
15C7 101C3
BI
15C7 101C3
BI
15C7 101C3
BI
15C7 101C3
BI
57
59
MEM_A_DQ<20>
MEM_A_DQ<21>
IN
MEM_A_DM<2>
63
65
101D3 15C7
BI
67
101D3 15B7 7C7
BI
MEM_A_DQ<23>
MEM_A_DQ<16>
101C3 15B7
69
71
J3100
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
MEM_A_DQ<4>
MEM_A_DQ<5>
BI
15B7 101D3
BI
15B7 101D3
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
15D5 101C3
BI
15D5 101C3
MEM_A_DQ<3>
MEM_A_DQ<2>
BI
15B7 101D3
BI
15B7 101D3
MEM_A_DQ<9>
MEM_A_DQ<13>
BI
15B7 101D3
MEM_A_DM<1>
MEM_RESET_L
IN
15A7 101C3
IN
33C3 32C2
MEM_A_DQ<11>
MEM_A_DQ<14>
BI
15B7 101D3
15B7 101D3
BI
7C7 15B7 101D3
MEM_A_DQ<29>
MEM_A_DQ<28>
BI
15C7 101D3
BI
15C7 101D3
MEM_A_DM<3>
IN
MEM_A_DQ<27>
MEM_A_DQ<31>
BI
15C7 101D3
BI
15C7 101D3
MEM_A_DQ<18>
MEM_A_DQ<17>
BI
15B7 101D3
BI
15B7 101D3
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
BI
15D5 101C3
MEM_A_DQ<19>
MEM_A_DQ<22>
70
72
BI
15B7 101C3
BI
7C7 15D5 101C3
BI
15B7 101D3
BI
15C7 101D3
KEY
BI
15D5 101C3
BI
7B7 15D5 101C3
BI
15C7 101C3
BI
15C7 101C3
BI
15D7 101C3
BI
15D7 101C3
IN
BI
101D3 15C7
61
15B7 101C3
BI
101D3 15C7
VSS
VREFDQ
VSS
DQ4
DQ5
DQ0
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-SM
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
VSS
DQS2
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
DDR3-SODIMM
(SYMBOL 1 OF 2)
15B7 101C3
BI
15D7 101C3
BI
15D7 101C3
BI
15D7 101C3
BI
15D7 101C3
PP0V75_S3_MEM_VREFCA_A
C3135
2.2UF
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
BI
15D5 101B3
BI
15D5 101B3
MEM_A_DQ<62>
MEM_A_DQ<63>
BI
15D7 101C3
BI
15D7 101C3
20%
6.3V
CERM
402-LF
29C1
C3136
0.1UF
20%
10V
CERM
402
190
192
194
196
198
200
202
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
OUT
32A5 49B8 21A4 21B3 55C1
BI
IN
52D6
52D6
204
207
208
=PP0V75_S0_MEM_VTT_A
=PP1V5_S3_MEM_A
6D3 108D3 31D7
MTG PIN
516S0657
C3150
DDR3 SO-DIMM Connector A
C3151
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
6D4
SYNC_MASTER=K50

SPD ADDR=0xA0(WR)/0xA1(RD)
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
31
109
Page Notes
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

32A5 108D3 6D3
=PP1V5_S3_MEM_B

- =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
C3200
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
C3201
10UF
C3210
C3211
C3212
C3213
C3214
C3215
C3216
C3217
C3218
C3219
C3220
C3221
C3222
C3223
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402

- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
29C1
PP0V75_S3_MEM_VREFDQ_B
(NONE)
y
r
a
n
i
m
il
C3230
C3231
2.2UF
73
203
CKE0
CKE1
VDD
VDD
A15
NC
A14
BA2
VDD
VDD
F-RT-SM
A12/BC*
A11
A7
A9
VDD
VDD
A6
A8
A4
A5
VDD
VDD
A2
A3
A0
A1
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ61
DQ56
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
205
206
MTG PIN
MTG PIN
75
NC 77
101B3 15C1
101B3 15C1
IN
101B3 15C1
IN
101B3 15C1
IN
IN
101B3 15B1
IN
101B3 15B1
IN
101B3 15B1
IN
101B3 15B1
IN
101B3 15B1
IN
101B3 15C1
IN
101B3 15C1
IN
101B3 15C1
IN
101B3 15C1
IN
101B3 15C1
IN
101B3 15B1
IN
MEM_B_BA<2>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
79
81
83
85
87
89
91
93
95
97
99
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
101
MEM_B_A<10>
MEM_B_BA<0>
107
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<1>
103
105
109
111
113
115
117
119
121
123
NC 125
127
101B3 15C3
BI
101B3 15C3
BI
101D1 15D1 7B7
BI
101D1 15D1
BI
101B3 15C3
BI
101A3 15C3 7B7
BI
MEM_B_DQ<32>
MEM_B_DQ<33>
129
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
135
MEM_B_DQ<34>
MEM_B_DQ<38>
131
133
137
139
141
143
145
101A3 15C3
BI
101A3 15C3
BI
MEM_B_DQ<44>
MEM_B_DQ<45>
147
149
151
101A3 15B3
IN
MEM_B_DM<5>
153
155
101A3 15D3
BI
157
101A3 15D3
BI
MEM_B_DQ<47>
MEM_B_DQ<46>
101A3 15D3
BI
101A3 15D3
BI
MEM_B_DQ<49>
MEM_B_DQ<52>
163
165
159
161
167
101D1 15D1
BI
101D1 15D1 7B7
BI
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
169
171
173
101A3 15D3
BI
101A3 15D3
BI
MEM_B_DQ<54>
MEM_B_DQ<51>
P
175
177
179
101A3 15D3
BI
101A3 15D3
BI
MEM_B_DQ<61>
MEM_B_DQ<60>
101A3 15B3
IN
MEM_B_DM<7>
101A3 15D3
BI
101A3 15D3
BI
MEM_B_DQ<58>
MEM_B_DQ<59>
181
183
185
187
189
6B4
=PPSPD_S0_MEM_B
R3240
10K
MEM_B_SA<0>
MEM_B_SA<1>
C3240
2.2UF
2
191
193
195
5%
1/16W
MF-LF
402
R3241
10K
20%
6.3V
CERM
402-LF
2
5%
1/16W
MF-LF
402
J3200
DDR3-SODIMM
MEM_B_CKE<0>
KEY
(SYMBOL 2 OF 2)
IN
197
199
201
209
20%
10V
CERM
402
CRITICAL
101B3 15A1
0.1UF
20%
6.3V
CERM
402-LF
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
MEM_B_CKE<1>
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_ODT<1>
136
138
140
142
144
146
148
150
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DM<4>
MEM_B_DQ<35>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
e
r
MTG PIN
MTG PIN
MTG PIN
152
154
156
158
160
162
164
166
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<53>
MEM_B_DQ<48>
168
170
172
MEM_B_DM<6>
174
MEM_B_DQ<50>
MEM_B_DQ<55>
176
178
180
182
184
186
188
101B3 15B3
IN
8C4
IN
15C1 101B3
101A3 15A3
BI
BI
IN
IN
15C1 101B3
101B3 15B3 7B7
BI
IN
15C1 101B3
101B3 15B3
BI
IN
15B1 101B3
101B3 15B3 7B7
BI
IN
15B1 101B3
101B3 15B3
BI
IN
15B1 101B3
101D1 15D1
BI
IN
15B1 101B3
101D1 15D1
BI
IN
15B1 101B3
101B3 15B3
BI
IN
15B1 101B3
101B3 15B3
BI
IN
15C1 101B3
101B3 15C3 7B7
BI
IN
15C1 101B3
101B3 15C3
BI
IN
15B1 101B3
101D1 15D1 7B7
BI
IN
15B1 101B3
101D1 15D1
BI
IN
15B1 101B3
101B3 15C3
BI
101B3 15C3
BI
MEM_B_DQ<0>
MEM_B_DQ<1>
7
9
11
MEM_B_DM<0>
13
15
MEM_B_DQ<6>
MEM_B_DQ<7>
17
19
21
MEM_B_DQ<8>
MEM_B_DQ<12>
23
25
27
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
29
31
MEM_B_DQ<10>
MEM_B_DQ<15>
33
MEM_B_DQ<25>
MEM_B_DQ<24>
39
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
45
MEM_B_DQ<26>
MEM_B_DQ<30>
51
53
35
37
41
43
47
49
55
126
128
132
134
15A1 101B3
101B3 15B3
MEM_B_A<15>
MEM_B_A<14>
124
130
IN
3
5
MEM_B_DQ<57>
MEM_B_DQ<56>
BI
15C3 101B3
BI
15C3 101B3
IN
15C3 101B3
BI
15C3 101A3
BI
15C3 101A3
BI
57
59
MEM_B_DQ<20>
MEM_B_DQ<21>
IN
MEM_B_DM<2>
63
65
101B3 15C3 7B7
BI
67
101B3 15B3
BI
MEM_B_DQ<23>
MEM_B_DQ<16>
101A3 15B3
69
71
J3200
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
MEM_B_DQ<4>
MEM_B_DQ<5>
BI
15B3 101B3
BI
15B3 101B3
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
15D1 101D1
BI
15D1 101D1
MEM_B_DQ<3>
MEM_B_DQ<2>
BI
15B3 101B3
BI
15B3 101B3
MEM_B_DQ<9>
MEM_B_DQ<13>
BI
15B3 101B3
MEM_B_DM<1>
MEM_RESET_L
IN
15A3 101A3
IN
33C3 31C2
MEM_B_DQ<11>
MEM_B_DQ<14>
BI
15B3 101B3
15B3 101B3
BI
15B3 101B3
MEM_B_DQ<29>
MEM_B_DQ<28>
BI
15C3 101B3
BI
15C3 101B3
MEM_B_DM<3>
IN
MEM_B_DQ<27>
MEM_B_DQ<31>
BI
15C3 101B3
BI
15C3 101B3
MEM_B_DQ<18>
MEM_B_DQ<17>
BI
15B3 101B3
BI
15B3 101B3
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
BI
15D1 101D1
MEM_B_DQ<19>
MEM_B_DQ<22>
70
72
BI
15B3 101A3
BI
7B7 15D1 101D1
BI
15B3 101B3
BI
15C3 101B3
KEY
BI
15C3 101A3
BI
7B7 15D1 101D1
BI
7B7 15D1 101D1
BI
15C3 101A3
BI
15C3 101A3
BI
15D3 101A3
BI
15D3 101A3
IN
BI
101B3 15C3
61
15B3 101A3
BI
101B3 15C3
VSS
VREFDQ
VSS
DQ4
DQ5
DQ0
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-SM
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
VSS
DQS2
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
DDR3-SODIMM
(SYMBOL 1 OF 2)
15B3 101A3
BI
15D3 101A3
BI
15D3 101A3
BI
15D3 101A3
BI
15D3 101A3
PP0V75_S3_MEM_VREFCA_B
C3235
2.2UF
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
BI
7B7 15D1 101D1
BI
15D1 101D1
MEM_B_DQ<62>
MEM_B_DQ<63>
BI
7B7 15D3 101A3
BI
15D3 101A3
20%
6.3V
CERM
402-LF
29C1
C3236
0.1UF
20%
10V
CERM
402
190
192
194
196
198
200
202
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
OUT
31A5 49B8 21A4 21B3 55C1
BI
IN
52D6
52D6
204
207
208
=PP0V75_S0_MEM_VTT_B
=PP1V5_S3_MEM_B
6D3 108D3 32D7
MTG PIN
C3250
DDR3 SO-DIMM CONNECTOR B
C3251
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
6D4
SYNC_MASTER=K50

516S0657
K50/K51: SPD ADDR=0XA2(WR)/0XA3(RD)
K9: SPD ADDR=0XA4(WR)/0XA5(RD)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
32
109
y
r
a
n
i
DDR3 RESET Support
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
6D3
6D1
=PP1V5_S3_MEMRESET
3.3V input must be stable before
before 1.5V starts to rise to
avoid glitch on MEM_RESET_L.
=PP3V3_S5_MEMRESET
1K
MEMRESET_HW
R3310
R3305
5%
1/16W
MF-LF
402
MEM_RESET_L
20K
MEMRESET_HW
R3300 1
MEM_RESET
10K
5%
1/16W
MF-LF
402
MEMRESET_HW
3
R3301 1
Q3305
MMDT3904-X-G
C3300
0.1UF
2
2
R3309
0
MMDT3904-X-G
1
31C2 32C2
5%
1/16W
MF-LF
402
m
il
MEMRESET_HW
1
20K
IN
Q3305
SOT-363-LF
MEMRESET_HW
16C3
MEMRESET_HW
6
2
OUT
MEMRESET_MCP
SOT-363-LF
MEM_RESET_RC_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
20%
10V
CERM
402
MCP_MEM_RESET_L
e
r
DDR3 Support
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
33
109
y
r
=PP3V3_S3_MINI 6D3
----------------------------------------3.3V S3 CURRENT
D0-D2,D3HOT
D3COLD |
MAX CONT.
1100MA
190MA |
MAX PEAK
2750MA
2750MA |
|
1.5V CURRENT
|
MAX CONT.
N/U
N/U
|
MAX PEAK
N/U
N/U
|
----------------------------------------NOTE: CURRENT DATA PER JAN 12,2008 PCIE MINI CEM ECN
|
|
|
|
|
|
|
NO STUFF
0
F-RT-SM
54
NO STUFF
17B6
R3401
2
5%
1/16W
MF-LF
402
OUT
17C6
102C3 17C3
102C3 17C3
OUT
IN
IN
PCIE_WAKE_L
RSVD_MINI_WLAN_ACTIVE
RSVD_MINI_BT_ACTIVE
MINI_CLKREQ_L
10
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
11
12
13
14
16
15
17B6 102D3 7C8
17B6 102D3 7C8
OUT
PCIE_MINI_D2R_N
OUT
PCIE_MINI_D2R_P
RESERVED
RESERVED
C3431
0.1uF
IN
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_N
102D3 PCIE_MINI_R2D_P
102D3
10%
16V
X5R
402
PLACEMENT_NOTE=PLACE CLOSE TO U1400.
C3430
0.1uF
102D3 17B3
IN
PCIE_MINI_R2D_C_P
2
10%
16V
X5R
402
e
r
17
KEY
NC
NC
NC
NC
NC
20
21
22
23
24
NC
NC
NC
NC
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
20%
10V
CERM 2
402
0.1uF
20%
10V
CERM 2
402
18
19
0.1uF
10uF
20%
6.3V 2
X5R
603
C3400 1 C3401 1
NC
MINI_RESET_L
IN
9C2
=SMBUS_MINI_SCL
=SMBUS_MINI_SDA
IN
52B3
BI
52B3
USB_MINI_N
USB_MINI_P
BI
20D3 103C3
BI
20D3 103C3
m
il
PLACEMENT_NOTE=PLACE CLOSE TO U1400.
102D3 17B3
NC
NC
C3420 1 C3421 1
a
n
i
ASOB226-S80N-7F
5%
1/16W
MF-LF
402
20%
10V
CERM 2
402
J3400
0.1uF
CRITICAL
R3400
1
C3410 1
NC
NC
NC
=PP1V5_S0_MINI 6C4
10uF
20%
6.3V 2
X5R
603
53
516S0391
STANDOFF FOR J3400

CRITICAL
SDF3400
STDOFF-4OD5.6H-1.35-TH
1
860-0691
PCI-E MiniCard Connector

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
34
109
=PP1V05_ENET_PHY
C3710
C3711
10%
16V
X5R
402
=PP3V3_ENET_PHY
38D2
(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
y
r
a
n
i
m
il
0.1UF
38D2
0.1UF
10%
16V
X5R
402
CRITICAL
L3715
FERR-120-OHM-1.5A
0402-LF
(43mA typ - 1000base-T)

(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
C3700
CRITICAL
L3705
FERR-120-OHM-1.5A
C3701
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
C3702
0.1UF
10%
16V
X5R
402
PP1V05_ENET_PHYAVDD
C3714
0402-LF
C3715
0.1UF
0.1UF
10%
16V
X5R
402
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
C3705
0.1UF
C3706
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
C3716
10%
16V
X5R
402
VOLTAGE=1.05V
0.1UF
10%
16V
X5R
402
=PP3V3_ENET_PHY_VDDREG
38C2
If internal switcher is used, must place 1x 22uF &

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
38C2
5%
1/16W
MF-LF
402
39
=RTL8211_ENSWREG
IN
40
10
36
28
45
44
37
21
15
5%
1/16W
MF-LF
402 2
RTL8211CLGR
R3752 1
R3751
4.7K
4.7K
=RTL8211_REGOUT
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
38C2
If internal switcher is not used, VDDREG and REGOUT can float.
U3700
ENSWREG
4.7K
AVDD12
4.7K
DVDD12
5%
1/16W
MF-LF
402 2
Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.
FB12
10K
R3725
VDDREG
NOSTUFF
AVDD33
R3720 1
DVDD33
41
R3750 1
REGOUT
48
RXC
19
TQFP
IN
ENET_TX_CTRL
104D3 18D3
IN
104D3 18C3
BI
ENET_MDC
ENET_MDIO
IN
ENET_RESET_L
IN
1/16W
MF-LF
R3724
1
0
5%
1/16W
MF-LF
402
RTL8211_PHYRST_L
C3725
0.1UF
e
r
RTL8211_RSET
20%
10V
CERM
402
TP_RTL8211_CLK125
R3730 1
2.49K
1%
1/16W
MF-LF
402
104D3 38B2
IN
402
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
22
23
24
25
26
27
30
31
29
46
32
TXC
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RGMII/MII
TXCTL
MDC
MDIO
PHYRSTB*
RSET
RXCTL
REFERENCE
43
16 104D3
17 104D3
18
13
MDI+[1]
MDI-[1]
MDI+[2]
MDI-[2]
MDI+[3]
MDI-[3]
11
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
RESET MEDIA DEPENDENT
104D3
14 104D3
MDI+[0]
MDI-[0]
MANAGEMENT
104D3
104D3
12
R3790
ENET_CLK125M_RXCLK_R
R3791
R3792
R3793
R3794
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
R3795
ENET_RXCTL_R
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
39C8 104D3
BI
39D8 104C3
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
39C7 104D3
BI
39C7 104C3
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
39C6 104D3
BI
39C6 104C3
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
39C5 104D3
BI
39C5 104C3
22
22
22
22
22
22
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
ENET_CLK125M_RXCLK
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
OUT
104D3 18D6
OUT
104D3 18D6
OUT
104D3 18D6
OUT
104D3 18D6
OUT
104D3 18D6
OUT
104D3 18D6
CLK125
CLOCK
42
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
CKXTAL1
CKXTAL2
LED
GND
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
35
38
NO STUFF
C3790
47
IN
IN
104D3 18D3
104D3 18D3
IN
ENET_CLK125M_TXCLK_R
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
104D3 18D3
104D3 18D3
18C3 7D6
5%
104D3 18D3
WF: Verify that ENET_RESET_L does not assert when WOL is active.
If true, RC and 0-ohm resistor should be removed.
If false, ENET_RESET_L should be removed.
22
33
R3780
ENET_CLK125M_TXCLK
IN
20
104D3 18D3
OMIT
CRITICAL
10PF
5%
50V
CERM
402
R3755 1
R3756 1
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3757
4.7K
5%
1/16W
MF-LF
402
Reserved for EMI

per RealTek request.
Ethernet PHY (RTL8211CL)

SYNC_MASTER=K50

Configuration Settings:
SIZE
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
DRAWING NUMBER
(PHY Address 00001)

(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
37
109
SOURCE SELECT
SIGNAL_MODEL=EMPTY
R3880
0
PM_SLP_RMGT_L
21C3
ENET_EN
38A8 38B8
5%
1/16W
MF-LF
402
ENET ALIASES
SIGNAL_MODEL=EMPTY
NO STUFF
y
r
R3881
0
PM_SLP_S4_L
70D8 50C3 49C5 7B4 102B3 21C3
2
5%
1/16W
MF-LF
402
38C5
38B5
PP1V05_RMGT
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_PHY
PP3V3_RMGT
=PP3V3_ENET_PHY
a
n
i
=RTL8211_ENSWREG
MAKE_BASE=TRUE
79C3 7C3 6D2
NC_PP3V3_ENET_PHY_VDDREG
C3800
0.1UF
7C3 6D2 6B8 76C1 38B7
20%
10V
CERM
402
R3800
PP3V3_S5_REG
R3801
20.0K
SSM6N15FEAPE
1%
1/16W
MF-LF
402
SOT563
SI2312BDS
10K
m
il
SOT23
PP1V05_RMGT
R3802
Q3810
69.8K
P1V05ENET_EN_L
Q3810
Q3800
G
1%
1/16W
MF-LF
402
P1V05ENET_SS
@ 1.8V VGS:
RDS(ON) = 47MOHM MAX
I(MAX) = 4.1A
C3801
0.01UF
10%
16V
2 CERM
402
1%
1/16W
MF-LF
402
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
38D5 38A8
IN
e
r
ENET_EN
3.3V ENET FET
38C8 7C3 6D2 6B8 76C1
PP3V3_S5_REG
R3861
P3V3ENET_EN_L
38D5 38B8
IN
ENET_EN
Q3860
2N7002
SOT23-HF1
D
1
0.033UF
10K
5%
1/16W
MF-LF
402
P
C3850
R3860 1
S
2
100K
5%
1/16W
MF-LF
402
10%
16V
X5R
402
SOT-23-HF
PP3V3_RMGT
37D7
37C6
=PP3V3_ENET_PHY_VDDREG
37C2
RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
@ 2.5V VGS:
RDS(ON) = 90MOHM MAX
I(MAX) = 1.7A (85C)
Q3850
NTR4101P
38D3
MAKE_BASE=TRUE
VOLTAGE=1.05V
18D3 18D7 25A5 25B6
37C2
MAKE_BASE=TRUE
NO_TEST=TRUE
PP1V05_S5_REG
37D2
=RTL8211_REGOUT
MAKE_BASE=TRUE
NO_TEST=TRUE
1.05V ENET FET
25A8
NOTE: NOT USING THE BUILT-IN 1.05V REGULATOR OF THE PHY
NC_RTL8211_REGOUT
18D3 25D6
R3895
104D3 18C3
38D3
IN
MCP_CLK25M_BUF0_R
22
OUT
104D3 37B6
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
VOLTAGE=3.3V
C3851
0.01UF
P3V3ENET_SS
10%
16V
CERM
402
Ethernet & AirPort Support

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
38
109
NOTE: DELTA RECOMMENDS CENTER-TAP BE FLOATING WHEN USING REALTEK PHY.
CHIP SIDE
y
r
CRITICAL
T3900
LFE9287APF
SOI
1 TCT1
104C3 37B3
ENET_MDI_N<0>
104D3 37B3
ENET_MDI_P<0>
2 TD1+ 1CT:1CT
a
n
i
3 TD14 TCT2
104D3 37B3
104C3 37B3
5 TD2+ 1CT:1CT
ENET_MDI_P<1>
ENET_MDI_N<1>
6 TD27 TCT3
104D3 37B3
ENET_MDI_P<2>
104C3 37B3
ENET_MDI_N<2>
8 TD3+ 1CT:1CT
9 TD3-
ENET_TCT
104D3 37B3
ENET_MDI_P<3>
104C3 37B3
ENET_MDI_N<3>
10 TCT4
CABLE SIDE
MCT1 24
ENET_MCT1
MX1+ 23
ENET_MDI_T_N<0>
104C3 39A4
MX1- 22
ENET_MDI_T_P<0>
104C3 39A5
ENET_MDI_T_P<1>
104C3 39A5
ENET_MDI_T_N<1>
104C3 39A4
MX3+ 17
ENET_MDI_T_P<2>
104C3 39A4
MX3- 16
ENET_MDI_T_N<2>
104C3 39A5
MCT2 21
ENET_MCT2
MX2+ 20
MX2- 19
MCT3 18
MCT4 15
ENET_MCT3
ENET_MCT4
11 TD4+ 1CT:1CT
MX4+ 14
ENET_MDI_T_P<3>
104C3 39A5
12 TD4-
MX4- 13
ENET_MDI_T_N<3>
104C3 39A4
157S0056 - 8 CORE
m
il
1
C3901
0.1UF
20%
2 10V
CERM
402
C3902
0.1UF
20%
2 10V
CERM
402
ALSO AVAILABLE 157S0057 - 12 CORE
C3903
0.1UF
20%
2 10V
CERM
402
C3904
0.1UF
20%
2 10V
CERM
402
R3900
75
5%
1/16W
MF-LF
2 402
R3901
75
5%
1/16W
MF-LF
2 402
R3902
75
5%
1/16W
MF-LF
2 402
R3903
75
5%
1/16W
MF-LF
2 402
PLACE ONE CAP PER TCT PIN
RTL8211 DOES NOT REQUIRE POWER ON MAGNETICS
e
r
ENET_MCT_BS
NOSTUFF
1
C3900
0.001UF
20%
2KV
2 CERM
1808
NOTE: BOB SMITH TERMINATION FOR EMC INVESTIGATION.
CRITICAL
J3900
RJ45-BLK-HB
F-ANG-TH
9
ETHERNET CONNECTOR
104C3 39C1
ENET_MDI_T_P<0>
104C3 39C1
ENET_MDI_T_P<1>
1
2
ENET_MDI_T_N<0>
SYNC_MASTER=K50

4
104C3 39C1
ENET_MDI_T_N<2>
104C3 39C1
ENET_MDI_T_P<3>
39D1 104C3
ENET_MDI_T_P<2>
39C1 104C3

ENET_MDI_T_N<1>
39C1 104C3
ENET_MDI_T_N<3>
39C1 104C3

10
SIZE
11
514-0639
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7840
10
OF
39
109
=PP3V3_FW_FWPHY
7 mA I/O
C4120
C4121
C4122
C4123
C4124
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
6D3 42C8 41B1 42B7 43A5 43B8
138 mA
L4130
120-OHM-0.3A-EMI
114 mA FireWire PHY
L4110
1
VOLTAGE=1.0V
C4110
1UF
10%
6.3V
CERM
402
110 mA Digital Core
C4131
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
C4100
1UF
10%
6.3V
CERM
402
C4132
17 mA PCIe SerDes
C4111
C4135
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
PP3V3_FW_FWPHY_VP25
C4136
VOLTAGE=3.3V
0402-LF
1UF
10%
6.3V
CERM
402
0 mA VReg PWR
C4101
C4102
C4103
C4104
C4105
C4106
C4141
1UF
1UF
1UF
1UF
1UF
1UF
1UF
0.1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
20%
10V
CERM
402
120-OHM-0.3A-EMI
2
0402-LF
2
0402-LF
L4135
120-OHM-0.3A-EMI
=PP1V0_FW_FWPHY
135 mA
PP3V3_FW_FWPHY_VDDA
VOLTAGE=3.3V
y
r
a
n
i
m
il
C4130
42D4
C4140
1UF
10%
6.3V
CERM
402
R4161 1
2.94K
1%
1/16W
MF-LF
402
22PF
2
R4162 1
470K
P
7B3
R4170
191
5%
50V
CERM
402
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
7B3
7B3
42C8
C4162
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
N13
J2
L13
D12
D1
A10
H13
K13
TP_FW643_OCR10_CTL
0.33UF
M13
10%
6.3V
CERM-X5R
402
J12
NC
J13
L9
L6
L5
L10
D8
D6
D5
M2
A12
L3
J1
K12
FW643_TRST_L
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
M1
X5R 402
2
10%
16V
0.1UF
X5R 402
C41761
10%
2
16V
0.1UF
IN
7D6 17C3 102C3
IN
7D6 17C3 102C3
IN
17B3 102C3
PCIE_FW_R2D_C_P
IN
17B3 102D3
PCIE_FW_D2R_N
OUT
7C8 102C3 17B6
PCIE_FW_D2R_P
OUT
7C8 102C3 17B6
X5R 402
PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100

PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100
7B3
7B3
=PP3V3_FW_FWPHY
6D3 42C8 41D2 42B7 43A5 43B8
7B3
7B3
NOSTUFF
C2
D13
E1
D2
L2
R4165 1
FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L
OUT
19B7
OUT
17C6
R4166
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
R4164
NAND_TREE
REXT
XO
XI NT-9
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show

NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
MISCELLANEOUS
CHIP RESET
NT-5 PERST*
IN
1
7D6 9C2 7B3
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
VREG_VSS
5%
1/16W
MF-LF
402
L12
HC49-USMD
G13
N1
N2
0.1UF
C41751
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
NT-2 (IPU) TRST*
K6
24.576M
L8
F13
N9
N10
M3
K10
Y4150
K1
L7
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
R0
TPCPS
102C3
10%
2
16V
5%
1/16W
MF-LF
2 402
K9
C4151
CRITICAL
1%
1/16W
MF-LF
402
B10
102C3
N6
PCIE_FW_R2D_C_N
X5R 402
C41711
10K
K8
B11
K7
5%
50V
CERM
402
e
r
FW643_R0
FW643_TPCPS
412
1
A2
TPBIAS0
TPBIAS1
TPBIAS2
K5
FW_CLK24P576M_XO
C3
K4
B7
N5
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
BI
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
N7
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
42B3
R4150
BI
7B3
22PF
1
BI
42B3
A4
J5
C4150
42D4
B4
J4
5%
1/16W
MF-LF
402
BI
H8
390K
BI
42A3
H10
R4160 1
42A3
N8
M4
NT-10 (IPD)
H7
=PPVP_FW_PHY_CPS
A6
H6
43B3
BI
B6
REFCLKN
REFCLKP
1394 PHY
H4
42B3
BI
A9
G8
42B3
B9
G10
BI
G7
BI
42C3
G6
BI
42C3
A3
G4
42B3
B3
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
TEST CONTROLLER
F8
BI
A5
F10
42B3
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F7
BI
A8
F6
BI
42B3
B8
F4
42B3
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
10%
2
16V
0.1UF
VREG_PWR
PCI EXPRESS PHY
E9
BI
VP25
BGA
E5
BI
42C3
E13
E4
42C3
E12
D10
IN
VP
FW643
DS0 (IPD) NT-19

DS1 (IPD) NT-20
DS2 (IPD) NT-21
D9
IN
42B7
F12
VDDH
VDD33
OMIT
CRITICAL
U4100
D7
42B7
FW_PHY_DS0
FW_PHY_DS1
FW_PHY_DS2
A11
ATBUSB
ATBUSH
ATBUSN
D4
IN
A13
B2
42B7
B13
L11
F1
VDD10
NC
NC
NC
G12
C1
C12
N3
N11
L1
K2
M12
H2
H12
E2
E10
B1
C13
A1
B12
PLACEMENT_NOTE=Place C4170 close to U1400

PLACEMENT_NOTE=Place C4171 close to U1400
C41701
FireWire LLC/PHY (FW643)

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
41
109
Termination
y
r
Place close to FireWire PHY
FW643 1.0V GENERATION

41B6
FW_P0_TPBIAS
VOLTAGE=1.86V
CRITICAL
Q4200
BCP6916DG
PP1V0_FW_VDD
MAX_NECK_LENGTH=3MM
MAKE_BASE=TRUE
VOLTAGE=1.0V
2
=PP3V3_FW_FWPHY
C4210
20%
2 10V
CERM
402
0.1UF
C4200
2.2UF
20%
2 6.3V
CERM
402-LF
C4201
C4211
0.1UF
20%
2 10V
CERM
402
C4212
10UF
20%
2 6.3V
CERM
805-1
C4213
10UF
20%
2 6.3V
CERM
805-1
=PP1V0_FW_FWPHY
C4250 R42501
0.33UF
41D7
R4251
56.2
10%
6.3V
2 CERM-X5R
402
SOT223-4
43B8 43A5 42B7 41D2 41B1 6D3
1%
1/16W
MF-LF
402 2
56.2
1%
1/16W
MF-LF
2 402
a
n
i
2.2UF
FW_P0_TPA_P
41C6 FW_P0_TPA_N
41B6 FW_P0_TPB_P
41B6 FW_P0_TPB_N
41B6
20%
2 6.3V
CERM
402-LF
NOTE: MULTIPLE VIAS TO DGND

NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINK
R42521
56.2
1%
1/16W
MF-LF
402 2
R4200
41A6
TP_FW643_OCR10_CTL
FW643_OCR10_CTL
MAKE_BASE=TRUE
75
FW_OCR10_CTL_R
5%
1/16W
MF-LF
402
m
il
e
r
=PP3V3_FW_FWPHY
NOSTUFF
R4255 1R4256 1R4257
41C6
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
FW_PHY_DS0
41C6
FW_PHY_DS1
41C6
FW_PHY_DS2
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643
HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY.
R4258
10K
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N
43B5 105D3
43C5 105D3
43C5 105D3
43C5 105D3
MAKE_BASE=TRUE
R4253
56.2
1%
1/16W
MF-LF
2 402
FW_P0_TPA_C
1394 PHY DATA/STROBE OPTIONS

43B8 43A5 41D2 41B1 42C8 6D3
C4254 1
220PF
5%
25V
CERM 2
402
R4254
4.99K
1%
1/16W
MF-LF
2 402
2ND & 3RD TPA/TPB PAIR UNUSED

41B6
FW_P1_TPBIAS
NC_FW_PORT1_TPBIAS
41B6
FW_P1_TPA_P
NC_FW_PORT1_TPA_P
41B6
FW_P1_TPA_N
NC_FW_PORT1_TPA_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
41B6
FW_P1_TPB_P
NC_FW_PORT1_TPB_P
MAKE_BASE=TRUE
NO_TEST=TRUE
41B6
NC_FW_PORT1_TPB_N
FW_P1_TPB_N
MAKE_BASE=TRUE
NO_TEST=TRUE
41B6
FW_P2_TPBIAS
NC_FW_PORT2_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
41B6
FW_P2_TPA_P
NC_FW_PORT2_TPA_P
41B6
FW_P2_TPA_N
NC_FW_PORT2_TPA_N
41B6
FW_P2_TPB_P
NC_FW_PORT2_TPB_P
41B6
FW_P2_TPB_N
NC_FW_PORT2_TPB_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NOTE: AGERES RECOMMENDATION FOR UNUSED PORTS
FW: 1394B MISC

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
42
109
R4300
NOSTUFF 1
10%
1W
MF
2512
CRITICAL
DE4300
SM
6C1
=PP12V_S5_FW
CRITICAL
VOLTAGE=12V
CRS08-1.5A-30V
5%
1/8W
MF-LF
805
12 VOLTS
7 WATTS MAX PER PORT
NOSTUFF
VOLTAGE=12V
2
SM
FW_PORT0_VP_F
VOLTAGE=12V
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS_FET
y
r
a
n
i
m
il
SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
FERR-250-OHM
0.75AMP-30V
PPVP_FW_PHY_CPS
R4301
1
CRITICAL
L4300
F4300
R4302
FW_PORTS_VP
1.00 2CRITICAL
43B6
FW_PORT0_VP
VOLTAGE=12V
SM
C4300
0.01UF
1.00 2
10% CRITICAL
1W
MF
2512
43B6 43B5
PP3V3_FW_ESD "Snapback"
& "Late VG" Protection

CRITICAL
DP4310
CRITICAL
DP4310
BAV99DW-X-G
SOT-363
5
BAV99DW-X-G
SOT-363
2
C4310 1
0.01UF
C4311
0.01UF
10%
50V
X7R 2
402
10%
50V
2 X7R
603-1
10%
50V
X7R 2
402
PORT 0
1394B
105D3 42C2
FW_PORT0_TPB_N
105D3 42C2
FW_PORT0_TPB_P
105D3 42C2
FW_PORT0_TPA_N
105D3 42C2
FW_PORT0_TPA_P
FW_PORT0_TPA_R
43C5 43B6
PP3V3_FW_ESD
CRITICAL
ESD Rail
R4390
[ LATE VG NOTES ]
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP
e
r
CRITICAL
D4390
SOT23
1
43B5 43C5
VOLTAGE=3.3V
MMBZ5227BLT1H
43C6
C4312 1
0.01UF
C4313
12
10
1
9
2
8
7
6
3
5
4
TPBTPB<R>
TPB+
VP
NC
VG
TPATPA<R>
TPA+
11
13
15
514-0542
0.001UF
10%
50V
CERM 2
402
0.01UF
10%
50V 2
X7R
402
10%
50V 2
X7R
402
R43351
1M
1%
1/16W
MF-LF
402 2
C4335
0.1UF
10%
50V
2 X7R
603-1
Q4351
BSS84
S0T23-3-HF
=PPVP_FW_PHY_CPS_FET
PPVP_FW_CPS
D
3
PP3V3_FW_ESD
1%
1/16W
MF-LF
402
C4332
F-ANG-TH
14
=PPVP_FW_PHY_CPS
41B7
MAKE_BASE=TRUE
VOLTAGE=12V
332
NOSTUFF
SOT-363
5
1394B-K2
R4350
470K
DP4311
BAV99DW-X-G
SOT-363
2
=PP3V3_FW_FWPHY
DP4311
BAV99DW-X-G
43A5 42B7 41D2 41B1 42C8 6D3
CRITICAL
CRITICAL
J4300
5%
1/16W
MF-LF
2 402
FWPHY_CPS_EN_R
1
R4351
330K
5%
1/16W
MF-LF
2 402
FIREWIRE CONNECTOR
FWPHY_CPS_EN
SYNC_MASTER=K50
3
D
43B8 42B7 41D2 41B1 42C8 6D3
=PP3V3_FW_FWPHY
Q4350
2N7002

SOT23-HF1

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
43
109
SATA PORT A0 FOR HDD
y
r
CRITICAL
J4510
EP00-081-91
C4510
M-ST-SM
1
102C3
102C3
2
10%
0.01UF
C4511
SATA_HDD_R2D_P
SATA_HDD_R2D_N
16V
CERM
0.01UF
SATA_HDD_R2D_C_P
IN
20D6 102C3
SATA_HDD_R2D_C_N
IN
20D6 102C3
402
10%
16V
CERM
402
10%
16V
CERM
402
SATA Activity LED
4
5
102C3
102C3
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
C4515
J4520
2
10%
0.01UF
518S0251
CRITICAL
0.01UF
C4516
16V
CERM
SATA_HDD_D2R_N
OUT
7B8 102C3 20D6
SATA_HDD_D2R_P
OUT
7B8 102C3 20D6
6B4
SATA PORT A1 FOR SLIMLINE ODD
47300-1042
20B6
F-RT-SM
14
50D3 49B8
15
C4517
S1
S2
S3
0.01UF
102C3
C4518
SATA_ODD_R2D_P
SATA_ODD_R2D_N
16V
CERM
402
10%
16V
CERM
402
10%
16V
CERM
402
0.01UF
102B3
10%
SATA_ODD_R2D_C_P
IN
20D6 102C3
SATA_ODD_R2D_C_N
IN
20D6 102C3
S4
S5
S6
102B3
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
0.01UF
P1
P2
0.01UF
C4520
S7
KEY
C4519
102B3
=PP5V_S0_SATA
10%
16V
CERM
SATA_ODD_D2R_N
OUT
7B8 102B3 20D6
SATA_ODD_D2R_P
OUT
7B8 102B3 20D6
6A4 6D6
=PP3V3_S0_ODD
P4
1
1C4531
C4530
P5
0.1UF
10%
2 25V
X5R
402
P6
R4530
0.1UF
10%
2 25V
X5R
402
33K
5%
1/10W
MF-LF
603
16
DEVELOPMENT
TP_MCP_SATALED_L
R4599 1
330
5%
1/10W
MF-LF
603
MCP_SATALED_R_L
DEVELOPMENT
DS4599
GREEN-3.6MCD
2.0X1.25MM-SM
2
SILK_PART=SATA ACTIVE
MCP_SATALED_L
MAKE_BASE=TRUE
SMC_EXCARD_OC_L
m
il
402
P3
=PP3V3_S0_SATALED
a
n
i
402
SMC_ODD_DETECT
518S0602
6B4
49B8
e
r
SATA Connectors
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
45
109
46C8 6C3
20C2
USB_EXTC_OC_L
CRITICAL
TPS2060
2
IN
OUT2 6
EN1*
OC2*
R4600
10K
6D1
0.1UF
20%
10V
2 CERM
402
0.01uF
20%
16V
CERM
402
C4631
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
USB_PWR_ENA_L
NOSTUFF
CRITICAL
1
C4621
PP5V_USB2_PORT3_F
VOLTAGE=5V
C4630
(PUT CAP ON CONNECTOR SIDE)
=PP3V3_S5_SMCUSBMUX
2
SM
GND TPAD
5%
1/16W
MF-LF
2 402
PP5V_USB2_PORT3
VOLTAGE=5V
USB/SMC DEBUG MUX
EN2*
0.1UF
L4630
FERR-250-OHM
OC1*
C4605
CRITICAL
OUT1
MSOP
U4601
C4650
0.1UF
CRITICAL
y
r
a
n
i
m
il
20%
10V
2 CERM
402
C4606
CRITICAL
150UF
20%
2 6.3V
POLY-TANT
CASE-D2-SM
50D3 49C5 49B8 7C4 51C4
51C5 50D3 7D4 49C5 49B8
SMC_RX_L
SMC_TX_L
M+
M-
F-ANG-TH
5
6
L4631
120-OHM-90MA
DLP0NS
Y+
U4650
J4630
USB-K50
CRITICAL
VCC
103C3
USB_D_MUXED_N
103C3
USB_PORT3_N
PI3USB102ZLE
103C3 20D3
USB_EXTD_P
USB_EXTD_N
D+
TQFN
103C3
103C3
USB_PORT3_P
USB_DEBUGPRT_EN_L
SEL=0: CHOOSE SMC
SEL=1: CHOOSE USB
SEL
2N7002
6 VBUS
SOT23-HF1
NOSTUFF
R4652
1
514-0640
1 GND
R4651
2 5 3 4
NOSTUFF
PM_EN_USB_PWR
49B8
50D3
GND
Q4600
3
9A6
D-
OE*
USB_D_MUXED_P
VBUS
DD+
GND
NC
IO
NC
IO
103C3 20D3
VDD
DD+
GND
SYM_VER-1
Y-
PORT 3
USB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2

PREVIOUSLY, PORT 3 HAD ITS OWN BUT EFI MAPS THAT TO EXPRESSCARD
SEE RDAR://6250424
=PP5V_S3_USB
D4630
5%
1/16W
MF-LF
402
RCLAMP0502N
SLP1210N6
CRITICAL
5%
1/16W
MF-LF
402
CRITICAL
L4620
FERR-250-OHM
USB_EXTA_OC_L
8
3
20C2
USB_EXTB_OC_L
CRITICAL
OUT1 7
PP5V_USB2_PORT1
VOLTAGE=5V
OC2*
EN2*
C4610
GND TPAD
1
C4601
0.1UF
20%
10V
2 CERM
402
0.01uF
20% (PUT CAP ON CONNECTOR SIDE)
16V
C4603
0.1UF
NOSTUFF
CRITICAL
20%
2 10V
CERM
402
C4602
150UF
C4611
CERM
402
0.1UF
20%
10V
2 CERM
402
CRITICAL
J4610
20%
2 6.3V
POLY-TANT
CASE-D2-SM
USB-K50
F-ANG-TH
5
CRITICAL
L4611
120-OHM-90MA
DLP0NS
SYM_VER-1
103C3 20C3
103C3 20C3
USB_EXTB_P
e
r
USB_EXTB_N
103C3
103C3
103D3 20D3
103D3 20D3
USB_EXTA_N
USB_PORT1_N
USB_PORT1_P
3
4
CRITICAL
J4620
USB-K50
F-ANG-TH
5
CRITICAL
L4621
120-OHM-90MA
DLP0NS
VDD
DD+
GND
SYM_VER-1
103C3 20C3
103C3 20C3
USB_EXTC_N
USB_EXTC_P
VBUS
DD+
GND
20%
16V
CERM
402
103C3
103C3
USB_PORT2_N
USB_PORT2_P
6 VBUS
VBUS
DD+
GND
7
8
514-0640
2 5 3 4
6 VBUS
D4620
514-0640
1 GND
RCLAMP0502N
SLP1210N6
CRITICAL
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
FERR-250-OHM
1
SM
PP5V_USB2_PORT0_F
VOLTAGE=5V
C4600
0.01uF
20% (PUT CAP ON CONNECTOR SIDE)
16V
CERM
402
CRITICAL
J4600
USB-K50
F-ANG-TH
5
CRITICAL
L4601
120-OHM-90MA
DLP0NS
VDD
DD+
GND
SYM_VER-1
103C3
103D3
USB_PORT0_N
USB_PORT0_P
1
2
3
4
VBUS
DD+
GND
EXTERNAL USB CONNECTORS

SYNC_MASTER=K50
NC
IO
NC
IO

1 GND

514-0640
SIZE
RCLAMP0502N
APPLE INC.
SLP1210N6
REV.
051-7840
SCALE
SHT
NONE
CRITICAL
DRAWING NUMBER
D4600
2 5 3 4
1 GND
2 5 3 4
6 VBUS
L4600
USB_EXTA_P
VDD
DD+
GND
CRITICAL
PP5V_USB2_PORT0
VOLTAGE=5V
VOLTAGE=5V
SM
PP5V_USB2_PORT1_F
C4620
0.01uF
(PUT CAP ON CONNECTOR SIDE)
FERR-250-OHM
OUT2 6
EN1*
L4610
MSOP
OC1*
PORT 1
20C2
IN
PORT 0
PP5V_USB2_PORT2_F
VOLTAGE=5V
PORT 2
TPS2060
=PP5V_S3_USB
SM
NC
IO
NC
IO
U4600
46D8 6C3
PP5V_USB2_PORT2
VOLTAGE=5V
CRITICAL
NC
IO
NC
IO
10
OF
46
109
CAMERA POWER FILTERING
K37L (BLUETOOTH) CONNECTOR
CRITICAL
L4700
53398-8604
FERR-250-OHM
47B4 6C3
=PP5V_S3_BNDI
M-ST-SM
5
2
SM
103C3
PP5V_S3_BNDI
VOLTAGE=5V
C4700
47B6
103C3
20%
6.3V
2 CERM
805-1
0.1UF
20%
10V
CERM 2
402
LAYOUT NOTE:
PLACE C4700, C4701 & L4700
NEAR J4700 PINS 4 AND 5 IN THE
ORDER LISTED, AND NOT ON
BOTH SIDES OF THE PIN.
m
il
CAMERA CONNECTOR
CRITICAL
L4701
e
r
SYM_VER-1
USB_CAMERA_P
USB_CAMERA_L_P
103C3 USB_CAMERA_L_N
103C3
SB HAS INTERNAL 15K PULL-DOWNS

103C3 20D3 7B8 USB_CAMERA_N
47D5
2
3
C4721
0.1UF
20%
10V
2 CERM
402
a
n
i
C4701 1
103C3 20D3 7B8
C4720
10UF
120-OHM-90MA
DLP0NS
10UF
PP5V_S3_BNDI
103C3 20D3
103C3 20D3
USB_IR_N
USB_IR_P
47D8 6C3
=PP5V_S3_BNDI
CRITICAL
J4700
STDOFF-4.0OD6.5H-1.35-2.4-TH
1
IR RECEIVER
CRITICAL
L4702
120-OHM-90MA
SYM_VER-1
103B3
CRITICAL
L4703
FERR-250-OHM
1
998-2240
ZH4731
7P5R2P1-NSP
1
CRITICAL
J4780
53398-8604
M-ST-SM
5
DLP0NS
4
103C3
USB_IR_L_N
USB_IR_L_P
PP5V_S3_BNDI_IR
VOLTAGE=5V
1
2
998-2240
ZH4741
3
4
7P5R2P1-NSP
1
SM
1
C4781
1UF
53398-8605
M-ST-SM
6
CRITICAL
SDF4721
MCP HAS INTERNAL 15K PULL-DOWNS

20C3 7B8 USB_BT_N
20D3 7B8 USB_BT_P
6D3 =PP3V3_S3_BT
20%
6.3V
2 CERM
805-1
y
r
J4720
CRITICAL
10%
6.3V
CERM
402
1
2
3
4
5
518S0553
Internal USB Connections

SYNC_MASTER=K51

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
47
109
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
50B7
50D7 50D1 6D1
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
y
r
a
n
i
m
il
C4902
22UF
20%
6.3V
CERM
805
U4900
50D5
OUT
ESTARLDO_EN
D10
SMC_P24
SMC_P26
7D4 103D3 51D5 19B3
BI
BI
7D4 103D3 51D4 19B3
BI
7D4 103D3 51D4 19B3
BI
51D5 7D4 103D3 19C3
IN
9D2 7D6
IN
103D3 9B2
7D4 51D4 19B7
IN
BI
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
50D5
BI
OUT
OUT
50D5
OUT
51C5 50D3 7D4 49C5 46D5
OUT
B7
A8
D8
D7
D6
50D3 49C5 7C4 51C4 46D5

52D5
IN
BI
D4
A5
(OC)
B4
A1
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
E10
C8
NC
NC
50C5
E12
D9
50D5
52C3
F11
A9
NC
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
D12
F13
NC
7D4 103D3 51D5 19B3 7D6 7B8
E11
E13
NC
50D5
D13
C12
NC
NC
NC
50D5
C13
C2
B2
C1
C3
G2
F3
(OC)
E4
P20
P21
P22
P23
P24
P25
P26
P27
P70
P71
P72
P73
P74
P75
P76
P77
N10
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P30
P31
P32
P33
P34
P35
P36
P37
P80
P81
P82
P83
P84
P85
P86
A7
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
J4
J12
J10
M11
L10
N11
N12
M13
N13
B6
NC
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLPS3_BUF2_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
C7
D5
A6
B5
C6
P40
P41
P42
P43
P44
P45
P46
P47
G3
H2
G1
H4
G4
F4
F1
P50
P51
P52
U4900
(DEBUG_SW_1)
(DEBUG_SW_2)
28B8 7C3 7C8
50D3 46D4
55C1 21B3 21A4 32A5 31A5
B
50D3
21C7
SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
50C3 SMC_PA5
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT
50D3
N3
50D3
N1
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
M3
M2
N2
L1
K3
L2
B8
NC
21C7
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
IN
50C3 SMC_PB3
(See below)
SMC_EXCARD_CP
IN
C9
OUT
45B5
50A6
B9
A10
C10
B10
NC
50D3 45C3
IN
50C5 50C3
IN
56D8
OUT
56B8
OUT
57D8
OUT
50D3
OUT
56C8
IN
56A8
IN
57C8
IN
50D3
IN
50C5
IN
50C5
IN
50D5
IN
50C5
IN
50C5
IN
50C5
IN
50D5
IN
50D5
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
C11
A11
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
M10
G13
F12
H13
G10
G12
H11
J13
N9
K10
L8
M9
N8
K9
L7
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
H12
SMC_VCL
R4999
NC
J11
50D5
SMC_ADAPTER_EN
K13
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
OUT
50B1
IN
50D3
IN
53C6
IN
53D6
IN
53C3
IN
53D3
IN
50C5
IN
50C5
IN
50C5
IN
50C5
OUT
21C7
OUT
IN
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
C4907
C4920
AVCC
U4900
IN
50C8
50C8
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
HS82117
LGA-HF
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
K1
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
PH0
PH1
PH2
PH3
PH4
PH5
E2
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
e
r
J3
K2
J1
K4
K5
NC
SMC_SYS_LED
SMC_LID
M6
L5
M5
NC
NC
SMC_MCP_SAFE_MODE
N4
L4
M4
NC
NC
NC
N7
K8
K7
K6
N6
M7
L6
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
F2
J2
A4
B3
C4
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
XTAL
EXTAL
A2
MD1
MD2
D1
NMI
E3
ETRST
H3
AVSS
L9
R4901
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
51C5 7D4
SMC_NMI
IN
51C4 7D4
SMC_TRST_L
IN
7D4 51C5
SMC_KBC_MDE
H1
VSS
52C3
IN
50C5 50D3
IN
50D3
IN
50D3
XW4900
SM
R4902
NO STUFF
1
R4998
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
6C8 9D6 50C3 70C8
IN
21C3 102B3 7B4 38D7 50C3 70D8
IN
50C3
IN
9B2 103D3
NOTE: P94 and P95 are shorted, P95 could be spare.
GND_SMC_AVSS
50B7 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54A4 54B4
54C3 54D3
52D5
IN
50C3
IN
51D4 7D4 50D3

51D4 7D4 50D3
OUT
51D5 7D4 50D3
IN
51D5 7D4 50D3
OUT
50A5
IN
50D3
OUT
50B5
IN
50D3
BI
52C3
BI
52C3
BI
52D3
BI
52D3
BI
52C5
BI
R4909 1
NC
LGA-HF
7C8 51D5 7D4 19B7
46D5 51C4 7C4 49B8 50D3
IN
E5
19C3 7C4 51D4
IN
BI
NC
(3 OF 3)
OMIT
7D4 51C4 50D6 7D6
10%
6.3V
CERM-X5R
402
VCL AVREF
HS82117
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
OUT
IN
VCC
0.47UF
0.1UF
20%
10V
CERM
402
46D5 49B8 7D4 50D3 51C5
BI
5%
1/16W
MF-LF
402
21C7 50D3
IN
4.7
E1
OUT
OUT
D11
K11
NC
NC
NC
L11
21C7
71C7 7C4
OUT
(1 OF 3)
OMIT
K12
20%
10V
CERM
402
H10
NC
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
21B7
L13
LGA-HF
M1
B13
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
HS82117
0.1UF
20%
10V
CERM
402
B1
A12
P10
P11
P12
P13
P14
P15
P16
P17
0.1UF
C5
IN
A13
20%
10V
CERM
402
C4906
B11
IN
70C1
B12
0.1UF
20%
10V
CERM
402
F10
70B1
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD_SMC
RSMRST_PWRGD
0.1UF
C4905
M12
OUT
C4904
L3
OUT
D2
50D5
50D5
C4903
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
52C5
OUT
50B3
OUT
50A2
OUT
50D5
50D3
NC
NC
BROKE SYNC FROM T18 ON 7/1/08; K50 NOW MASTER
SMC
SYNC_MASTER=K50

SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
49
109
50D7 49D4 6D1
49A8
SMS_Z_AXIS
49A8
ALS_LEFT
NC_SMS_Z_AXIS
NO_TEST=TRUE
MAKE_BASE=TRUE
=PP3V3_S5_SMC
SMC_ONOFF_L
SMC_LID
SMC_PH2
SMC_TX_L
SMC_RX_L
SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_EXCARD_OC_L
SMC_PA0
SMC_PA1
SMC_BIL_BUTTON_L
SMC_FAN_3_CTL
SMC_FAN_3_TACH
SMC_BC_ACOK
SMC_ADAPTER_EN
USB_DEBUGPRT_EN_L
49C5 50C5
TP_ALS_LEFT
49B5
MAKE_BASE=TRUE
49A8
C5000
CRITICAL
0.1uF
20%
10V
CERM
402
DEVELOPMENT
S5000
EVQQXT03W
NCP303LSN
SOT23-5-HF
7C3
SMC_MANUAL_RST_L
NC
C5001
CD
NC
GND
10%
16V
CERM
402
TP_ALS_RIGHT
51C5 7D4 49C5 49B8 46D5
R5000
49C5 49B8 7C4 51C4 46D5
UNUSED TP/NC ALIASES
5%
1/16W
MF-LF
402
49B8
49C5
49A5
ALS_GAIN
NC_ALS_GAIN
49B5 7D4 51D5
NO_TEST=TRUE
TP_SMC_PM_G2_EN
MAKE_BASE=TRUE
SMC_RESET_L
OUT
7D6 51C4 7D4 49C3

49D5
SMC_PM_G2_EN
7D4 51D5 49B5
MAKE_BASE=TRUE
49C8
0.01UF
3
OUT
IN
49A5
MAKE_BASE=TRUE
SM-HF
1
ALS_RIGHT
1K
U5000
SMC_SYS_KBDLED
49B5 7D4 51D4
TP_SMC_SYS_KBDLED
49B5 7D4 51D4
MAKE_BASE=TRUE
SMC_EXCARD_PWR_EN
49C8
SMS_ONOFF_L
49D8
SMC_RSTGATE_L
TP_SMC_EXCARD_PWR_EN
49B8
TP_SMS_ONOFF_L
49B8
MAKE_BASE=TRUE
SILK_PART=SMC RESET
49C5
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
49C8
SMC_P24
49C8
SMC_P26
49A8
TP_SMC_P24
49A8
MAKE_BASE=TRUE
49C8
SILK_PART=PWR BTN
POWER_BUTTON_L
Y5020
20.000M
SM-4
49C3
518S0550
ESTARLDO_EN
TP_ESTARLDO_EN
=SMC_SMS_INT
49B5
R5091
SMC_SMS_INT
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
49C5
SMC_DCIN_ISENSE
49C5
SMC_PBUS_VSENSE
SMC_12V_S0_ISENSE
53B1
SMC_12V_S0_VSENSE
49C5
SMC_BATT_ISENSE
54D6 53D5 6B4
53B2
SMC_12V_S5_ISENSE
49C5
SMC_NB_MISC_ISENSE
53B1
MAKE_BASE=TRUE
CRITICAL
49B8
SMC_12V_S5_VSENSE
53B4
MAKE_BASE=TRUE
R5010
1K
1
S5010
SMC_ONOFF_L OUT
2
5%
1/16W
MF-LF
402
DEVELOPMENT
5%
50V
CERM
402
=PP3V3_S5_SMC
=PP3V3_S0_SMC
MAKE_BASE=TRUE
22PF
SMC_EXTAL
49B8 46D4
MAKE_BASE=TRUE
C5021
TP_SMC_P41
NO STUFF
ANALOG SENSORS
2
5%
50V
CERM
402
CRITICAL
SMC_P41
21C7 49D5
MAKE_BASE=TRUE
M-ST-SM
3
22PF
1
49C8
53398-8602
C5020
SMC_XTAL
10K
100K
10K
10K
100K
2.0K
100K
10K
10K
10K
10K
10K
10K
10K
10K
100K
100K
10K
10K
10K
MAKE_BASE=TRUE
J5010
49C3
49C5
TP_SMC_P26
MAKE_BASE=TRUE
POWER BUTTON
R5032
R5033
R5034
R5035
R5036
R5037
R5038
R5039
R5040
R5041
R5042
R5043
R5096
R5090
R5092
R5095
R5097
R5047
R5049
R5098
y
r
a
n
i
m
il
49D8
49B8 45C3
MAKE_BASE=TRUE
SMC Crystal Circuit
UNUSED TP/NC ALIASES - PORT D - INTERNAL PULLUPS
SMC Reset Button / Brownout Detect

50D1 49D4 6D1
SMS_X_AXIS
SMC_1V5_S0_VSENSE
49A8
SMS_Y_AXIS
49A8
SMC_NB_DDR_ISENSE
SMC_GFX_OVERTEMP_L
R5099
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1/16W
54C3
MAKE_BASE=TRUE
49C5 50D3
C5010
SMC_MCP_CORE_VSENSE
SMC_1V5_S0_ISENSE
54B4
49A8
20%
10V
CERM
402
SMC_NB_CORE_ISENSE
SMC_MCP_CORE_ISENSE
70C8 49C5 9D6 6C8
54B4
MAKE_BASE=TRUE
R5046
R5094
R5088
SMC_CASE_OPEN
PM_SLPS3_BUF2_L
ISENSE_CAL_EN MAKE_BASE=TRUE
SMC_PB3
PM_SLP_S4_L MAKE_BASE=TRUE
PM_SLP_S5_L
49B5
54D3
MAKE_BASE=TRUE
0.1UF
SM-HF
53B8
49B8
70D8 49C5 38D7 7B4 102B3 21C3

49C5
SMC_PA5
10K
MAKE_BASE=TRUE
EVQQXT03W
1
49A8
50C5 49B8
R5093
10K
100K
100K
R5089
100K
5%
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MISC. SIGNAL ALIASES
SMC PROCHOT 3.3V LEVEL SHIFTING
49A8
SILK_PART=SYS POWER
SMC_ANALOG_ID
ACDC_TEMP
6D6
MAKE_BASE=TRUE
SMC AVREF Supply
50C3 49B8
SMC_GFX_OVERTEMP_L
50B4 50A8 6B4
MXM_ALERT_L
=PP3V3_S0_SMC_LS
85B8
MAKE_BASE=TRUE
CRITICAL
49C8
SMC_GFX_THROTTLE_L
MXM_PWR_LEVEL
13D6 12B3 11C6 10D5 6D4
85B8
=PP1V05_S0_CPU
VR5065
=PP5V_S5_AVREF
6C1
PP3V3_S5_AVREF_SMC
SOT23-3
1
IN
OUT
R5020
49D4
VOLTAGE=3.3V
1
3
C5065
C5066
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
C5067
10%
16V
CERM
402
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
1
353S1381
353S1278
ALL
Intersil ISL60002-33
e
r
49C2 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54A4 54B4
54C3 54D3
VOLTAGE=0V
49B5
SMC_MCP_SAFE_MODE
=PP3V3_S0_SMC_LS
1
1
R5061
1K
R5064
62K
LOW: -0.3V TO 0.5V

HIGH: 2.0V TO 3.6V
FROM HDD
55D6
HDD_OOB_TEMP
IN
R5063 1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
TO SMC
SMC_HDD_OOB_TEMP
MAKE_BASE=TRUE
R5060
1
3.3K
HDD_OOB_TEMP_R
MMBT3904G
2
200K
5%
1/16W
MF-LF
402 2
TO SMC
SMC_PROCHOT_3_3_L
R5070
3.3K
21A4 21B3
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
MCP_SPKR
TO CPU
100B3 14B6 10C5
R5071
CPU_PROCHOT_L
BI
3.3K
49D5
Q5077
MMDT3904-X-G
SOT-363-LF
4
21C3
5%
1/16W
MF-LF
402
OUT
CPU_PROCHOT_BUF
CPU_PROCHOT_L_R
Q5077
MMDT3904-X-G
SOT-363-LF
5%
1/16W
MF-LF
402
FROM SMC
Q5095
2N7002DW-X-G
49A5
SMC_PROCHOT
IN
SOT-363
SIL: FOR DEVELOPMENT USE ONLY
6D3
SMC & MXM THERMTRIP LEVEL SHIFTING
=PP3V3_S3_SMC
DEVELOPMENT
R5075
50C2 50A8 6B4
=PP3V3_S0_SMC_LS
MXM
1K
MXM
5%
1/16W
MF-LF
2 402
SYS_LED_AN
1
R5068
10K
R5069
5%
1/16W
MF-LF
2 402
LED5075
2
MXM_THRMTRIP
SYS_LED_CATH
49B8
49B5
MXM
Q5075
85B8
2N7002
G
SOT23-HF1
IN
MXM_OVERT_L
PM_THRMTRIP_L
6
Q5096
49A5
IN
SMC_THRMTRIP
10C6 100B3 14B7
2N7002DW-X-G
2
SOT-363
MXM
OUT
PULL-UP ON PAGE 14
Q5095
FROM SMC
SOT-363
Q5096
FROM MXM
DEVELOPMENT
5%
1/16W
MF-LF
402
2N7002DW-X-G
GREEN-3.6MCD
2.0X1.25MM-SM
SMC_SYS_LED
MXM_THRMTRIP_L
3.3K
5%
1/16W
MF-LF
2 402
DEVELOPMENT
R5018
MXM
SILK_PART=SIL
Q5060
SOT23
5%
1/16W
MF-LF
402
SMC_EXCARD_CP
FOR <RDAR://PROBLEM/5925345>
HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

50C2 50B4 6B4
SMC_IG_THROTTLE_L
R5019
TABLE_ALT_ITEM
GND_SMC_AVSS
5%
1/16W
MF-LF
402
0.01UF
2
51
GND
5%
1/16W
MF-LF
2 402
IG
REF3133
R5078
470
MAKE_BASE=TRUE
2N7002DW-X-G
2
SOT-363
SMC Support
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
50
109
LPC+SPI Connector
FRANK CONNECTOR
CRITICAL
LPCPLUS
J5100
55909-0374
51C8 51C3 7D4 6D1

7D4 6A4
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
7D4 103D3 49C8 19B3
BI
7D4 103D3 49C8 19B3 7D6 7B8
BI
7C4 51A8
IN
51A8 7C4
OUT
49C8 7D4 103D3 19C3
IN
19B7 7D4 49C5 7C8
OUT
50D3 49B5 7D4
OUT
7D4 9D2
50D3 7D4 49B5
IN
OUT
49C1 7D4
IN
49C1 7D4
OUT
50D3 7D4 49C5 49B8 46D5
IN
61C6 6D1
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
C5144
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
9B2 103D3 7D4
IN
BI
BI
19B3 49C8 103D3 7D4

19B3 49C8 103D3 7D4
OUT
51C7 7C4
IN
51A8 7C4
IN
51C8 7C4
BI
19B7 49C8 7D4
IN
19C3 7C4 49C5
OUT
7D4 49B5 50D3
OUT
7D4 49B5 50D3
OUT
7D6 50D6 7D4 49C3
OUT
7D4 49C1
OUT
46D5 7C4 49B8 49C5 50D3
OUT
18B7 7C4
MCP79 Internal SPI MUX Support
51D5 51C8 7D4 6D1
20%
2 10V
CERM
402
20K
100K
7C4
51D4
2 GND
VCC 5
51D4 7C4
OUT
SPI_ALT_CS_L
R5145
4 103B3 SPI_CS0_L
3
B0
VER 1
Pull-up on debug card
NOSTUFF
CRITICAL
R5146
1
NOSTUFF
0
SPI_CS0_R_L
NOSTUFF
R5141 1
Q5140
470
5%
1/16W
MF-LF
402 2
SSM3J16FV
R5142
IN
21B3 103B3
5% PLACEMENT_NOTE=Place near U1400

1/16W
MF-LF
402
From Frank Card
LPC_FRAME_R_L
OUT
19C5 103D3
5% PLACEMENT_NOTE=Place near J5100

1/16W
MF-LF
402
SPI_CS1_R_L_USE_MLB
=SPI_CS1_R_L_USE_MLB
BI
MAKE_BASE=TRUE
NOSTUFF
PLACEMENT_NOTE=PLACE NEXT TO U5100
21C7
R5143
SPI_CS1_R_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R5147
1
LPC_FRAME_PU
SOD-VESM-HF
LPCPLUS
103D3
SPIROM_USE_MLB
5%
1/16W
MF-LF
402 2
NOSTUFF
R5140 1
U5100
NC7SB3157P6X
SC70
1 B1
SEL 6
=PP3V3_S0_LPCPLUS
=PP3V3_S5_LPCPLUS
SPI_MLB_CS_L
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
Not supported in Rev A01 MCP79 silicon
0.1UF
R51441
OUT
6B4
61C6
516S0573
=PP3V3_S5_LPCPLUS
=PP3V3_S5_ROM
5%
1/16W
MF-LF
402 2
y
r
a
n
i
m
il
LPC_AD<0>
LPC_AD<1>
Alternate SPI ROM Support

51D5 51C3 7D4 6D1
M-ST-SM
31
32
To Frank Card
PLACEMENT_NOTE=PLACE NEXT TO U5100
e
r
2
5% PLACEMENT_NOTE=PLACE NEAR R5147
1/16W
MF-LF
402
MCP79 Rev A01 requires external MUX, Rev B01 should support internal MUX
SPI Bus Series Resistance Option

LPCPLUS
R5156
51D4 7C4
OUT
SPI_ALT_CLK
51D5 7C4
OUT
LPCPLUS
R5157
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place next to R6150
SPI_ALT_MOSI
LPCPLUS
R5158
7C4 51D5
IN
SPI_ALT_MISO
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPI_CLK_R
IN
7B8 21B3 103B3 61C6
SPI_MOSI_R
IN
21B3 103B3 61C2
SPI_MISO
OUT
LPC+SPI Debug Connector
7B8 61B2 103B3 21B3
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
51
109
MCP79 SMBUS "0" CONNECTIONS
SMC "0" SMBus Connections
SMC "A" SMBus Connections

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
52C8 6B4
=PP3V3_S0_SMBUS
R5200 1
MCP79
U1400
(MASTER)
7A4
21C3 13B6
106D3
7A4
21C3 13B6
106D3
6B4
R5201
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
SO-DIMM "A"
SMC
J3100
(Write: 0xA0 Read: 0xA1)
U4900
(MASTER)
=PP3V3_S0_SMBUS_SMC_0_S0
6D3
R5250 1
=I2C_SODIMMA_SCL
31A5
49B8
SMB_0_S0_CLK
106D3
=I2C_SODIMMA_SDA
31A5
49C5
SMB_0_S0_DATA
106D3
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MXM TEMP
R5251
4.7K
R5270 1
SMC
GPU ON CARD - J8400

NV INSIDE (WRITE: 0X9E READ: 0X9F)
MXM CARD (WRITE: 0X98 READ: 0X99)
SMBUS_SMC_0_S0_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
5%
1/16W
MF-LF
402
=SMB_MXM_THRM_SCL
85B8
49A5
SMB_A_S3_CLK
106D3
=SMB_MXM_THRM_SDA
85B8
49A5
SMB_A_S3_DATA
106D3
MAKE_BASE=TRUE
SO-DIMM "B"
32A5
=I2C_SODIMMB_SDA
32A5
100K
5%
1/16W
MF-LF
402
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
y
r
a
n
i
m
il
MCP TEMPS
J3200
(WRITE: 0XA2 READ: 0XA3)
=I2C_SODIMMB_SCL
R5271
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS 0 ALSO GOES TO THE XDP CONNECTOR
100K
U4900
(MASTER)
UNUSED SMC "BATTERY A" SMBUS CONNECTIONS
EMC1403-2: U5535
(WRITE: 0X9A READ: 0X9B)
=SMB_MCP_THRM_SCL
55C2
=SMB_MCP_THRM_SDA
55C2
DIODE1: DIE
6D1
=PP3V3_S5_SMBUS_SMC_BSA
DIODE2: HEATSINK
R5280 1
SMC
SMC "B" SMBus Connections
100K
U4900
(MASTER)
5%
1/16W
MF-LF
402 2
49B5
SMB_BSA_CLK
106D3
49B5
SMB_BSA_DATA
106D3
R5281
100K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
6B4
=PP3V3_S0_SMBUS_SMC_B_S0
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
R5260
SMC
49A5
52D8 6B4
4.7K
U4900
(MASTER)
MCP79 SMBUS "1" CONNECTIONS

C
5%
1/16W
MF-LF
402 2
SMB_B_S0_CLK
106D3
R5261
CPU DIE TEMP
4.7K
EMC1042-2: U5570
(WRITE: 0X9A READ: 0X9B)
5%
1/16W
MF-LF
2 402
SMBUS_SMC_B_S0_SCL
SMC "MANAGEMENT" SMBUS CONNECTIONS
=SMB_CPU_THRM_SCL
55C4
=SMB_CPU_THRM_SDA
55D4
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS
49A5
SMB_B_S0_DATA
106D3
SMBUS_SMC_B_S0_SDA
6B4
=PP3V3_S0_SMBUS_SMC_MGMT
MAKE_BASE=TRUE
MCP79
U1400
(MASTER)
21C3
21C3
R5202 1
2.2K
5%
1/16W
MF-LF
402 2
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
R5203
2.2K
5%
1/16W
MF-LF
2 402
MIKEY
J9800
(WRITE: 0X72 READ: 0X73)
=I2C_AUDIO_SCL
98C7
=I2C_AUDIO_SDA
98B7
1
2
3
4
5
6
=SMB_REMOTE_TEMP_SCL
55A6
=SMB_REMOTE_TEMP_SDA
55A6
4.7K
U4900
(MASTER)
EMC1047-1, U5500, SEE TABLE

ODD TEMP
LCD TEMP
AMBIENT TEMP
CPU HEATSINK
MXM HEATSINK
HDD TEMP
R5290
SMC
REMOTE TEMPS
EMC1047-1 HEX DIODE SENSOR

DIODE
FUNCTION
5%
1/16W
MF-LF
402 2
49C5
SMB_MGMT_CLK
106D3
49C8
SMB_MGMT_DATA
106D3
R5291
VREF DAC
4.7K
U2900
(Write: 0x98 Read: 0x99)
5%
1/16W
MF-LF
2 402
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
e
r
29C7
MARGINGING CONTROL
U2901
J3400
M35E: NO TEMPERATURE SENSOR
M35B: (WRITE: 0X90 READ: 0X91)
=SMBUS_MINI_SCL
34C3
29C7
=I2C_VREFDACS_SDA
MAKE_BASE=TRUE
PCI-E MINI CARD
=SMBUS_MINI_SDA
=I2C_VREFDACS_SCL
MAKE_BASE=TRUE
=I2C_PCA9557D_SCL
29A8
=I2C_PCA9557D_SDA
29A8
34C3
DIGITAL LCD TEMP
J5560
TMP275: U1
=SMB_LCD_TEMP_SCL
55A4
=SMB_LCD_TEMP_SDA
55A4
SMBUS CONNECTIONS
SYNC_MASTER=DEREK

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
52
109
53D3
MXM PWRSRC VOLTAGE SENSE
PPV_S0_MXM_PWRSRC
MXM_PWR_SENSE
(SCALING 12V INPUT VOLTAGE TO SMC)
R5353
18.2K
SCALE
53B6 12D7 11D6 11B5 6D4
SMC_GPU_VSENSE 49C5
R5309
SM
1
PCB: PLACE C5359 WITHIN 1" OF SMC (U4900)
ADC IS 10BIT 0 TO 1023

0 TO 3.3V
XW5309
=PPVCORE_S0_CPU
COUNT
.0129 V/COUNT
4 V/V
CPU Voltage Sense / Filter
1%
1/16W
MF-LF
2 402
CPUVSENSE_IN
4.53K
SMC_CPU_VSENSE
1%
1/16W
MF-LF
402
Place short near U1000 center
MXM_PWR_SENSE
GND_SMC_AVSS
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D3 54A4 54B4
54C3 54D3
Place RC close to SMC
y
r
a
n
i
m
il
GND_SMC_AVSS
=PP3V3_S0_SMC
6A4
R5380
0.025
1
3
=PPV_S0_MXM_PWR
CRITICAL
MXM_PWR_SENSE
VCC
IMVP6_PMON
4.53K
1%
1/16W
MF-LF
402
SMC_CPU_ISENSE
OUT
GND
49C5
C5370
20%
6.3V
X5R
402
49C2 50B7 53A2 53A4 53B1 53C3 53D3 53D6 54A4 54B4
54C3 54D3
PCPU = VPMON / (17.5 * .0021)
COUNT
.0087518 A/COUNT

0 TO 3.3V
84C1
PART#
MXM_PWRSRC_SENSOR_P
108C3 MXM_PWRSRC_SENSOR_N
5
1
TABLE_5_HEAD
QTY
DESCRIPTION
CRITICAL
BOM OPTION
107S0063
25 MILLIOHM
R5380
CRITICAL
K50_BETTER
SMC_GPU_ISENSE
49C5
107S0111
18 MILLIOHM
R5380
CRITICAL
24_INCH_MXM
132S0242
CAP,0.082UF,402
C5381
CRITICAL
MXM_PWR_SENSE
116S0090
RES,10KOHM,5%,402
C5381
CRITICAL
IG
TABLE_5_ITEM
TABLE_5_ITEM
OMIT
353S2291
GAIN = 20
GND_SMC_AVSS
SCALE
2.778 A/V
108C3
C5381
0.082UF
0.22UF
.0064453 A/COUNT
2 A/V

0 TO 3.3V
=PPV_S0_MXM_PWRSRC
K51 SET FOR APPROX 1.98V AT 5.5A ON PWRSRC
COUNT
SCALE
53D5
MAKE_BASE=TRUE
VOLTAGE=12V
MAX4073TAXK+G65
SC70
OUT
PPV_S0_MXM_PWRSRC
U5380
RS_P
RS_M
R5370
K50 SET FOR APPROX 2V AT 4A ON PWRSRC
2
4
C5380
20%
6.3V
2 X5R
402
CPU SUPPLY POWER SENSE FILTER
1%
1W
MF
2512-1
MXM_PWR_SENSE
0.22UF
IN
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D6 54A4 54B4
54C3 54D3
OMIT
MXM PWRSRC (GPU CORE & MEM) CURRENT SENSE

54D6 50C1 6B4
71C5
20%
6.3V
2 X5R
402
1%
1/16W
MF-LF
2 402
20%
6.3V
X5R
402
C5359
0.22UF
6.04K
0.22UF
2
R5354
49C5
OUT
C5309
10%
16V
CERM-X7R
402
GND_SMC_AVSS
OMIT
TABLE_5_ITEM
TABLE_5_ITEM
49C2 50B7 53A2 53A4 53B1 53C6 53D3 53D6 54A4 54B4
54C3 54D3
12V RAILS CURRENT/VOLTAGE SENSE
R5381
0.018
1%
1W
MF
2512
6D6
CPU POWER SENSE CALIBRATION CIRCUIT
PP12V_S5_INPUT
1
3
2
4
PP12V_S5
6C2 7C3 53B5
7D3 6D7 6B8 6B6 78C1
SENSE_12V_S5_N
SENSE_12V_S5_P
PP3V3_S0
53B3 108C3
12V_PWR_SENSE
53B3 108C3
R5382
=PP12V_S0_CPU
6D8
DEVELOPMENT
12D7 11D6 11B5 53D8 6D4
R5339
CRITICAL
=PPVCORE_S0_CPU
ISENSE_CAL_EN_LS12V
DEVELOPMENT
10K
5%
1/16W
MF-LF
2 402
Q7640
G
DEVELOPMENT
1DEVELOPMENT
1%
1/4W
MF-LF
1206 2
R5342
5%
1/16W
MF-LF
2 402
CPUVCORE_ISENSE_CAL
R5341
10K
e
r
1.00
470K
SOT-23-HF
ISENSE_CAL_EN_L
R53431
DEVELOPMENT
NTR4101P
DEVELOPMENT
CRITICAL
5%
1/16W
MF-LF
2 402
Q5341
ISENSE_CAL_EN_L_R
FDC796NG
SUPERSOT-6
1 2
3 DEVELOPMENT
Q5339
2N7002
ISENSE_CAL_EN
12V_PWR_SENSE
8
1%
1W
MF-LF
2512
50C3
CRITICAL
20%
6.3V
2 X5R
402
0.010
72D7 71D8 6A4
C5382
0.22UF
OMIT
Switches in fixed load on power supplies to calibrate current sense circuits
SOT23-HF1
S
2
3 5
PP12V_S0_INPUT
1
3
VCC
U5381
2
4
PP12V_S0
70B8 6A6 7D3 53B3
53C4 108C3
53C4 108C3
SENSE_12V_S0_N
SENSE_12V_S0_P
12V_PWR_SENSE
MAX4377TAUA
53B3 108C3
53B4 108C3
53B3 108C3
53B4 108C3
SENSE_12V_S5_N
SENSE_12V_S5_P
2
3
UMAX-HF
RS1_M
OUT1
RS1_P
OUT2
SENSE_12V_S0_P
SENSE_12V_S0_N
5
6
RS2_P
RS2_M
1
7
SMC_12V_S5_ISENSE_R
R5383
1
53B4 7D3 6A6 70B8
12V_PWR_SENSE
1%
1/16W
MF-LF
402
SMC_12V_S0_ISENSE
50C3
OMIT
1
C5383
20%
6.3V
X5R
402
C5384
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
18.2K
1%
1/16W
MF-LF
2 402
OMIT
0.22UF
R5387
18.2K
1%
1/16W
MF-LF
2 402
SMC_12V_S5_VSENSE
SMC_12V_S0_VSENSE
50C3
12V_PWR_SENSE
R5386
1%
1/16W
MF-LF
2 402
4.53K
R5385
50C3
R5384
1
12V_PWR_SENSE
6.04K
SMC_12V_S0_ISENSE_R
353S2292
GAIN = 20
PP12V_S0
SMC_12V_S5_ISENSE
12V_PWR_SENSE
PP12V_S5
1%
1/16W
MF-LF
402
GND
53C4 7C3 6C2
4.53K
R5388
6.04K
0.22UF
GND_SMC_AVSS
50C3
12V_PWR_SENSE
C5386
20%
6.3V
2 X5R
402
54A4 54B4 54C3 54D3

49C2 50B7 53A2 53A4
53C3 53C6 53D3 53D6
1%
1/16W
MF-LF
2 402
C5388
0.22UF
20%
6.3V
2 X5R
402
49C2 50B7 53A2 53B1 53C3 53C6 53D3 53D6 54A4

54B4 54C3 54D3
GND_SMC_AVSS
49C2 50B7 53A4 53B1 53C3 53C6 53D3 53D6 54A4 54B4
54C3 54D3
TABLE_5_HEAD
QTY
DESCRIPTION
CRITICAL
BOM OPTION
107S0069
PART#
10 MILLIOHM
R5382
CRITICAL
K50_BETTER
107S0112
8 MILLIOHM
R5382
CRITICAL
24_INCH_MXM
107S0070
RES,0 OHM,2512
R5381,R5382
CRITICAL
IG
107S0111
18 MILLIOHM
R5381
CRITICAL
12V_PWR_SENSE
RANGE
TABLE_5_ITEM
10A
TABLE_5_ITEM
12.5A
TABLE_5_ITEM
Current & Voltage Sensing
TABLE_5_ITEM
5.5A
SYNC_MASTER=K50
TABLE_5_ITEM
116S0090
RES,10K0HM,5%,402
C5383,C5384
IG

TABLE_5_ITEM
132S0080
CAP,0.22UF,20%,6.3V,X5R,402
C5383,C5384
12V_PWR_SENSE
12V_PWR_SENSE SHOULD BE STUFFED FOR MXM CONFIGS

IG CONFIGS WILL NOT HAVE THE SENSORS, SO CAPS FROM THE RC FILTER
BECOME RESISTORS TO GROUND (SO SMC READS 0)

SIZE
IG CONFIGS DO NOT NEED 12V POWER SENSE BECAUSE THE CONFIGURATION DOES NOT DRAW
CURRENT WHICH APPROACHES THE ACDC SPEC
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
53
109
53D5 50C1 6B4
=PP3V3_S0_SMC
MCP_PWR_SENSE
OMIT
R5400
78A5
PP1V5_S0_FET
1
3
1.5V S0 CURRENT SENSE
20%
6.3V
2 X5R
402
2
4
PP1V5_S0
1%
1/4W
MF-LF
1206
C5400
0.22UF
0.002
MCP_PWR_SENSE
V+
70A8 6C6 7D3 54C5
SENSE_1V5_S0_N
5 IN-
108C3
SENSE_1V5_S0_P
4 IN+
R5401
INA210
SC70
MCP_PWR_SENSE
U5400
108C3
OUT
4.53K2
SMC_1V5_S0_ISENSE_R
SMC_1V5_S0_ISENSE
1%
1/16W
MF-LF
402
REF 1
C5401
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
104S0018
RES,2 MILLIOHM,1206
R5400
CRITICAL
MCP_PWR_SENSE
101S0414
RES,0 OHM,1206,20MILLIOHM MAX
R5400
CRITICAL
PRODUCTION
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54A4
54B4 54C3
a
n
i
TABLE_5_HEAD
PART#
y
r
MCP_PWR_SENSE
1
GND
353S2073
GAIN = 200V/V
TRANSFER RATIO = 0.4V/A
50C3
1.5V S0 VOLTAGE SENSE
TABLE_5_ITEM
MCP_PWR_SENSE
R5402
4.53K2
PP1V5_S0
54D6 7D3 6C6 70A8
SMC_1V5_S0_VSENSE
1%
1/16W
MF-LF
402
50C3
MCP_PWR_SENSE
1
C5402
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
m
il
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54A4
54B4 54D3
MCP CORE CURRENT SENSE

MCP_PWR_SENSE
R5404
74C6
IN
MCPCORES0_IMON
4.53K
SMC_MCP_CORE_ISENSE
NOSTUFF
1%
1/16W
MF-LF
402
R5405
e
r
50C3
C5404
0.22UF
4.53K
1%
1/16W
MF-LF
402 2
OUT
MCP_PWR_SENSE
20%
6.3V
X5R
402
GND_SMC_AVSS
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54A4
54C3 54D3
SCALE IS 0.116 V/A
MCP CORE VOLTAGE SENSE

MCP_PWR_SENSE
R5403
74C7 7D3 6D6 74D1 74B8
PPMCPCORE_S0_REG
4.53K2
SMC_MCP_CORE_VSENSE
1%
1/16W
MF-LF
402
50C3
MCP_PWR_SENSE
1
C5403
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
49C2 50B7 53A2 53A4 53B1 53C3 53C6 53D3 53D6 54B4
54C3 54D3
MCP CURRENT AND VOLTAGE SENSE

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
54
109
REMOTE THERMAL SENSORS

CPU T-Diode Thermal Sensor
HEATSINKS, AMBIENT, PANEL AND DISKS
CPU_TDIODE
PLACE DISK SENSOR CONNS BOTTOM SIDE, TOP EDGE OF MLB
R5570
SENSOR CH6
SENSOR CH1
55B8 55A5 6B4
L5550
SILK_PART=ODD TEMP
J5551
L5553
55D6 108D3 55A8
SNS_T_DP1_DN6
55D8 108D3 55A8
HS8802F-B
FERR-220-OHM
FERR-220-OHM
SNS_T_DN1_DP6
2
108C3
L5554
108C3
SNS_ODD_P
SNS_ODD_N
55D8 108D3 55A8
SNS_T_DP1_DN6
SNS_T_DN1_DP6
108D3 10C6
L5552
FERR-220-OHM
0402
CRITICAL
50A8
HDD_OOB_TEMP
10%
50V
CERM
402
SENSOR CH2
FERR-220-OHM
55C6 108D3 55A8
SNS_T_DP2_DN3
55C8 108D3 55A8
SNS_T_DN2_DP3
108C3
L5523
SNS_LCD_P
108C3 SNS_LCD_N
108C3
=SMB_CPU_THRM_SDA
=SMB_CPU_THRM_SCL
55C8 108D3 55A8
SNS_T_DP2_DN3
6A4
0402
CRITICAL
CRITICAL
518S0677
518S0570
108C3 21C3
BI
m
il
PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU
SENSOR CH5
SNS_T_DP4_DN5
J5510
55B8 108D3 55A8
SNS_T_DN4_DP5
0402
1
SNS_CPU_H_P
108C3 SNS_CPU_H_N
L5511
L5513
FERR-220-OHM
55B6 108D3 55A8
SNS_T_DN4_DP5
SNS_MXM_P
108C3 SNS_MXM_N
108C3
1
2
0402
55B8 108D3 55A8
0402
CRITICAL
518S0678
CRITICAL
MXM
REMOTE THERMAL SENSORS (HEATSINKS AND DISKS)

=PP3V3_S0_TSENS
R5500
1
22
PP3V3_S0_TSENS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
55D8 55D6 108D3
1UF
10%
10V
X5R
402-1
SNS_T_DN1_DP6
DIFFERENTIAL_PAIR=SNS_T1
SIGNAL_MODEL=EMPTY
C5502
55D8 55D6 108D3

55C8 55C6 108D3
SNS_T_DP1_DN6
SNS_T_DP2_DN3
3 DN1/DP6
2 DP1/DN6
4 DP2/DN3
5 DN2/DP3
0.0022UF
10%
50V
CERM
402
55C8 55C6 108D3
55B8 55B6 108D3
SNS_T_DN2_DP3
SNS_T_DP4_DN5
8 DP4/DN5
7 DN4/DP5
SMDATA 9
SMCLK 10
=SMB_REMOTE_TEMP_SDA
=SMB_REMOTE_TEMP_SCL
C5504
MCP_TDIODE
1
DP1
DN1
TSSOP
100K
1UF
EMC1403-2-AIZL
R5536 1
C5535
5%
1/16W
MF-LF
402
10%
10V
X5R
402-1
R5537
10K
5%
1/16W
MF-LF
402
R5538
THERM*
MCPTHMSNS_THERM_L
ALERT*
MCPTHMSNS_ALERT_L
10%
50V
CERM
402
=SMB_MCP_THRM_SDA
BI
52D3
10
=SMB_MCP_THRM_SCL
BI
52D3
DP2/DN3
SMDATA
DN2/DP3
SMCLK
MEM_EVENT_L
31A5 32A5 49B8 21A4 21B3
5%
1/16W
MF-LF
402
MCP_THMDIODE_N
0.0022UF
GND
MCP_TDIODE
L5535
353S2224
FERR-220-OHM
1
108C3
MCPTHMSNS_D2_P
SIGNAL_MODEL=EMPTY
0402
MCP_TDIODE
MCP_TDIODE
FERR-220-OHM
1
C5537
PLACEMENT NOTE: PLACE U5535 NEAR MCP, TOP SIDE UNDER HEATSINK
0.0022UF
L5536
2
108C3
10%
50V
CERM
402
MCPTHMSNS_D2_N
0402
DIGITAL LCD TEMP SENSOR

SILK_PART=D LCD TEMP
55D4 55B8 6B4
=PP3V3_S0_TSENS
DEVELOPMENT
J5560
DEVELOPMENT
C5560
53398-8605
M-ST-SM
6
1UF
10%
10V
X5R
402-1
NC
1
2
52C3
52B3
52C3
52B3
=SMB_LCD_TEMP_SDA
=SMB_LCD_TEMP_SCL
BROKE SYNC FROM K50 ON 7/9
Thermal Sensors
4
5
SYNC_MASTER=DEREK

CRITICAL
518S0681
GND
SIGNAL_MODEL=EMPTY
C
MCP_TDIODE
518S0679
MCP_TDIODE
CRITICAL
MCP_TDIODE
CRITICAL
MCP_TDIODE
U5500
TSSOP
SIGNAL_MODEL=EMPTY
C5503
CRITICAL
VDD
P
2
0.0022UF
10%
50V
CERM
402
C5501
EMC10471AIZL
55D4 55A5 6B4
SIGNAL_MODEL=EMPTY
518S0678
(DIFFERENT FROM K50)
BI
MCPTHMSNS_FILT_P
MCPTHMSNS_FILT_N
108C3
e
r
SNS_T_DP4_DN5
108C3
FERR-220-OHM
M-ST-SM
4
M-ST-SM
3
MXM
53389-8603
53398-8602
0402
108C3
J5535
J5511
MXM
L5512
FERR-220-OHM
M-ST-SM
3
SILK_PART=MCP HSK
SILK_PART=MXM HSK
53398-8602
CPU_THRM_ALERT
U5535
C5536
108C3 21C3
55B6 108D3 55A8
VOLTAGE=3.3V
MCP_THMDIODE_P
DETECT MCP DIE TEMPERATURE
SILK_PART=CPU HSK
CPU_THRM_THERM
PP3V3_S0_MCPTHMSNS_R
MCP_TDIODE
SENSOR CH4
ALERT_L
VDD
(DIFFERENT FROM K50)
L5510
22
5%
1/16W
MF-LF
402
0402
FERR-220-OHM
R5535
=PP3V3_S0_MCPTHMSNS
THERM_L
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP_TDIODE
SNS_AMB_P
SNS_AMB_N
FERR-220-OHM
FERR-220-OHM
SNS_T_DN2_DP3
108C3
5%
1/16W
MF-LF
2 402
MCP T-Diode Thermal Sensor
M-RT-SM
3
0402
0402
55C6 108D3 55A8
HS8802F-B
L5521
J5521
L5522
FERR-220-OHM
M-RT-SM
4
7 SMDATA
8 SMCLK
a
n
i
SENSOR CH3
SILK_PART=AMBIENT TEMP
53780-8603
L5520
100K
5%
1/16W
MF-LF
402 2
GND
5
PLACE SENSOR CONNS BOTTOM SIDE CORNER
SILK_PART=LCD TEMP
y
r
R5572
10K
10%
10V
X5R
402-1
353S2223
52C3
J5520
CPU_THERMD_N
52C3
PLACE ANALOG LCD TEMP CONN BOTTOM SIDE, TOP EDGE OF MLB
CPU_TDIODE
1
MSOP
CRITICAL
518S0677
0402
518S0570
C5580
OUT
CPU_TDIODE
R55711
C5570
1UF
U5570
2 DP
3 DN
0.0022UF
108D3 10C6
EMC1402-2-ACZL
SIGNAL_MODEL=EMPTY
CPU_TDIODE
CPU_TDIODE
CRITICAL
1
VDD
CPU_THERMD_P
OUT
1
SNS_HDD_P
2 108C3 SNS_HDD_N
2
108C3 HDD_OOB_TEMP_FILT 3
0402
VOLTAGE=3.3V
M-RT-SM
4
FERR-220-OHM
55D6 108D3 55A8
53780-8603
L5551
PP3V3_S0_CPUTHMSNS_R
2
5%
1/16W
MF-LF
402
FERR-220-OHM
108C3
0402
J5550
2
0402
M-RT-SM
3
22
=PP3V3_S0_TSENS
SILK_PART=HDD TEMP
0.0022UF
10%
50V
CERM
402
55B8 55B6 108D3
SIZE
2
DRAWING NUMBER
SNS_T_DN4_DP5
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
55
109
FAN 0
CRITICAL
57D6 56C6 6A4
L5610
=PP12V_S0_FAN
220-OHM-1.4A
1
PP12V_S0_FAN0_L
0603
57D7 56B7 6D1
=PP3V3_S5_FAN
1
1.5K
R5606
1.5K
5%
1/4W
MF-LF
2 1206
10K
5%
1/16W
MF-LF
2 402
R56031
R5602
5%
1/8W
MF-LF
805 2
1
CRITICAL
5
3.9K
F0_GATESLOWDN
CRITICAL
6
7
8
1
2
3
C5601
J5600
Q5602
a
n
i
1
D5600
20%
2 16V
ELEC
6.3X5.5-SM1-HF
SOT23
R5600
10K
47K
CRITICAL
5%
1/16W
MF-LF
2 402
R5699
2
L5600
FERR-220-OHM
1
FAN_TACH0
ADDED TO PROTECT SMC
m
il
FAN 1
57D6 56D7 6A4
57D7 56D7 6D1
=PP12V_S0_FAN
=PP3V3_S5_FAN
1
R5611
10K
5%
R5610
1.5K
1/16W
MF-LF
2 402
e
r
1
F1_GATESLOWDN
Q5605
2N7002
57C7 56C7 6B4
R5601
10K
5%
1/16W
MF-LF
2 402
47K
FAN_TACH1
5%
1/16W
MF-LF
402
SOT23-HF1
=PP3V3_S0_FAN
R5698
2 16V
X7R
805
D5601
MMBD914XG
FAN_0_GND
518S0592
R5620
0
5%
1/10W
MF-LF
2 603
C5608
2.2UF
10%
C5628
2.2UF
10%
2 16V
X5R
603
2PP12V_S0_FAN1_L
0603
C5609
0.01UF
20%
2 16V
CERM
402
2 16V
X5R
603
HD FAN
Q5603
NTHS5443T1H
1206A-03-HF
CRITICAL
J5601
HS8804F-B
CRITICAL
M-RT-SM1
5
L5640
220-OHM-1.4A
FAN_1_PWR
2
0603
FAN_1_PWR_L
MOTOR CONTROL
TACH
GND
12V DC
518S0592
FAN_TACH1_L
CRITICAL
1
C5605
100UF
20%
2 16V
ELEC
6.3X5.5-SM1-HF
1 SOT23
CRITICAL
C5603
0.47UF
10%
MOTOR CONTROL
TACH
GND
12V DC
6
7
8
L5630
CRITICAL
5
1
2
3
SMC_FAN_1_TACH
R5609
3.9K
5%
1/8W
MF-LF
805 2
220-OHM-1.4A
1.5K
5%
1/8W
MF-LF
805
SMC_FAN_1_CTL
49A8
R56071
5%
1/4W
MF-LF
2 1206
F1_VOLTAGE8R5
49A8
0402
5%
1/16W
MF-LF
402
NOTE:
C5602
100UF
MMBD914XG
FAN_0_PWR_L
FAN_TACH0_L
CRITICAL
=PP3V3_S0_FAN
1
SMC_FAN_0_TACH
2
0603
57C7 56B7 6B4
FAN_0_PWR
SOT23-HF1
M-RT-SM1
5
L5620
220-OHM-1.4A
2N7002
HS8804F-B
CRITICAL
10%
2 16V
X7R
805
y
r
ODD FAN
0.47UF
1206A-03-HF
SMC_FAN_0_CTL
0.01UF
NTHS5443T1H
49A8
C5607
20%
2 16V
CERM
402
2 16V
CERM
1206-1
Q5600
5%
1/8W
MF-LF
805
49B8
4.7UF
20%
R5605
F0_VOLTAGE8R5
C5606
FAN_1_GND
CRITICAL
L5601
FERR-220-OHM
R5630
0
1
1
2
0402
5%
1/10W
MF-LF
2 603
HD AND OD FAN
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
56
109
FAN 2
CRITICAL
56D7 56C6 6A4
L5710
=PP12V_S0_FAN
220-OHM-1.4A
1
2
0603
56D7 56B7 6D1
=PP3V3_S5_FAN
y
r
R5705
1.5K
5%
1/16W
MF-LF
2 402
49A8
R57011
R5704
10K
1.5K
5%
1/4W
MF-LF
2 1206
5%
1/8W
MF-LF
805 2
SMC_FAN_2_CTL
C5708
4.7UF
20%
CRITICAL
5
C5709
0.01UF
20%
2 16V
CERM
402
2 16V
CERM
1206-1
R5703
F2_VOLTAGE8R5
3.9K
CPU FAN
F2_GATESLOWDN
1206A-03-HF
NTHS5443T1H
5%
1/8W
MF-LF
805
Q5700
2N7002
1
2
3
CRITICAL
D5700
1
MMBD914XG
SOT23
R5700
10K
C5702
100UF
20%
2 16V
ELEC
6.3X5.5-SM1-HF
CRITICAL
5%
1/16W
MF-LF
2 402
0603
=PP3V3_S0_FAN
M-ST-SM
5
220-OHM-1.4A
FAN_2_PWR
56C7 56B7 6B4
CRITICAL
SOT23-HF1
J5700
53398-8604
L5720
10%
16V
2 X7R
805
Q5702
CRITICAL
a
n
i
0.47UF
3
D
C5701
6
7
8
L5701
FERR-220-OHM
1
FAN_TACH2
FAN_2_PWR_L
FAN_TACH2_L
FAN_2_GND
R5797
SMC_FAN_2_TACH
47K
R5720
0
0402
49A8
PP12V_S0_FAN2_L
MOTOR CONTROL
TACH
GND
12V DC
5%
1/10W
MF-LF
2 603
m
il
5%
1/16W
MF-LF
402
e
r
CPU FAN
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
57
109
y
r
a
n
i
C
51C8 6D1
=PP3V3_S5_ROM
R6100 1
3.3K
R6150
51A6 103B3 21B3 7B8
IN
SPI_CLK_R
IN
SPI_MLB_CS_L
R6101
C6100
3.3K
20%
10V
CERM
402
CRITICAL
VDD
U6100
0.1UF
5%
1/16W
MF-LF
2 402
m
il
0
2
103B3
5%
1/16W
MF-LF
402
SPI_CLK
SI
SCK
R6190
10K
5%
1/16W
MF-LF
402 2
SPI_WP_L
SPI_HOLD_L
CE*
WP*
HOLD*
OMIT
SO
VSS
4
e
r
5%
1/16W
MF-LF
2 402
5 103B3
SST25VF016B
R6191
10K
16MBIT
SOI
PLACEMENT_NOTE=PLACE CLOSE TO U6100

51C8
5%
1/16W
MF-LF
402 2
R6152
0
SPI_MOSI
R6105
103B3
SPI_MISO_R
5%
1/16W
MF-LF
402
SPI_MOSI_R
IN
21B3 103B3 51A6
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO
OUT
7B8 51A6 103B3 21B3
5%
1/16W
MF-LF
402
MCP79 SPI Frequency Select
Frequency
SPI_MOSI
SPI_CLK
31 MHz
42 MHz
25 MHz
1 MHz
NOTE: MCP79 only issues READ (0x03) commands

not READ_FAST (0x0B). Limits SPI bus
frequency and part selection.
SST25VF016B max speed for READ command is 25MHz.
SPI ROM
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
61
109
S5 POWER RAIL SEQUENCING

12V_S5 SUPPLIED BY AC/DC MAX RAMP TIME < 50MS MAX RAMP RATE 10V/MS
12V_S5
STARTUP (BOOT OR WAKE) TIMING

3V3_S5 SWITCHER LOGIC POWERED BY INTERAL LDO, SOURCED FROM 12V_S5
BOOT UP
3V3_S5
1V05_S5 SWITCHER SOURCED FROM 3V3_S5 AND ENABLED FROM 3V3_S5_PGOOD
1V05_S5
SB: PM_SLP_S3_L
SB: PM_SLP_S4_L
y
r
a
n
i
m
il
VREGS: ALL_SYS_PWRGD
99 MS
SMC: IMVP_VR_ON
RMGT POWER RAIL SEQUENCING
IMVP: VR_PWRGOOD_DELAY
PM_SLP_RMGT_L FOLLOWS PM_SLP_S4_L TIMING CLOSELY

MCP: PM_SLP_RMGT_L
3V3_RMGT FET SOURCED FROM 3V3_S5, ENABLED BY PM_SLP_RMGT_L
3V3_RMGT
1V05_RMGT
1V05_RMGT FET SOURCED FROM 1V05_S5, ENABLED BY PM_SLP_RMGT_L
AND GATE: MCP_PS_PGOOD

ALL_SYS_PWRGD * VR_PWRGOOD_DELAY
SMC STARTS
COUNT
State

MCP: PM_SLP_S4_L
5V_S3 SWITCHER LOGIC POWERED BY INTERNAL LDO (EN BY SLP_S4_L)

OUTPUT SOURCED FROM 12V_S5 AND ENABLED BY PM_SLP_S4_L + LDO OUTPUT GOOD
5V3_S3
3V3_S3 FET GATED BY PM_SLP_S4_L

3V3_S3
1V5_S3 SWITCHER LOGIC POWERED BY 5V_S3 SO ENABLED BY PGOOD_5V_S3
SOURCED BY 12V_S5; MUST RAMP IN < 2MS
1V5_S3
IMVP6 ON
Manageability
SMC_PM_G2_ENABLE
PM_S4_STATE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_M_L
N/A
Sleep (S3/M1)
On
Soft-Off (S5/M1)
On
Sleep (S3/M-Off)
Off
Soft-Off (S5/M-Off)
Off
Battery Off (G3Hot)
N/A
Run (S0/M0)
SHUT DOWN (SHUTDOWN OR SLEEP) TIMING

POWER RAILS ON DURING THIS TIME
SB SAYS
SUSPEND SOON
SLEEP OR SHUTDOWN
SB: PM_SUS_STAT#
NOTE: NO SEQUENCING REQUIREMENTS FOR THESE 3 RAILS
e
r
SB: PM_SLP_S3_L
12V_S0 SUPPLIED BY AC/DC, GATED BY PM_SLP_S3_L

12V_S0
5V_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT

5V_S0
SB: PM_SLP_S3_L
SB: PM_SLP_S4_L
POWER RAILS SHUT DOWN

CPU VTT_PWRGD LOW
VREGS: ALL_SYS_PWR_GD
SMC SAYS SHUTDOWN CPU

VREG IN RESPONSE TO
OS COMMANDS
SMC: IMVP_VR_ON
3V3_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT; SLOWER THAN 5V_S0
3V3_S0
1V8_S0 LDO SOURCED FROM 5V_S0, ENABLED BY 5V_S0 WITH RC DELAY

1V8_S0
IMVP6: VR_PWRGOOD_DELAY
1V5_S0 FET SOURCED FROM 1V5_S3, GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

1V5_S0
MCP_VCORE
1V05_S0
MCP_VCORE REGULATOR INTERNAL LOGIC POWERED FROM 5V_S3, SOURCED FROM 12V_S5,
ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY
MCP: CPUPWRGD
1V05_S0 REGULATOR SHARES INTERNAL LOGIC POWER WITH 3V3_S5 REG, SOURCED FROM 12V_S0
ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY
CPU_VCORE
VTT_S0_DDR_LDO
AND GATE: MCP_PS_PGOOD
POWER SEQUENCING BLOCK DIAGRAM
CLK GEN DISABLED

CPU VCORE OFF
CPU_PWRGD DISABLED
SB PWROK DISABLE
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
69
109
State
1
SMC_PM_G2_ENABLE (PORTABLES)
PM_SLP_S4_L
PM_SLP_S3_L
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
Power Control Signals

MXM POWER SEQUENCE
3.3V,5V S3 enable
FROM MCP (6)

50C3 49C5 38D7 7B4 102B3 21C3
(PM_S4_STATE_L)
PM_SLP_S4_L
IN
=P3V3S3_EN
MAKE_BASE=TRUE
85B2
OUT
78D4
Enable FET
IN
ALL_SYS_PWRGD_R
=PM_MXM_PGOOD_PULLUP
70B1 6B7 7B4 7C3 7C4
MAKE_BASE=TRUE
PM_MXM_EN
=5VREG_EN
OUT
73C6
85B8
OUT
ENABLE REGULATOR
MXM CARD INPUT POWER ARE 12V_S0, 3V3_S0, 5V_S0

ALL_SYS_PWRGD ENABLES MXM REGULATORS
PM_MXM_PGOOD IS OPEN DRAIN SIGNAL, ITS PULLED UP TO ALL_SYS_PWRGD
78B7 6C3
=PP5V_S3_PWRCTL
1
R7072
100K
5%
1/16W
MF-LF
2 402
PGOOD_5V_S3
9A7
=DDRREG_EN OUT
MAKE_BASE=TRUE
Enable regulator
C7058
=PP3V3_S5_PWRCTL
70C1 70B3 70B1 70A3 6D1
75C8
0.1UF
R7040
100K
5%
1/16W
MF-LF
2 402
5 TC7SZ08AFEAPE
SOT665
49C5 9D6 6C8

50C3
IN
(PM_SLP_S3_L)
PM_SLPS3_BUF2_L
U7059
PM_SLP_S3_L_AND_S0_RDY
(PM_SLP_S3_L_BUF)
From SMC (6)
R7080
39K
5%
1/16W
MF-LF
402
R7081
OUT
78D7
Enable FET
=P3V3S0_EN
OUT
78C4
Enable FET
5%
1/16W
MF-LF
402
R7082
y
r
a
n
i
m
il
=P5VS0_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
10K
S0_RDY
MAKE_BASE=TRUE
43K
FROM COMPARATOR
70B4 PGOOD_1V5_S3
FROM COMPARATOR
70B4 PGOOD_12V_S0
20%
10V
CERM
402
=PP3V3_S5_PWRCTL
R7031
1K
5%
1/16W
MF-LF
402
MCPDDR_EN
=MCPDDR_EN
OUT
78A7
Enable FET DELAY OF ~15MS FROM PM_SLP_S3_L
=1V05S0_EN
OUT
76B7
Enable regulator DELAY OF ~18MS FROM PM_SLP_S3_L
=MCPCORES0_EN
OUT
74C6
Enable regulator DELAY OF ~16MS FROM PM_SLP_S3_L
MAKE_BASE=TRUE
CPUVTTS0_EN
MAKE_BASE=TRUE
MCPCORES0_EN
MAKE_BASE=TRUE
1.5V_S3 NEED TO BE ON BEFORE S0 FET ON

12V_S0 NEED TO BE ON BEFORE MCP REG AND 1.05_S0 REG EN
C7080
C7081
C7082
0.47UF
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
CERM-X5R
402
CERM-X5R
402
CERM-X5R
402
79B4
RSMRST_PWRGD
49D8
OUT
To SMC (2)
1
C7031
0.1UF
10%
2 16V
X5R
402
FROM THIS SMC GENERATES PM_RSMRST_L

WHICH GOES INTO PGOOD_SB OF MCP
DELAY IS ABOUT 200MS
=PP3V3_S5_PWRCTL
S0 RAILS PGOOD
PGOOD Comparators
=PP12V_S5_PWRCTL
PGOOD_1V05_S5
1V05V_S0 DERIVES FROM 3.3V_S5
70D8 70C1 70B1 70A3 6D1
6C1
6D1 70A3 70B1 70B3 70D8
R7033
10K
1
1
R7013
R70181
33.2K
84.5K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1 IG
1%
1/16W
MF-LF
402
XW7000
7D3 6A6
53B4 53B3
PP12V_S0
R7000
OMIT
SM
4.99K2
6D3
=PPDDR_S3_PGCMP
R7001
2 1V5S3_PG_CMP
1
SM
USING COMPARTOR INSTEAD OF REGULATOR

PGOOD OUTPUT BECAUSE IF 5V_S3 DOES
NOT COME UP, PPDDR REGULATOR HAS
NO INTERNAL POWER TO PULL PGOOD
LOW
R7002
1V60 IF 1.8V CMP
XW7003
4V12 IF 5V CMP
R7004
5VS0_PG_CMP
4.7K 2
1
1%
1/16W
MF-LF
402
2
SM
OMIT
XW7004
54C5 7D3 6C6
54D6
PP1V5_S0 1
(12VS5_1V27_REF)
1V5S3_COMP_REF
12VS5_1V60_REF
1V8S0_COMP_REF
12VS5_1V27_REF
1V5S0_COMP_REF
7
8
9
10
11
-1
+1
-2
+2
-3
+3
-4
+4
SOI-HF
1%
1/16W
MF-LF
402
OUT1
OUT2
OUT3
OUT4
GND
70B4
70A4
PGOOD_1V8S0_OR_5VS0
1.21K2
1%
1/16W
MF-LF
402
R7014
R70191
100K
SM
OMIT
PLACE SHORTS CLOSE TO PLANE CUTS
1%
1/16W
MF-LF
402
10K
1%
1/16W
MF-LF
402
CAN I USE ALIAS OR DO I NEED INLINE RESISTOR?
6B4
C7020
20%
10V
CERM
402
PLACE RESISTORS CLOSE TO U7020
=PP3V3_S0_PWRCTL
R7007
R7006
49.9K
1%
1/16W
MF-LF
402
49.9K
1%
1/16W
MF-LF
402
R7008
R7030
49.9K
1%
1/16W
MF-LF
402
PGOOD_12V_S0
5%
1/16W
MF-LF
402
OUT
70C8
OUT
70C8
74C6
PGOOD_1V5_S3
S0_PWR_CMP_PGOOD
U7020 Y
PGOOD_1V8S0_OR_5VS0
OUT
70B4
13
PGOOD_1V5_S0
OUT
70B4
ALL_SYS_PWRGD_SMC
R7099
1
33
ALL_SYS_PWRGD_R
(PULLUPS ARE NEAR LOADS)
IRF7410
IRF7413
FDS4435
IRF7406
IRF6402
SI2302
C7056
=PP3V3_S5_PWRCTL
0.1uF
1
70D3 6B7 7B4 7C3 7C4
OUT
5%
1/16W
MF-LF
402
12
70D8 70C1 70B3 70B1 6D1
49D8
OUT
MAKE_BASE=TRUE
PGOOD_1V05_S0
IN
33
5%
1/16W
MF-LF
402
20%
10V
CERM
402
Rds(on)
7mOHM
18mOHM
35mOHM
70mOHM
65mOHM
115mOHM
13A
9.6A
8.8A
5.8A
3.7A
1.6A
Vgs +/8V
20V
25V
20V
12V
8V
PGOOD and Power Sequencing
R7021
4 ALL_SYS_PWRGD
PGOOD_MCPCORE_S0
IN
1%
1/16W
MF-LF
402
85B3 85B8
IN
PM_MXM_PGOOD
7C4 71C7 7C7
IN
VR_PWRGOOD_DELAY
SYNC_MASTER=K50
MC74VHC1G08
SOT23-5-HF
U7056
MCP_PS_PWRGD
OUT
21B7

HYSTERESIS NUMBERS CALCULATED BASED ON OUPTPUT PULL UP OF 3.3V
ALL_SYS_PWRGD IS ALSO AN INPUT TO THIS

AND GATE BY THE FACT THAT
PM_MXM_PGOOD IS PULLED UP TO IT

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
SIZE
DRAWING NUMBER
REV.
TABLE_5_ITEM
114S0341
RES,19.1K,1%,402
R7020
MXM
APPLE INC.
051-7840
SCALE
SHT
NONE
R7098
S0_PWR_REG_PGOOD
76B3
14
TC7SZ08AFEAPE
SOT665
MAKE_BASE=TRUE
10K
10K
6D1 70A3 70B3 70C1 70D8
0.1UF
PGOOD_1V5_S0
(1.30V/1.22V; 80MV HYSTERESIS)
R7003
1V5S0_PG_CMP
12VS5_9V00_REF
12VS0_COMP_REF
MXM
SM
e
r
49.9K
V+
U7010
LM339A
1%
1/16W
MF-LF
1V8S0_PG_CMP 402
OMIT
PP5V_S0
2.0K 2
XW7002
=PP1V8_S0_PGCMP
6A6 78D5
7D3
IG
1
6C4
1.21K2
1
1%
1/16W
MF-LF
402
OMIT
R70051
1%
1/16W
MF-LF
402
XW7001
20%
16V
CERM
603
CRITICAL
12VS0_PG_CMP 1
=PP3V3_S5_PWRCTL
2 402
0.1UF
R7020
64.9K
1%
1/16W
MF-LF
C7010
10
OF
70
109
These caps are for Q7100

CRITICAL
R7120
53B8 6A4
72D7
=PP12V_S0_CPU
10
C7109
PPVIN_S5_IMVP6_VIN
CRITICAL
C7150
470UF
VOLTAGE=12V
1%
1/16W
MF-LF
402
C7196
20%
16V
POLY
TH-HF
0.1UF
10%
16V
X5R
402
72D7 6A4
C7156
10UF
10UF
10%
25V
X5R
1206-1
10%
25V
X5R
1206-1
10%
25V
X5R
805
U7101
PP5V_S0_IMVP6_VDD
C7126
R7121
10
R7199
1%
1/16W
MF-LF
402
C7130
499
LAYOUT NOTE:
(IMVP6_NTC)
Place R7126 in hot

spot of reg circuit.
1
CRITICAL
R7126
C7110
470K
R7197
2
2
(NO IMVP6 PROCHOT)
100A3 12C1
IN
100A3 12C1
IN
100A3 12C1
IN
100A3 12C1
IN
100A3 12C1
IN
100A3 12C1
IN
100A3 12C1
IN
100B3 14A3
10B2
0.01uF
402
10%
16V
CERM
402
9D6
IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>
CPU_DPRSTP_L
100A3 IMVP_DPRSLPVR
IMVP6_PSI_L
IN
IN
R7127
7C4 49D8
4.02K
C7105
R7108
70A3 7C4 7C7
2
2
IN
OUT
147K
0.015UF
10%
16V
X7R
402
1%
1/16W
MF-LF
402
OUT
VR_PWRGD_CLKEN_L
IMVP_VR_ON
VR_PWRGOOD_DELAY
IMVP6_VR_TT_L
IMVP6_NTC
VIN
VDD
71A8
VID6
U7100
33
VID5
QFN
32
VID4
31
VID3
30
VID2
29
VID1
28
VID0
FCCM 24
IMVP6_PMON
OUT
53C8
IMVP6_FCCM
OUT
71A8
72C7
71A8
10%
50V
CERM
402
71A8
71A8
PWM1 27
36
DPRSLPVR
PWM2 26
PSI*
PWM3 25
39
3V3
38
CLK_EN*
IMVP6_PWM3
VR_ON
B
1
ISEN2 22
VR_TT*
ISEN3 21
NTC
SOFT
RBIAS
10
VSUM 17
OCSET 7
71A8
VO 16
71A8
COMP
VW
10%
50V
CERM
402
(IMVP6_VW)
1
C7107
180K
5%
1/16W
MF-LF
402
5%
50V
CERM
402
- 55W PENRYN MODT PROCESSORS: 68A CONTINUOUS CURRENT

SET R7116 TO 18.2K; OC TRIP POINT OF 86.8A, WORST CASE MIN OF 76A.
71C4 72B1
72C1 71C4
71C4
71B5
71C7
71C7
71B7
71B7
71B7
71B7
72C7 71C5
P
R7110
6.98K
47PF
(IMVP6_COMP)
IMVP6_OCSET
IMVP6_VSUM
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB
IMVP6_COMP
IMVP6_VW
IMVP6_FCCM
C7131
e
r
TPAD
71D5
108D3 71D4
71D4
71D4
71D4
72C1 71C3
71D3
72A7 71D2
72A7 71D1
I864
71D4
Q7101
RJK0349DPA
IMVP6_PWM1
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_FET_RC1
IMVP6_VSUM1
IMVP6_VO1
IMVP6_BOOT1_RC
5%
1/4W
MF-LF
1206
0.22UF
20%
25V
X5R
603
NOSTUFF
SM
2
72A7 71A6
72A7
71A6
R7104 1
C7121
OMIT
0.0022UF
10%
50V
CERM
402
R7100
C7112
10%
25V
CERM
402
1 2 3
R7141 1
10K
5%
1/16W
MF-LF
402
1%
1/10W
MF-LF
603
0.22UF
1
1%
1/16W
MF-LF
402
10%
10V
CERM
402
R7101
3.65K
1%
1/10W
MF-LF
2 603
IMVP6_UGATE2
PHASE 7
IMVP6_PHASE2
71A4 4
LGATE
IMVP6_LGATE2
OUT
71A6 72C1
(IMVP6_ISEN1)
THRML
PAD
C7148
C7118
0.1UF
10%
25V
X5R
402
C7120
0.1UF
10%
25V
X5R
402
10%
25V
2 X5R
402
EMC: C7148
PLACE AT L7102.5
CRITICAL
C7146
0.1UF
Q7102
72B1 71A8
10%
25V
X5R
402
RJK0365DPA
NOSTUFF
MLP5X6-LFPAK-WPAK
OUT
71A8
72C1
OUT
71A8
NOSTUFF
C7116
10%
50V
CERM
402
10K
1%
1/10W
MF-LF
603
L7101
1 2 3
0.36UH-45A
(IMVP6_PHASE2)
C7129
18.2K
180pF
1%
1/16W
MF-LF
402
R7116
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
Q7103
RJK0349DPA
71A4
OMIT
R7130 1
R7115
11K
0.033UF
10%
16V
X5R
402
SMB
5%
1/4W
MF-LF
1206
1 2 3
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
B340LBXG
NOSTUFF
IMVP6_VO_R
CRITICAL
72A7
71A4
IMVP6_FET_RC2
C7102
NOSTUFF
C7128
0.0022UF
10%
50V
CERM
402
10%
50V
CERM
402
R7105
10%
6.3V
CERM-X5R
402
10K
C7111
10%
25V
CERM
402
1%
1/16W
MF-LF
402
0.0047UF
1 2 3
R7107
IMVP6_VO2
1
5%
1/16W
MF-LF
402
C7104
0.22UF
1
10%
10V
CERM
402
R7106
3.65K
1%
1/10W
MF-LF
2 603
10KOHM-5%
0.33uF
IMVP6_VSUM2
RJK0349DPA
C7192
0.0022UF
72A7 71A4
Q7105
R7131
OMIT
MLP5X6-LFPAK-WPAK
SM
2
SM
CRITICAL
2.61K
XW7102
DCR=0.84 MOHM
OMIT
XW7101
OMIT
D7101
MLP5X6-LFPAK-WPAK
(IMVP6_VO)
C7134
CRITICAL
R7102
1.0
CRITICAL
MSQ1211R36LE-TH
R7118
R7140 1
CRITICAL
1K
0.001uF
9.31K
C7103
0.0047UF
10%
50V
CERM
402
0603-LF
2
(IMVP6_ISEN2)
LAYOUT NOTE:
PLACE CLOSE TO L7100
(IMVP6_VSUM)
(IMVP6_VO)
R7122
IMVP6_VSEN_P
100A3
CPU_VCCSENSE_P
5%
1/16W
MF-LF
402
IMVP6_VSEN_N
100A3
10%
16V
CERM
402
0.01uF
2
CPU_VCCSENSE_N
5%
1/16W
MF-LF
402
C7132
IN
11B5 100A3
IN
11A5 100A3
10%
16V
CERM
402
DPRSLPVR
DPRSTP*
PSI*
Operation
Mode
3/2-PHASE
CCM
2/1-PHASE
CCM
1
1
108D3 71C4
71C4
71C4
I849
71C5
71C5
71B3
72A7 71B2
72A7 71B1
71C4
I865
71C4
IMVP6 CPU VCORE REGULATOR
R7123
1
NOSTUFF
C7133
0.01uF
RJK0349DPA
0.0022UF
72A7 72B1
20%
6.3V
X5R
402
SM
1
10%
16V
CERM
402
0.22UF
XW7100
CRITICAL
C7190
IMVP6_VO1
NOSTUFF
IMVP6_VSUM1
Q7104
NOSTUFF
C7100
XW7104
SM
B340LBXG
IMVP6_FET_RC1
71A6
OUT
(44A/60A MAX PEAK CURRENT)

OMIT
XW7103
SMB
10K
C7127
5%
1/16W
MF-LF
402
D
72C1 6D6 7D3
DCR=0.84 MOHM
OMIT
D7100
1.0
CRITICAL
CRITICAL
R7103
MLP5X6-LFPAK-WPAK
IMVP6_BOOT2
SIGNAL_MODEL=EMPTY
(FREQUENCY SET TO 304KHZ)
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
RTN 13
19
390pF
10%
50V
CERM
402
R7114 1
71C5
72A7
72C7
IMVP6_DFB
VSEN 12
FB
IMVP6_COMP_RC
UGATE 8
71A4
GND_IMVP6_SGND
330PF
2
EMC: C7145
PLACE AT L7100.2
PPVCORE_CPU
IMVP6_BOOT2_RC
603
OMIT
VOLTAGE=0V
OMIT
C7136
4.7uF
1
R7143
20%
R7117
VSS
C7113
2 6.3V
CERM
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
VDIFF
R7109
C7114
10%
25V
X5R
402
0.36UH-45A
71A4 1
BOOT
6 FCCM
OUT
IMVP6_ISEN1
71A4 IMVP6_ISEN2
IMVP6_ISEN3
ISEN1 23
PGOOD
11
(IMVP6_FB)
C7145
L7100
1 2 3
0.1UF
DROOP 14
1%
1/16W
MF-LF
402
1.82K
1%
1/16W
MF-LF
402 2
10%
25V
X5R
805
CRITICAL
MLP5X6-LFPAK-WPAK
IN
IMVP6_FB
IMVP6_COMP
IMVP6_VW
71A4 108D3
41
IMVP6_LGATE1
CRITICAL
2 PWM
0.01uF
604
VCC
(IMVP6_FCCM)
IMVP6_VDIFF_RC
R7111 1
10UF
10%
25V
X5R
805
0.1UF
MSQ1211R36LE-TH
QFN
DFB 15
IMVP6_PHASE1
U7102
IMVP6_PWM2
C7106
680PF
C7108
10UF
10%
25V
X5R
1206-1
y
r
a
n
i
m
il
PHASE 7
ISL6208
71A4
DPRSTP*
IMVP6_RBIAS
20%
25V
X5R
603
1 2 3
PMON 2
37
40
(GND_IMVP6_SGND)
71A8 IMVP6_VDIFF
1
C7101
10UF
(IMVP6_PHASE1)
71A4
34
35
(GND_IMVP6_SGND)
71A8 IMVP6_SOFT
1%
1/16W
MF-LF
402
402
IMVP6_NTC_R
8D4
20%
16V
POLY
TH-HF
2 X5R
(300KHZ)
CRITICAL
GND
C7155
470UF
LAYOUT NOTE:
PLACE R7108 CLOSE TO RBIAS PIN
C7154
0.22UF
PAD
10%
25V
X5R
402
0.1UF EMC: C7147

10%
PLACE AT Q7100.5
25V
MLP5X6-LFPAK-WPAK
C7115
THRML
GND
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
10%
25V
X5R
402
C7119
RJK0365DPA
0.1UF
Q7100
IMVP6_BOOT1
IMVP6_UGATE1
71A6
LGATE
2.0K
10%
16V
X5R
402
1%
1/16W
MF-LF
402
0.1uF
499
R7119
0
5%
1/16W
MF-LF
402
71A6 8
UGATE
71A6 108D3
VOLTAGE=3.3V
71A6 1
BOOT
6 FCCM
(IMVP6_FCCM)
PP3V3_S0_IMVP6_3V3
2 PWM
IMVP6_PWM1
20
PM_DPRSLPVR
71A6
ISL6260CCRZ
=PP3V3_S0_IMVP
6.3V
CERM
603
QFN
1UF
10%
25V
X5R
603-1
C7117
0.1UF
CRITICAL
1%
1/16W
MF-LF
402
IMVP6_BOOT1_RC
C7135
4.7uF
R71421
20%
ISL6208
VOLTAGE=5V
18
10
VCC
R7112
1
C7147
D
71A6
IN
=PP5V_S0_IMVP
21C7 100A3
C7152
10UF
CRITICAL
6B4
These caps are for Q7102
IMVP6_PWM2
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
IMVP6_FET_RC2
IMVP6_VSUM2
IMVP6_VO2
IMVP6_BOOT2_RC
3/2-PHASE
2/1-PHASE
IMVP6 CPU VCore Regulator

SYNC_MASTER=K50
DCM
DCM

I850

SIZE
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
I866
DRAWING NUMBER
10
OF
71
109
IMVP6 CPU VCORE REGULATOR
D
71D8 53B8 6A4
=PP12V_S0_CPU
71D8 6A4
=PP5V_S0_IMVP
y
r
a
n
i
m
il
CPUV_PHASE3
1 CPUV_PHASE3
C7235
4.7uF
NO_CPUV_PHASE3
2
R7210
20%
6.3V
CERM
603
ISL6208
QFN
71A8 71C5
IN
2 PWM
IN
IMVP6_FCCM
6 FCCM
72A7 1
BOOT
IMVP6_UGATE3
PHASE 7
IMVP6_PHASE3
72A7 4
LGATE
IMVP6_LGATE3
0.22UF
72A7
IMVP6_BOOT3_RC
5%
1/16W
MF-LF
402
THRML
10%
25V
X5R
402
10%
25V
X5R
402
10%
25V
X5R
402
CRITICAL
C7254
EMC: C7247
PLACE AT Q7200.5
CPUV_PHASE3 CPUV_PHASE3
C7255
470UF
20%
16V
POLY
TH-HF
C7201
CPUV_PHASE3
C7208
10UF
10UF
10UF
10%
25V
X5R
1206-1
10%
25V
X5R
1206-1
10%
25V
X5R
1206-1
CPUV_PHASE3
Q7200
10%
25V
402
CPUV_PHASE3
CRITICAL
L7200
1 2 3
CPUV_PHASE3
CRITICAL 2
1
R7203
CPUV_PHASE3
CRITICAL
RJK0349DPA
5%
1/4W
MF-LF
1206
OMIT
SM
72A7
CPUV_PHASE3 1
IMVP6_FET_RC3
72A7
1 2 3
IMVP6_VSUM3
RJK0349DPA
CPUV_PHASE3
NOSTUFF
C7200
0.0022UF
C7290
0.0022UF
10%
50V
CERM
402
10%
50V
CERM
402
R7200
10K
5%
1/16W
MF-LF
402
1%
1/10W
MF-LF
603
10%
25V
CERM
402
1%
1/16W
MF-LF
402
0.0047UF
1 2 3
10K
CPUV_PHASE3 1
C7212
2
R7201
R7241
CPUV_PHASE3
CRITICAL
MLP5X6-LFPAK-WPAK
NOSTUFF
R7204
Q7204
IMVP6_VO3
NOSTUFF
72A7
SM
B340LBXG
MLP5X6-LFPAK-WPAK
71D1 6D6 7D3
XW7204
DCR=0.84 MOHM
XW7203
SMB
PPVCORE_CPU
OMIT
MSQ1211R36LE-TH
D7200
1.0
Q7201
(55A/64A MAX CURRENT)
0.36UH-45A
EMC: C7245
PLACE AT L7200.2
2 X5R
MLP5X6-LFPAK-WPAK
20%
25V
X5R
603
C7245
0.1UF
RJK0365DPA
PAD
9
IMVP6_BOOT3
72A7 8
UGATE
72A7 108D3
GND
0.1UF
CPUV_PHASE3
CRITICAL
C7215
R7250
U7201
IMVP6_PWM3
CPUV_PHASE3
CPUV_PHASE3
VCC
72A7 71C5
C7211
0.1UF
CPUV_PHASE3
CRITICAL
CPUV_PHASE3
C7210
0.1UF
CPUV_PHASE3
10K
1%
1/16W
MF-LF
2 402
CPUV_PHASE3
C7247
CPUV_PHASE3
C7203
IMVP6_ISEN1
IN
71C3 71A6
IN
71C4 71A8
IMVP6_ISEN3
IN
71C5 72A7
IMVP6_VSUM
OUT
71A8 71C4
0.22UF
1
IMVP6_VO
10%
10V
CERM
402
CPUV_PHASE3
3.65K
1%
1/10W
MF-LF
2 603
CPUV_PHASE3
NO TEST FOR CPU VREG, ADDED K2/K3

71A6 71D1
IN
71A4 71B1
IN
72A7 72C2
IN
71A6 71D2
IN
71A4 71B2
IN
72A7 72C3
IN
72C7 71C5
108D3 72C6
72C6
72C6
72C6
72B1 71C5
72C3
72A7 72C3
72A7 72C2
72C5
IMVP6_VO1
IMVP6_VO2
IMVP6_VO3
IMVP6_VSUM1
IMVP6_VSUM2
IMVP6_VSUM3
IMVP6_PWM3
IMVP6_PHASE3
IMVP6_BOOT3
IMVP6_UGATE3
IMVP6_LGATE3
IMVP6_ISEN3
IMVP6_FET_RC3
IMVP6_VSUM3
IMVP6_VO3
IMVP6_BOOT3_RC
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
e
r
IMVP6 3RD PHASE
I51
I43
I44
I45
I46
I48
I47
I49
I50
I57
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
72
109
=PPVIN_S5_P5VS3
5V S3 REGULATOR
6C1 73D5
CRITICAL
1
C7342 C7300
270UF
10UF
20%
10%
16V
ELEC
8X12-TH-HF X5R-CERM
0805
C7335
C7332
10UF
2
10UF
10%
16V
X5R-CERM
0805
2 16V
10%
16V
X5R-CERM
0805
=PPVIN_S5_P5VS3
6C1 73D4
10%
16V
X5R
603
C7354
B0530WXG
SOD-123-HF
11
10
10%
35V
X5R-CERM
0805
5VS3_TG
CRITICAL
U7300
C7331
10%
16V
X5R
402
R73011
100K
0.1UF
2
5%
1/16W
MF-LF
402 2
C7316
0.1UF
10%
16V
X5R
402
C7303
10%
16V
X5R
402
ILIM
FREQ/PLLFLTR
RUN
TK/SS
5VS3_ITH
73A3
IN
TG 13
SW 14
BOOST 12
C7315
5%
50V
CERM
402
5VS3_SENSEN
SWITCHNODE
PLACE XW CLOSE
TO L7320 OMIT
C7307
100PF
5%
50V
2 CERM
402
1 2 3
MLP5X6-LFPAK-WPAK
5V_SNUBBER
1%
1/10W
MF
2 603
C7325
20PF
5%
50V
2 CERM
402
S3
1.5K
C7302
(5VS3_VOUT)
RA
R73051
43.2K
1%
1/16W
MF-LF
402 2
C7309
330UF
20%
6.3V 2
POLY-TANT
CASE-D3L-SM
C7301
10UF
20%
6.3V
2 CERM
805-1
100PF
5%
50V
CERM 2
402
10UF
20%
6.3V
2 CERM
CRITICAL
1
C7322
805-1
C7305
330UF
20%
2 6.3V
POLY-TANT
CASE-D3L-SM
LTCMODE
Mode
CONT MODE
BURST MODE
10%
10V
CERM
402
1.24K
10K
1%
1/16W
MF-LF
402 2
(5VS3_FB)
LTCINTVCC
73C7
R7311
100K
5%
1/16W
MF-LF
2 402
5VREG_PS_L
Q7303
SI2301BDS
SM-HF
CRITICAL
1
D
3
PM_SLPS3_BUF1_R_L
R7312
100K
R7310
PM_SLPS3_BUF1_L
1%
1/16W
MF-LF
402 2
R73071
5VS3_SENSEN_R
e
r
94D7 9D6
CRITICAL
8.06K
OMIT
1%
1/16W
MF-LF
402 2
R7362
0.499
XW7301
SM
1
R73361
C7317
5VS3_FB
CTLSH3-30M833
1
0.22UF
S0
6C4 7D3
R73061
1%
1/16W
MF-LF
2 402
PM_SLP3_BUF1_L 5VREG_PS_L
CRITICAL
D7300
XW7300
5VS3_SENSE
RJK0349DPA
PP5V_S3_REG
PLACE XW CLOSE
TO L7320 2
RB
R7302
24.9K
STATE
PEAK=8.86A
AVE=7.3A
10%
25V 2
X5R
402
TLM833
C7363
0.0022UF
10%
50V
2 CERM
402
Q7335
5%
1/16W
MF-LF
402
0.1UF
SM
CRITICAL
C7304 1
L7320
5% MIN_NECK_WIDTH=0.2 MM
10%
1/10W
25V
MF-LF
X5R
603
402
R7304
5V_S3
K50/K51
POWER BUDGET
2.2UH-10A-11.6M-OHM
0.1UF
100PF
10%
25V
X5R
402
CRITICAL
C7326
1 5V_BOOT1_R 2
0.1UF
1 2 3
17
8
10%
50V
2 CERM
5VS3_ITH_R 402
1
5VS3_SENSEP
FB 4
C7306
0.001UF
C7356
5VS3_SW
R7324
THRM
GND PAD
EMC: C7304,C7356
PLACE AT L7320.1
RJK0365DPA
MLP5X6-LFPAK-WPAK
5V_BOOT1
SENSE+ 6
SENSE- 5
LTCMODE 15 MODE/PLLIN
CRITICAL
Q7330
ITH
BG 9 5VS3_BG
0.1UF
2
7
16
1
SM
LTCINTVCC
5VS3_FREQ
=5VREG_EN
5VS3_TK_SS
SOFT START TIME 80MS
10%
25V
X5R
402
108D3
QFN
70D6
0.1UF
LTC3851EUD
73B4
C7353
10%
25V
X5R
402
INTVCC VIN
OSCILLATED AT APPR. 330KHZ
0.1UF
D7301
4.7UF
C7334
y
r
a
n
i
m
il
EMC: C7353,C7354
PLACE AT Q7330
2.2UF
C7345
5%
1/16W
MF-LF
2 402
Q7360
MMBT3904G
5V_S3 REGULATOR
SOT23
5%
1/16W
MF-LF
402
SYNC_MASTER=K50
LTCMODE

73C6

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
73
109
MCP CORE
6A4
R7460
2.2
1
2
=PP5V_S3_MCPREG
R7461
1K
R7490
21A3 21C3
21A3 21C3
IN
IN
MCP_VID<0>
MCPCORES0_RBIAS
5%
1/16W
MF-LF
402
MCP_VID<1>
R7491
1
IN
2
5%
1/16W
MF-LF
402
MCP_VID<2>
70B4
5%
1/16W
MF-LF
402
1NOSTUFF
R7480
20.0K
R7481
20.0K
1%
1/16W
MF-LF
2 402
31
25
26
27
OUT PGOOD_MCPCORE_S0
70C5
1%
1/16W
MF-LF
2 402
IN
MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCPCORES0_OS0
MCPCORES0_OS1
=MCPCORES0_EN
MCPCORES0_FDE
23
24
29
30
32
8
9
MCPCORES0_VSEN
MCPCORES0_RTN
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
R7482
20.0K
R7483
20.0K
BOOT 17 MCPCORES0_BOOT
PHASE 19
108D3
0.2 MM
0.25 MM
5%
1/10W
MF-LF
603
2 MCPCORES0_BOOT_R
0.25 MM
0.2 MM
MCPCORES0_COMP
PLACE XW NEAR THE MCP,

CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP
MCPCORES0_RSEN_H
XW7463
SM
2
MCPCORES0_RSEN_L
C7470
0.001UF
(MCPCORES0_RTN)
R7477
133K
1
2
P
C7479 1
0.001UF
10%
50V 2
X7R
402
5%
50V
CERM
402-1
MCPCORES0_COMP_C
100
1%
1/16W
MF-LF
402
R7479
1%
1/16W
MF-LF
402
20%
2V
POLY
CASE-D2-HF
C7484
C7465
10UF
330UF-0.009OHM
20%
4V
X5R
603
20%
2V
POLY
CASE-D2-HF
C7483 1
10UF
20%
4V
X5R
603
C7469
0.0027UF
10%
50V
CERM
402
MCPCORES0_ISP_R
(=PPMCPCORE_S0_REG)
MCPCORES0_OCSET
33
OMIT
XW7402
SM
2 MCPCORES0_ISN_R
1
(MCPCORES0_VO)
R7467
1K
R7469
9.53K
THRM_PAD
15
VSS
1%
1/16W
MF-LF
2 402
R7470
10K
C7473
0.12UF
10KOHM-5%
CRITICAL
1%
1/16W
MF-LF
2 402
10%
10.0V
2 CERM-X5R
402
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
R7473
10K
XW7461
OMIT
(MCPCORES0_ISP)
(MCPCORES0_ISN)
1%
1/16W
MF-LF
2 402
C7477
0.1UF
10%
2 25V
X5R
402
C7478
0.1UF
10%
2 25V
X5R
402
R7475
59.0K
1%
1/16W
MF-LF
2 402
(MCPCORES0_ICOMP)
NEED NEW TABLE?
Rev A01
Rev A01P Production
Voltage
Voltage
Voltage
000
+1.224V
+1.355V
+1.060V
001
+1.158V
+1.243V
+0.994V
010
+1.101V
+1.216V
+0.937V
011
+1.047V
+1.124V
+0.885V
100
+0.996V
+1.065V
+0.830V
101
+0.952V
+0.994V
+0.789V
110
+0.913V
+0.977V
+0.752V
111
+0.876V
+0.917V
+0.719V
VID<2:0>
(MCPCORES0_FB)
C7482
2.21K2
1
20%
4V
X5R
603
1%
R7465
1/16W 0603-LF
MF-LF
2 402
560PF
MCPCORES0_VDIF_C
C7466
10UF
R7464
11.3K
(MCPCORES0_COMP)
R7478
CRITICAL
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
402
C7468
330UF-0.009OHM
R7476
6.98K
C7481
560PF
1%
1/16W
MF-LF
402
R7472
150K
e
r
(MCPCORES0_VW)
10%
25V
2 X5R
SM
1%
1/10W
MF
2 603
CRITICAL
1
0.1UF
XW7460
MCPCORES0_SNUBBER
VOLTAGE=0V
1%
1/16W
MF-LF
2 402
C7480
68PF
10%
50V
2 CERM
402
RJK0349DPA
1 C7467
C7463
0.0022UF 2OMIT
ISP 13 MCPCORES0_ISP
ISN 11 MCPCORES0_ISN
GND_MCPCORES0_AGND
10%
2 50V
X7R
402
R7471
100
10%
16V
X7R-CERM 2
402
(MCPCORES0_VSEN)
1
MLP5X6-LFPAK-WPAK
SM
R7468
20
1%
1/16W
MF-LF
402
OMIT
C7476
0.1UF
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
OMIT
R7466
20
F = 200-300 KHZ
MMD12EZ-SM
R7462
0.499
7 VDIFF
20
R7463
100
Q7465
402
L7460
OCSET 3
PGND
SM
CRITICAL
CRITICAL
GATE_NODE=TRUE
2 X5R
1.0UH-29A-2.5MOHM
1 2 3
6 FB
PPMCPCORE_S0_REG
XW7462
10%
25V
CERM-X7R
10V
603
5%
(MCPCORES0_LGATE) 4
MAX CURRENT: 20A
0.1UF
1 2 3
5 COMP
(MCPCORES0_PHASE)
SWITCHNODE
5
SWITCH_NODE=TRUE
ICOMP 10 MCPCORES0_ICOMP
PPMCPCORE_S0_REG
74B8 6D6 7D3 54B5 74C7
Vout = See below
1 C7457
C7464
PPMCPCORE_S0_REG
MCPCORES0_FB
74C7 54B5 7D3 6D6 74D1
10%
25V
X5R
805
0.22UF
MCPCORES0_PHASE
LGATE 21 MCPCORES0_LGATE
10%
25V
X5R
805
C7475
10UF
EMC: C7467,C7457
PLACE AT L7460
RJK0365DPA
MLP5X6-LFPAK-WPAK
R7474
UGATE 18 MCPCORES0_UGATE
805
Q7460
GATE_NODE=TRUE
10%
2 25V
X5R
C7474
10UF
CRITICAL
VIN 14
VO 12 MCPCORES0_VO
MCPCORES0_VDIFF
54B5 7D3 6D6 74D1 74B8
(MCPCORES0_UGATE)
QFN
PGOOD
VID0
VID1
VID2
OFFSET0
OFFSET1
VR_ON
AF_EN
FDE
VSEN
RTN
10%
25V
X5R
402
4 VW
MCPCORES0_VW
1
C7462
1UF
0.1UF
10%
25V
X5R
402
C7460
10UF
20%
16V 2
ELEC
8X12-TH-HF
1 C7472
10%
16V
2 X5R
402
U7401
28 IMON
MCPCORES0_IMON
54B5
1NOSTUFF
y
r
a
n
i
m
il
1 RBIAS
PVCC
2 SOFT
MCPCORES0_SOFT
R7492
21A3 21C3
VDD
5%
1/16W
MF-LF
2 402
1 C7455
0.1UF
10%
16V
X5R 2
402
0.6 mm
0.2 MM
22
C7461
1UF
EMC:
PLACE AT Q7460
VOLTAGE=12V
C7471
270UF
5V_S3_MCPREG_VIN
ISL6263D
6D3
=PP3V3_S3_MCPREG
=PPVIN_S0_MCPCORE
CRITICAL
5%
1/10W
MF-LF
603
16
6C3
10%
50V
CERM
402
(MCPCORES0_VDIFF)
MCP CORE REGULATOR

SYNC_MASTER=K50

(Also A01Q)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
74
109
1.5 V DDR SUPPLY

D
D
PPDDR_S3_REG
y
r
a
n
i
m
il
VOUT
PEAK
AVG
= 1.5V
= 14.75A
= 8.33A
C7555
10UF
6C3
4.7
6C1
=PPVIN_S5_DDRREG
EMC CAPS
PLACE CLOSE TO FET
CRITICAL
R7505
=PP5V_S3_DDRREG
20%
6.3V
X5R
603
C7530
PP5V_S3_DDRREG_V5FILT
VOLTAGE=5V
5%
1/16W
MF-LF
402
CRITICAL
C7531
270UF
270UF
20%
16V
ELEC
8X12-TH-HF
20%
16V
ELEC
8X12-TH-HF
C7532
10%
16V
X5R-CERM
0805
C7510
0.1UF
10UF
20%
16V
CERM
603
C7511
0.1UF
20%
16V
2 CERM
603
10%
10V
X5R
402
V5FILT
VLDOIN
6 COMP
IN
7D3 6D4
PPVTT_S3_DDR_BUF
7D3 6D6
PPVTT_S0_DDR_LDO
10 S3
11 S5
13 PGOOD
VDDQ/VTTREF Enable
VDDQ PGOOD
10mA max load
VBST 22
U7500
DRVH 21
LL 20
Vout = VTTREF
DRVL 19
20%
6.3V
CERM-X5R
C7561
22UF
805-3
NC
NC
CS 16
7 NC0
12 NC1
20%
6.3V
CERM-X5R
805-3
VDDQSET 9
VTTGND
THRM_PAD GND
Q7530
MLP5X6-LFPAK-WPAK
C7525
R7525
5%
1/10W
MF-LF
603
DDRREG_VBST_R
(DDRREG_LL)
CRITICAL
Q7535
RJK0349DPA
5%
25V
2 NP0-C0G
402
MLP5X6-LFPAK-WPAK
DDRREG_FB
1 2 3
603
C
PPDDR_S3_REG
20%
2 2V
POLY
CASE-D2-HF
CRITICAL
20%
2V 2
POLY
CASE-D2-HF
C7541
330UF-0.009OHM
1%
1/10W
MF
2 603
SM
C7545
10UF
20%
6.3V
X5R
603
XW7545
C7550
STATE
S0
S3
S5
S3
HI
LO
LO
S5 VDDQ VTTREF
ON
HI
ON
ON
HI
ON
LO
OFF
OFF
VTT
ON
OFF
OFF
10%
16V
X5R
402
e
r
2
XW7500
SM
GND_DDRREG_SGND
VOLTAGE=0V
SM
PLACEMENT_NOTE=PLACE NEXT TO L7530

1
NO STUFF
C7520
1
1
5%
50V
CERM
402
R7520
15.0K
100PF
(DDRREG_VDDQSNS)
0.033UF
6D4 7D3
VOUT = 1.50V
14.75A MAX OUTPUT
(Q7335 limit)
f = 400 kHz
R7562
0.499
XW7535
1
C7563
1000PF
1V5_SNUBBER
PLACEMENT_NOTE=Place next to Q7335
C7540
330UF-0.009OHM
(DDRREG_DRVL)
(DDRREG_CSGND)
CRITICAL
DDRREG_CS
DDRREG_CSGND
MSQ12111R5LE-TH
20%
16V
2 CERM
L7530
1.5UH-22A-3.12MOHM
SWITCHNODE
10%
50V
X7R-CERM
805
C7513
0.1UF
20%
16V
CERM
603
CRITICAL
1 2 3
0.1UF
C7512
0.1UF
RJK0365DPA
PGND CS_GND
18
22UF
2 VTTSNS
DDRREG_VTTSNS
NO_TEST=TRUE
FEEDBACK THROUGH SHORT
SHOULD NOT NEED TP
C7560
DDRREG_DRVL
GATE_NODE=TRUE
CRITICAL
DDRREG_LL
SWITCH_NODE=TRUE
25
CRITICAL
DDRREG_DRVH
GATE_NODE=TRUE
SYM (2 OF 2)
24 VTT
SM
1
DDRREG_VBST
QFN
5 VTTREF
Vout = VDDQSNS/2
1%
1/16W
MF-LF
402 2
MODE 4
VTT Enable
TPS51116
XW7560
CRITICAL
10K
17
70D6
DDRVTT_EN
=DDRREG_EN
TP_PGOOD_DDRREG_S3
R7510 1
VDDQSNS 8
CRITICAL
IN
DDRREG_VDDQSNS
(DDRREG_DRVH)
V5IN
C
78A4 9C2
EMC CAPS
PLACE CLOSE TO L7530
1UF
2
23
20%
6.3V
CERM
603
14
C7505
4.7UF
15
C7500
1%
1/16W
MF-LF
2 402
<Ra>
(DDRREG_FB)
Vout = 0.75V * (1 + Ra / Rb)
R7521
15.0K
1%
1/16W
MF-LF
402
<Rb>
1.5V DDR SUPPLY

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
75
109
3.3V S5 AND 1.05 S0 RAILS
y
r
a
n
i
m
il
INPUT POWER OF 12V_S5
6C1
=PP12V_S5_REG
6C1
EMC CAPS
PLACE CLOSE TO FET
=PPVIN_S5_P3V3S5
CRITICAL
C7680
C7681 1
20%
16V
POLY
6.3X9-TH
R7650
2.2
C7612
C7610
10UF
10UF
10%
16V
X5R-CERM
0805
10%
16V
X5R-CERM
0805
C7611
0.1UF
20%
16V
CERM
603
20%
16V
CERM
603
Q7610
C7622
0.1UF
FDMS9600S
MLP
1
(P1V05S0_UGATE)
C7601
GATE_NODE=TRUE
10UF
10%
16V
X5R
1206
PP5V_S5_LDO
Q1
C7670
1UF
10
10%
16V
X5R
603
SW
8
(P1V05S0_LGATE)
GATE_NODE=TRUE
7
1
C7614
1.5UH-12A
10%
50V
X7R
603-1
(P1V05S0_PHASE)
SWITCHNODE
MMD06EZ-SM
f = 200 kHz
PLACEMENT_NOTE=Place next to C7516
SWITCH_NODE=TRUE
P1V05S0_BOOT
P1V05S0_UGATE
108D3 P1V05S0_PHASE
P1V05S0_LGATE
(=P1V05S0_EN)
SM
1
CRITICAL
C7615
C7617
10UF
10UF
10%
16V
X5R-CERM
0805
10%
16V
X5R-CERM
0805
C7621
1
1
330UF-0.009OHM
2
20%
2V 2
POLY
CASE-D2-HF
C7623
C7616
0.1UF
0.1UF
20%
16V
CERM
603
20%
16V
CERM
603
C7662
1000PF
XW7616
5%
25V
2 NP0-C0G
402
EN LDO ASAP
P1V05S0_VSNS
R7663
0.499
P1V05S0_FB
P1V05S0_ILIM
OMIT
1V05_SNUBBER
1
R7620
USING 0.5% RES SO RAIL NEVER

LESS THAN 1.025V
5%
50V
CERM
402
<Rb>
=1V05S0_EN
R7614
1%
1/16W
MF-LF
2 402
Vout = 0.7V * (1 + Ra / Rb)

IN
150K
0.5%
1/16W
MF
2 402
70C5
R7621
6
17
15
16
18
10
14
9
11
12
29
4
C7625
0.1UF
20%
16V
2 CERM
603
6C2 7C3
C7689
VIN
BOOT1
UGATE1
PHASE1
LGATE1
OUT1
EN1
BYP
FB1
ILIM1
SKIP*
EN_LDO
20%
6.3V
CERM
603
108D3
3V3S5_SW
SWITCHNODE
LDO
LDOREFIN
CRITICAL BOOT2
UGATE2
PHASE2
QFN
LGATE2
OUT2
EN2
U7600
SEL A3V3 S5
K50/K51
POWER BUDGET
CRITICAL
FDMS9600S
7
8
24
26
25
23
30
27
REF 1 76A6
POK1 13
POK2 28
K50 PEAK=4.94A
K50 AVE=2.18A
CRITICAL
R7666
3V3_BOOT2
0.25MM
0.2MM
L7660
2.2UH-10A-13.6MOHM
23V3_BOOT2_R
Q1
0.25MM
5%
0.2MM
1/10W
MF-LF
603
EN REG ASAP
AFTER LDO OUT
10
SW
C7666
0.1UF
10%
2 25V
X5R
402
R7675 1
200K
3V3S5_ILIM
5%
1/16W
MF-LF
2 402
3V3S5_REF
Q2
1UF
10%
16V
X5R
603
7 6 5
PGOOD_1V05_S0
OUT
70B4
5
20
38C8
38B7 6B8
6D2 7C3
R7662
0.499
CRITICAL
C7691 1
0.1UF
OMIT
XW7651
SM
1%
1/10W
MF
2 603
10UF
20%
16V
CERM 2
603
C7693 1
C7694
20%
2 6.3V
CERM
805-1
C7626
330UF
20%
6.3V 2
POLY-TANT
CASE-D3L-SM
1
0.1UF
C7692
10UF
20%
16V
PGOOD_3V3_S5
20%
2 CERM
6.3V
2 CERM
603
NC
NC
PP3V3_S5_REG
C7663
1000PF
5%
25V
2 NP0-C0G
402
3V3_SNUBBER
C7675
(3.3V NOMINAL)
MMD06EZ-SM
3V3S5_BG
REFIN2 32
ILIM2 31
9 4 3 2
MLP
3V3S5_TG
2 TON
3V3REG_TON
100PF
0.5%
1/16W
MF
402
10.0K
PEAK=8.3A
AVE=4.4A
e
r
C7620
<Ra>
1V05_S0
K50/K51
POWER BUDGET
76A6
NO STUFF
5.23K
1%
1/10W
MF
2 603
EMC CAPS
PLACE CLOSE
TO L
Q7660
PVCC VCC
5%
1/10W
MF-LF
603
0.1UF
L7610
1
ISL6237
CRITICAL
(R7614 LIMIT)
3V3REG_VCC
805-1
NC
THRM_PAD GND
21
6.7A MAX OUTPUT
20%
16V
CERM
603
VOLTAGE=5V
33
P1V05S0_BOOT_R
PP1V05_S0_REG
19
R7610
Q2
Vout = 1.058V
0.1UF
10%
16V
X5R-CERM
0805
4.7UF
76A6
7D3 6D6
C7624
10UF
PGND
22
10%
16V
X5R-CERM
0805
C7683
VOLTAGE=12V
CRITICAL
10UF
PPVIN_S5_3V3_1V05_R
EMC CAPS
PLACE CLOSE TO FET
=PPVIN_S0_P1V05S0
C7613
10%
16V
X5R-CERM
0805
5%
1/8W
MF-LF
2 805
INPUT POWER OF 12V_S0
6A4
10UF
100UF
3V3S5_OUT
C7685 1
0.1UF
10%
16V
X7R-CERM 2
402
EMC CAPS
PLACE CLOSE
TO L
R7667
121K
1%
1/16W
MF-LF
2 402
GND_PP3VREG_SGND
VOLTAGE=0V
OMIT
1
XW7650
SM
SELECTS SWITCHING FREQUENCY

76C5
3V3REG_VCC
1 NOSTUFF
R7643
EN_LDO TIED TO 12V_S5 TO EN LDO FIRST & REGULATOR INTERNAL LOGIC GETS POWER
EN2 (3V3_S5) IS TIED TO VCC, TIED INTERNALLY TO PVCC
TIED EXTERNALLY TO LDO OUT. SO REGULATOR IS ENABLED
3V3REG_TON
AS SOON AS LDO OUTPUT IS GOOD
5%
1/16W
MF-LF
2 402
EN1 (1.05_S0) CONTROLLED SEPARATELY
1.05VS0/3.3V S5 SUPPLIES
76B5
SYNC_MASTER=K50
R7622
0
2
76B4
5%
1/16W
MF-LF
402

3V3S5_REF

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
76
109
IRF7410GPBF
IRF7410GPBF
6C3
PP5V_S0
SO-8
=PP5V_S3_S0FET
C7801
R7800 1
5%
1/16W
MF-LF
402
10%
10V
X5R
402
2
2
4
C7800
P5VS0_SS
1%
1/16W
MF-LF
402
10%
16V
CERM
402
=P5VS0_EN
y
r
a
n
i
m
il
2
C7850
R7851
0.01UF
61.9K
P3V3S3_SS
1%
1/16W
MF-LF
402
10%
16V
CERM
402
Q7851
70D6
BSS138_G
Q7801
IN
10%
16V
X5R
402
70C5
0.033UF
P3V3S3_EN_L
0.01UF
147K
P5VS0_EN_L
5%
1/16W
MF-LF
402
R7801
C7851
10K
0.15UF
10K
R7850
6B7 6C8 6D4 7D3
8
3
PP3V3_S3
SO-8
=PP3V3_S5_S3FET
6C1
70A8 6A6 7D3
CRITICAL
Q7850
3.3V S3 FET
CRITICAL
Q7800
5V S0 FET
=P3V3S3_EN
IN
BSS138_G
SOT23
SOT23
CRITICAL
Q7853
3.3V S0 FET
IRF7410GPBF
SO-8
=PP3V3_S5_S0FET
6C1
PP3V3_S0
53C3 6B6 6B8 6D7 7D3
3
2
C7852
R7852 1
5%
1/16W
MF-LF
402
10%
25V
X5R
402
100K
1%
1/16W
MF-LF
402
R7853
P3V3S0_EN_L
0.1UF
10K
C7853
0.033UF
P3V3S0_SS
10%
16V
X5R
402
Q7854
70C5
=P3V3S0_EN
IN
BSS138_G
SOT23
MCP79 DDRVTT FET
B
70D8 6C3
1.5V S0 FET
=PP5V_S3_PWRCTL
6D3
e
r
=PPDDR_S3_S0FET
C7829
0.1UF
P
R7827
33.2K
R7825
10K
1%
1/16W
MF-LF
402
R7826
P1V5S0_EN_L
3
6 7
10K
1%
1/16W
MF-LF
402
Q7825
FDS8870_G
IN
=MCPDDR_EN
PP1V5_S0_FET
Q7827
54D7
6C3
VTTCLAMP_L
Q7875
90mA max load @ 0.9V

81mW max power
I
IRF7410
IRF7413
FDS4435
IRF7406
IRF6402
SI2302
5%
1/16W
MF-LF
402
SOT563
100K
SOT23
C7826
10%
10V
CERM
402
Q7875
P1V5S0_EN_L_RC
NO STUFF
C7876
SSM6N15FEAPE
20%
50V
CERM
402
5
75C8 9C2
IN
SYNC_MASTER=K50
Rds(on)
7mOHM
18mOHM
35mOHM
70mOHM
65mOHM
115mOHM
Vgs +/8V
20V
25V
20V
12V
8V
0.001UF
SOT563
13A
9.6A
8.8A
5.8A
3.7A
1.6A
S3 & S0 FETs
VTTCLAMP_EN
0.068UF
2
SSM6N15FEAPE
R7876 1
2
1
10
=PP5V_S3_VTTCLAMP
BSS138_G
=PPVTT_S0_VTTCLAMP
5%
1/10W
MF-LF
603
MAKE_BASE=TRUE
VOLTAGE=1.5V
SOT23-HF1
6D4
Q7826
R7875
SO-8
2N7002
70C5
CONFIRM USING THIS FET
CRITICAL
P1V5S0_SS
1%
1/16W
MF-LF
402
10%
25V
X5R
402
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.

DDRVTT_EN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
78
109
y
r
a
n
i
m
il
MCP 1.05V_S5 AUXC SUPPLY

=PP3V3_S5_P1V05S5
R7922
1
(ENABLED AT 2,8V MINIMUM)

1
R7923
23.2K
1%
1/16W
MF-LF
402
C7920
20%
6.3V
CERM
805
1V05S5_AVIN
2.2UH-3.25A
NOSTUFF
0.1UF
10%
402
U7950
TPS62510
7 MODE
C7901
2 16V
X5R
OVT
C7981
BQA
FB
PG
10%
2 16V
X5R
402
PP1V05_S5_REG
<Ra>
1%
1/16W
MF-LF
402
C7982
5%
2 50V
CERM
402
1V05S5_FB
<Rb>
R7981
38C6 6D2 7C3
Vout = 1.05V
R7980
49.9K
22PF
AGND PGND THRM_PAD
0.1UF
EN
1 1V05S5_SW 1
SWITCHNODE
11
CRITICAL SW
CRITICAL
L7920
IHLP1616BZ-SM
AVINPVIN
P1V05_S5_EN
22UF
5%
1/16W
MF-LF
402
10
6D1
MAX Current = 1.5A
C7983
FREQ = 1Mhz
22UF
20%
6.3V
CERM
805
66.5K
PGOOD_1V05_S5 70C2
1%
1/16W
MF-LF
402
VOUT = 0.6V * (1 + Ra / Rb)
e
r
1V05 S5 POWER SUPPLY

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
79
109
y
r
a
n
i
m
il
MCP ONLY 1.8V_S0 POWER SUPPLY

=PP5V_S0_1V8
IG
R8020
49.9K
IG
1
C8016
10UF
6A4
IG
CRITICAL
IG
CRITICAL
VIN
1%
1/16W
MF-LF
402 2
U8001
L8010
TPS62200
4
20%
10V
2 X5R
805
1V8S0_EN
SW 5
GND
10UH-1.7A
SOT23-5-LF
FB
EN
1V8_SW
SWITCHNODE
108D3
PP1V8_S0_REG
6C6 7D3
MSCDRI5D48-SM
VOUT = 1.8V
MAX CURRENT = 300MA
IG
IG
C8025
R80101
0.68UF
<RA)
10%
6.3V
CERM 2
402
1V8_FB
47.5K
1%
1/16W
MF-LF
402 2
IG
R80111
VOUT = 0.5 * (1 + RA/RB)
18.2K
<RB)
e
r
1%
1/16W
MF-LF
402 2
NOSTUFF
C8012
IG
33PF
C8013
IG
10UF
20%
10V
X5R 2
805
5%
50V
CERM 2
402
C8014 1
10UF
20%
10V
X5R 2
805
NOSTUFF
C8015
100PF
5%
50V
CERM 2
402
1V8 POWER SUPPLY

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
80
109
Page Notes
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC
(NONE)

- MXM
=PP3V3_S0_MXM
MXM
CRITICAL
MXM
100K
MXM_CLKREQ_L
155
153
87C7
MXM_RESET_L
156
86A4 102D3
86A4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86B4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86C4 102D3
86D4 102D3
86D4 102D3
86D4 102D3
86D4 102D3
86D4 102D3
86D4 102D3
86D4 102D3
102D3 86A5
102D3 86A5
102D3 86A5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86B5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86C5
102D3 86D5
19
CLK_100M_MXM_P
CLK_100M_MXM_N
86A4 102D3
MXM_PCIE_STD_SWING_L
87C7
87C7
154
102D3 86D5
102D3 86D5
102D3 86D5
102D3 86D5
102D3 86D5
102D3 86D5
MXM_PCIE_D2R_N<0>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_N<2>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<5>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_P<6>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_N<11>
MXM_PCIE_D2R_P<11>
MXM_PCIE_D2R_N<12>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>
MXM_PCIE_D2R_P<15>
147
149
141
143
135
137
121
123
115
117
109
111
103
105
97
99
91
93
85
87
79
81
73
75
67
69
61
63
55
57
49
51
MXM_PCIE_R2D_N<0>
MXM_PCIE_R2D_P<0>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<8>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_N<10>
MXM_PCIE_R2D_P<10>
MXM_PCIE_R2D_N<11>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<12>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_N<14>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<15>
148
150
142
144
136
138
120
122
114
116
108
110
102
104
96
98
90
92
84
86
78
80
72
74
66
68
60
62
54
56
48
50
F-RT-SM
(2 OF 4)
APPLE P/N: 516S0676
CLK_REQ*
DP_A_AUX*
DP_A_AUX
PEX_STD_SW*
DP_A_HPD
PEX_REFCLK
PEX_REFCLK*
DP_A_L0*
DP_A_L0
PEX_RST*
DP_A_L1*
PEX_RX0*
DP_A_L1
PEX_RX0
DP_A_L2*
PEX_RX1*
DP_A_L2
PEX_RX1
DP_A_L3*
PEX_RX2*
DP_A_L3
PEX_RX2
DP_B_AUX*
PEX_RX3*
DP_B_AUX
PEX_RX3
PEX_RX4*
DP_B_HPD
PEX_RX4
DP_B_L0*
PEX_RX5*
DP_B_L0
PEX_RX5
DP_B_L1*
PEX_RX6*
DP_B_L1
PEX_RX6
DP_B_L2*
PEX_RX7*
DP_B_L2
PEX_RX7
DP_B_L3*
PEX_RX8*
DP_B_L3
PEX_RX8
PEX_RX9*
DP_C_AUX*
PEX_RX9
DP_C_AUX
PEX_RX10*
DP_C_HPD
PEX_RX10
PEX_RX11*
DP_C_L0*
PEX_RX11
DP_C_L0
PEX_RX12*
DP_C_L1*
PEX_RX12
DP_C_L1
PEX_RX13*
DP_C_L2*
PEX_RX13
DP_C_L2
PEX_RX14*
DP_C_L3*
PEX_RX14
DP_C_L3
PEX_RX15*
DP_D_AUX*
PEX_RX15
DP_D_AUX
PEX_TX0*
DP_D_HPD
PEX_TX0
PEX_TX1*
DP_D_L0*
PEX_TX1
DP_D_L0
PEX_TX2*
DP_D_L1*
PEX_TX2
DP_D_L1
PEX_TX3*
DP_D_L2*
PEX_TX3
DP_D_L2
PEX_TX4*
DP_D_L3*
PEX_TX4
DP_D_L3
PEX_TX5*
PEX_TX5
PEX_TX6*
PEX_TX6
PEX_TX7*
PEX_TX7
PEX_TX8*
PEX_TX8
PEX_TX9*
PEX_TX9
PEX_TX10*
PEX_TX10
PEX_TX11*
PEX_TX11
PEX_TX12*
PEX_TX12
PEX_TX13*
PEX_TX13
PEX_TX14*
PEX_TX14
PEX_TX15*
PEX_TX15
y
r
a
n
i
m
il
6B4 85A6 84D8 85C2
MXM
B35P101-111
5%
1/16W
MF-LF
402 2
85C2
=PP3V3_S0_MXM
J8400
R84001
DP
85C2 84D2 85A6 6B4
PCI-E
6A4
277
279
MXM_DP_A_AUX_N
MXM_DP_A_AUX_P
276
MXM_DP_A_HPD
253
255
259
261
265
267
271
273
MXM_DP_A_ML_N<0>
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2>
MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>
J8400
=PP5V_S0_MXM
MXM_DP_B_AUX_N
MXM_DP_B_AUX_P
274
MXM_DP_B_HPD
246
248
252
254
258
260
264
266
MXM_DP_B_ML_N<0>
MXM_DP_B_ML_P<0>
MXM_DP_B_ML_N<1>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>
223
225
MXM_DP_C_AUX_N
MXM_DP_C_AUX_P
234
MXM_DP_C_HPD
199
201
205
207
211
213
217
219
MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>
MXM_DP_C_ML_N<1>
MXM_DP_C_ML_P<1>
MXM_DP_C_ML_N<2>
MXM_DP_C_ML_P<2>
MXM_DP_C_ML_N<3>
MXM_DP_C_ML_P<3>
230
232
MXM_DP_D_AUX_N
MXM_DP_D_AUX_P
236
MXM_DP_D_HPD
206
208
212
214
218
220
224
226
MXM_DP_D_ML_N<0>
MXM_DP_D_ML_P<0>
MXM_DP_D_ML_N<1>
MXM_DP_D_ML_P<1>
MXM_DP_D_ML_N<2>
MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>
e
r
F-RT-SM
(4 OF 4)
87A8
87A8
MXM
87A8
270
272
MXM
B35P101-111
C8410
MXM
0.001UF
87B8
10%
2 50V
X7R
402
87B8
87B8
C8401
22UF
20%
2 6.3V
CERM
805
1
3
5
7
9
C8415
MXM
0.001UF
3V3
278
280
10%
2 50V
X7R
402
C8416
22UF
20%
2 6.3V
CERM
805
5V
PWR_SRC
=PPV_S0_MXM_PWRSRC
53C3
E2
E1
87B8
87B8
MXM
87B8
87B8
C8400
22UF
87B8
MXM SPEC POWER REQUIREMENTS
87C4
20%
2 35V
ELEC
6.3X5.5-SM1
MXM
MXM
C8412
0.001UF
10%
50V
2 X7R
402
MXM
C8413
0.001UF
10%
50V
2 X7R
402
C8414
0.001UF
10%
50V
2 X7R
402
(NOT NECESSARILY THE SAME FOR EVERY MODULE)

VOLTAGE
CURRENT
POWER
87C4
87C4
3V3
5V
PWR (7-20V)
87C4
87C4
3.3 W
12.5 W
PLATFORM DEPENDENT
1.0 A
2.5 A
UP TO 10 A
87C4
87C4
87C4
87C4
87C4
87C4
87D4
87D4
87D4
87D4
87D4
87D4
87D4
87D4
87D4
87D4
87D4
87B4
87B4
87B4
87B4
87B4
87B4
87B4
87B4
87B4
87B4
87B4
MXM PCIe, DP & Power

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
84
109
Page Notes
- =PP3V3_S0_MXM

- =SMB_MXM_THRM_DATA
- =PM_MXM_PGOOD_PULLUP
- =SMB_MXM_THRM_CLK
PULLUPS & PULLDOWNS AT MXM CONNECTOR
J8400
B35P101-111
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
87D7
TP_MXM_DVI_HPD
31
MXM_LVDS_A_CLK_N
MXM_LVDS_A_CLK_P
176
178
LVDS_LCLK*
LVDS_LCLK
MXM_LVDS_A_DATA_N<0>
MXM_LVDS_A_DATA_P<0>
200
202
LVDS_LTX0*
LVDS_LTX0
194
196
LVDS_LTX1*
LVDS_LTX1
188
190
LVDS_LTX2*
LVDS_LTX2
182
184
LVDS_LTX3*
LVDS_LTX3
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
169
171
LVDS_UCLK*
LVDS_UCLK
MXM_LVDS_B_DATA_N<0>
MXM_LVDS_B_DATA_P<0>
LVDS_UTX1*
LVDS_UTX1
181
183
LVDS_UTX2*
LVDS_UTX2
175
177
LVDS_UTX3*
LVDS_UTX3
50C3
52D3
50C3
50A4
LVDS_UTX0*
LVDS_UTX0
187
189
70D3
PM_MXM_EN
PM_MXM_PGOOD
MXM_PWR_LEVEL
8
6
18
VGA_DISABLE*
PWR_EN
PWRGOOD
PWR_LEVEL
=SMB_MXM_THRM_SCL
=SMB_MXM_THRM_SDA
34
32
SMB_CLK
SMB_DAT
MXM_ALERT_L
MXM_OVERT_L
TP_MXM_TH_PWM
22
20
24
TH_ALERT*
TH_OVERT*
TH_PWM
TP_MXM_VGA_DDC_CLK
TP_MXM_VGA_DDC_DAT
160
158
VGA_DDC_CLK
VGA_DDC_DAT
TP_MXM_VGA_BLUE
TP_MXM_VGA_GREEN
TP_MXM_VGA_HSYNC
TP_MXM_VGA_RED
TP_MXM_VGA_VSYNC
172
170
164
168
162
VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC
MXM_VGA_DISABLE_L
21
GPIO0
GPIO1
GPIO2
26
28
30
TP_MXM_GPIO0
TP_MXM_GPIO1
TP_MXM_GPIO2
HDMI_CEC
29
TP_MXM_HDMI_CEC
DVI_HPD
85B3 70A3
52D3
193
195
F-RT-SM
(3 OF 4)
38
39
40
41
42
43
44
45
PNL_BL_EN
25
MXM_PNL_BL_EN
87D7
PNL_BL_PWM
27
MXM_PNL_BL_PWM
87C7
PNL_PWR_EN
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
PRSNT_L*
PRSNT_R*
WAKE*
23
10
159
12
161
163
165
167
227
229
231
233
235
237
238
239
240
241
242
243
245
247
249
14
16
281
2
MXM_PNL_PWR_EN
TP_MXM_WAKE_L
PLACE CLOSE TO J7800
P
=PP3V3_S0_MXM
6B4 84D2 84D8 85C2
MXM
C8570
0.1UF
R8570
0
5%
1/16W
MF-LF
402 2
I2C ADDRESS: AC 8
VCC
3 E2/NC2 MXM
5
2 E1/NC1 CRITICALSDA
1 E0/NC0
SCL 6
MXM_ROM_WP
7 WC* U8570
M24C02-WMN6TPHF
SO8
VSS
4
87D7
11
13
15
17
36
37
46
47
52
53
58
59
64
65
70
71
76
77
82
83
88
89
94
95
100
101
106
107
112
113
118
119
124
125
133
134
139
140
GND
e
r
MXM_DETECT_L
MXM_DETECT_R
MXM SYSTEM INFORMATION ROM
STUFF FOR WRITE PROTECT

NOSTUFF
85D2
OEM0
OEM1
OEM2
OEM3
OEM4
OEM5
OEM6
OEM7
LVDS
87D7
87D7
LVDS_DDC_CLK
LVDS_DDC_DAT
SYSTEM MANAGEMENT
87D7
35
33
MANAGEMENT
POWER/THERMAL
87C7 85A6
MXM_LVDS_DDC_CLK
MXM_LVDS_DDC_DAT
B35P101-111
F-RT-SM
(1 OF 4)
ANALOG DISPLAY
87C7 85A6
y
r
a
n
i
m
il
MXM
MXM
J8400
9C6 85B3
85B3
FLOAT = NORMAL VGA MODE

GND = SECONDARY DISPLAY CARD
GND
145
146
151
152
157
166
173
174
179
180
185
186
191
192
197
198
203
204
209
210
215
216
221
222
228
244
E3
250
251
256
257
262
263
268
269
275
282
283
E4
85D6
R8510
MXM_VGA_DISABLE_L
MF-LF 5%
NOSTUFF
1/16W
402
R8504
FLOAT = LOW SWING

GND = HIGH SWING
84C8
MXM_PCIE_STD_SWING_L
MF-LF 5%
MXM
1/16W
402
=PP3V3_S0_MXM
6B4 85A6 84D2 84D8
R8500
85B6 9C6
MXM_DETECT_L
100K 2
MF-LF
5% 1/16W
402
PULLED TO GROUND ON MXM

WE DONT USE CARD DETECT
R8501
85B6
MXM_DETECT_R
100K 2
MF-LF
5% 1/16W
402
=PM_MXM_PGOOD_PULLUP
70D4
SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
R8503
70A3 85B8
PM_MXM_PGOOD
10K
MF-LF 5%
1/16W
402
20%
2 10V
CERM
402
MXM_LVDS_DDC_DAT
MXM_LVDS_DDC_CLK
MXM I/O
85D8 87C7
SYNC_MASTER=K50
85D8 87C7

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
85
109
SLOTB MXM TX CAPS

102D3 9C6
102D3 9C6
IN
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
102D3 9C6
IN
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
IN
B
102D3 9C6
102D3 9C6
IN
IN
102D3 9C6
IN
102D3 9C6
IN
102D3 9C6
102D3 9C6
102D3 9C6
102D3 9C6
IN
IN
IN
IN
PEG_R2D_C_N<0>
MXM
PEG_R2D_C_P<0>
MXM
C8600 0.1UF 1
C8601 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_R2D_P<15>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<14>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<14>
PEG_R2D_C_N<2>
MXM
MXM_PCIE_R2D_P<13>
MXM
C8604 0.1UF 1
C8605 0.1UF 1
2 10% 16V X5R 402
PEG_R2D_C_P<2>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<13>
PEG_R2D_C_N<3>
MXM
PEG_R2D_C_P<3>
MXM
PEG_R2D_C_N<4>
MXM
PEG_R2D_C_P<4>
MXM
PEG_R2D_C_N<5>
PEG_R2D_C_P<5>
PEG_R2D_C_N<6>
PEG_R2D_C_P<6>
MXM
PEG_R2D_C_N<8>
MXM
PEG_R2D_C_P<8>
MXM
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_P<12>
C8608 0.1UF 1
C8609 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_R2D_P<11>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<11>
C8614 0.1UF 1
C8615 0.1UF 1
C8616 0.1UF 1
C8617 0.1UF 1
C8618 0.1UF 1
MXM C8619 0.1UF 1
MXM
C8620 0.1UF 1
MXM C8621 0.1UF 1
MXM
C8622 0.1UF 1
MXM C8623 0.1UF 1
MXM
C8624 0.1UF 1
MXM C8625 0.1UF 1
MXM
PEG_R2D_C_N<13>
MXM
PEG_R2D_C_P<13>
MXM
C8626 0.1UF 1
C8627 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_R2D_P<10>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<10>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<9>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<9>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<8>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<8>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<7>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<7>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<6>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<6>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<5>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<5>
MXM
PEG_R2D_C_P<14>
MXM
PEG_R2D_C_N<15>
MXM
PEG_R2D_C_P<15>
MXM
C8628 0.1UF 1
C8629 0.1UF 1
C8630 0.1UF 1
C8631 0.1UF 1
e
r
2 10% 16V X5R 402
MXM_PCIE_R2D_P<4>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<4>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<3>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<3>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<2>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<2>
PEG_R2D_C_N<14>
MXM_PCIE_R2D_N<12>
C8612 0.1UF 1
MXM C8613 0.1UF 1
MXM
PEG_R2D_C_N<10>
MXM_PCIE_R2D_P<12>
MXM
PEG_R2D_C_P<7>
PEG_R2D_C_P<9>
2 10% 16V X5R 402

2 10% 16V X5R 402
C8610 0.1UF 1
MXM C8611 0.1UF 1
PEG_R2D_C_N<7>
PEG_R2D_C_N<9>
C8606 0.1UF 1
C8607 0.1UF 1
MXM
OUT
102D3 84A8
OUT
102D3 84A8
102D3 84B8
IN
102D3 84B8
IN
MXM_PCIE_D2R_P<15>
MXM
MXM_PCIE_D2R_N<15>
MXM
C8632 0.1UF 1
C8633 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<0>
2 10% 16V X5R 402
PEG_D2R_P<0>
y
r
a
n
i
m
il
2 10% 16V X5R 402
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
SLOTB MXM RX CAPS
C8602 0.1UF 1
MXM C8603 0.1UF 1
MXM
2 10% 16V X5R 402
MXM_PCIE_R2D_P<1>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<1>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<0>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<0>
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
102D3 84B8
IN
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84A8
102D3 84B8
IN
102D3 84B8
IN
102D3 84B8
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84A8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
OUT
OUT
IN
2 10% 16V X5R 402
PEG_D2R_P<1>
MXM_PCIE_D2R_N<14>
C8634 0.1UF 1
MXM C8635 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<1>
MXM_PCIE_D2R_P<13>
MXM
PEG_D2R_P<2>
MXM
C8636 0.1UF 1
C8637 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_D2R_N<13>
2 10% 16V X5R 402
PEG_D2R_N<2>
MXM_PCIE_D2R_P<12>
MXM
PEG_D2R_P<3>
MXM
C8638 0.1UF 1
C8639 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_D2R_N<12>
2 10% 16V X5R 402
PEG_D2R_N<3>
MXM_PCIE_D2R_P<11>
MXM
PEG_D2R_N<4>
MXM
C8640 0.1UF 1
C8641 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_D2R_N<11>
2 10% 16V X5R 402
PEG_D2R_P<4>
MXM_PCIE_D2R_P<10>
MXM
PEG_D2R_N<5>
MXM
C8642 0.1UF 1
C8643 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_D2R_N<10>
2 10% 16V X5R 402
PEG_D2R_P<5>
MXM_PCIE_D2R_P<9>
MXM
PEG_D2R_P<6>
MXM
C8644 0.1UF 1
C8645 0.1UF 1
2 10% 16V X5R 402
MXM_PCIE_D2R_N<9>
2 10% 16V X5R 402
PEG_D2R_N<6>
MXM_PCIE_D2R_P<8>
MXM
C8646 0.1UF 1
C8647 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<7>
MXM_PCIE_D2R_N<8>
MXM
2 10% 16V X5R 402
PEG_D2R_P<7>
C8648 0.1UF 1
C8649 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<8>
2 10% 16V X5R 402
PEG_D2R_P<8>
C8650 0.1UF 1
C8651 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<9>
2 10% 16V X5R 402
PEG_D2R_P<9>
MXM_PCIE_D2R_P<14>
MXM
MXM_PCIE_D2R_P<7>
MXM
MXM_PCIE_D2R_N<7>
MXM
MXM_PCIE_D2R_P<6>
MXM
MXM_PCIE_D2R_N<6>
MXM
MXM_PCIE_D2R_P<5>
MXM
MXM_PCIE_D2R_N<5>
MXM
MXM_PCIE_D2R_P<4>
MXM
MXM_PCIE_D2R_N<4>
MXM
MXM_PCIE_D2R_P<3>
MXM
C8652 0.1UF 1
C8653 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<10>
2 10% 16V X5R 402
PEG_D2R_P<10>
C8654 0.1UF 1
C8655 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<11>
2 10% 16V X5R 402
PEG_D2R_P<11>
2 10% 16V X5R 402
PEG_D2R_N<12>
MXM_PCIE_D2R_N<3>
C8656 0.1UF 1
MXM C8657 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_P<12>
MXM_PCIE_D2R_P<2>
MXM
MXM_PCIE_D2R_N<2>
MXM
MXM_PCIE_D2R_P<1>
MXM
MXM_PCIE_D2R_N<1>
MXM
MXM_PCIE_D2R_P<0>
MXM
MXM_PCIE_D2R_N<0>
MXM
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
7B7 102D3 9C6
OUT
7B7 102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
OUT
102D3 9C6
102D3 84B8
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
OUT
102D3 84B8
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
102D3 84C8
IN
C8658 0.1UF 1
C8659 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<13>
2 10% 16V X5R 402
PEG_D2R_P<13>
C8662 0.1UF 1
C8663 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_P<14>
2 10% 16V X5R 402
PEG_D2R_N<14>
C8660 0.1UF 1
C8661 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<15>
2 10% 16V X5R 402
PEG_D2R_P<15>
MXM PCIE CAPS

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
86
109
Page Notes
- =PP5V_DP_AUX
85C8
MXM_LVDS_A_DATA_P<3..0>
LVDS_EG_A_DATA_P<3..0>
UNUSED DP INTERFACES
107C2 89B6 89C6 89D6 90A6 90A8
MAKE_BASE=TRUE

(NONE)
85C8
MXM_LVDS_A_DATA_N<3..0>
LVDS_EG_A_DATA_N<3..0>
107C2 89B6 89C6 89D6 90A6 90A8
MAKE_BASE=TRUE
85C8
MXM_LVDS_B_DATA_P<3..0>
LVDS_EG_B_DATA_P<3..0>
84B5
MXM_DP_C_ML_N<0..3>
TP_MXM_DP_C_ML_N<0..3>
84B5
MXM_DP_C_ML_P<0..3>
TP_MXM_DP_C_ML_P<0..3>
107C2 89A6 89C3 89D3 90A8 90B6
MAKE_BASE=TRUE
MAKE_BASE=TRUE

(NONE)
85C8
MXM_LVDS_B_DATA_N<3..0>
LVDS_EG_B_DATA_N<3..0>
107C2 89A6 89C3 89D3 90A6 90B8
MAKE_BASE=TRUE
MAKE_BASE=TRUE
85C8
85C8
85C8
85C8
MXM_LVDS_A_CLK_N
MXM_LVDS_A_CLK_P
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
LVDS_EG_A_CLK_N
MAKE_BASE=TRUE
LVDS_EG_A_CLK_P
MAKE_BASE=TRUE
LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
LVDS_EG_B_CLK_P
MAKE_BASE=TRUE
85C6
MXM_PNL_BL_EN
LVDS_BKL_ON
MXM_PNL_PWR_EN
MXM_PNL_BL_PWM
LVDS_EG_PANEL_PWR
MAKE_BASE=TRUE
LVDS_EG_BKL_PWM
MAKE_BASE=TRUE
85C6
85C6
MAKE_BASE=TRUE
85D8 85A6
85D8 85A6
MXM_LVDS_DDC_DAT
MXM_LVDS_DDC_CLK
LVDS_EG_DDC_DATA
MAKE_BASE=TRUE
LVDS_EG_DDC_CLK
MAKE_BASE=TRUE
84C8
84C8
CLK_100M_MXM_P
CLK_100M_MXM_N
GPU_CLK100M_PCIE_P
MAKE_BASE=TRUE
GPU_CLK100M_PCIE_N
MAKE_BASE=TRUE
84C8
MXM_RESET_L
PEG_RESET_L
MAKE_BASE=TRUE
84C5
MXM_DP_C_AUX_N
TP_MXM_DP_C_AUX_N
89B6 107C2
MAKE_BASE=TRUE
y
r
a
n
i
m
il
89B6 107C2
84C5
MXM_DP_C_AUX_P
84B5
MXM_DP_C_HPD
TP_MXM_DP_C_AUX_P
MAKE_BASE=TRUE
89C3 107C2
TP_MXM_DP_C_HPD
89C3 107C2
MAKE_BASE=TRUE
6D6 8D3 90A3 90C4
90A3 90B8
90D6
89A3 90A6
89B3 90A8
9C6 102C3
9C6 102C3 7C3
9C2 90D4
84C5
MXM_DP_B_ML_N<0..3>
TP_MXM_DP_B_ML_N<0..3>
84C5
MXM_DP_B_ML_P<0..3>
TP_MXM_DP_B_ML_P<0..3>
84C5
MXM_DP_B_AUX_N
TP_MXM_DP_B_AUX_N
84C5
MXM_DP_B_AUX_P
TP_MXM_DP_B_AUX_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
84C5
MXM_DP_B_HPD
TP_MXM_DP_B_HPD
MAKE_BASE=TRUE
MXM
EXTERNAL DP CONN
THESE ALIASES ARE TO CONFORM WITH K50/K52 SHARED CONNECTOR PAGE
84C5
MXM_DP_A_ML_N<0>
DP_EG_ML_N<0>
84C5
MXM_DP_A_ML_P<0>
DP_EG_ML_P<0>
107D2 91D8
MAKE_BASE=TRUE
e
r
107D2 91C8
MAKE_BASE=TRUE
84C5
MXM_DP_A_ML_N<1>
DP_EG_ML_N<1>
107D2 91C8
MAKE_BASE=TRUE
84C5
MXM_DP_A_ML_P<1>
DP_EG_ML_P<1>
107D2 91C8
MAKE_BASE=TRUE
84C5
MXM_DP_A_ML_N<2>
DP_EG_ML_N<2>
84C5
MXM_DP_A_ML_P<2>
DP_EG_ML_P<2>
107D2 91B8
MAKE_BASE=TRUE
107D2 91B7
MAKE_BASE=TRUE
84C5
MXM_DP_A_ML_N<3>
84C5
MXM_DP_A_ML_P<3>
DP_EG_ML_N<3>
MXM_DP_D_ML_N<0..3>
TP_MXM_DP_D_ML_N<0..3>
84B5
MXM_DP_D_ML_P<0..3>
TP_MXM_DP_D_ML_P<0..3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
84B5
MXM_DP_D_AUX_N
TP_MXM_DP_D_AUX_N
84B5
MXM_DP_D_AUX_P
TP_MXM_DP_D_AUX_P
84B5
MXM_DP_D_HPD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
107D2 91C4
MAKE_BASE=TRUE
DP_EG_ML_P<3>
84B5
TP_MXM_DP_D_HPD
MAKE_BASE=TRUE
107D2 91C4
MAKE_BASE=TRUE
84C5
MXM_DP_A_HPD
DP_EG_HPD
91B4
MAKE_BASE=TRUE
84D5
MXM_DP_A_AUX_N
DP_EG_AUXCH_N
MAKE_BASE=TRUE
84C5
MXM_DP_A_AUX_P
DP_EG_AUXCH_P
93C4 107D2
93B4 107D2
MAKE_BASE=TRUE
MXM ALIASES
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
87
109
IG
RP8906
0
107D2 18B3
107C2 18B3
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
IG
RP8900
1
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
87D5 107C2 90A8

107C2 18B3
87D5 107C2 90A6
107C2 18B3
5%
1/16W
SM-LF
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
87D5 107C2 90B6

87D5 107C2 90B8
5%
1/16W
SM-LF
RP8907
0
0
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
107D2 18B3
107C2 18B3
y
r
a
n
i
m
il
IG
IG
RP8901
1
107C2 18B3
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
87D5 107C2 90A6
107C2 18B3
87D5 107C2 90A8
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
87D5 107C2 90B6

87D5 107C2 90B8
5%
1/16W
SM-LF
5%
1/16W
SM-LF
IG
RP8908
0
IG
RP8902
107C2 18B3
0
107D2 18B3
107C2 18B3
107C2 18B3
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
LVDS_EG_B_DATA_P<3>
LVDS_EG_B_DATA_N<3>
87D5 107C2 90A8
87D5 107C2 90A6
5%
1/16W
SM-LF
87D5 107C2 90A8

87D5 107C2 90A6
5%
1/16W
SM-LF
CRITICAL
L8950
90-OHM
IG
DLP0NS
RP8909
SYM_VER-1
IG
107C2 18B3
RP8903
107C2 18B3
0
107D2 18B3
107C2 18B3
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_EG_A_DATA_P<3>
LVDS_EG_A_DATA_N<3>
87D5 107C2 90A6
e
r
CRITICAL
L8900
90-OHM
DLP0NS
RP8904
SYM_VER-1
0
107D2 18B3
107D2 18B3
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
107C2 87D5
107C2
5%
1/16W
SM-LF
IG
0
107C2 18B3
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
3
5%
1/16W
SM-LF
LVDS_EG_A_CLK_L_P
107C2 90A8
LVDS_EG_A_CLK_L_N
107C2 90A6
PLACE IT CLOSE TO J9002
RP8905
107C2 18B3
LVDS_EG_A_CLK_P
87D5 LVDS_EG_A_CLK_N
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
107C2 87D5
107C2
5%
1/16W
SM-LF
87D5 107C2 90A8
5%
1/16W
SM-LF
IG
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
90D4 90A8 90D5
LVDS_EG_B_CLK_L_P
107C2 90A8
LVDS_EG_B_CLK_L_N
107C2 90A6
PLACE IT CLOSE TO J9002
IG
R89501
R89511
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2.7K
18B3
=PP3V3_DDC_LCD
IG
18A3
LVDS_EG_B_CLK_P
87D5 LVDS_EG_B_CLK_N
2.7K
IG
RP8950
0
1
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
LVDS_EG_DDC_CLK
LVDS_EG_DDC_DATA
87C5 90A8
87C5 90A6
5%
1/16W
SM-LF
87D5 107C2 90B6
87D5 107C2 90B8
LVDS MUX RESISTORS

SYNC_MASTER=SIJI

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
89
109
INVERTER INTERFACE
6A4 =PP3V3_S0_VIDEO
=PP3V3_DDC_LCD
89B5 90A8 90D4
Page Notes
IG

- =PPV_S0_LCD_20INCH
- =PP3V3_S0_VIDEO
18B6
R9080
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
LVDS_IG_BKL_PWM
IG
1
R9074

(NONE)
MXM
R9075
0
1K
5%
1/16W
MF-LF
402 2
90A8 89B5 90D5
=PP3V3_DDC_LCD
1

IG, MXM
R9079
0
1
LVDS_EG_BKL_PWM
2
5
10K
LCD_PWM_MUX
5%
1/16W
MF-LF
402
NOSTUFF
R90781
TC7SZ08AFEAPE
IG
U9020 Y
87C5 9C2
PEG_RESET_L 1
CRITICAL
29.4K
Q9000
FDC638P_G
PPV_LCD_SW
VOLTAGE=12V
1%
1/16W
MF-LF
402
4
2
PPV_LCD_CONN
12V FOR 24 INCH LCD

1
C9001
10UF
0.001uF
10%
16V
X5R-CERM
1210
20%
50V
CERM
402
PLACE NEAR J9002

3
D
Q9001
2N7002
90A3 87D5
LVDS_EG_PANEL_PWR1
SOT23-HF1
S
2
R90701
100K
5%
1/16W
MF-LF
402 2
e
r
CRITICAL
SDF9000
STDOFF-4.0OD4.6H-1.35-2.4-TH
1
516S0241
CRITICAL
J9002
53307-8630
F-ST-SM
89A6 107C2 87D5
89D3 107C2
89D3 107C2
107C2 89C2
10
89C3 107C2 87D5
11
12
89D6 107C2
13
14
15
16
17
18
89C6 107C2 87D5
19
20
107C2
21
22
23
24
25
26
89D6 107C2
90D4 89B5 90D5
90C5 90A6 6A7
=PP3V3_DDC_LCD
PPV_LCD_CONN
LVDS_EG_B_DATA_N<0>
87D5 LVDS_EG_B_DATA_N<1>
87D5 LVDS_EG_B_DATA_N<2>
89B6
89B3
LVDS_EG_B_CLK_L_P
LVDS_EG_B_DATA_P<3>
87D5 LVDS_EG_A_DATA_P<0>
87D5 LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
89B5 LVDS_EG_A_CLK_L_P
87D5 LVDS_EG_A_DATA_P<3>
107C2
87C5 LVDS_EG_DDC_CLK
27
28
29
30
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_CLK_L_N
LVDS_EG_B_DATA_N<3>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<2>
LVDS_EG_A_CLK_L_N
LVDS_EG_A_DATA_N<3>
LVDS_EG_DDC_DATA
TC7SZ08AFEAPE
SOT665
IG
LCD_PWM_R
C9010
0.001uF
20%
50V
CERM
402
CRITICAL
LCD_PWM
87D5 107C2 89A6
IG
87D5 107C2 89D3

89C2 107C2
R9050
18B6
87D5 107C2 89C3
LVDS_IG_BKL_ON
LVDS_BKL_ON
87D5 6D6 8D3 90C4
5%
1/16W
MF-LF
402
87D5 107C2 89D6
87D5 107C2 89D6
IG
87D5 107C2 89C6

89B5 107C2
87D5 107C2 89B6
PPV_LCD_CONN
18B6
R9051
0
LVDS_IG_PANEL_PWR
LVDS_EG_PANEL_PWR
87D5 90B8
5%
1/16W
MF-LF
402
6A7 90A8 90C5
87C5 89A3
INTERNAL DISPLAY CONNS

SYNC_MASTER=SIJI
SDF9001
IG
IG
R90601
R90611
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
1K
5%

1K

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
6D8
87D5 107C2 89D3
STDOFF-4.0OD4.6H-1.35-2.4-TH
2
2
SM
Panel has 4.7K DDC pull-ups

MXM also has 2.2K pull-ups
m
il
LCD_PWREN_L_RC
LCD_PWREN_DIV_L
6A7 90A6 90A8
SM
C9020
100K
5%
1/16W
MF-LF
402 2
VOLTAGE=12V
FERR-250-OHM
6
LCD_PWREN_DIV
R9002 1
L9000
SM
LCD_PWM_FILT
a
n
i
0.1UF
R9001
C9000
10%
50V
X7R
603-1
LVDS_BKL_ON
90A3 8D3 6D6 87D5
PANEL POWER SEQUENCING
L9050
FERR-250-OHM
5%
1/16W
MF-LF
402
=PPV_S0_LCD_24INCH
5%
1/16W
MF-LF
402 2
CRITICAL
R9081
47
U9021 Y
100K
20%
10V
CERM
402
LCD_PWM_GATE1
INVERTER CONNECTOR INCORPORATED INTO AC/DC CONNECTOR
LCD (LVDS) INTERFACE
VOLTAGE=5V
y
r
0.1UF
20%
10V
CERM
402
R9000 1
IG
C9050
SOT665
5%
1/16W
MF-LF
402 2
6A4
0.1UF
MXM
87C5
IG
C9051
10
OF
90
109
D
107D2 9C6
16V
C9100
10%
402
107D2 87B5
DP_EG_ML_N<0>
16V
MXM
2
10%
107D2 94C8
C9150
402
X5R
107D2 9C6
0.1UF1
DP_IG_ML_N<3>
16V
107D2 87B5
0.1UF1
DP_EG_ML_P<0>
16V
MXM
2
10%
C9152
402
16V
107D2 9C6
IG
0.1UF1
DP_IG_ML_P<0>
10%
402
IG
0.1UF1
DP_IG_ML_N<1>
16V
107D2 87B5
DP_EG_ML_N<3>
X5R
402
X5R
107D2 87B5
DP_EG_ML_P<3>
16V
MXM
2
10%
C9154
402
X5R
107D2 9C6
107D2 87B5
0.1UF1
DP_EG_ML_P<1>
16V
MXM
2
10%
C9156
402
0.1UF1
DP_IG_ML_P<1>
16V
107D2 9C6
0.1UF1
DP_IG_ML_N<2>
16V
IG
2
10%
IG
2
X5R
C9108
402
X5R
107D2 87B5
0.1UF1
DP_EG_ML_N<2>
16V
107D2 87B5
10%
0.1UF1
DP_EG_ML_P<2>
16V
C9158
402
X5R
MXM
2
10%
C9160
402
X5R
DP_ML_P<2>
107D2 9C6
P
0.1UF1
DP_IG_ML_P<2>
16V
10%
IG
C9110
402
X5R
87A6
e
r
DP_ML_N<2>
MXM
107D2 94C8
C9106
402
10%
m
il
X5R
107D2 94B8
107D2 94B8
9B6
C9112
X5R
C9162
402
MXM
10%
X5R
C9164
402
0.1UF1
16V
DP_ML_P<1>
107D2 9C6
DP_IG_ML_P<3>
IG
10%
X5R
DP_ML_N<3>
DP_ML_P<3>
107D2 94C1
107D2 94C1
C9114
402
X5R
MXM
R9124
0
1
DP_EG_HPD
5%
1/16W
MF-LF
402
DP_HPD
94A6
IG
R9125
0
1
DP_IG_HPD
0.1UF1
DP_EG_ML_N<1>
R9130
MXM
107D2 87B5
107D2 94C8
MXM
10%
0.1UF1
16V
DP_ML_N<1>
402
0.1UF1
16V
C9104
10%
107D2 94C8
C9102
IG
10%
a
n
i
X5R
DP_ML_P<0>
107D2 9C6
y
r
X5R
DP_ML_N<0>
0.1UF1
IG
0.1UF1
DP_IG_ML_N<0>
20.0K
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MAY SHARE THE COMMON PAD BETWEEN R9125 AND R9130
DP MUX SUPPORT
SYNC_MASTER=K50
PLACE THESE CAPACITORS ATLEAST 1INCH AWAY FROM DP CONNECTOR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
91
109
y
r
DP_AUX_CH_C_N
BI
IG
IG
SIGNAL_MODEL=EMPTY
C9300
R9300
9B6
BI
DP_IG_DDC_DATA 1 33
93C2 94C2 107D2
0.1UF
107D2
5%
1/16W
MF-LF
402
DP_AUX_CH_SW_N
10%
16V
X5R
402
DP_AUX_CH_C_P
a
n
i
93B2 94C2 107D2
BI
IG
SIGNAL_MODEL=EMPTY
DP_IG_DDC_CLK
9B6
IN
R9301
1
33
5%
1/16W
MF-LF
402
IG
C9301
0.1UF
107D2
DP_AUX_CH_SW_P
10%
16V
X5R
402
MXM
C9350
IG
3
SSM6N15FEAPE
Q9300
S 1
BI
DP_IG_AUX_CH_N
107D2 18B6
93D4 94C2 107D2
DP_IG_AUX_CH_P
DP_AUX_CH_C_N
SSM6N15FEAPE
SOT563
Q9350
G 2
BI
MXM
107D2 18B6
10%
16V
X5R
402
SOT563
G 5
107D2 87A6
D 6
SSM6N15FEAPE
SOT563
DP_EG_AUXCH_N
IG
Q9300
0.1UF
IG
m
il
=PP5V_S0_DP_AUX_MUX
1K
93C5 6A4
5%
1/16W
MF-LF
2 402
=PP5V_S0_DP_AUX_MUX
R9302
93C7 6A4
100K
MXM
5%
1/16W
MF-LF
2 402
R9352
107D2 87A6
100K
5%
1/16W
MF-LF
2 402
DDC_CA_DET_LS5V_L
MXM
C9351
0.1UF
DP_EG_AUXCH_P
e
r
SSM3K15FV
DP_CA_DET
IN
G 1
DP_IG_CA_DET
OUT
18B6
MXM
Q9350
MXM
93C4 94C2 107D2
SSM6N15FEAPE
SOT563
SOD-VESM-HF
94A8
D 3 SOD-VESM-HF
D 3
SSM3K15FV
DP_AUX_CH_C_P
DDC_CA_DET_LS5V
Q9351
Q9301
10%
16V
X5R
402
S 4
R9303
S 2
DISPLAYPORT SUPPORT
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
93
109
NOSTUFF
F9400
0.75AMP
94C4 94B8 94A6 6B4
=PP3V3_S0_DPCONN
PP3V3_S0_DPFUSE
VOLTAGE=3.3V
SM-HF
CRITICAL
U9400
5 IN
CRITICAL
73A6 9D6
4 EN
PM_SLPS3_BUF1_L
D9410
1
RCLAMP0524P
C9480
9 NC
NO STUFF
GND
NO STUFF
C9485
MF-LF 402
FL9400
12-OHM-100MA
4
91C5 107D2
IN
91D5 107D2
IN
DP_ML_P<0>
DP_ML_N<0>
PP3V3_S0_DPPWR
VOLTAGE=3.3V
TCM1210-4SM
SYM_VER-2
C9400
0.01UF
20%
6.3V
2 X5R
603
MF-LF 402
5% 1/16W
10UF
1/16W
R9410 1
SM-1
5%
y
r
a
n
i
m
il
L9400
400-OHM-EMI
CRITICAL
R9400
TP_DP_OC
20%
2 10V
CERM
402
20%
6.3V
2 X5R
603
IO 1
NC 10
OC* 3
GND
2
C9481
0.1UF
10UF
SLP2510P8
2 IO
TPS2051B
SOT23
OUT 1
CRITICAL
D9410
RCLAMP0524P
20%
50V
CERM
603
94D7 94B8 94A6 6B4
SLP2510P8
=PP3V3_S0_DPCONN
APPLE PART NO 514S0277
5%
1/16W
5%
J9400
NO STUFF
R9411 1
GND
DSPLYPRT-K50
MF-LF 402
1/16W
R9420
IN
IN
DP_ML_P<1>
DP_ML_N<1>
TCM1210-4SM
SYM_VER-2
DP_ML_CONN_P<0>
107D2 DP_ML_CONN_N<0>
107D2
FL9401
12-OHM-100MA
91C5 107D2
DP_ML_CONN_P<1>
107D2
11
13
15
DP_ML_CONN_P<2>
107D2
4
IN
TCM1210-4SM
SYM_VER-2
R9412 1
D9411
5% 1/16W
RCLAMP0524P
R9402 1
2 IO
5%
1/16W
MF-LF 402
MF-LF 402
IO 1
NC 10
GND
9 NC
=PP3V3_S0_DPCONN
R9442
R9443 1
100K
100K
1%
1/16W
MF-LF
402
94D7 94C4 94B8 6B4
DP_CA_DET
OUT
1%
1/16W
MF-LF
402 2
Q9440
G
5
91B2
2N7002DW-X-G
DP_CA_DET_L_Q
SOT-363
G
2
Q9440
1
SOT-363
2N7002DW-X-G
HDMI_CEC
MF-LF 402
5% 1/16W
MF-LF 402
FL9403
12-OHM-100MA
10
TCM1210-4SM
SYM_VER-2
DP_ML_CONN_P<3>
DP_ML_P<3>
DP_ML_N<3>
107D2
12
14
16
DP_AUX_CH_C_P
DP_AUX_CH_C_N
18
e
r
107D2 91C2
93B2 93C4 107D2

93C2 93D4 107D2
20
R9421 1
R9425
CRITICAL
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
D9411
RCLAMP0524P
SLP2510P8
5 IO
IO 4
NC 7
6 NC
RCLAMP0504F
SC70-6-1
DP_CA_DET_Q
=PP3V3_S0_DPCONN
OUT
R9445
R9444 1
10K
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
DP_HPD
DisplayPort Connector
Q9441
2N7002DW-X-G
SOT-363
DP_HPD_L_Q
SYNC_MASTER=K50
Q9441

DP_HPD_Q
2N7002DW-X-G
SOT-363
S
4
R94231
100K
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
107D2 91C2
IN
D9400
1M
IN
CRITICAL
R94221
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NO STUFF
SLP2510P8
100K
NO STUFF
R9413 1
1M
NO STUFF
CRITICAL
93B8
ML_LANE3N
GND
AUX_CHP
AUX_CHN
DP_PWR
NO STUFF
1/16W
SHIELD PINS
DP_ML_P<2>
DP_ML_N<2>
94D7 94C4 94A6 6B4
DP_HPD
DP_C_A_DET
HDMI_CEC
GND
ML_LANE3P
GND
ML_LANE0P
ML_LANE0N
GND
ML_LANE1P
ML_LANE1N
GND
ML_LANE2P
ML_LANE2N
RETURN
21
91B5 107D2
IN
17
19
FL9402
12-OHM-100MA
91B5 107D2
5%
CRITICAL
MF-LF 402
91C5 107D2
R9403
F-ANG-SM1
22
NO STUFF
R9401
IO 4
NC 7
6 NC
GND
5 IO
10
OF
94
109
CRITICAL
CRITICAL
SDF9800
SDF9801
STDOFF-4.0OD3.5H-1.35-TH
STDOFF-4.0OD3.5H-1.35-TH
y
r
a
n
i
m
il
APN 518S0671
CRITICAL
J9800
52893-8626
F-RT-SM
28
9A7
GND_AUDIO_SPKRAMP
C9800
1UF
10%
25V
X7R 2
805
5
6
7
6A4
R9800
19D7
AUD_IPHS_SWITCH_EN
98C4 6A4
5%
1/16W
MF-LF
402
R9810
10K
=PP5V_S0_AUDIO
NOSTUFF
10
C9801
11
0.1UF
13
103B3 21D2
6A4 98C6
6B4 98C6
NOSTUFF
20%
10V
CERM 2
402
12
21D7 HDA_SDIN0
5%
1/16W
MF-LF
402 2
=PP5V_S0_AUDIO
=PP3V3_S0_AUDIO
=PP12V_S0_AUDIO_SPKRAMP
C9802
0.1UF
20%
10V
2 CERM
402
14
HDA_SDOUT
15
16
HDA_BIT_CLK
103B3 21D2 HDA_RST_L
103B3 21D2 HDA_SYNC
98C4 6B4 =PP3V3_S0_AUDIO
103B3 21D2
17
18
19
20
R9801
21C3 21A4
AUD_I2C_INT_L
AUD_IPHS_SWITCH_EN_CONN
AUD_I2C_INT_L_CONN
=I2C_AUDIO_SCL
R9803
=I2C_AUDIO_SDA
5%
1/16W
MF-LF
402
CRITICAL
17B6
AUD_IP_PERIPHERAL_DET
26
e
r
SDF9804
STDOFF-4.0OD3.5H-1.35-TH STDOFF-4.0OD3.5H-1.35-TH
INTERNAL PULLUP IN MCP79 (P16)
25
CRITICAL
SDF9803
R9804
0
MIKEY SUPPORT
24
27
5%
1/16W
MF-LF
402
52C6
22
I2C_AUDIO_SCL
I2C_AUDIO_SDA
AUD_IP_PERIPHERAL_DET_CONN
R9802
52C6
21
23
5%
1/16W
MF-LF
402
PULLUP ON PAGE 21
5%
1/16W
MF-LF
402
STANDOFFS ARE 860-0893
MLB: AUDIO CONNECTOR

SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
98
109
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET
LAYER
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
FSB_DSTB
=3x_DIELECTRIC
LAYER
FSB_ADDR
=STANDARD
TABLE_SPACING_RULE_ITEM
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
FSB_ADSTB
=2x_DIELECTRIC
FSB_1X
=STANDARD
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
0.175 MM
0.175 MM
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
LAYER
WEIGHT
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
CPU_AGTL
CPU_AGTL
TOP,BOTTOM
CPU_8MIL
0.2 MM
CPU_COMP
0.6 MM
CPU_GTLREF
0.6 MM
SR DG recommends at least 25 mils, >50 mils preferred
?
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
0.6 MM
MOST CPU SIGNALS WITH IMPEDANCE REQUIREMENTS ARE 50-OHM SINGLE-ENDED.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
e
r
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
0.2 MM
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints
PHYSICAL_RULE_SET
LAYER
CLK_FSB_100D
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=100_OHM_DIFF
MINIMUM NECK WIDTH
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SPACING_RULE_SET
CLK_FSB
FSB_DATA
FSB_DATA_GROUP0_PP
FSB_50S
FSB_DATA
FSB_DSTB0_PP
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1_PP
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1_PP
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2_PP
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2_PP
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3_PP
CLK_FSB
MAXIMUM NECK LENGTH

=100_OHM_DIFF
LAYER
TOP,BOTTOM
DIFFPAIR NECK GAP
=100_OHM_DIFF
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3_PP
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0_PP
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0_PP
FSB_50S
FSB_ADDR
FSB_ADSTB0_PP
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP1_PP
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1_PP
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L_PP
FSB_50S
FSB_1X
FSB_50S
FSB_1X
FSB_1X_PP
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X_PP
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X_PP
FSB_50S
FSB_1X
FSB_1X_PP
FSB_50S
FSB_1X
FSB_1X_PP
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC_PP
CPU_50S
CPU_AGTL
MCP_BSEL
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_8MIL
CPU_ASYNC_PP
CPU_50S
CPU_AGTL
CPU_ASYNC_PP
CPU_50S
CPU_AGTL
CPU_ASYNC_PP
CPU_50S
CPU_AGTL
CPU_ASYNC_PP
CPU_50S
CPU_AGTL
CPU_PROCHOT
CPU_50S
CPU_AGTL
=4x_DIELECTRIC
CPU_A20M_L
MCP_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU_PP
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
CPU_50S
CPU_AGTL
CPU_IERR_L
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI_K50
CPU_50S
CPU_ITP
XDP_TDO_K50
CPU_50S
CPU_ITP
XDP_TMS_K50
CPU_50S
CPU_ITP
XDP_TCK_K50
CPU_50S
CPU_ITP
XDP_TRST_L_K50
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
FSB_CLK_ITP
FSB_CLK_MCP
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_ASYNC_PP
=100_OHM_DIFF
WEIGHT
FSB_A_L<5..3>
FSB_A_L<6>
FSB_A_L<16..7>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<26..17>
FSB_A_L<27>
FSB_A_L<35..28>
FSB_ADSTB_L<1>
CPU_ASYNC_PP
FSB_D_L<0>
FSB_D_L<15..1>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_D_L<16>
FSB_D_L<31..17>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_D_L<40..32>
FSB_D_L<41>
FSB_D_L<47..42>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<58..48>
FSB_D_L<59>
FSB_D_L<63..60>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
7D7 7D8 10C4 14D3

10C4 14D3
7D7 7D8 10C4 14D6
7D7 7D8 10C4 14D6
10C4 14D6
7D7 7D8 10C4 14D3
10B4 10C4 14C3 14D3
10B4 14D6
7D7 7D8 10B4 14D6

10B4 14D6
10C2 14C3
y
r
a
n
i
m
il
FSB 2X
Signals
FSB 1X signals shown in signal table on right.

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB_50S
WEIGHT
FSB_DATA
FSB_DATA_GROUP0
SPACING_RULE_SET
FSB_DATA
FSB_50S
=1:1_DIFFPAIR
FSB 4X Signal Groups
FSB 1X Signals
FSB_DSTB_50S
FSB_DATA_GROUP0_PP
7D7 7D8 10C2 14C3
10C2 14B3 14C3
7D7 7D8 10C2 14D6
10C2 14D6
7D7 7D8 10C2 14D6
10B2 10C2 14B3
7D7 7D8 10B2 14B3
10B2 14B3
7D7 7D8 10B2 14D6
10B2 14D6
7D7 7D8 10B2 14D6
10D8 14D6
7D7 7D8 10D8 14D6
10D8 14C6 14D6
7C7 7C8 10D8 14B6

7D7 7D8 10D8 14B6
10C8 10D8 14C6
7D7 7D8 10C8 14C6
10C8 14C6
7D7 7D8 10C8 14B6
10D6 14B6
7D7 10D6 14B6 23C3
14B6
7D7 10D6 14B6
10D6 14B3
7D7 10D6 14B6
10D6 14B3
10D6 14B6
7D7 10D6 14B6

7D7 10D6 14B6
7D7 10D6 14B6
14A3 23C3 10D6 13C2

14A6 10D6
14B6 10D6
7D8 14A3 10C8
23B6 23C6
10C8 14B7
7D8 14A3 10C8
7D8 14A3 10D6

7D8 14A3 10C8
7D8 14A3 10B8
10C5 14B6 50B3
14A3 7B4 10B2 13C7

7C8 14A3 10B8
7D8 14A3 10C8
10C6 50B1 14B7

14A3 10B2
14A3 10B2
14A3 10B2 71C7

7C7 14A3 10B2
14A6
14A6
14A6
14A6
7C8 14B3 10B6
7C8 14B3 7B3 10B6
14B3 7A4 13C3

14B3 7A4 13C3
14A4
14A4
10D6
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
21C7 71C8
71C7
29B2 10B4
10B3
10B3
10B3
10B3
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
13B3 7A4 10B6 10C6
CPU/FSB Constraints
10C6 7A4 10B6 13B3

13B3 7A4 10B6 10C6
SYNC_MASTER=K50
13B6 7A4 10A6 10C6

13B3 7A4 10A6 10C6
10C6 13C6 7B4

10C5 13C6 7B4

7A4 13C4
CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N

12C1 71C7

11B5 71A3
SIZE
11A5 71A3
DRAWING NUMBER
71A5
71A5
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
100
109
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
NET_TYPE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
PHYSICAL
SPACING
=STANDARD
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK_P<1..0>
MEM_A_CLK_N<1..0>
MEM_40S_VDD
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
Memory Net Properties
NET_TYPE
DIFFPAIR NECK GAP

MEM_40S
=STANDARD
PHYSICAL
SPACING
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
15B5 31C5 31C7
MEM_B_DQS0
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
15B5 31C5 31C7
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
LAYER
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
=70_OHM_DIFF
SPACING_RULE_SET
MEM_A_CNTL
MEM_CLK2MEM
=4:1_SPACING
MEM_CTRL2CTRL
=2:1_SPACING
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
=2.5:1_SPACING
?
MEM_CMD2CMD
=1.5:1_SPACING
MEM_40S_VDD
MEM_CMD
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0_PP
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
?
MEM_CMD2MEM
=3:1_SPACING
MEM_A_DQ_BYTE1_PP
MEM_DATA2DATA
=1.5:1_SPACING
MEM_DATA2MEM
=3:1_SPACING
MEM_DQS2MEM
=3:1_SPACING
MEM_2OTHER
=3:1_SPACING
MEM_A_DQ_BYTE1
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_40S
MEM_DATA
MEM_40S
MEM_DATA
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3_PP
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5_PP
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_DQS
MEM_CMD
MEM_CLK2MEM
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_70D
MEM_DATA
MEM_A_DQ_BYTE0
MEM_CTRL
MEM_DATA
MEM_CTRL
MEM_DATA
MEM_40S
MEM_CMD2MEM
NET_SPACING_TYPE1
MEM_40S
MEM_CLK
MEM_A_DQ_BYTE7_PP
MEM_A_DQ_BYTE7
MEM_A_DQS1_PP
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_DATA
MEM_DQS
MEM_DATA2MEM
MEM_A_DQS2_PP
MEM_A_DQS3_PP
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_A_DQS4_PP
MEM_A_DQS5_PP
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_CTRL
MEM_2OTHER
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DQS
MEM_DQS
MEM_DQS2MEM
MEM_2OTHER
MEM_DQS
MEM_2OTHER
MCP MEM COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
MCP_MEM_COMP
ALLOW ROUTE
ON LAYER?
Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
0.175 MM
0.175 MM
SPACING_RULE_SET
LAYER
WEIGHT
0.2 MM
MCP_MEM_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D_VDD
MEM_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0_PP
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
e
r
MEM_70D
MEM_70D
MEM_A_DQS7
MEM_B_CLK
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_DQS
MEM_DQS
Need to support MEM_*-style wildcards!
DQ signals should be matched within 5 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_DQS
MEM_70D
MEM_DQS
DDR2:
DDR3:
MEM_DQS
MEM_70D
MEM_70D
DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_DATA
MEM_70D
MEM_A_DQS6
MEM_DATA
MEM_DATA
MEM_A_DQ_BYTE2_PP
Memory Bus Spacing Group Assignments
MEM_40S
MEM_A_DQ_BYTE2
MEM_B_DQ_BYTE1_PP
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2_PP
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3_PP
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4_PP
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7_PP
MEM_40S
MEM_DATA
MEM_B_CKE<1..0>
MEM_B_CS_L<1..0>
MEM_B_ODT<1..0>
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<5..0>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<15..9>
MEM_B_DQ<22..16>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<31..26>
MEM_B_DQ<37..32>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<61..56>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
DIFFPAIR NECK GAP
=STANDARD
MEM_B_DQS1
15A5 31D5 31D7

15B5 31C5 31C7
MEM_B_DQS2_PP
15B5 31C5
15B5 15C5 31C5 31C7
MEM_B_DQS3
15C5 31C5 31C7
15C5 31C5
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
15B7 15C7 31B2 31B4 31C2

31C4
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
15C7 31C4
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
15C5 31C7
y
r
a
n
i
m
il
MEM_A_CMD
MEM_CTRL2MEM
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ<6..0>
MEM_A_DQ<7>
MEM_A_DQ<13..8>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<23..17>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<31..26>
MEM_A_DQ<39..32>
MEM_A_DQ<46..40>
MEM_A_DQ<47>
MEM_A_DQ<55..48>
MEM_A_DQ<58..56>
MEM_A_DQ<59>
MEM_A_DQ<63..60>
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<1..0>
MEM_B_CLK_N<1..0>
WEIGHT
MEM_A_CKE<1..0>
MEM_A_CS_L<1..0>
MEM_A_ODT<1..0>
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
15C5 31C7
MEM_B_DQS5_PP
15B7 31C2 31C4 31D2 31D4

7C7 15B7 31C4
MEM_B_DQS6_PP
15B7 31C2 31C4

7C7 15B7 31C2
15B7 31C4
15D1 32C2
15D1 32D2
15D1 32C4
15D1 32C4
7B7 15D1 32B2
15D1 32C2
15D1 32C4
7B7 15D1 32C4
7B7 15D1 32B5

7B7 15D1 32B5
7B7 15D1 32B7
15D1 32B7
15D1 32A5
7B7 15D1 32A5
7C7 15B7 31B4
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
16C6
16C6
7C7 15C7 31C4
15C7 31C2 31C4
15C7 31B5 31B7 31C5 31C7

15C7 15D7 31B5 31B7
7C7 15D7 31B7
15D7 31B5 31B7

15D7 31A7 31B5
7C7 15D7 31A7
15D7 31A5 31A7 31B7

15A7 31C4
15A7 31C2
15B7 31B4
15B7 31C2
15B7 31B5
15B7 31B7
15B7 31B5
15B7 31A7
15D5 31C2
15D5 31D2
7C7 15D5 31C4
15D5 31C4
7C7 15D5 31B2

15D5 31C2
7C7 15D5 31C4
15D5 31C4
7B7 15D5 31B7

15D5 31B7
7B7 15D5 31B5

15D5 31B5
15D5 31B7
7B7 15D5 31B7

15D5 31A5
15D5 31A5
15B1 32C5 32C7

15B1 32C5 32C7
15A1 32D5 32D7
15B1 32C5 32C7
15B1 32C5
15B1 15C1 32C5 32C7

15C1 32C5 32C7
15C1 32C5
15C1 32C7
15C1 32C7
15B3 32C2 32D2 32D4

7B7 15B3 32C4
15B3 32C4
7B7 15B3 32C4
15B3 32C2 32C4
15B3 15C3 32B2 32B4 32C2 32C4
7B7 15C3 32B4

15C3 32C4
7B7 15C3 32C4
15C3 32C2 32C4

15C3 32B5 32B7 32C5 32C7
7B7 15C3 32B7
15C3 32B5
15C3 15D3 32B5 32B7
15D3 32B5 32B7
15D3 32A7 32B5 32B7
7B7 15D3 32A5
15D3 32A5
15A3 32C4
15A3 32C2
15B3 32B4
Memory Constraints
15B3 32C2
15B3 32B5
SYNC_MASTER=K50
15B3 32B7
15B3 32B5
15B3 32A7

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7840
SCALE
SHT
NONE
15D1 32B7
7B7 15D1 32B7
10
OF
101
109
PCI-Express
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
=3X_DIELECTRIC
0.5 MM
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PEG_D2R_MXM3
PCIE_90D
PCIE
PEG_D2R_MXM3_PP
PCIE_90D
PCIE
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
PEG_R2D
CLK_PCIE
PCIE
PCIE_90D
WEIGHT
PCIE
PCIE_90D
?
MCP_PEX_COMP
0.2 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SATA
=4x_DIELECTRIC
SATA_TERMP
0.2 MM
SATA
TOP,BOTTOM
PCIE_MINI_R2D
PCIE_MINI_D2R_PP
PCIE_FW_R2D_PP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
PCIE_FW_D2R_PP
MCP_PE0_REFCLK
MCP_PE1_REFCLK
MCP_PE2_REFCLK_PP
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
MCP_DV_COMP
MCP_PEX_CLK_COMP
MCP_50S
MCP_PEX_COMP
MCP_IFPAB_RSET
MCP_DV_COMP
MCP_PEX_COMP
MCP_IFPAB_VPROBE
MCP_50S
MCP_PEX_COMP
SATA_HDD_R2D
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
MCP_50S
SATA_TERMP
MCP_SATA_TERMP
PM_SLP_S3_L
PM_SLP_S4_L
PCIE_90D
MCP_HDMI_VPROBE
SATA_ODD_D2R_PP
PCIE
MCP_DV_COMP
SATA_ODD_R2D
e
r
PCIE_90D
MCP_HDMI_RSET
SATA_HDD_D2R_PP
9C6 86A7 86B7 86C7 86D7

9C6 86A7 86B7 86C7 86D7
7B7 86A1 86B1 86C1 86D1 9C6
7B7 86A1 86B1 86C1 86D1 9C6
86A5 86B5 86C5 86D5 84A8 84B8
86A5 86B5 86C5 86D5 84A8 84B8
84C8 86A4 86B4 86C4

84C8 86C4
y
r
a
n
i
m
il
PEG_D2R_MXM3
SATA Interface Constraints
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
MXM_PCIE_R2D_P<15..0>
MXM_PCIE_R2D_N<15..0>
MXM_PCIE_D2R_P<7..0>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_P<15..9>
MXM_PCIE_D2R_N<15..0>
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
GPU_CLK100M_PCIE_P
GPU_CLK100M_PCIE_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
MCP_PEX_CLK_COMP
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
MCP_SATA_TERMP
PM_SLP_S3_L
PM_SLP_S4_L
84B8 84C8 86C4 86D4
84B8 84C8 86A4 86B4 86C4 86D4

34C6
34C6
17B3 34B8
17B3 34C8
7C8 34C8 17B6
7C8 34C8 17B6

7D6 41C3
7D6 41C3
17B3 41C1
17B3 41C1
7C8 41C1 17B6

7C8 41C1 17B6
41C3
41C3
9C6 87C5
9C6 87C5 7C3
17C3 34C6
17C3 34C6
7D6 17C3 41C2

7D6 17C3 41C2
18A6 26C7
18A6 26C7
17A6
18A3 26C6
18A3 26C6
20D6 45D5
20D6 45D5
45D7
45D7
7B8 45C5 20D6

7B8 45D5 20D6
45D7
45D7
20D6 45C5
20D6 45C5
45C7
45C7
7B8 45C5 20D6

7B8 45C5 20D6
45C7
45C7
20A6
21C3 7B4 9D7
21C3 7B4 38D7 49C5 50C3 70D8
MCP Constraints 1
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
102
109
PCI Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
PCI_REQ0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_CLK33M_MCP
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_AD_2PP
LPC_55S
LPC
LPC_AD
LPC_55S
LPC
LPC_55S
LPC
LPC_55S
LPC
LPC_55S
LPC
SPACING_RULE_SET
LAYER
WEIGHT
PCI
=STANDARD
?
CLK_PCI
0.2 MM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LPC_FRAME_L
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
LPC
0.15 MM
?
CLK_LPC
0.2 MM
LPC
LPC_55S
LPC
LPC_CLK33M
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
MCP_USB_RBIAS
MCP_USB_RBIAS
USB_EXT
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_EXT
USB_EXT
USB_EXT_MUXED
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_USB_RBIAS
=STANDARD
0.2 MM
0.2 MM
=STANDARD
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
USB_MINI
USB_CAMERA
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
USB
USB
TOP,BOTTOM
USB_BT_PP
USB_IR
SMBus Interface Constraints
USB_IR
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPI_CLK
SPI_MOSI
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
SMB
SPI_MISO
SPI_CS0
HD Audio Interface Constraints
e
r
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
HDA
MCP_HDA_COMP
0.2 MM

SPI Interface Constraints
=STANDARD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
0.2 MM
SPI
7B3 19D2 19D7

19C5
19C5
19B3 49C8 51D5 7D4
7B8 7D6 19B3 49C8 51D5 7D4
19B3 49C8 51D4 7D4
19B5
19C3 7D4 49C8 51D5
51C2
HDA_BIT_CLK
HDA_RST_L
HDA_SDOUT
HDA_SYNC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
MCP_50S
SPI
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_RST_L
HDA_RST_R_L
HDA_SDOUT
HDA_SDOUT_R
HDA_SYNC
HDA_SYNC_R
19C5 51C1
19C3 9D4
19B3 9B4
9B2 49C8
9B2 7D4 51D4

21B3 9B4
9B2 49C5
20C4
20D3 46A7
20D3 46A7
46A5
46A5
20C3 46B6
20C3 46B6
46B5
46B5
20C3 46B3
20C3 46B3
46B2
46B2
20D3 46D5
20D3 46D5
46D4
46D4
46D3
46D3
20D3 34B3
20D3 34B3
7B8 20D3 47B7

7B8 20D3 47B7
47B6
47B6
7B8 20D3 47D4

7B8 20C3 47D4
20D3 47B4
20D3 47B4
47B3
47B3
7B8 21B3 51A6 61C6
61C5
21B3 51A6 61C2

61C4
7B8 51A6 61B2 21B3
61B4
21B3 51C6
51C7
21D2 98C6
21D4 21A7
21D2 98C6
21D4 21A7
21D2 98C6
21D4 21A7
21D2 98C6
21D4 21A7
PHYSICAL_RULE_SET
7B3 19D2 19D7
y
r
a
n
i
m
il
LPC_55S
LPC_RESET_L
MCP_SUS_CLK
PCI_REQ0_L
PCI_REQ1_L
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD<0>
LPC_AD<1>
LPC_AD<3..2>
LPC_AD_R<3..0>
LPC_FRAME_L
LPC_FRAME_PU
LPC_FRAME_R_L
LPC_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
MCP_USB_RBIAS_GND
USB_EXTA_P
USB_EXTA_N
USB_PORT0_P
USB_PORT0_N
USB_EXTB_P
USB_EXTB_N
USB_PORT1_P
USB_PORT1_N
USB_EXTC_P
USB_EXTC_N
USB_PORT2_P
USB_PORT2_N
USB_EXTD_P
USB_EXTD_N
USB_D_MUXED_P
USB_D_MUXED_N
USB_PORT3_P
USB_PORT3_N
USB_MINI_P
USB_MINI_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_L_P
USB_CAMERA_L_N
USB_BT_P
USB_BT_N
USB_IR_P
USB_IR_N
USB_IR_L_P
USB_IR_L_N
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
MCP Constraints 2
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
103
109
MCP RGMII (Ethernet) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_MII_COMP
=STANDARD
0.2 MM
0.2 MM
=STANDARD
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_CLK25M_BUF0_R
18C6
18C6
18C3 38B3
38B2 37B6
MCP_BUF0_CLK
=3:1_SPACING
ENET_MII
0.3 MM
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_RXCLK
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD_STRAP
ENET_RXD
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI
0.6 MM
e
r
ENET_MDIO
ENET_MDC
ENET_CLK125M_RXCLK
ENET_CLK125M_RXCLK_R
ENET_RXD<0>
ENET_RXD_R<0>
ENET_RXD<3..1>
ENET_RXD_R<3..1>
ENET_RX_CTRL
ENET_RXCTL_R
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_MDI_T_P<3..0>
ENET_MDI_T_N<3..0>
18C3 37B6
18D3 37B6
37C1 18D6
37C4
y
r
a
n
i
m
il
ENET_RXD
RTL8211CLGR (ETHERNET PHY) CONSTRAINTS

PHYSICAL_RULE_SET
ENET_MDIO
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
37C1 18D6
37C4
37C1 18D6
37C4
37B1 18D6
37B4
18D3 37C7
18D3 37C6
18D3 37C6
18D3 37B6
37B3 39C5 39C6 39C7 39C8

37B3 39C5 39C6 39C7 39D8
39C1 39A4 39A5
39C1 39D1 39A4 39A5
Ethernet Constraints
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
FIT;
REV.
051-7840
10
OF
104
109
FireWire Interface Constraints
FireWire Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_0_TPA
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
SPACING_RULE_SET
LAYER
WEIGHT
FW_0_TPB
FW_TP
=3:1_SPACING
FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N
42C2 43B5
42C2 43C5
42C2 43C5
42C2 43C5
PORT 1 & 2 NOT USED
e
r
y
r
a
n
i
m
il
FireWire Constraints
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
10
051-7840
OF
105
109
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
PHYSICAL
SPACING
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SMB
=2x_DIELECTRIC
e
r
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
52D2
52D2
52C5
52C5
52D5
52D5
52C2
52C2
106D3 52C2
106D3 52C2
y
r
a
n
i
m
il
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
106D3 52C2
106D3 52C2
13B6 21C3 7A4 52D8

13B6 21C3 7A4 52D8
SMC Constraints
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
106
109
NET_TYPE
Digital Video Signal Constraints

PHYSICAL
SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
DP_ML_MXM3
DP_100D
DISPLAYPORT
DP_ML_MXM3
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
0.5 MM
0.5 MM
=STANDARD
=STANDARD
=STANDARD
DP_ML_MXM3
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
=3x_DIELECTRIC
87B5 91B8 91C4 91C8 91D8

9C6 91B8 91C8 91D4 91D8
91B5 91C2 91C5 94B8 94C1 94C8
91B5 91C2 91C5 91D5 94B8 94C1 94C8
94C4 94C5
94C4 94C5
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_IG_AUX_CH
DP_AUX_CH
LVDS_A_CLK_MXM3
LVDS_A_DATA_MXM3
LVDS_B_CLK_MXM3
LVDS_B_DATA_MXM3
LVDS_A_CLK_MXM3
LVDS_A_DATA_MXM3
LVDS_B_CLK_MXM3
LVDS_B_DATA_MXM3
e
r
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
LVDS_100D
GND
LVDS_100D
GND
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
GND
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N
DP_AUX_CH_C_P
DP_AUX_CH_C_N
DP_EG_AUXCH_P
DP_EG_AUXCH_N
18B6 93C8
y
r
a
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i
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il
DP_AUX_CH
DP_AUX_CH
87B5 91B7 91C4 91C8

9C6 91B7 91B8 91C4 91C8
LVDS
DP_ML_MXM3
DP_EG_ML_P<3..0>
DP_IG_ML_P<3..0>
DP_EG_ML_N<3..0>
DP_IG_ML_N<3..0>
DP_ML_P<3..0>
DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
LVDS_100D
GND
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<3..0>
LVDS_IG_A_DATA_N<3..0>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<3..0>
LVDS_IG_B_DATA_N<3..0>
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P<3..0>
LVDS_EG_A_DATA_N<3..0>
LVDS_EG_B_CLK_P
LVDS_EG_B_CLK_N
LVDS_EG_B_DATA_P<3..0>
LVDS_EG_B_DATA_N<3..0>
LVDS_EG_A_CLK_L_P
LVDS_EG_A_CLK_L_N
LVDS_EG_B_CLK_L_P
LVDS_EG_B_CLK_L_N
18B6 93C8
93C6
93D5
93B2 93C4 94C2

93C2 93D4 94C2
87A6 93B4
87A6 93C4
18B3 89B8
18B3 89B8
18B3 89B8 89C8 89D8

18B3 89B8 89C8 89D8
18B3 89C5
18B3 89C5
18B3 89A8 89C5 89D5

18B3 89A8 89C5 89D5
87D5 89B6
87D5 89B6
87D5 89B6 89C6 89D6 90A6 90A8

87D5 89B6 89C6 89D6 90A6 90A8
87D5 89C3
87D5 89C3
87D5 89A6 89C3 89D3 90A8 90B6

87D5 89A6 89C3 89D3 90A6 90B8
89B5 90A8
89B5 90A6
89C2 90A8
89C2 90A6
GRAPHICS CONSTRAINTS
SYNC_MASTER=K50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
107
109
7
LAYER
WEIGHT
=STANDARD
K50/K51 SPECIFIC NET PROPERTIES
SPACING_RULE_SET
NET_TYPE
GND
PHYSICAL
SPACING
PPDDR_MEM
=STANDARD
WEIGHT
PPDDR_MEM
PPDDR_MEM
SPACING_RULE_SET
LAYER
SWITCHNODE
GND_P2MM
0.20 MM
1000
PWR_P2MM
0.20 MM
1000
SWITCHNODE
SWITCHNODE
SWITCHNODE
SWITCHNODE
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SWITCHNODE
SPACING_RULE_SET
GND
GND_P2MM
MEM_CMD
GND
GND_P2MM
MEM_CTRL
GND
GND_P2MM
SWITCHNODE
SWITCHNODE
THERM_DIFF
MEM_DATA
GND
GND_P2MM
MEM_DQS
GND
GND_P2MM
PPDDR_MEM
PWR_P2MM
MEM_CMD
PPDDR_MEM
PWR_P2MM
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
MEM_CLK
THERM_DIFF
THERM_DIFF
THERM_DIFF
MEM_CTRL
PPDDR_MEM
THERM_DIFF
PWR_P2MM
MEM_DATA
PPDDR_MEM
PWR_P2MM
MEM_DQS
PPDDR_MEM
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SPACING_RULE_SET
CLK_PCIE
GND
GND_P2MM
PCIE
GND
GND_P2MM
CLK_FSB
GND
GND_P2MM
CPU_COMP
GND
GND_P2MM
THERM_DIFF
THERM_DIFF
SATA
GND
CPU_GTLREF
GND
GND_P2MM
CPU_VCCSENSE
GND
GND_P2MM
GND_P2MM
THERM_DIFF
USB
GND
GND_P2MM
FSB_DSTB
GND
THERM_DIFF
GND_P2MM
THERM_DIFF
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERM_DIFF
THERMAL
THERM_DIFF
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERMAL
THERM_DIFF
THERM_DIFF
THERM_DIFF
THERM_DIFF
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
PWR
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
THERMAL
4:1_SPACING
SWITCHNODE
SWITCHNODE
THERMAL
PWR
PWR_P2MM
THERMAL
GND
GND_P2MM
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
THERM_DIFF
1:1_DIFFPAIR
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
LAYER
MEM_40S
TOP
OVERRIDE
OVERRIDE
MEM_40S_VDD
TOP
OVERRIDE
OVERRIDE
MEM_70D
TOP
OVERRIDE
OVERRIDE
PCIE_90D
TOP
OVERRIDE
OVERRIDE
USB_90D
TOP
OVERRIDE
OVERRIDE
MCP_DV_COMP
TOP
OVERRIDE
OVERRIDE
MCP_MEM_COMP
TOP
OVERRIDE
OVERRIDE
MCP_MII_COMP
TOP
OVERRIDE
OVERRIDE
MCP_USB_RBIAS
TOP
OVERRIDE
OVERRIDE
MCP_DV_COMP
OVERRIDE
OVERRIDE
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
0.1 MM
0.1 MM
MAXIMUM NECK LENGTH

600 MIL
OVERRIDE
600 MIL
OVERRIDE
600 MIL
OVERRIDE
500 MIL
OVERRIDE
500 MIL
0.1 MM
0.1 MM
0.1 MM
0.1 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
e
r
DIFFPAIR NECK GAP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
6D3 31A5 31D7

6D3 32A5 32D7
71D4 71A6
71C4 71A4
72C6 72A7
80C5
79C5
76C6
y
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i
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SWITCHNODE
MEM_CLK
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
IMVP6_PHASE1
IMVP6_PHASE2
IMVP6_PHASE3
1V8_SW
1V05S5_SW
P1V05S0_PHASE
3V3S5_SW
5VS3_SW
MCPCORES0_PHASE
SNS_T_DP1_DN6
SNS_T_DN1_DP6
SNS_T_DP2_DN3
SNS_T_DN2_DP3
CPU_THERMD_P
CPU_THERMD_N
SNS_T_DP4_DN5
SNS_T_DN4_DP5
MCP_THMDIODE_P
MCP_THMDIODE_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MXM_PWRSRC_SENSOR_P
MXM_PWRSRC_SENSOR_N
SENSE_12V_S0_P
SENSE_12V_S0_N
SENSE_12V_S5_P
SENSE_12V_S5_N
SENSE_1V5_S0_P
SENSE_1V5_S0_N
SNS_LCD_P
SNS_LCD_N
SNS_ODD_P
SNS_ODD_N
SNS_CPU_H_P
SNS_CPU_H_N
SNS_HDD_P
SNS_HDD_N
HDD_OOB_TEMP_FILT
SNS_AMB_P
SNS_AMB_N
SNS_MXM_P
SNS_MXM_N
MCPTHMSNS_FILT_P
MCPTHMSNS_FILT_N
76C3
73C5
74C5
55A8 55D6 55D8

55A8 55D6 55D8
55A8 55C6 55C8
55A8 55C6 55C8
10C6 55D4
10C6 55D4
55A8 55B6 55B8
55A8 55B6 55B8

21C3 55C4
21C3 55C4
55B3
55B3
53C4
53C4
53B3 53B4
53B3 53B4
53B3 53C4
53B3 53C4
54D6
54D6
55C7
55D7
55D7
55B7
55B7
55D6
55D6
55D6
55C6
55C6
55B6
55B6
55B4
55B4
OVERRIDE
500 MIL
OVERRIDE
500 MIL
OVERRIDE
K50/K51 SPECIFIC CONSTRAINTS
500 MIL
OVERRIDE
SYNC_MASTER=K50
OVERRIDE
0.25 MM
250 MIL
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
55C7

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
108
109
K50/K51 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
CONSTRAINTS FOR BGA AREA

PHYSICAL CONSTRAINTS
SPACING_RULE_SET
LAYER
WEIGHT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
BGA_P1MM
=DEFAULT
BGA_P2MM
0.2 MM
BGA_P3MM
0.3 MM
DEFAULT
=50_OHM_SE
=50_OHM_SE
100 MM
0 MM
0 MM
STANDARD
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
D
27P4_OHM_SE
TOP,BOTTOM
0.345 MM
0.085 MM
=STANDARD
27P4_OHM_SE
0.275 MM
0.085 MM
=STANDARD
y
r
a
n
i
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il
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA_P1MM
BGA_P1MM
MEM_CLK
BGA_P1MM
BGA_P2MM
CLK_FSB
BGA_P1MM
BGA_P2MM
CLK_PCIE
BGA_P1MM
BGA_P1MM
FSB_DSTB
FSB_DSTB
BGA_P1MM
BGA_P1MM
CLK_LPC
BGA_P1MM
BGA_P1MM
CLK_PCI
BGA_P1MM
BGA_P1MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MCP_FSB_COMP
BGA_P1MM
BGA_P2MM
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
40_OHM_SE
TOP,BOTTOM
0.19 MM
0.085 MM
=STANDARD
40_OHM_SE
0.15 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
0.125 MM
0.085 MM
15 MM
50_OHM_SE
0.1 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
55_OHM_SE
TOP,BOTTOM
0.1 MM
0.085 MM
=STANDARD
55_OHM_SE
0.075 MM
0.075 MM
=STANDARD
=STANDARD
=STANDARD
MCP_MEM_COMP
BGA_P1MM
BGA_P2MM
MCP_PEX_COMP
BGA_P1MM
BGA_P2MM
MCP_HDA_COMP
BGA_P1MM
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL6
0.155 MM
0.085 MM
=STANDARD
0.135 MM
0.1 MM
70_OHM_DIFF
TOP,BOTTOM
0.185 MM
0.085 MM
=STANDARD
0.125 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL6
0.099 MM
0.085 MM
12 MM
0.200 MM
0.1 MM
90_OHM_DIFF
TOP,BOTTOM
0.121 MM
0.085 MM
=STANDARD
0.18 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL6
0.081 MM
0.085 MM
=STANDARD
0.25 MM
0.1 MM
100_OHM_DIFF
TOP,BOTTOM
0.115 MM
0.085 MM
=STANDARD
0.180 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
TOP,BOTTOM
0.085 MM
0.085 MM
=STANDARD
0.3 MM
0.15 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.085 MM
1:1_DIFFPAIR
TOP,BOTTOM
=STANDARD
=STANDARD
=STANDARD
0.125 MM
0.085 MM
e
r
SPACING RULE SET

SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
0.150 MM
DEFAULT
0.1 MM
2X_DIELECTRIC
STANDARD
=DEFAULT
2X_DIELECTRIC
3X_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
3X_DIELECTRIC
1.5:1_SPACING
0.15 MM
2:1_SPACING
0.2 MM
4X_DIELECTRIC
4X_DIELECTRIC
2.5:1_SPACING
0.25 MM
5X_DIELECTRIC
3:1_SPACING
0.3 MM
5X_DIELECTRIC
4:1_SPACING
0.4 MM
WEIGHT
SPACING_RULE_SET
LAYER
CLK_SPACING_0.5MM
0.5 MM
CLK_SPACING_0.6MM
0.6 MM
GND_P2MM
0.2 MM
1000
PWR_P2MM
0.2 MM
1000
SWITCHNODE
0.6 MM
P
TOP,BOTTOM
0.160 MM
0.220 MM
TOP,BOTTOM
0.240 MM
0.300 MM
TOP,BOTTOM
0.320 MM
0.380 MM
TOP,BOTTOM
0.400 MM
K50/K51 RULE DEFINITIONS

SYNC_MASTER=K50

1000

CONSTRAINTS ARE BASED ON MCP79 DESIGN GUIDE DG-03328-001_V06

PCI,LPC,SMB,HDA,SPI,RGMII,SMBUS ARE ROUTED AS 55 OHM SE SIGNALS

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7840
10
OF
109
109

LB# 820-2347 Schematic Diagram (Project K50)

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LB# 820-2347 Schematic Diagram (Project K50)

Enviado por

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Formatos disponíveis

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Power Block Diagram

Power Conn / Alias

Functional / ICT Test

UNUSED SIGNAL ALIAS/STAND OFF

SIGNAL & GND ALIASES

CPU Power & Ground

CPU Decoupling & VID

eXtended Debug Port (XDP)

MCP CPU Interface

MCP Memory Interface

MCP Memory Misc

MCP PCIe Interfaces

MCP Ethernet & Graphics

MCP PCI & LPC

MCP SATA & USB

MCP HDA & MISC

MCP Power & Ground

MCP Standard Decoupling

MCP Graphics Support

FSB/DDR3 Vref Margining

MEMORY COUPLING CAPS

DDR3 SO-DIMM Connector A

DDR3 SO-DIMM CONNECTOR B

PCI-E MiniCard Connector

Ethernet PHY (RTL8211CL)

Ethernet & AirPort Support

FireWire LLC/PHY (FW643)

FW: 1394B MISC

MCP CURRENT AND VOLTAGE SENSE

POWER SEQUENCING BLOCK DIAGRAM

PGOOD and Power Sequencing

IMVP6 CPU VCore Regulator

IMVP6 3RD PHASE

MCP CORE REGULATOR

1.5V DDR SUPPLY

1V05 S5 POWER SUPPLY

1V8 POWER SUPPLY

MXM PCIe, DP & Power

MXM PCIE CAPS

LVDS MUX RESISTORS

INTERNAL DISPLAY CONNS

MLB: AUDIO CONNECTOR

K50/K51 SPECIFIC CONSTRAINTS

K50/K51 RULE DEFINITIONS

EXTERNAL USB CONNECTORS

Internal USB Connections

LPC+SPI Debug Connector

Current & Voltage Sensing

LAST_MODIFIED=Thu Oct 30 17:51:22 2008

DIMENSIONS ARE IN MILLIMETERS

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

LAST_MODIFIED=Thu Oct 30 17:51:22 2008

(UP TO FOUR PORTS)

FAN CONN AND CONTROL

J5600, J5601, J5700

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY