ALU PROGRAM library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.

all; entity alu is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); sl : in std_logic_vector(2 downto 0); fg : out std_logic_vector(2 downto 0); r : out std_logic_vector(3 downto 0)); end alu; architecture Behavioral of alu is component add is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f :out std_logic_vector (2 downto 0)); end component; component sub is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); d : out std_logic_vector(3 downto 0); f :out std_logic_vector(2 downto 0)); end component; component com is Port ( x : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f : out std_logic_vector(2 downto 0)); end component; component an is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f : out std_logic_vector(2 downto 0)); end component; component orop is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f: out std_logic_vector(2 downto 0)); end component; component zor is

Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f : out std_logic_vector(2 downto 0)); end component; component inc is Port ( x :in std_logic_vector(3 downto 0); z :out std_logic_vector(3 downto 0); f :out std_logic_vector(2 downto 0)); end component; component dec is Port ( x : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f : out std_logic_vector(2 downto 0)); end component; signal ra:std_logic_vector(3 downto 0); signal fa:std_logic_vector(2 downto 0); signal rs:std_logic_vector(3 downto 0); signal fs:std_logic_vector(2 downto 0); signal rc:std_logic_vector(3 downto 0); signal fc:std_logic_vector(2 downto 0); signal ran:std_logic_vector(3 downto 0); signal fan:std_logic_vector(2 downto 0); signal rin:std_logic_vector(3 downto 0); signal fin:std_logic_vector(2 downto 0); signal rdec:std_logic_vector(3 downto 0); signal fdec:std_logic_vector(2 downto 0); signal ro:std_logic_vector(3 downto 0); signal fo:std_logic_vector(2 downto 0); signal rx:std_logic_vector(3 downto 0); signal fx:std_logic_vector(2 downto 0); begin k1: add port map (a,b,ra,fa); k2: sub port map (a,b,rs,fs); k3: com port map (a,rc,fc); k4: an port map (a,b,ran,fan); k5: orop port map (a,b,ro,fo); k6: zor port map (a,b,rx,fx); k7: inc port map (a,rin,fin); k8: dec port map (a,rdec,fdec); process(a,b,sl,ra,fa,rs,fs,rc,fc,ran,fan,ro,fo,rx,fx,rin,fin,rdec,fdec) begin if sl="000" then

r<=ra; fg<=fa; elsif sl="001" then r<=rs; fg<=fs; elsif sl="010" then r<=rc; fg<=fc; elsif sl="011" then r<=ran; fg<=fan; elsif sl="100" then r<=ro; fg<=fo; elsif sl="101" then r<=rx; fg<=fx; elsif sl="110" then r<=rin; fg<=fin; else r<=rdec; fg<=fdec; end if; end process; end behavioral;