`include "reg_siso.

v"
`timescale 1ns/100ps
module reg_siso_tb;
reg
reg
reg
reg

clk;
reset_n;
shift;
data_in;

wire [3:0]data;
wire [3:0]data_next;
wire data_out;
reg_siso a1

always
#10 clk=~clk;
initial
begin
clk=0;
reset_n=0;
shift=0;
data_in=0;
#10
reset_n=1;
shift=1;
data_in=1;
#20
reset_n=1;
shift=1;
data_in=1;
#20
reset_n=1;
shift=1;
data_in=1;
#20
reset_n=1;
shift=1;
data_in=1;
#20
reset_n=1;
shift=1;
data_in=1;
#20
reset_n=1;
shift=1;

(data,
data_next,
data_in,
shift,
reset_n,
clk,
data_out );

data_in=0;
#20
reset_n=1;
shift=1;
data_in=0;
#20
reset_n=1;
shift=1;
data_in=0;
#20
$stop;
$finish;
end
endmodule