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Published Standards
IMIS Intimate Memory Interface Specification: by 3D-IC Alliance Wide IO DRAM (JESD229): by JEDEC 3D1-0912 Terminology for TSV Geometrical Metrology: by SEMI MS5-1211 Test Method for Wafer Bond Strength Measurements Using Micro-Chevron Structures: by SEMI Specification related to thin wafer handling : by SEMI Testing DFT/ATPG Test access architecture for 3D stacked IC and DFT : by IEEE 3D-IC Qualifications 3D IC packaged and unpackaged evaluations and qualifications : by JEDEC 3D-IR Reliability Test Methods Tests for 3D IC reliability : by JEDEC 3D Memory stack with TSV 3D memory stack for DDR3 and DDR4 using TSV : by JEDEC Model formats Electrical, thermal, stress : by Si2 JC-63 3D stacked packaging : by JEDEC Specification for Identification and marking of bonded wafer stacks : by SEMI
Roadblocks in its development Lack of standards Problems in testing Heat dissipation Insufficient EDA solutions Advantages of 3D IC
Smaller footprint: More function and transistors fit into a smaller chip area Heterogeneous integration Lesser fabrication costs as existing processes can be used Shorter interconnects Increased Bandwidth with wider buses feasible Improved security against reverse engineering
Fig 3: Showing the pin configuration of Channel A of Wideband IO standard. There are total 4 such channels in the standard.