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Required reading
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 8, Synchronous Sequential Circuits Sections 8.5, 8.8
Optional Reading
Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 6, Finite State Machines
begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Process statement
inside process you can use only sequential statements
Concurrent Statements
end ARCHITECTURE_NAME;
Serial Adder
11 0 00 0 01 1 10 1 01 0 10 0 11 1
G 00 1 G: carry-in = 0 H: carry-in = 1
10
1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY serial IS 4 GENERIC ( length : INTEGER := 8 ) ; 5 PORT ( Clock : IN STD_LOGIC ; 6 Reset : IN STD_LOGIC ; 7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0)); 9 END serial ;
11
18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 19 SIGNAL s, Low, High, Run : STD_LOGIC ;
12
BEGIN
Low <= '0' ; High <= '1' ; ShiftA: shiftrne GENERIC MAP (N => length) PORT MAP ( A, Reset, High, Low, Clock, QA ) ; ShiftB: shiftrne GENERIC MAP (N => length) PORT MAP ( B, Reset, High, Low, Clock, QB ) ;
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11 0 00 0 01 1 10 1 01 0 10 0 11 1
G 00 1 G: carry-in = 0 H: carry-in = 1
14
15
46 WITH y SELECT 47 s <= QA(0) XOR QB(0) WHEN G, 48 NOT ( QA(0) XOR QB(0) ) WHEN H ; 49 Null_in <= (OTHERS => '0') ; 50 ShiftSum: shiftrne GENERIC MAP ( N => length ) 51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ;
16
62 END Behavior ;
17
11 0 00 0 01 1 10 1 01 0 10 0 11 1
G 00 1 G: carry-in = 0 H: carry-in = 1
18
Present state
Output s 01 10 11
G H
G G
G H
G H
H H
0 1
1 0
1 0
0 1
19
Present state y 0 1
Output 01 s 1 0 1 0 0 1 10 11
20
a b
Reset
21
00
G0 s = 0 00 00
11
H0 s = 0
01 10
01 10
11
11
01 10
01 10
G1 s = 1
00
H1 s = 1
11
22
Present state
Nextstate
ab =00 G0 G0 G1 G1
01 G1 G1 H0 H0
10 G1 G1 H0 H0
11 H0 H0 H1 H1
Output s
G0 G1 H0 H1
0 1 0 1
23
Present state G0 G1 H0 H1
Nextstate ab =00 G0 G0 G1 G1 01 G1 G1 H0 H0 10 G1 G1 H0 H0 11 H0 H0 H1 H1
Output s 0 1 0 1
24
Y2
Q Q
y2
Clock Reset
25
26
r1 r2 r3
g1
Arbiter
g2 g3
clock
ECE 448 FPGA and ASIC Design with VHDL 27
gnt1g1 = 1 x0x
1xx gnt2g2 = 1 xx0 x1x gnt3g3 = 1 xx1
ECE 448 FPGA and ASIC Design with VHDL 28
01x
001
gnt1g1 = 1
r2 r1 gnt2g2 = 1 r3 r2 gnt3g3 = 1 r3
ECE 448 FPGA and ASIC Design with VHDL 29
r 1r 2
r 1r 2 r 3
30
32