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Sr. Engineer @ ARM Research Based in Cambridge, UK 4+ years at ARM
Before we start
Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
AMBA Family
AMBA-1 AMBA-2
AHB AMBA-3 AHB-Lite AMBA-4
Acronyms AMBA Advanced Microcontroller Bus Architectures AHB Advanced High-Performance Bus
Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
Master-Slave Architecture
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AHB-Lite
Master 0
Slave #1
Slave #2
Slave #3
Slave #4
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AHB-Lite transactions
Master Register Read Register Write Burst Read Burst Write Slave Can make Master wait Can give error response
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AHB-Lite Features
Single Clock Edge operation Uni-directional busses No tri-state signals Good for synthesis Pipelined Operation
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MEM CONTROLLER
AHB-Lite
VGA
UART
GPIO
PS2-KB
TIMER
7SEG
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MEM CONTROLLER
PSRAM (16MB)
AHB-Lite
VGA
UART
GPIO
PS2-KB
TIMER
7SEG
VGA
UART
PS2
7-SEG Display
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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
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AHB-Lite Master
Read Data
Global Signals
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AHB-Lite Slave
Slave Select
AHB-Lite Slave
Transfer Response
Read Data
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Transfer Response
Read Data
Global Signals
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SEL2
AHB-Lite Slave
SEL3
FF
MUX SEL
AHB-Lite Slave
MUX
Transfer Response, Rdata 2
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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
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Read Data
AHB-Lite Master
Global Signals
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AHB-Lite Slave
Read Data
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31
HSIZE[1:0]
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HTRANS[1:0]
HTRANS Type Description
00
01
IDLE
BUSY
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NON-SEQ
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SEQ
Transactions
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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
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HADDR [31:0]
HWRITE
HWDATA [31:0]
Data (A)
HREADY
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HADDR [31:0]
HWRITE
HRDATA [31:0]
Data (A)
HREADY
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OKAY A
OKAY B
HREADY
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Pipelined Operation
Address & Control Wdata Transfer Response AHB-Lite Master Read Data AHB-Lite Slave ADDR SEL1
SEL2
AHB-Lite Slave
FF
MUX SEL
AHB-Lite Slave
MUX
Transfer Response, Rdata 2
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HRESP
OKAY A
OKAY A
HREADY
AHB-Lite Slave 2
FF
MUX SEL
HREADYOUT 1
AHB-Lite Slave 3
HREADYOUT 2
MUX
HREADYOUT 3
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ERROR
It is permissible to continuously drive HRESP Low in a system which does not wish to generate any errors.
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ERROR Response
A+4
undef
HREADY
HRESP
ERROR
ERROR
If HRESP = ERROR, CM0-DS takes an exception and you should implement appropriate exception handler to catch the error
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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)
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Global Signal
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HCLK
HADDR HSEL_A HWRITE HTRANS HREADY
A NONSEQ B NONSEQ C NONSEQ
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HCLK
HADDR HSEL_A HWRITE HTRANS HREADY HWDATA
A B A NONSEQ B NONSEQ C NONSEQ
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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Advanced
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Shared Slave
Master 0 Master 1
Slave #1
Slave #2
Slave #4
Master 0 can access slaves #1, #2 & #3 Master 1 can access slaves #3 & #4 Contention occurs only if Master 0 & Master 1 try to access slave #3 sametime
Multi-layer
ARM DMA
Slave Mux
Slave Mux
Slave Mux
Slave Mux
Slave #1
Slave #2
Slave #3
Slave #4
Generalizing on previous slide Contention occurs only if Master 0 & Master 1 try to access same slave at same time
On-chip RAM
DMA Slave
UART
Timer
Master 0 can access private RAM, APB and external interface Master 1 can access DMA slave, APB and external interface
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Further Information
ARM IHI 0033 - AMBA 3 AHB-Lite Protocol Specification
http://infocenter.arm.com/
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THE END
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