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Seminar Agenda
Overview of ST Microcontroller Portfolio Introduction to Cortex-M Core STM32 General Purpose Lines
Product-Line Overview (F100/F101/F103) Walk through the main peripherals ST Standard Peripheral Library Live demonstration of the STM32 Value Discovery Kit Product-Line Overview (L15x) Low-Power modes and consumption Specific Peripherals Product-Line Overview (F105/7 & next) Ethernet & USB Host Peripherals Third Party Stacks Audio Support pp Product-Line Overview (W108) RF Performances Wireless Stacks (Zigbee, RF4CE, proprietary) Third Party Compiler & IDE Boards and Debuger ST Libraries
STM32 Wireless
STM32 Tools
** 256KB, 384KB, or 512KB Performance and Access devices *** 256KB, 384KB, or 512KB devices except Value line where present on all memory range
STM32F103/1RE STM32F103/1RE STM32F103/1RE STM32F100RE STM32F103/1RD STM32F100RD STM32F105/7RC STM32F103/1RC STM32F100RC STM32F105/7RB
STM32F103/1VE STM32F103/1VE STM32F103/1VE STM32F100VE STM32F103/1VD STM32F100VD STM32F105/7VC STM32F103/1VC STM32F100VC STM32F105/7VB STM32F103VB STM32F101VB STM32F105V8 STM32F103/1V8 STM32F100V8
STM32F103/1ZC STM32F100ZC
128 K
STM32F103/2/1CB STM32F100CB
64 K 32 K 16 K
STM32F103/1T8
STM32F103/2/1C8 STM32F100C8
STM32F103/1T6
STM32F103/2/1C6 STM32F100C6
CortexTM-M3 CPU
4- to 4 t 64-Kbyte 64 Kb t SRAM 6 lines Full compatibility across 115part numbers
STM32F103/1T4
STM32F103/2/1C4 STM32F100C4
36 pins i QFN
48 pins i LQFP
64 pins i LQFP/BGA(1)
General-purpose I/O
Fully configurable 18 MHz max toggle rate
Advanced timers
Multi-mode 16-bit timers Motor control timers* Watchdog and SysTick timers Real-time clock with battery backup
*Device dependant
System S t peripherals i h l
12-channel DMA controller* Flexible system memory controller (FSMC)*
*Device dependant
Advanced PLLs for single Xtal operation or core and a d pe peripherals p e as Accurate RC oscillator with trimming register Power-on reset Low-voltage detect (brown-out) Watchdog timers Tamper detect
Reset circuitry
I Integrated t t d low-voltage l lt regulator l t for f single i l 2.0 2 0 V to t 3.3 V operation Clock enable/disable for each peripheral
STM32 Seminar November 2010
<14 A
Run mode ~ 0.5 mA/MHz 0.27 mA/MHz peripheral off Startup time from stop <6 s Startup time from standby 50 s
3.4 A
Stop - All clocks off, reset active, RAM on (register content preserved)
Standby - All clocks off, reset active, RAM off but 20 bytes available for backup
FSMC ETM SDIO IS 12 channels DMA 2 PWM ti 2xPWM timers 3xADCs Up to 112 I/Os (144 pins package)
JTAG/SW Debug ETM
Nested vect IT Ctrl
CORTEXTM-M3 CPU
72 MHz
Power Supply
Reg 1.8V
Int. RC oscillators
40KHz + 8MHz
Bridge
Synchronized AC Timer
2 x 16-bit PWM
6 x 16-bit 16 bi Timer Ti
(ma ax 72MHz)
2 x Watchdog
(independent & window)
Temperature Sensor
2 x I2C
CORTEXTM-M3 CPU
36 MHz
Power Supply
Reg 1.8V
Int. RC oscillators
40KHz + 8MHz
2 x Watchdog
(independent & window)
2 x SPI 4 x USART/LIN
Smartcard / IrDa M d Modem C Control t l
Temperature Sensor
2 x I2C
STM32F10x XL Density
Fla ash I/F
up to 1MB Flash up to t 96KB RAM MPU (transparent for the user if not used) 6 additional timers RWW Flash
Power Supply
Reg 1.8V
Int. RC oscillators
40KHz + 8MHz
Bridge g
Synchronized AC Timer
2 x 16-bit PWM
10 x 16-bit Timer
(max 7 72MHz)
2 x Watchdog
(independent & window)
T Temperature t Sensor S
2 x I2C
24KB-32kB SRAM 84B Backup Data FSMC SRAM/ NOR/ LCD parallel interface Clock Control
ARM Peripheral Bus
JTAG/SW Debug
Nested Vect IT Ctrl
Int. RC oscillators
40KHz + 8MHz
Rich connectivity
11 communications peripherals
1 x Systick Timer
DMA
FSMC
SRAM, NOR, memories support. LCD Parallel interface 8/16-bit Intel 8080 and Motorola 68K
up to t 12 Ch Channels l
Bridge Bridge
(max 24MHz)
1 x 16-bit PWM
ARM P Peripheral Bus
Synchronized AC Timer
10 x 16-bit Timer
(ma ax 24MHz)
Enhanced control
16-bit motor control timer 10x 16-bit PWM timers
1 x CEC
2 x Watchdog
(independent & window)
4 x USART/LIN
2 x12-bit DAC
Smartcard / IrDa Modem Control
1 x 12-bit ADC
up to 16 channels
1 x USART/LIN
Smartcard/IrDa Modem Control
2 x SPI 2 x I2C
Temperature Sensor
From 16-Kbyte up to 512-Kbyte Flash From 48-pin to 144-pin packages Under $1 most accessible STM32
From $0 $0.85 85 (resale 10 Ku) for 16-Kbyte devices in LQFP48 package
FSMC IS
Interface to audio DAC for hi fi audio hi-fi di quality lit Parallel interface to graphic module
Audio for the user Voice and music SD card for software upgrade
SDI O
QVGA LCD
SD Wi-Fi card to home network
0xFFFF FFFF
Reserved
0xE000 0000
Boot Mode
Aliasing
BOOT0 0 1 1 User Flash User Flash is selected as boot space SystemMemory is selected as boot space Embedded SRAM is selected as boot space
0 1
Reserved
0x4000 0000
Peripherals
Reserved
0x0801 FFFF
SystemMemory: contains the Bootloader used to re-program the FLASH through USART1.
For more details refer to AN2606 & UM0462 A PC Windows Demonstrator is available as well.
Flash
0x0800 0000
0x2000 0000
SRAM
Reserved
0x0000 0000
CODE
Bit-Band region
Boot from SRAM : In the application initialization code you have to Relocate the Vector Table in SRAM using the NVIC Exception Table and Offset register
System Architecture - MD
Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
BusMatrix added to Harvard architecture allows parallel access
Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz toggling I/Os)
Flash I/F
I-bus
CORTEX-M3
D-bus
FLASH
Bu usMatrix x
Master 1
System
SRAM Slave
APB2 AHB
GPIOA,B,C,D,E - AFIO USART1- SPI1 - ADC1,2 TIM1 - EXTI USART2,3 - SPI2 - I2C1,2 TIM2,3,4 - IWDG WWDG USB CAN BKP PWR
APB1
Arbiter
Embedded FLASH
Access time: 35ns Halfword (16-bit) program time: 52.5 s (Typ) Page / Mass Erase Time: 20ms
InstructionsBUS
16 bits Thumb 32 bits Thumb-2
16 bits Thumb-2
32 bits Thumb-2
Thumb-2 64 b bits
32 bits
32 16 16 Bits Thumb-2
64 bit ts
ARRAY
32 bits Data 8 bit Data
16-bit Data
* The data (constant or literals ) are provided with the highest priority using the D-Bus.
CRC Features
CRC-based techniques are used to verify data transmission or storage integrity Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Single input/output 32-bit data register CRC computation p done in 4 AHB clock cycles y (HCLK) General-purpose 8-bit register (can be used for p p g ( temporary storage)
AHB Bus 32-bit (read access) Data register (Output)
DMA Features
7/12 independently configurable channels: hardware requests or software trigger on each channel. Software programmable priorities: Very high, High, Medium or Low. (Hardware priority in case of equality). Programmable and Independent source and destination transfer data size: Byte, Halfword or Word. 3 event flags for each channel: DMA Half Transfer Transfer, DMA Transfer complete and DMA Transfer Error. Memory-to-memory, y y, peripheral-to-memory, p p y, memory-to-peripheral y p p transfers and peripheral-to-peripheral transfers Faulty channel is automatically hardware disabled in case of bus access error Programmable number of data to be transferred: up to 65535. Support for circular buffer management
TIM3_CC4 SPI1_TX
TIM1_CC2 TIM3_UP
OR
OR
OR
OR
OR
OR
OR
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
Channel1
Channel2
Channel3
Channel4
Channel5
Channel6
Channel7
D DMA
DMA REQUEST
1 cycle
1 cycle
5 cycles
1 cycle
Address computation
Bus access
Acknowledgement phase
If source or destination is a peripheral on APB, Bus access will include more cycles due to the AHB/APB bridge latency and APB transfer duration, depending on the AHB/APB ratio.
9 9
APB AHB = 1:1 APB:AHB 1 1 -> + 2 cycles l APB:AHB = 1:2 -> + 3-4 cycles
9 9
If the CPU is running, the DMA access (AHB or APB) may be delayed by 1 bus cycle on each of the buses For RAM access, , any y read after write access takes 1 extra cycle y
9
Example: APB:AHB = 1:1 ,DMA APB->AHB transfer and CPU is only accessing RAM (no APB access) The maximum latency between 2 DMA accesses will be 12 cycles
RESET Sources
System RESET
Resets except R t all ll registers i t t some RCC registers and BKP domain Sources Low level on the NRST p pin (External Reset) WWDG end of count condition IWDG end of count condition A soft software (through are reset (thro gh NVIC) Low power management Reset
External RESET NRST
VDD
RPU
Filter
SYSTEM RESET WWDG RESET IWDG RESET Software RESET Power RESET Low power management RESET
P RESET Power
Resets all registers except BKP domain Sources Power On/Power down Reset (POR/PDR) When exiting STANDBY mode
On-Chip Oscillators
Multiple clock sources for full flexibility in RUN/Low Power modes
HSE (High Speed External oscillator): 4MHz to 16MHz main osc which can be multiplied by the PLL to frequencies t provide id a wide id range of ff i Can be bypassed with external clock HSI (High Speed Internal RC): factory trimmed internal RC oscillator 8MHz +/- 1% over 0-70C temp range
Feeds System clock after reset or exit from STOP mode for fast startup ( p time : 2us max) ) (startup Backup clock in case HSE osc is failing Note: When the HSI is used as a PLL clock input input, the maximum system clock frequency that can be achieved is 64 MHz.
LSI (Low Speed Internal RC): 40KHz internal RC for IWDG and optionally for the RTC used for Auto Wake-Up Wake Up (AWU) from STOP/STANDBY mode LSE (Low Speed External oscillator): 32.768kHz osc provides a precise time base with very low power consumption (max 1A). Optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode. Can be bypassed with external clock
Clock Scheme
System Clock (SYSCLK) sources RTC Clock (RTCCLK) sources
9 LSE 9 LSI 9 HSE clock divided by 128
9 HSI
9 HSE 9 PLL
USB Clock (USBCLK) provided from the internal PLL Clock-out capability p y on the MCO pin (PA.08) / max 50MHz
Clock Security System (CSS) to backup clock in case of HSE clock failure (HSI feeds the system clock)
Enabled by SW w/ interrupt capability linked to Cortex NMI
HCLK up to 72MHz PCLK1 up to 36MHz PLLCLK SYSCLK up to 72 MHz AHB Prescaler /1,2512 APB1 Prescaler /1,2,4,8,16
If (APB1 pres =1) Else
HSI RC
8MHz
TIMxCLK TIM2,3,4
PCLK2 up to 72MHz SYSCLK HSI MCO HSE /2 PLLCLK /128 OSC32_IN LSE OSc OSC32_OUT ADC Prescaler /2,4,6,8 USB Prescaler /1,1.5 ~40KHz 40KHz LSI RC IWDGCLK ADCCLK CSS APB2 Prescaler /1,2,4,8,16
If (APB2 pres =1) Else
x1 x2
TIM1CLK
32.768KHz
RTCCLK
USBCLK 48MHz
General G l Purpose P and d Alternate Alt t Function I/O (GPIO and AFIO)
62
GPIO Features
Up to 80 multifunction bi-directional I/O ports available: 80% IO ratio
Standard I/Os 5V tolerant The GPIOs can sink 25mA ( total currents sunk is 150mA ) 18 MHz Toggling Configurable Output Speed up to 50 MHz Up to 16 Analog Inputs Alternate Functions pins (like USARTx, TIMx, I2Cx, SPIx, CAN, USB) Up to 80 GPIOs can be set-up as external interrupt (up to 16 lines at time) One I/O can be used as Wake-Up from STANDBY (PA.00) One I/O can be set-up as Tamper Pin (PC.13) All Standard I/Os are shared in 5 ports (GPIOA..GPIOE) Atomic Bit Set and Bit Reset using BSRR and BRR registers Locking mechanism to avoid spurious write in the IO registers
When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the configuration of the port bit until the next reset (no write access to the CRL and CRH registers corresponding bit).
Analog Input
To On-chip Peripherals
Analog Input Input Floating (Reset State) Input Pull-Up 0 0
ON OFF
Read
1 0
1 0
TTL Schmitt Trigger Input Driver ON/OFF VSS VDD Output Driver
Pull - Down P
VDD or VDD_FT(1)
Write
1 1
VSS
OUTPUT CONTROL
VSS
(1)
VDD for standard I/Os and VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
I/O pin
RTC Features
Clock sources 32.768 kHz dedicated oscillator (LSE) Low frequency (40kHz), low power internal RC(LSI) HSE divided by 128 3 Event/Interrupt sources Second Overflow Alarm (also connected to EXTI Line 17 for Auto Wake-Up from STOP) Register protection against unwanted write operations RTC core & clock configuration in Backup domain Independent VBAT voltage supply Reset only by Backup domain reset up from STANDBY RTC config kept after reset or wake wake-up Calibration Capability RTC clock divided by 64 can be output on Tamper pin for calibration Then the clock can be adjusted from 0 to to 121ppm by a step of 1ppm Possibility to output the Alarm pulse or Second pulse on Tamper pin (even when the device is in STANDBY mode)
RTC Control Register (CR) RTC Counter RTC Divider RTC Alarm RTC Prescaler = fRTC
RTCSEL [1:0]
HSE OSC
Backup Domain
WWDG features
Configurable time-window, can be programmed to detect abnormally late or early application behavior Conditional reset
Reset (if watchdog activated) when the down counter value becomes less than 40h (T6=0) Reset (if watchdog activated) if the down counter is reloaded outside id the h time-window i i d
WWDG Reset eset WWDG_CFR comparator = 1 when T6:0 > W6:0 CM P Write WWDG_CR WDGA T6 T5 T4 T3 T2 T1 T0 W6 W5 W4 W3 W2 W1 W0
To prevent WWDG reset: write T[6:0] bits (with T6 equal to 1) at regular intervals while the counter value is lower than the time-window value ( (W[6:0]) [ ]) Early Wakeup Interrupt (EWI): occurs whenever the counter reaches 40h can be used to reload the down counter WWDG reset flag (in RCC_CSR) to inform when a WWDG reset occurs Min-max timeout value @36MHz (PCLK1): 113s / 58.25ms
WWDG_CR
PRESCALER (WDGTB)
W[6:0] 3Fh
Refresh Window
time
Best suited to applications which require the watchdog to react within an accurate timing window
T6 bit Reset
IWDG features
Selectable HW/SW start through option byte Advanced security features:
IWDG clocked l k db by it its own dedicated d di t d low-speed l d clock l k (LSI) and thus stays active even if the main clock fails Once enabled the IWDG cant be disabled (LSI cant be disabled too) S f Reload Safe R l d Sequence S (k ) (key) IWDG function implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY)
12-bit reload value LSI (40KHz) 8-bit PRESCALER 12-bit down counter
VDD voltage domain 1.8V voltage domain
Prescaler Register
Status Register
Reload Register
Key Register
To prevent IWDG reset: write IWDG_KR with AAAAh key value at regular intervals before the counter reaches 0 CSR) to inform when a IWDG reset flag (in RCC RCC_CSR) IWDG reset occurs Min-max timeout value @40KHz (LSI): 100s / 26.2s
IWDG Reset
Best suited to applications which require the watchdog to run as a totally independent process outside the main application
conversion time at 56 MHz ( y X*14Mhz) ) 1s (or any 1.17s conversion time at 72 MHz
Conversion range: 0 to 3.6 V 2 4V to 3.6 36V ADC supply requirement: 2.4V ADC input range: VREF- VIN VREF+ (VREF+ and VREF- available only in LQFP100
package)
Dual mode (on devices with 2 ADCs): 8 conversion mode Up to 18 multiplexed channels:
16 external channels 2 internal channels: connected to Temperature sensor and internal reference voltage (VREFINT = 1.2V)
ADCCLK
PCLK2
ADC_IN0 ADC_IN1
. . .
ADC_IN15
Injected Channels
Up to 16
Regular Channels
End of conversion
Analog Watchdog
TIM1_TRGO TIM1_CC4 TIM1_TRGO CC1 TIM2_CC TIM3_CC4 TIM4_TRGO Ext_IT_15 JEXTSEL[2:0] bits JEXTRIG bit Start Trigger (injected group)
AWD
EOC
JEOC
Flags
AWDIE
TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 Ext_IT_11 EXTSEL[2:0] bits EXTRIG bit Start Trigger (regular group)
EOCIE JEOCIE
ADC
1.5 cycles 7.5 cycles Sa ample Time Selectio on 13.5 cycles
ADCCLK
28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles 239.5 cycles
SMPx[2:0]
Sequencer
Up to 16 conversions with different order, different sampling time and d oversampling li possibility. ibili
Example: - Conversion of channels: 1, 2, 8, 4, 7, 3 and 11 - Different sampling time. - Oversampling of channel 7.
Channel1
Channel2
Channel8
Channel4
Channel7
Channel7
Channel7
Channel3
Channel11
1.5 cycles
13.5 cycles
7.5 cycles
7.5 cycles
71.5 cycles
28.5 cycles
1.5 cycles
CHx Start
Stop
CHx
. . .
CHx
. . .
CHn
CHn
Stop
Example: - Conversion of channels: 0 0, 1 1, 2 2, 4 4, 5 5, 8 8, 9 9, 11 11, 12 12, 13 13, 14 and 15 - Discontinuous mode - Number of channel is 3
1st trigger gg
2nd trigger gg
3rd trigger gg
Channel0
Channel1
Channel2
Channel4
Channel5
Channel8
Channel9
Channel11
Channel12
4th trigger
h trigger 5th
Note: Do not use discontinuous mode for both Channel13 Channel14 Channel15 Channel0 Channel1 Channel2 regular and injected together. It can be used only for one group channel
End of Conversion
ADC_IN0 ADC_IN1
. . .
ADC_IN15
Analog Watchdog
Low Threshold High Threshold
AWD
Status Register
DMA
DMA available only on ADC1 DMA request generated on each ADC1 end of regular channel conversion (Not in injected channels)
DMA Request Channel0 Channel1 DMA Request Channel2 DMA Request Channel3 DMA Request Channel4 DMA Request Channel5 DMA Request Channel6 DMA Request Channel7 DMA Request Channel8 DMA Request
ConvertedValue_Tab[9]
Channel8 conversion result Channel7 conversion result Channel6 conversion result
Example: - Conversion of regular channels: 0, 1, 2, 3, 4, 5, 6, 7 and 8 - Converte data stored in ConvertedValue_Tab[9] - DMA transfer enabled (destination address auto incremented)
ADC1 DR register
. . .
Channel5 conversion result Channel4 conversion result Channel3 conversion result Channel2 conversion result Channel1 conversion result Channel0 conversion result
Note: EOC flag cleared at end of regular channels conversion due to DMA access to ADC1 DR register
Up to 4 injected channels
VREFINT
GPIO Ports
ANALOG MUX
Up to 16 regular channels
ADC1 Analog
External event (Regular group) External event synchronization
ADC2 Analog
Data register
Digital g ta S Slave a e
EOC/JEOC
Features overview
General Purpose Feature 16-bit Counter
Auto Reload Up down and centered counting Up, modes Programmable direction of the channel: Output Compare: Toggle, PWM Input Capture PWM Input Capture input/output
ETR
Clock ITR 1 ITR 2 ITR 3 ITR 4
Trigger/Clock Controller
Trigger Output
BKIN
Counter Modes
There are three counter modes:
9 Up counting mode 9 Down counting D ti mode d 9 Center-aligned mode
Up counting
Down counting
UEV
RCR = 2
UEV
105
Trigger Controller
0xD7
M t Master
SCK MISO MOSI NSS
8-bit long g
0xD7
VDD
0xD739
Master
SCK MISO MOSI NSS SS VDD NSS SCK MISO MOSI
Slave
Full Duplex
Simplex Communication
SPI supports simplex communication mode:
Bidirectional: 1 Clock and 1 bi-directional data wire (One
control)
Rx-Only: 1 Clock and 1 unidirectional data wire Tx-Only
Master
SCK MISO MOSI NSS SCK MISO MOSI VDD NSS
Slave
Master
SCK MISO MOSI NSS VDD NSS SCK MISO MOSI
Slave
BiBi -directional
Rx Only (Slave)
Slave
Slave
Both Master and Slave NSS pins i could ld b be used df for other th purpose
dynamic change of
SCK MISOMOSI NSS
Master/Slave operations: No hardware limitation to switch from master to slave or slave to t master t in i the th same application
Master
Master
Slave
Slave
Each device can be a unique master by enabling its NSS as output and driving it low: all
SCK MISOMOSI NSS
Master
Slave
VDD
Master
SDA SCL SDA SCL
Slave
Slave address 1 Slave address 2
Up to 4 4.5 5 Mbps
Support pp hardware flow control ( (CTS and RTS) ) Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability S Support t for f DMA
Receive DMA request Transmit DMA request q
Synchronous Mode
USART supports Full duplex synchronous communication mode
Full-duplex, F ll d ple three three-wire ire s synchronous nchrono s transfer USART Master mode only Programmable clock polarity (CPOL) and phase (CPHA) Programmable Last Bit Clock generation Transmitter Clock output (SCLK)
Master
SCLK Rx Tx SCK MISO MOSI NSS
Slave
USART
Full Duplex
SPI
USART
SIR Transmit Encoder
Tx/ SW_Rx
IrDA OUT
USART Tx
Half Duplex
USART
Tx
SCLK
USART1 Tx
USART2 Tx
Half Duplex
Transmission
Three transmit mailboxes Configurable transmit priority Time Stamp on SOF transmission
Reception
Two receive FIFOs with three stages 14 scalable filter banks
Identifier list features
USB Features
Full speed USB 2 2.0 0 transfer (certified on USB USB.org). org) Configurable endpoints transfer mode type: control, bulk, interrupt and Isochronous. Configurable number of endpoints: up to 8 bidirectional endpoints and 16 monodirectional endpoints. USB suspend/resume support. Dedicated SRAM Area (Packet Memory Area) up to 512bytes (shared with bxCAN). Dynamic buffer allocation according to the user needs. transfers Special double buffer support for Isochronous and Bulk transfers.
PMA
Endpointx Buff 1
USB IP
Endpointx Buff 0
CPU
New IPs
SDIO I2S2 and I2S3 (multiplexed with SPI2 and SPI3) DAC FSMC
Flash I/F
Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators 32KHz + 4~16MHz Int. RC oscillators 40KHz + 8MHz PLL
Up to 64kB SRAM
SRAM/NOR/NAND/ PC C Cards d
FSMC
84B Backup data Reset Clock Control CRC ARM Peripheral Bus Bridge (max 36MHz) 1x bxCAN 2.0B 6 x 16-bit Timer 4x USART/LIN Smartcard / IrDa Modem Control 2x SPI/I2S 2x I2C 12-bit DAC Temp Sensor 2 channels 1x USB 2.0FS RTC / AWU
2 x 1616-bit PWM
Synchronized AC Timer
Bridge
(m max 72MHz)
174
FSMC Features
4 Banks to support External memory FSMC external access frequency is 36MHz when HCLK is at 72MHz Independent chip select control for each memory bank Independent configuration for each memory bank Interfaces with static memory-mapped devices including:
static random access memory (SRAM) read-only memory (ROM) NOR Flash memory PSRAM
Interfaces parallel LCD modules: Intel 8080 and Motorola 6800 Interfaces with Cellular RAM and COSMO RAM, both synchronous and asynchronous random accesses NAND Flash and 16-bit PC Cards
With ECC hardware up to 8 Kbyte for NAND memory 3 possible interrupt sources (Level, Rising edge and falling edge)
Programmable timings to support a wide range of f devices External asynchronous wait control Code execution only from external SRAM or NOR Flash
NOR Signals
Shared Signals
AHB Bus
Configuration g Registers NAND Signals NAND/PC Card Memory y Controller PC Card Signals
Bank 2 256 MB
0x7FFF FFFF 0x8000 0000
Bank 4 256 MB
PC Card
0x9FFF FFFF
FSMC_NE[4:1] LCD /CS FSMC_Ax LCD RS LCD D[15:0] LCD /RD LCD /WR
LCD /RD: The ready signal indicates to the 8080 that valid memory or input data is available on the 8080 data bus. LCD /WR: The /WR signal is used for memory write or I/O output control. The data on the data bus is stable while the /WR is active low (/WR = 0). LCD RS: RAM Data/ Register Data Selection LCD /CS: Chip Select LCD D[0:15]: D[0 15] Bidirectional Bidi ti l data d t bus b
NOR/SRA M Bank
DAC Features
Two DAC converters: one output channel for each one 8-bit or 12-bit monotonic output Left or right data alignement in 12-bit mode Synchronized update capability Noise-wave or Triangular-wave generation Dual DAC channel independent or simultaneous conversions DMA capability for each channel External triggers for conversion DAC supply 2.4V to 3.6 V pp y requirement: q Conversion range: 0 to 3.6 V DAC outputs range: 0 DAC_OUTx VREF+ (VREF+ and VREF- available only in 100
SWTRIGx
Mask Amplitude
DHRx
LFSRx
Trianglex
12 bits
DORx
12 bits
SDIO interface
Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1 Rev1.1) 1) Data transfer up to 48 MHz
AHB Interface
SDIO Adapter
SDIO_D[7:0]
AHB Bus
HCLK/2
SDIOCLK (HCLK)
SDIO Adapter
The SDIO adapter: bus master that p provides an interface to a multimedia card stack or to a secure digital memory card.
Adapter register block: contains all t i t SDIO system registers . Control unit: contains the power management functions and the clock divider for the memory card clock. Adapter Registers g
SDIO_CK
SDIO_CMD
Command path: sends commands to and receives responses from the d I l t command d cards. Implement transmission state machine Data path: transfers data to and from cards. Implement p data transmission state machine
AHB Bus
SDIO_D[7:0]
FIFO
HCLK/2
SDIOCLK (HCLK)
Data FIFO: contains a 32-bit wide, 32word deep data buffer, and transmit and receive logic logic.
SDIO SDIO_CMD
SDIO_CK SDIO_D0 SDIO D1 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_D4 SDIO_D5 SDIO_D6 SDIO_D7
7 6 5 4 3 2 1 11 10 9 8 13 12
CE-ATA Devices
1
SDIO SDIO_CMD
SDIO_CK SDIO D0 SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_D4 SDIO_D5 SDIO_D6 SDIO_D7 _
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C CE-ATA A
Master clock may be output to drive an external audio component. Ratio is fixed at 256xFs (where Fs i is th the audio frequency). 256 F ( h F di sampling li f ) Support for DMA (16-bit wide).
230
I2S
CK SD WS
Application Note is available from www.st.com/mcu AN2739: Using high-density STM32F103xx to play audio files with an external IS audio codec
I2S
CK (SCK) SD (MISO) WS (NSS) MCLK *
0xD7 WS
0xD739 WS
232
Simplex Communication
I2S supports t only l simplex i l communication i ti mode d :
Simplex, three-wire synchronous audio transfer
I2C controls t l *
The Th master t and d slave l configuration is managed only y by y software. The master device is the CK and WS generator.
STM32F10x
CK SD WS ** MCLK
Audio Codec
SD WS MCLK Digital Interface e Analog Interfac ce CK
The master/slave modes and transmit/receive directions can be switched dynamically y y by y software.
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DSP library PID, IIR, FFT, FIR (free with license agreement)
Free USB device library from ST: ANSI-C source code available, supporting many USB classes (mass storage, HID, DFU, CDC, audio)
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Application code
User library configuration g
To be modified in project
stm32f10x_conf.h
Include this file to your application files
API layer
stm32f10x.h
STM32 HW W
HW Peripherals registers(PPP)
Most of the settings is in 1fromN convention and allow to use concatenation, like:
GPIO_Pin_0 | GPIO_Pin_1, what means that pins 0 and 1 from will be configured in the same time
STM32 Discovery-kit
Development Toolchain support
ECLIPSE Dev Tools : Free Atollic TrueSTUDIO lite version with unlimited code-size and usage-time. IAR EWARM KEIL MDK-ARM
Price: $9.90
Large number of software examples available at www.st.com/stm32-discovery for a quick start to evaluate and p with the STM32 Value line develop
STM32 Seminar November 2010
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84mm
Two User LEDs (Green and Blue) One user Push Button Extension E i h header d f for all ll QFP64 I/O I/Os for quick connection to prototyping board or easy probing
User button Led Blue Led Green
42mm
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Thank You !
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