A

MYALL Block Diagram

CLK GEN.

Mobile CPU

IDT CV125

Dothan
3

400MHz

400 MHz

RGB
LVDS

400 MHz

Int.
MIC In

27

34
INPUTS

LCD

OUTPUTS
VCC_CORE

24,25

24,25

DMI I/F

Codec

DCBATOUT

VRAMx4

Nvidia
G72M-V

6,7,8,9,10

11,12

Mic In

ISL6218CV-T

13

400MHz

0.844~1.3V
27A

SYSTEM DC/DC
TPS51120 35

100MHz

Azalia

PCI BUS

ALC861

INPUTS

ENE
CB1410

DCBATOUT

PWR SW

25

24,25

27

PCMCIA

CP2211

26

CPU DC/DC
14

www.kythuatvitinh.com

DDR II
Line In27

CRT

400MHz

Intel 910GM (UMA)

Intel 915PM (DIS)

11,12

Project Code: 91.4G501.001

PCB: 05244-Rev.

19

4, 5

HOST BUS

DDR II

(Ref. rename from 12/6)

G792

OUTPUTS
3D3V_S5
5V_S5

APL5912-LAC
APL5308-25AC
36
INPUTS
OUTPUTS

ONE SLOT
25

Line Out

5V_S5

1D5V_S0

3D3V_S0

2D5V_S0

27

INT.SPKR

Mini-PCI

ICH6-M

OP AMP

802.11A/B/G

LAN
10/100

G1421B 27

27

SYSTEM DC/DC
ISL6227
INPUTS

TXFM

RTL8110CL

23

22, 23

MODEM
MDC Card

28

RJ4523

5V_S5
DCBATOUT
3D3V_S3

PCIE X1

TPS51100DGQ

PCI MINI CARD

25

21

DDR_VREF_S3

CHARGER
ISL6255

15,16,17,18

Golden
Finger

USB

L1: Signal 1
L2:VCC
L3: Signal 2
L4: Signal 3
L5: GND
L6: Signal 4

USB

SATA
24,25

HDD

CDROM

20

20

37

5V_S5

SATA

PATA

DDR_VREF

LPC BUS

PCB Layer Stackup

37

OUTPUTS

KBC

Xbus

INPUTS

512 K

OUTPUTS

PM39LV040-70JCE

ENE KB3910

30

BIOS ROM

38

29

31

DCBATOUT

5 PORT

BT+
16.8V

3A

21
<Core Design>
1

21

SATA

Touch
Pad 30

MINI USB
BlueTooth

24,25

(co-lay)

INT_KB
30

LED BDx1
(another circuit)

Wistron
Corporation
Digitally
signed by dd
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DN: cn=dd, o=dd, ou
Title
BLOCK DIAGRAM email=dddd@yahoo.
Size
Document Number
Rev
c=US
Custom
SA
MYALL Date: 2009.11.29
07:5
Date: Friday, February 10, 2006
Sheet
1
52
of
+07'00'
E

Alviso Strapping Signals

and Configuration
Pin Name

ICH6-M Integrated Pull-up

and Pull-down Resistors ICH6-M

page 7

EDS 14308

0.8V1

Configuration

Strap Description

ACZ_BIT_CLK, DPRSLP#, EE_DIN,

CFG[2:0]

CFG[3:4]

Reversed

CFG5

DMI x2 Select

CFG6

DDR I / DDR II

CFG7

CPU Strap

CFG[8:11]

Reversed

CFG[12:13]

XOR/ALL Z test
straps

CFG[14:15]
CFG16

CFG17
CFG18

FSB Frequency Select

CFG19
CFG20

000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed

EE_DOUT, GNT[5]#/GPO[17],
ICH6 internal 20K pull-ups
GNT[6]#/GPO[16], LDRQ[1]/GPI[41],

LAD[3:0]#/FB[3:0]#, LDRQ[0],
0
1
0
1

=
=
=
=

DMI
DMI
DDR
DDR

x2
x4
II
I

PME#, PWRBTN#, TP[3]

(Default)

0 = Prescott
1 = Dothan (Default)

LAN_RXD[2:0]

ICH6 internal 10K pull-ups

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,

ICH6 internal 20K pull-downs

ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)

SPKR, EE_CS,
USB[7:0][P,N]

ICH6 internal 15K pull-downs

www.kythuatvitinh.com
Reversed

FSB Dynamic ODT

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled
(Default)

DD[7], SDDREQ

ICH6 internal 11.5K pull-downs

LAN_CLK

ICH6 internal 100K pull-downs

Reversed

CPU core VCC

Select

0 = 1.05V (Default)
1 = 1.5V

CPU VTT Select

0 = 1.05V (Default)
1 = 1.2V

Reversed

ICH6-M IDE Integrated Series

Termination Resistors

PCI Routing

DD[15:0], DIOW#, DIOR#, DREQ,

SDVOCRTL
_DATA

SDVO Present

0 = No SDVO device present

(Default)
1= SDVO device present

NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.

IDSEL

IRQ

REQ/GNT

1410

25

B.F.G

MiniPCI

21

LAN

23

approximately 33 ohm

DDACK#,

IORDY, DA[2:0], DCS1#,

DCS3#, IDEIRQ

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Memo
Size
A3

Document Number

Date: Friday, February 10, 2006

Rev

SA

MYALL
Sheet

of

52

1 R436

MYALL SC

29
24
22
16

SCD1U16V2ZY-2GP

1
2

1
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1
2

2
1
SRN33J-5-GP-U
U58

2 33R2J-2-GP

MYALL SB

8
7
6
5

PCLK_KBC
PCLK_PCM
PCLK_LAN
CLK_ICHPCI

PCLK_MINI_1
PCLK_KBC_1
PCLK_PCM_1
PCLK_LAN_1

1
2
3
4

56
3
4
5

H/L: 100/96MHz

SS_SEL

RN79
SRN33J-4-GP

FS_A

9
8

ITP_EN

H/L : CPU_ITP/SRC7

<2nd>

LVDS
LVDS#

17
18

SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#

19
20
22
23
24
25
26
27
31
30
33
32

CPU2_ITP/SRC7
CPU2_ITP#/SRC7#

36
35

CPU0
CPU0#
CPU1
CPU1#

44
43
41
40

CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA

54
53
16
12

PCI0
PCI1
PCI2
PCI3

PCI_STOP#

46
47

SCL
SDA

RN73 SRN33J-5-GP-U
DREFCLK_1
2
DREFCLK#_1
1

14
15

DOT96
DOT96#

XTAL_IN
XTAL_OUT

50
49

XTAL_IN
XTAL_OUT

52
39

REF
IREF

10

VTT_PWRGD#/PD

11,18 SMBC_ICH
11,18 SMBD_ICH

3
4

7 DREFCLK
7 DREFCLK#

SC22P50V2JN-4GP

C571
1
2

16 CLK_ICH14
X4
X-14D31818M-31GP

SC MYALL

FS_C

FS_B

FS_A

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CPU

R520
1

R402

2 33R2J-2-GP
2
475R2F-L1-GP

VTT_PWRGD#

C568
SC27P50V2JN-2-GP

266M
133M
200M
166M
333M
100M
400M
Reserved

CLK_ICH14 & CLK14_SIO

need equal length

PCIF1/SEL100/96#
PCIF0/ITP_EN

55

16 PM_STPPCI#

CPU_SEL1 7
CPU_SEL0 4,7

C558

DREFSSCLK1
DREFSSCLK#1

3
4

DREFSSCLK 7
DREFSSCLK# 7

RN74
2
1

RN75

CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#

3
4

CLK_PCIE_MINI1 25
CLK_PCIE_MINI1# 25

SRN33J-5-GP-U

RN76

www.kythuatvitinh.com
1KR2J-1-GP

C555

2 33R2J-2-GP

R400 1

28 PCLK_MINI

DY
R401

R427
1KR2J-1-GP

C556

? CHECK
31 PCLK_FWH

R438
1KR2J-1-GP

C574

OUT
(VTT_PWRGD#)
H
Hi - Z

1D05V_S0

3D3V_CLKGEN_S0

SCD1U16V2ZY-2GP

1 R411
2
0R0603-PAD
C580

C591

SCD1U16V2ZY-2GP

SC4D7U10V5ZY-3GP

EN
(6218_PGOOD)
L

3D3V_48MPWR_S0

C557

C565

IN
(3D3V_S0)
H

3D3V_S0

1 R444
2
2R3J-2-GP

SC4D7U6D3V3KX-GP

3D3V_APWR_S0

SC10U10V5ZY-1GP

3D3V_S0

1 R408
2
0R0603-PAD

3D3V_S0

2
6

VSS_PCI
VSS_PCI

VDD_SRC
VDD_SRC

34
21

51
45
38
13
29

VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC

VDD_PCI
VDD_PCI

7
1

VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC

48
42
37
11
28

3D3V_S0

2
1

3
4
SRN33J-5-GP-U

CLK_PCIE_PEG 42
CLK_PCIE_PEG# 42

RN77

CLK_SRCT3
CLK_SRCN3
CLK_SRCT4
CLK_SRCN4
CLK_PCIE_ICH1
CLK_PCIE_ICH#1
CLK_MCH_3GPLL1
CLK_MCH_3GPLL#1

2
1

RN72

CPU_SEL0
CPU_SEL1
FS_A

CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15

4 SRN33J-5-GP-U
3

1
2

RN71 1
2

CLK_CPU_BCLK1
CLK_CPU_BCLK#1
CLK_MCH_BCLK1
CLK_MCH_BCLK#1

3
4
SRN33J-5-GP-U

4
3

CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

SRN47J-7-GP

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

RN69

1
2

4 SRN33J-5-GP-U
3

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

RN70

1
2

4 SRN33J-5-GP-U
3

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16,34

R437
1
22R2J-2-GP

CLK48_ICH 16

3D3V_CLKGEN_S0
RN82
CLK_PCIE_MINI1#
CLK_PCIE_MINI1

1
2
SRN49D9F-GP

4
3
RN84

CLK_PCIE_SATA#
CLK_PCIE_SATA

3D3V_APWR_S0
3D3V_48MPWR_S0

1
2

CLK_PCIE_PEG#
CLK_PCIE_PEG

IDTCV125PAG-GP

1
2

4
3
SRN49D9F-GP
RN83
4
3

8
7
6
5

SRN49D9F-GP

SB

1
2
3
4

RN78
SRN10KJ-4-GP

CLK_CPU_BCLK
CLK_CPU_BCLK#

RN66 1
2

4 SRN49D9F-GP
3

CLK_MCH_BCLK
CLK_MCH_BCLK#

RN67 1
2

4 SRN49D9F-GP
3

Delete EMI CAP(EC1-EC6) by EMI request

2
S

R434
10KR2J-2-GP

1
G

2N7002PT-U

32,34 6218_PGOOD

RN64 1
2

4 SRN49D9F-GP
3

DY

CLK_PCIE_ICH
CLK_PCIE_ICH#

RN65 1
2

4 SRN49D9F-GP
3

R435
10KR2J-2-GP

DY
Q33

CLK_MCH_3GPLL
CLK_MCH_3GPLL#
ITP_EN
SS_SEL

VTT_PWRGD#

<Core Design>
DREFSSCLK
DREFSSCLK#

RN81

DREFCLK
DREFCLK#
RN80

2
1

3
4

2
1

3
4

Wistron Corporation

SRN49D9F-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Clock Generator - IDT125

SRN49D9F-GP
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet

of

52

U31A
BGA479-SKT6-GPU1

6 H_ADSTB#0
6 H_REQ#[4..0]

H_REQ#0 R2
H_REQ#1 P3
H_REQ#2 T2
H_REQ#3 P1
H_REQ#4 T1

TPAD28

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

TP36
1D05V_S0

ADS#
BNR#
BPRI#

N2
L1
J3

H_ADS# 6
H_BNR# 6
H_BPRI# 6

DEFER#
DRDY#
DBSY#

L4
H2
M2

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

BR0#

N4

H_BREQ#0 6

IERR#
INIT#

A4
B5

LOCK#

J2

R95
56R2J-4-GP

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0

H_INIT# 15

B11
H1
K1
L2
M3

RESET#
RS0#
RS1#
RS2#
TRDY#

Place testpoint on
H_IERR# with a GND
0.1" away

H_IERR#

H_LOCK# 6
H_CPURST# 6
H_RS#[2..0]

H_RS#0
H_RS#1
H_RS#2

6
U31B
BGA479-SKT6-GPU1

H_D#[63..0]

www.kythuatvitinh.com
C2
D3
A3

A20M#
FERR#
IGNNE#

15
15
15
15

C6
D1
D4
B4

STPCLK#
LINT0
LINT1
SMI#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

62.10079.001
<connector>

H_HIT# 6
H_HITM# 6

BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28

TP18
TP23
TP20
TP26
TP19
TP22

PROCHOT#
THERMDA
THERMDC

B17
B18
A18

CPU_PROCHOT#

THERMTRIP#

C17

PM_THRMTRIP-I# 7,15,19

ITP_CLK1
ITP_CLK0
BCLK1
BCLK0

A15
A16
B14
B15

CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3

H_THERMDA 19
H_THERMDC 19

PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)

<CHANGE>

MYALL SB

To V-CORE SWITCH
0R3-0-U-GP1 R98

3,7 CPU_SEL0
1D05V_S0

TP25

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#

Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#16
H23
H_D#17
G25
H_D#18
L23
H_D#19
M26
H_D#20
H24
H_D#21
F25
H_D#22
G24
H_D#23
J23
H_D#24
M23
H_D#25
J25
H_D#26
L26
H_D#27
N24
H_D#28
M25
H_D#29
H26
H_D#30
N25
H_D#31
K25
H_DSTBN#1 K24
H_DSTBP#1 L24
H_DINV#1
J26

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#

AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

TP33
TPAD28

E1
C16
C14

TPAD28

1
XDP_TDI

2 150R2F-1-GP

R93

R100 1

2 39D2R3F-GP

XDP_TDO

R92

2 54D9R2F-L1-GP

H_CPURST#

R89

2 54D9R2F-L1-GP

XDP_DBRESET# R94

2 150R2F-1-GP

XDP_TCK

1 R99

2 27D4R2F-L1-GP

R360
2KR3F-L-GP

TP28
TP47
TP41
TP97

C3
AF7
AC1
E26

TPAD28
TPAD28
TPAD28
TPAD28
GTLREF0

3D3V_S0

R91

XDP_TRST#

All place within 2" to CPU

AD26

RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0

Layout Note:
0.5" max length.

COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#

G1
B7
C19
E4
A6

TEST1
TEST2

C5
F23

COMP0
COMP1
COMP2
COMP3

R121
R124
R140
R141

H_DSTBN#[3..0]

H_DSTBP#[3..0]

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

1D05V_S0

1
1
1
1

2
2
2
2

27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP

H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6

R96
200R2F-L-GP

H_PWRGD 15,19
H_CPUSLP# 6,15
TEST1
TEST2

TPAD28 TP27
TPAD28 TP34

BSEL[1:0] Freq.(MHz)
(A Stepping)
LL
100
LH
133
BSEL[1:0] Freq.(MHz)
(B Stepping)
LH
100
LL
133

<Core Design>

Wistron Corporation

680R2F-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (1 of 2)
Size
A3

Document Number

Date: Friday, February 10, 2006

A

62.10079.001
<connector>
<CHANGE>

XDP_TMS

R358
1KR2F-3-GP

1 2

2 56R2F-1-GP

BSEL0
BSEL1

MISC

1D05V_S0

CPU_PROCHOT# R90

PSI#

P25
P26
AB2
AB1

H_DINV#[3..0]

15 H_A20M#
15 H_FERR#
15 H_IGNNE#

K3
K4

HIT#
HITM#

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25

DATA GRP 0
DATA GRP 2

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1

H_TRDY# 6

6 H_ADSTB#1

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

DATA GRP 1
DATA GRP 3

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

ADDR GROUP 1
XTP/ITP SIGNALS

P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3

CONTROL

6 H_A#[31..3]

HCLK THERM

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

ADDR GROUP 0

Rev

MYALL

SA
Sheet
E

of

52

VCC_CORE_S0

U31D
A2
A5
A8
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11

VCC_CORE_S0
U31C
BGA479-SKT6-GPU1

F26
B1
N1
AC26

VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21

C416
SCD01U16V2KX-3GP

VCCA0
VCCA1
VCCA2
VCCA3

1D5V_S0

C417
SC10U10V5ZY-1GP

G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6

VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

1D05V_S0

VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5

P23
W4
E2
F2
F3
G3
G4
H4

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

34
34
34
34
34
34

TC9

DY

ST100U6D3VBM-9GP

1
2

C164
SCD1U16V2ZY-2GP

1
2

C159
SCD1U16V2ZY-2GP

62.10079.001
<connector>
<CHANGE>

C190
SCD1U16V2ZY-2GP

TPAD28 TP48

TP_VSSSENSE

AF6

C202
SCD1U16V2ZY-2GP

VSSSENSE

TPAD28 TP44

TP_VCCSENSE

AE7

C203
SCD1U16V2ZY-2GP

1D05V_S0

VCCSENSE

1
2

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24

VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

www.kythuatvitinh.com
C199
SCD1U16V2ZY-2GP

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58

AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21

BGA479-SKT6-GPU1

Layout Note:

1
2

C423
SC10U6D3V5KX-1GP

1
2

C444
SC10U6D3V5KX-1GP

C421
SC10U6D3V5KX-1GP

C420
SC10U6D3V5KX-1GP

1
2

1
2

1
2

C445
SC10U6D3V5KX-1GP

DY

C422
SC10U6D3V5KX-1GP

C211
SCD1U16V2ZY-2GP

DY

1
2

1
2

DY

C155
SCD1U16V2ZY-2GP

DY

C158
SCD1U16V2ZY-2GP

C212
SCD1U16V2ZY-2GP

DY
1

C443
SC10U6D3V5KX-1GP

2
VCC_CORE_S0

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

VCC_CORE_S0

C210
SCD1U16V2ZY-2GP

VCCSENSE and VSSSENSE lines

should be of equal length.

C442
SC10U6D3V5KX-1GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (2 of 2)
Document Number

Date: Friday, February 10, 2006

B

<CHANGE>

Wistron Corporation

Size
A3
A

<connector>
62.10079.001

<Core Design>

VCC_CORE_S0

Rev

MYALL

SA
Sheet
E

of

52

H_XRCOMP

R351
24D9R2F-L-GP

U35A

4 H_D#[63..0]
4

1D05V_S0

54D9R2F-L1-GP
R349

H_XSCOMP

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

C1
C2
D1
T1
L1
P1

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCPURST#

F8
B9
E13
J11
A5
D5
E7
H10

HCLKINN
HCLKINP

AB1
AB2

HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

www.kythuatvitinh.com
1

H_YRCOMP

R369
24D9R2F-L-GP

1D05V_S0

54D9R2F-L1-GP
R363

H_YSCOMP
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

1D05V_S0

1
1

H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4

CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#

R155
200R2F-L-GP

H_VREF

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4

H_DBSY# 4
H_DEFER# 4

H_DINV#[3..0]

H_DPWR# 4
H_DRDY# 4

H_DSTBN#[3..0]

H_DSTBP#[3..0]

TPAD28 TP42
H_HIT# 4
H_HITM# 4
H_LOCK# 4

TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2

TPAD28 TP37

H_REQ#[4..0]

H_RS#[2..0]

H_CPUSLP# 4,15
H_TRDY# 4

H_YSWING

R367
221R2F-2-GP

R153
100R2F-L1-GP-U

C460
SCD1U16V2ZY-2GP

R355
100R2F-L1-GP-U

H_XSWING

1D05V_S0

C218
SCD1U16V2ZY-2GP

R354
221R2F-2-GP

HOST

1D05V_S0

H_A#[31..3]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

71.0GMCH.08U
C487
SCD1U16V2ZY-2GP

R366
100R2F-L1-GP-U

<Core Design>

Place them near to the chip

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (1 of 5)
Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet
E

of

52

1D05V_S0

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

16
16
16
16

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

16
16
16
16

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

Y31
AA35
AB31
AC35

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AA33
AB37
AC33
AD37

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

Y33
AA37
AB33
AC37

DMITXP0
DMITXP1
DMITXP2
DMITXP3

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

CFG0

R144
TP45 TPAD28
TP46 TPAD28

CPU_SEL1 3
CPU_SEL0 3,4

3 CLK_MCH_3GPLL#
3 CLK_MCH_3GPLL

R145
CFG6

SDVOC_CTRLDATA H24
SDVOC_CTRLCLK H25
AB29
AC29
A15
C16
A17
J18
B15
B16
B17

2K2R2J-2-GP

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

?CHECK DISABLE VGA

UMA
UMA
UMA

14 GMCH_DDCCLK
14 GMCH_DDCDATA
2
14 GMCH_BLUE
2
2 14 GMCH_GREEN
2
2
14 GMCH_RED
2
1
R335
14 GMCH_VSYNC
1R147
14 GMCH_HSYNC
1
2 R148

1
2

40D2R2F-GP

40D2R2F-GP

11,12
11,12
11,12
11,12

M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP

DDR_VREF_S3

1
BC4

1
C520

SMYSLEW

E24 DDCCLK
E23 DDCDATA
E21 BLUE
D21 BLUE#
C20 GREEN
B20 GREEN#
A19 RED
B19 RED#
GMCH_VSYNC_1
H21 VSYNC
2
GMCH_HSYNC_1
G21 HSYNC
2 39R2J-L-GP
39R2J-L-GP
CRTIREF
J20 REFSET

SM_OCDCOMP0
SM_OCDCOMP1

AP14
AL15
AM11
AN10

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

SCD1U16V2ZY-2GP

SC2D2U6D3V3MX-1-GP

SCD1U16V2ZY-2GP

UMA

267R2F-1-GP

DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

0R2J-GP
1 R149
SRN10KJ-5-GP
3
4

VGA

UMA

LBKLT_CRTL

G72

LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

13 GMCH_TXACLK13 GMCH_TXACLK+
13 GMCH_TXBCLK13 GMCH_TXBCLK+

B30
B29
C25
C24

LACLKN
LACLKP
LBCLKN
LBCLKP

13 GMCH_TXAOUT013 GMCH_TXAOUT113 GMCH_TXAOUT2-

B34
B33
B32

LADATAN0
LADATAN1
LADATAN2

LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
LIBG

L_LVBG
L_VREFH
L_VREFL

TPAD28
TPAD28
TPAD28

R156

2GMCH_VSYNC_1

1 R344
2
0R2J-GP

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

TP39
TP43
TP40

G72

2D5V_S0

G72

0R2J-GP
1 R345

13 CLK_DDC_EDID
13 DAT_DDC_EDID
13 GMCH_LCDVDD_ON

10KR2J-2-GP
VGATE_PWRGD 2
1

DY

0R2J-GP
1 R336

UMA
UMA

29 BL_ON

J23
PM_BMBUSY# 16
J21 PM_EXTTS#0
H22 PM_EXTTS#1
F5
PM_THRMTRIP-I# 4,15,19
AD30
VGATE_PWRGD 16,32
AE29
1
2
PLT_RST1# 16,18,25,29,31,42,47
R159
150R2J-L1-GP-U
MYALL SC
A24
DREFCLK# 3
A23
DREFCLK 3
C37
DREFSSCLK# 3
D37
DREFSSCLK 3

0R2J-GP
1 R146

2
1

UMA

G72
G72
G72

PCI-EXPRESS GRAPHICS

AF22
AF16

BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#

71.0GMCH.08U
SC2D2U6D3V3MX-1-GP

R123
0R2J-GP

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

G72

1D05V_S0

1
BC3
2

1
C517

SMXSLEW

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

AN16
AM14
AH15
AG16

M_CS#0
M_CS#1
M_CS#2
M_CS#3

M_OCDCOMP0
M_OCDCOMP1

R158

AP21
AM21
AH21
AK21

1D05V_S0

0R2J-GP
1 R122

150R2F-1-GP R1291
0R2J-GP
1 R130
150R2F-1-GP R1311
0R2J-GP
1 R132
150R2F-1-GP R1341
0R2J-GP
1 R133

LVDS

11,12
11,12
11,12
11,12

Layout Note:
Route as short
as possible
1

M_CKE0
M_CKE1
M_CKE2
M_CKE3

MUXING

11,12
11,12
11,12
11,12

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

PM

AN33
AK1
AE10
AJ33
AF5
AD10

DDR

11 M_CLK_DDR#3
11 M_CLK_DDR#4

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

CLK

11 M_CLK_DDR#0
11 M_CLK_DDR#1

AM33
AL1
AE11
AJ34
AF6
AC10

NC

11 M_CLK_DDR3
11 M_CLK_DDR4

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

EXP_COMPI
EXP_ICOMPO

D36
D34

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

1
2
24D9R2F-L-GP

PEG_RXN[15..0]

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

42

PEG_RXP[15..0] 42

www.kythuatvitinh.com

11 M_CLK_DDR0
11 M_CLK_DDR1

R160

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

U35G

MISC

16
16
16
16

AA31
AB35
AC31
AD35

CFG/RSVD

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI

16
16
16
16

1D5V_S0
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die

CFG[2:0] Freq.(MHz)
101
400
001
533

TV

R152
10KR2J-3-GP

U35B

GMCH_HSYNC_1

13 GMCH_TXAOUT0+
13 GMCH_TXAOUT1+
13 GMCH_TXAOUT2+

A34
A33
B31

LADATAP0
LADATAP1
LADATAP2

13 GMCH_TXBOUT013 GMCH_TXBOUT113 GMCH_TXBOUT2-

C29
D28
C27

LBDATAN0
LBDATAN1
LBDATAN2

13 GMCH_TXBOUT0+
13 GMCH_TXBOUT1+
13 GMCH_TXBOUT2+

C28
D27
C26

LBDATAP0
LBDATAP1
LBDATAP2

G72

PM_EXTTS#0
PM_EXTTS#1

RN59

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

SDVOB_RN_1
SDVOB_GN_1
SDVOB_BN_1
SDVOB_CLKN_1
SDVOC_RN_1
SDVOC_GN_1
SDVOC_BN_1
SDVOC_CLKN_1
TXN8
TXN9
TXN10
TXN11
TXN12
TXN13
TXN14
TXN15

C466
C468
C473
C474
C477
C478
C483
C484
C489
C491
C495
C497
C500
C503
C508
C509

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

SDVOB_RP_1
SDVOB_GP_1
SDVOB_BP_1
SDVOB_CLKP_1
SDVOC_RP_1
SDVOC_GP_1
SDVOC_BP_1
SDVOC_CLKP_1
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15

C463
C465
C469
C472
C475
C476
C479
C482
C485
C488
C492
C494
C498
C499
C504
C507

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

42 PEG_TXN[15..0]

2
2
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
42 PEG_TXP[15..0]

SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V

G72
G722 SCD1U16V

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

2 SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V

G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G722
G72
G72

71.0GMCH.08U

1D8V_S3

DY

R161
80D6R2F-L-GP

2D5V_S0

RN14
LCTLA_CLK
LCTLB_DATA

M_RCOMPN

1
2

4
3

SRN2K2J-1-GP
RN13

M_RCOMPP

CLK_DDC_EDID 1
DAT_DDC_EDID 2

R162
80D6R2F-L-GP

4
3

SRN2K2J-1-GP
BL_ON
LBKLT_CRTL

4 RN12
3

1
2
SRN100KJ-6-GP

LIBG

1 R143

<Core Design>

1K5R2F-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (2 of 5)
Size
Custom

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet
E

of

52

U35C
11 M_A_DQ[63..0]

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

U35D

SA_BS0#
SA_BS1#
SA_BS2#

AK15
AK16
AL21

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

AN15
AP16
AF29
AF28
AP15

SA_RCVENIN#
SA_RCVENOUT#

11 M_B_DQ[63..0]
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

SB_BS0#
SB_BS1#
SB_BS2#

AJ15
AG17
AG21

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

AH14
AK14
AF15
AF14
AH16

SB_RCVENIN#
SB_RCVENOUT#

M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_A[13..0] 11,12

M_A_CAS# 11,12
M_A_RAS# 11,12
TP51 TPAD28
TP49 TPAD28
M_A_WE# 11,12

Place Test PAD Near to Chip

as could as possible

71.0GMCH.08U

DDR SYSTEM MEMORY B

www.kythuatvitinh.com
DDR SYSTEM MEMORY A

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11

M_B_A[13..0] 11,12

TP50
TP52

M_B_CAS# 11,12
M_B_RAS# 11,12
TPAD28
TPAD28
M_B_WE# 11,12

Place Test PAD Near to Chip

ascould as possible

71.0GMCH.08U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (3 of 5)
Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet
E

of

52

ST330U2D5VDM-9GP
L26
0R0805-PAD

BLM18BB221SN1D-GP

TC33

0R0805-PAD

0R0805-PAD
C453
SC10U10V5ZY-1GP

C511
SC10U10V5ZY-1GP

C505
SC10U10V5ZY-1GP

L27
1D5V_DPLLB_S0

C455
SCD1U16V2ZY-2GP

C510
SCD1U16V2ZY-2GP

L31

2
1D5V_MPLL_S0

1 R136

G72

0R3-0-U-GP

C450
SC4D7U6D3V3KX-GP

C209
SCD1U16V2ZY-2GP

0R2J-GP

UMA

Layout Notes: VSSA_CRTDAC

Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.

C201
SCD1U16V2ZY-2GP

2
2D5V_S0

1D05V_S0

L25

BLM18BB221SN1D-GP
C449
SCD1U16V2ZY-2GP

2
C448
SCD47U10V3ZY-GP

1
R126

1KR2J-1-GP

2
D4

G72

L32

1
1D05V_S0

SSM5818SLPT-GP

1D5V_HPLL_S0

Size
A3

C454

C223
SC4D7U10V5ZY-3GP

1D05V_S0

C506
SCD1U16V2ZY-2GP
VCCP_GMCH_CAP4

C496

VCCP_GMCH_CAP2
VCCP_GMCH_CAP3

VCCA_3GBG
VSSA_3GBG

F37
G37

Y29
Y28
Y27

0R2J-GP

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

C237
SCD1U16V2ZY-2GP

1D8V_S3

2D5V_TXLVDS_S0

C234
SC10U10V5ZY-1GP

0R2J-GP
2 R337
1

G72

G72

Route VSSA_CRTDAC gnd from GMCH to

decoupling cap ground lead and then
connect to the gnd plane.
<Core Design>

Date: Friday, February 10, 2006

Sheet
E

SCD1U16V2ZY-2GP

2D5V_CRTDAC_S0

DY

ST330U2D5VDM-9GP

R338

UMA
R348

SC2D2U6D3V3MX-1-GP

TC32

G72

SCD22U16V3ZY-GP
2

0R2J-GP

C527
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

VCCP_GMCH_CAP1

C540
SCD1U16V2ZY-2GP

C539
2
1

AE37
W37
U37
R37
N37
L37
J37

Note: All VCCSM

pins shorted
internally

AF20
AP19
AF19
AF18

Note: All VCCSM

pins shorted
internally
SCD1U16V2ZY-2GP
C521

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

SCD1U16V2ZY-2GP
C526

C446
SC4D7U10V5ZY-3GP

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

1 MYALL DIS 0206

B28
A28
A27

0R0603-PAD

1 R135

2
C425
SC10U10V5ZY-1GP

C481

1D5V_DPLLA_S0

L14

R339

1D5V_HMPLL_S0

2D5V_ALVDS_S0

C228

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

0R0603-PAD

1D05V_S0

2D5V_S0

R341 2

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

0R0603-PAD

VCC_SYNC

2D5V_ALVDS_S0

2D5V_S0

K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

H20

0R0603-PAD

0R0805-PAD

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

R375

F19
E19
G19

C451
SCD1U16V2ZY-2GP

V1.8_DDR_CAP1 1
AM37
2
V1.8_DDR_CAP2 1
AH37
2
AP29 V1.8_DDR_CAP5
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
2
1
AH26
AG26
AF26
AE26
SC10U10V5ZY-1GP
AP25
AN25
AM25
2
1
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
2
1
AE21
C542
AE20
SC10U10V5ZY-1GP
AE19
AE18
AE17
AE16
2
1
AE15
C233
AE14
SC10U10V5ZY-1GP
AP13
AN13
AM13
AL13
2
1
AK13
C541
AJ13
SC10U10V5ZY-1GP
AH13
AG13
AF13
AE13
AP12
AN12
2
1
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8 V1.8_DDR_CAP6
V1.8_DDR_CAP4
AM1
2
1
V1.8_DDR_CAP3
AE1
2
1

B22
B21
A21

A35

B26
B25
A25

D19
H17

H18
G18

VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

F17
E17
D18
C18
F18
E18

C447

AC2
AC1
B23
C35
AA1
AA2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

VCCHV0
VCCHV1
VCCHV2

VCCA_LVDS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCCDQ_TVDAC

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

2D5V_TVDAC_S0

GMCH_VCC_SYNC

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17

1D5V_S0

1
C204
SC10U10V5ZY-1GP

0R0805-PAD

2
C219
SCD1U16V2ZY-2GP

1
1

1D5V_S0

G72

C226
SCD1U16V2ZY-2GP

C224
SCD1U16V2ZY-2GP

VCC 1D05_S0 for low speed

graphic clock.1D5V_S0 for
high speed clock.default
use 1D05V_S0

Route ASSATVBG gnd from GMCH to

decoupling cap groung lead and
then connect to the gnd plane

C225
SCD1U16V2ZY-2GP

www.kythuatvitinh.com
0R2J-GP

G72

UMA R343

0R2J-GP
2 R347
1

C215
SC4D7U6D3V3KX-GP

1D5V_DLVDS_S0

0R2J-GP

C222
SC4D7U6D3V3KX-GP

UMA
R346

SCD47U10V3ZY-GP

2
C220
SC4D7U6D3V3KX-GP

R342
0R2J-GP

C227
SC4D7U6D3V3KX-GP

POWER

1D5V_DLVDS_S0
E

R334 2

1
R383

2
1D5V_S0

C248
ST100U6D3VBM-9GP
0R0603-PAD

R340 2
C452
SCD01U16V2KX-3GP

1 MYALL DIS 0206

R157

R352

Document Number
of

2D5V_S0
2D5V_TXLVDS_S0
1D5V_S0

C513
SC10U10V5ZY-1GP

1 MYALL DIS
0207 REMOVE
R142

1D5V_S0

0R0603-PAD

1 MYALL DIS 0206

2D5V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (4 of 5)
MYALL
Rev
52

SA

C462
SCD1U16V2ZY-2GP

0R0603-PAD

U35E

71.0GMCH.08U

Route ASSA3GBG gnd from GMCH to

decoupling cap groung lead and
then connect to the gnd plane

C470
SCD22U16V3ZY-GP

71.0GMCH.08U

A
B

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NTTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26

1D8V_S3

Place these Hi-Freq decoupling caps near GMCH

C239
SCD1U16V2ZY-2GP

C236
SCD1U16V2ZY-2GP

C232
SCD1U16V2ZY-2GP

C231
SCD1U16V2ZY-2GP

www.kythuatvitinh.com
C235
SC10U10V5ZY-1GP

1D05V_S0

Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

U35H

L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

71.0GMCH.08U

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

VSSALVDS

U35F

Y1
D2
G2
J2
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

B36

AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

A
B
C

VSS

Size
A3

Date: Friday, February 10, 2006

Sheet
E

10

C240
SCD1U16V2ZY-2GP

1D05V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
Document Number

GMCH (5 of 5)

MYALL
of
Rev
52

SA

NCTF

<Core Design>
1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

8,12 M_B_BS#2

BA0
BA1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

11
29
49
68
129
146
167
186

/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

ODT0
ODT1

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

/RAS
/WE
/CAS

108
109
113

M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12

/CS0
/CS1

110
115

M_CS#2 7,12
M_CS#3 7,12

CKE0
CKE1

79
80

CK0
/CK0

30
32

CK1
/CK1

164
166

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SDA
SCL

195
197

SMBD_ICH_1
SMBC_ICH_1

VDDSPD

199

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

107
106

8,12 M_B_BS#0
8,12 M_B_BS#1

8 M_B_DQ[63..0]

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

SA0
SA1

198
200

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VREF
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

GND

GND

201

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

8,12 M_A_BS#2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

8,12 M_A_BS#0
8,12 M_A_BS#1

107
106

BA0
BA1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

11
29
49
68
129
146
167
186

/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

ODT0
ODT1

1
2

M_CKE2 7,12
M_CKE3 7,12
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR4 7
M_CLK_DDR#4 7
M_B_DM[7..0] 8

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

8 M_A_DQ[63..0]
SRN33J-5-GP-U
RN22

1
2

4
3

SMBD_ICH 3,18
SMBC_ICH 3,18

3D3V_S0

DM2

8,12 M_A_A[13..0]

DM1

8,12 M_B_A[13..0]

3D3V_S0

/RAS
/WE
/CAS

108
109
113

M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12

/CS0
/CS1

110
115

M_CS#0 7,12
M_CS#1 7,12

CKE0
CKE1

79
80

M_CKE0 7,12
M_CKE1 7,12

CK0
/CK0

30
32

M_CLK_DDR0 7
M_CLK_DDR#0 7

CK1
/CK1

164
166

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0]

SDA
SCL

195
197

VDDSPD

199

SA0
SA1

198
200

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SMBD_ICH_1
SMBC_ICH_1
3D3V_S0

1
2

202
2

C280
SC4D7U6D3V3KX-GP

DDR_VREF_S3

BC1

7,12 M_ODT0
7,12 M_ODT1
DDR_VREF_S3
C311
SC4D7U6D3V3KX-GP

7,12 M_ODT2
7,12 M_ODT3

8 M_A_DQS#[7..0]

8 M_B_DQS[7..0]

8 M_A_DQS[7..0]

202
2

8 M_B_DQS#[7..0]

BC2

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VREF
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

GND

GND

201

NORMAL TYPE

NORMAL TYPE

1D8V_S3

10KR2J-3-GP

www.kythuatvitinh.com

R206

1D8V_S3

DDR2-200P-3-UGP

DDR2-200P-2-GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

High 5.2mm
2nd source:62.10017.661

High 9.2mm
2nd source:62.10017.A61

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR Socket
Size
Document Number
Custom
Date:
A

Rev

SA

MYALL

Friday, February 10, 2006

Sheet
E

11

of

52

PARALLEL TERMINATION

Put decap near power(0.9V) and pull-up resistor

Decoupling Capacitor

DDR_VREF

C328
SCD1U16V2ZY-2GP

1
2

C327
SCD1U16V2ZY-2GP

C326
SCD1U16V2ZY-2GP

C325
SCD1U16V2ZY-2GP

C307
C293
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

C310
C279
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

1
2
1
2

1
2
1

C308
C277
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

SRN56J-2-GP

M_B_A9
M_B_A5
M_B_A3
M_B_A1

1
2
3
4

RN20

8
7
6
5

C309
C278
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

SRN56J-2-GP

M_CKE2 7,11
M_B_BS#2 8,11

M_B_A[13..0] 8,11

M_A_A[13..0] 8,11

C295
C274
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

8
7
6
5

M_CS#3 7,11
M_ODT3 7,11

SRN56J-4-GP
RN19
1
2
3 M_B_A12
4 M_B_A8

Put decap near power(0.9V)

and pull-up resistor

DDR_VREF

1
2

M_ODT1 7,11

4
3

C294
C276
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

M_CKE0 7,11

2 56R2J-4-GP

2 56R2J-4-GP

1 R221
RN23

C292
C275
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

1 R222

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RN28

8
7
6
5

1
2
3
4

M_B_A13

M_ODT2 7,11
M_CS#2 7,11
M_B_RAS# 8,11

1D8V_S3

Place these Caps near DM1

SRN56J-2-GP

C271
SC2D2U6D3V3MX-1-GP

C272
SC2D2U6D3V3MX-1-GP

C270
SC2D2U6D3V3MX-1-GP

C285
SC2D2U6D3V3MX-1-GP

C288
SC2D2U6D3V3MX-1-GP

M_B_BS#1 8,11

M_B_A0
M_B_A2
M_B_A4

1
2
3
4

8
7
6
5

RN27

SRN56J-2-GP
RN26

8
7
6
5

1
2
3
4

M_B_A6
M_B_A7
M_B_A11

M_CKE3 7,11

SRN56J-2-GP
RN21

8
7
6
5

1
2
3
4

M_B_A10
M_B_WE# 8,11
M_B_BS#0 8,11
M_B_CAS# 8,11
1D8V_S3

SRN56J-2-GP

Place these Caps near DM2

RN38

C622
SC2D2U6D3V3MX-1-GP

C319
SC2D2U6D3V3MX-1-GP

C624
SC2D2U6D3V3MX-1-GP

C318
SC2D2U6D3V3MX-1-GP

SRN56J-2-GP
2

C320
SC2D2U6D3V3MX-1-GP

M_ODT0 7,11
M_CS#0 7,11
M_A_RAS# 8,11

M_A_A13

1
2
3
4

8
7
6
5

RN37

8
7
6
5

1
2
3
4

M_A_A0
M_A_A2
M_A_A4

M_A_BS#1 8,11

SRN56J-2-GP
RN34

8
7
6
5

1
2
3
4

M_A_WE#
M_A_BS#0
M_A_CAS#
M_CS#1

8,11
8,11
8,11
7,11

SRN56J-2-GP
RN35

8
7
6
5

1
2
3
4

M_A_A9
M_A_A12
M_A_A8

M_A_BS#2 8,11

SRN56J-2-GP
RN36

8
7
6
5

1
2
3
4

M_A_A6
M_A_A11
M_A_A7

<Core Design>
1

M_CKE1 7,11

SRN56J-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

RN33

8
7
6
5

1
2
3
4

M_A_A5
M_A_A3
M_A_A1
M_A_A10

Title

DDR2 Termination Resistor

SRN56J-2-GP

Size
A3

Document Number

Rev

Date: Friday, February 10, 2006

A

SA

MYALL
Sheet
E

12

of

52

5V_S0

LED
LCDVDD
3D3V_S0

Layout 40 mil

WLAN_LED# 3

U18

5V_S0

BAV99PT-GP-U
2
D13

WLAN_LED#

25,28 WLAN_LED#

DY

2 R253

1 120R2F-GPK

A LED6

LED-Y-47-GP
2

1 LED3

1
1
2
3

R276

UMA

C371
SC1U10V3ZY-6GP

BLT_LED#_1 3

DY

R254
R257
R255
R256

120R2F-GP
120R2F-GP
K
120R2F-GP
120R2F-GP
LED-Y-47-GP
K

1
1
1
1

LED-Y-47-GP
2

LCD_TXAOUT2+
LCD_TXAOUT2LCD_TXACLK+
LCD_TXACLK-

2
0R2J-L1-GP

1
2
3
4

G72

SB

8
7
6
5

GMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXACLK+
GMCH_TXACLK-

7
7
7
7

1
2
3
4

LCD/INVERTER CONN

8
7
6
5

LVDS_TXACLKLVDS_TXACLK+
LVDS_TXAOUT2LVDS_TXAOUT2+

44
44
44
44

2 R252
1
470R2J-2-GP

29 BLT_LED#_1

1
LED-B-27-U-GP

RN53

DY

R274
0R2J-L1-GP

5V_S0

LED5

UMASRN0J-4-GP

G72
2N7002PT-U
Q19

1 LED7

LED BD CONN
D23
2005/11/11
add R between connector and LED signal

IDE_LED# 20

A LED4

LED-G-62-GP
RN57

1
R275

A LED8

R277
10KR2J-2-GP

G72

47 NV_LCDVDD_ON#

D12

FRONT_PWRLED#2
STDBY_LED#
2
CHARGE_LED# 2
DC_BATFULL#
2

29 FRONT_PWRLED#
29 STDBY_LED#
29 CHARGE_LED#
29 DC_BATFULL#

BAV99PT-GP-U

1
AAT4280IGU-1-T1GP
C370
SCD1U16V2ZY-2GP

5V_S5

LED-G-62-GP

6
5
4

C367
SC1U10V3ZY-6GP

3D3V_S0

IN
GND
IN

LCDVDD_ON_1

2
1KR2J-1-GP

7 GMCH_LCDVDD_ON

OUT
GND
ON/OFF#

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1

SC MYALL CHANGE

53
54

SC10U35V0ZY-GP
2
2

2 SC100P50V2JN-U

DY

C361
SCD1U25V3ZY-3GP

C363

UMASRN0J-4-GP
RN52

DY

1
2
3
4

8
7
6
5

1 MYALL DIS 0206

LVDS_TXBOUT1+
LVDS_TXBOUT1LVDS_TXBOUT0+
LVDS_TXBOUT0-

44
44
44
44

SCD1U25V3ZY-3GP
3D3V_S0
LCD_TXACLKLCD_TXACLK+

1
2
3
4

8
7
6
5

7 CLK_DDC_EDID
47 G72_LCD_EDID_CLK

LVDS_TXBCLK+ 44
LVDS_TXBCLK- 44
LVDS_TXBOUT2+ 44
LVDS_TXBOUT2- 44

0R2J-GP
1 R281

47 G72_LCD_EDID_DAT

ODD CHANNEL

4
3

CAP_LED# 29
220R2J-L2-GP
NUM_LED# 29
220R2J-L2-GP
WLAN_LED# 25,28
220R2J-L2-GP
BLT_LED#_2 29
WIRELESS_BTN# 29
BLT_BTN# 29
INT_MIC 27

2D5V_S0

G72

R350
R353
R359
R357
R356

UMA
0R2J-GP
1 R280

NUM_LED# /
IDE_LED# DY
1000p near
LEDBD1 BY EMI
REQUEST

SRN2K2J-1-GP
RN47

4
3
D

2 Q20
FDN337N-1-GP

7 DAT_DDC_EDID

LCD_TXBOUT1LCD_TXBOUT1+

LCD_TXBCLKLCD_TXBCLK+

680R2F-GP

Q21
FDN337N-1-GP

EVEN CHANNEL

LCD_TXBOUT0LCD_TXBOUT0+

LCD_TXBOUT2LCD_TXBOUT2+

100R2F-L1-GP-U

G72 SRN0J-4-GP

LCD_TXAOUT0LCD_TXAOUT0+

MEDIA_LED#

2
2
2
2
2

DY DY DY DY DY DY

RN51

8
7
6
5

C457C459C471C467C456
C464C458
SC1000P50V3JN-GP SC1000P50V3JN-GP SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
3D3V_S0
SC1000P50V3JN-GP
CAP_LED# /
SC1000P50V3JN-GP

UMASRN0J-4-GP
1
2
3
4

1
1
1
1
1
1

ACES-CON12-GP
GMCH_TXBOUT2- 7
GMCH_TXBOUT2+ 7
GMCH_TXBCLK- 7
GMCH_TXBCLK+ 7

LCD_TXAOUT2LCD_TXAOUT2+
LCD_TXAOUT1LCD_TXAOUT1+

R357;R359

G72 SRN0J-4-GP
LCD_TXBOUT2LCD_TXBOUT2+
LCD_TXBCLKLCD_TXBCLK+

2
3
4
5
6
7
8
9
10
11
12
14

R361
10KR2J-3-GP

EC21

1
2

1
C364

DY
SC10U10V5ZY

8
7
6
5

RN55

LCDVDD
EDID_CLK
EDID_DAT

RN56

1
2
3
4

5V_S0

LEDBD1
13
1

EC52

G72
UMA

SCD1U16V2ZY-2GP

52

C360 1

SCD1U16V2ZY-2GP

G72 SRN0J-4-GP

RN61
SRN10KJ-5-GP

C200
SC1U16V3KX-2GP
2

1 R278
2
0R0603-PAD

EDID_CLK

1 R279
2
0R0603-PAD

EDID_DAT

51

FPBACK 29
SC100P50V2JN-U
1

C358
2

DCBATOUT

50

BRIGHTNESS 29

49

C655

48

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NP2
55

EC65

2006.01.11

LCD_TXBOUT0LCD_TXBOUT0+
LCD_TXBOUT1LCD_TXBOUT1+

SCD1U50V3ZY

47

45
NP1
1

46

1
1

LCD1

8
7
6
5

1
2

7
7
7
7

RN54

GMCH_TXBOUT0GMCH_TXBOUT0+
GMCH_TXBOUT1GMCH_TXBOUT1+

RB731U-1GP-U

UMASRN0J-4-GP
1
2
3
4

SB

ODD_LED# 20 3D3V_S0

44
44
44
44

1
1
1
1
1

LVDS_TXAOUT1LVDS_TXAOUT1+
LVDS_TXAOUT0LVDS_TXAOUT0+

2
2
2
2
2

7
7
7
7

R492 MYALL
0R2J-GP

SATA_LED# 15

1
1

GMCH_TXAOUT0+
GMCH_TXAOUT0GMCH_TXAOUT1+
GMCH_TXAOUT1-

2
2

LCD_TXAOUT0+
LCD_TXAOUT0LCD_TXAOUT1+
LCD_TXAOUT1-

MEDIA_LED# 5

G72 SRN0J-4-GP
RN58
1
8
2
7
3
6
4
5

EC51
SCD1U16V2ZY-2GP

1 MYALL DIS 0206

DY DY

SC MYALL

SC MYALL

<Core Design>

IPEX-CON44-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD CONN & LED

Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet

13

of

52

CRT CONNECTOR
Ferrite bead impedance: 75ohm@100MHz

DAT_DDC1_5

12

7
5V_S0

R552
29 CRT_DEC

CRT_VSYNC1

R550
10KR2J-3-GP

CRT_G

13

CRT_HSYNC1
5V_CRT_S0

9
14
4

C1
SCD1U16V3KX-3GP

15
1

DY
0R2J-GP

5V_CRT_S0 add
0.1u near CRT1
request by EMI
R551
0R2J-GP

MH2
16

CLK_DDC1_5

VIDEO-15-21-U1GP

5V_S0

10

Hsync & Vsync level shift

DY

EC2

EC43

CRT_B

EC44

DY

BLM18BA100SN1DGP

EC3

SC6D8P50V2DN-GP

DY

EC47

SC6D8P50V2DN-GP

DY

SC6D8P50V2DN-GP

EC45

CRT_B

SC3P50V2CN-1-GP

R1

150R2F-1-GP

UMA

R265
150R2F-1-GP

150R2F-1-GP

R258

SC3P50V2CN-1-GP

2
8

SC3P50V2CN-1-GP

7 GMCH_BLUE

11

CRT_R
CRT_G

L1
GMCH_O_BLUE

G72

0R2J-GP
1 R4
0R2J-GP
1 R5

43 CRT_BLUE

MH1
6

BLM18BA100SN1DGP

UMA

7 GMCH_GREEN

17

CRT_R

L19
GMCH_O_GREEN

G72

0R2J-GP
1 R267
0R2J-GP
1 R266

CRT1

75 Ohm Impedance

BLM18BA100SN1DGP

43 CRT_GREEN

UMA

L20

50 Ohm Impedance

GMCH_O_RED

G72

7 GMCH_RED

0R2J-GP
1 R260
0R2J-GP
1 R259

43 CRT_RED

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2

C5
SCD1U16V2ZY-2GP

ESD Protection Diode

GMCH_O_VSYNC

G72

CRT_HSYNC1

U1B

BAV99PT-GP-U
2

TSAHCT125PW-GP

CRT_VSYNC1

CRT_G 3

D15

DDC_CLK & DATA level shift

1
2

EC42

EC40
SC100P50V2JN-3GP

SC100P50V2JN-3GP

EC1

BAV99PT-GP-U
2

EC41
SC10P50V2JN-4GP

DY

SC10P50V2JN-4GP

DY

DY

CLK_DDC1_5

C11
SC33P50V2JN-3GP

C12
SC33P50V2JN-3GP

D16

DY

DAT_DDC1_5

CRT_VSYNC1

UMA

CRT_R 3

TSAHCT125PW-GP
U1A

1 R15
0R2J-GP

CRT_HSYNC1

0R2J-GP
UMA2
1 R16

14

G72

BAV99PT-GP-U
2

7 GMCH_VSYNC

43 VSYNC

GMCH_O_HSYNC

7 GMCH_HSYNC

43 HSYNC

14

5V_S0

0R2J-GP
1 R14
0R2J-GP
1 R13

CRT_B 3

D1

DY

5V_S0
D14

3D3V_S0

2D5V_S0

5V_CRT_S0

MYALL SC CHANGE

1
2

1
R263 R264
0R2J-2-GP
0R2J-2-GP

SRN2K2J-1-GP
RN43

4
3

4
3

RN44

RB751V-40-1-GP
EC46
SCD01U16V2KX-3GP

DY

SRN2K2J-1-GP
RN45

1
2

1
2

2D5V_S0 3D3V_S0

4
3

1
5V_CRT_S0

UMA G72
G

UMA G72SRN2K2J-1-GP

7 GMCH_DDCDATA

43 G72_CRT_EDID_CLK
7 GMCH_DDCCLK

0R2J-GP
1 R2
0R2J-GP
1 R3

2
2

G72
UMA
0R2J-GP
1 R262
0R2J-GP
1 R261
G72
UMA

2
2

EDIT_DAT_Q_S
S
D
FDN337N-1-GP
Q1

DAT_DDC1_5
<Core Design>

Wistron Corporation

43 G72_CRT_EDID_DAT

EDIT_CLK_Q_S
S

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CLK_DDC1_5
Title

FDN337N-1-GP
Q18

CRT Connector
Size
Custom

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet

14

of

52

1D05V_S0

SC20P50V2JN-1GP

MYALL SB CHANGE TO 20P

FROM 22P;C586/587
R429
10MR2J-L-GP

MYALL SB

BAT_D2

LPC_LAD[0..3]
RCT_X1 Y1
RCT_X2 Y2

2 20KR2F-L-GP

RCT_RST#

AA2

RTCRST#

R200 1

2 1MR2J-1-GP

INTRUDER#
INTVRMEN

AA3
AA5

INTRUDER#
INTVRMEN

R430 1

19 INTRUDER#

D12
B12
D11
F13

C583
SCD1U16V2ZY-2GP

4
3

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

P2
N3
N5
N4

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LDRQ[0]#
LDRQ[1]#/GPI[41]

N6
P4

LPC_LDRQ#0
LPC_LDRQ1

LFRAME#/FWH[4]

P3

29,31

TP70 TPAD28
TP69 TPAD28
LPC_LFRAME# 29,31
1D05V_S0

A20GATE
A20M#

AF22
AF23

KA20GATE_1 29
H_A20M# 4

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ACZ_RST#_R

A10

ACZ_RST#

F11
F10
B10

1
R226

2
39R2J-L-GP

TPAD28
ACZ_SDATAOUT_R C9

AC19

13 SATA_LED#

BAT

EC64

20
20
20
20

2 SCD01U16V2KX-3GP

AE3
AD3
AG2
AF2

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

1 R197
1 R202

DY

1 MYALL
RTC_AUX_S5

P.H. for internal VCCSUS1_5

INTVRMEN

R190
0R2J-GP

DY

IDE_PDIORDY
INT_IRQ14
IDE_PDDACK#
IDE_PDIOW#
IDE_PDIOR#

H_PWRGD 4,19

IGNNE#
INIT3_3V#
INIT#
INTR

AG26
AE22
AF27
AG24

H_IGNNE# 4

RCIN#

AD23

KBRCIN#_1 29

NMI
SMI#

AF25
AG27

H_NMI 4
H_SMI# 4

STPCLK#

AE26

H_STPCLK# 4

THRMTRIP#

AE23

AC2
AC1

SATA_CLKN
SATA_CLKP

AG11
AF11

SATARBIAS#
SATARBIAS

AF16
AB16
AB15
AC14
AE16

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

H_FERR_R

CPUPWRGD/GPO[49]

AG25

CPU

AF24

R413 1

2 56R2J-4-GP

FWH_INIT#

H_FERR# 4

31

H_INIT# 4

H_INTR 4

H_THERMTRIP_R

C265
SC4700P50V2KX-1GP

R187
75R2F-2-GP

1 R195
2
56R2J-4-GP

PM_THRMTRIP-I# 4,7,19
Layout Note: R632 needs to placed
within 2" of ICH6, R634 must be placed
within 2" of R632 w/o stub.

IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20

DCS1#
DCS3#

AD16
AE17

IDE_PDCS1# 20
IDE_PDCS3# 20

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

DDREQ

AB14

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

IDE_PDDREQ

20

Place within 500 mils

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH6-M (1 of 4)
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

A

1D05V_S0

DY

AC16
AB17
AC17

DA[0]
DA[1]
DA[2]

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

R196
24D9R2F-L-GP
20
20
20
20
20

FERR#

SATALED#

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_RBIAS#_PN
R189
100KR2J-1-GP

ACZ_SDO

20R0603-PAD AD7
20R0603-PAD AC7
AF6
AG6
DIS 0206

3 CLK_PCIE_SATA#
3 CLK_PCIE_SATA

1
2

ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]

H_DPRSLP# 4
H_DPSLP# 4

ACZ_BIT_CLK
ACZ_SYNC

H_CPUSLP# 4,6

AE24
AD27

C10
B9

AE27

DPRSLP#
DPSLP#

BIT_CLK
ACZ_SYNC_R

ACZ_SDATAIN0
21 ACZ_SDATAIN1

21,26 ACZ_SDATAOUT

LANRXD[0]
LANRXD[1]
LANRXD[2]
LANTXD[0]
LANTXD[1]
LANTXD[2]

SC MYALL 26

TP103

E12
E11
C13

R407
56R2J-4-GP

CPUSLP#

21,26 ACZ_RST#

LAN_RSTSYNC

AC-97/AZALIA

2nd source: 20.F0736.003

LAN_CLK

C12
C11
E13

21 ACZ_BTCLK_MDC
26 ACZ_BITCLK
21,26 ACZ_SYNC

39R2J-L-GP1 R233
2
39R2J-L-GP1 R232
2
1
2
39R2J-L-GP
R467
1 R466
2
200R2J-L1-GP

F12

B11

SATA
IDE

10KR2J-3-GP

2
3

BAT

R229

RTC1
ACES-CON3-GP

RTCX1
RTCX2

LAN

BAT54C-1-GP

1
2

U61A

2
C586
SC20P50V2JN-1GP

R199
1KR2J-1-GP

KBRCIN#_1
KA20GATE_1

LPC_LDRQ1

DY

10KR2J-3-GP
R210
2

RN16
SRN10KJ-5-GP

C268
SC1U10V3ZY-6GP

H_DPSLP#

LPC

X-32D768KHZ-38GPU
D8

R198
56R2J-4-GP

X5

RTC

RTC_AUX_S5

3D3V_AUX_S5

3D3V_S0

2
C587
3

Sheet
E

15

of

52

2C299
2C298
2C306
2C305

Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
PCIE_RXN1 25
PCIE_RXP1 25
PCIE_TXN1 25
PCIE_TXP1 25

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

MiniC

U61C

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

J6
H6
G4
G2

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#

A3
E1
R2
C3
E3
C5
G5
J1
J2

PLTRST#
PCICLK
PME#

R5
G6
P6

PCI

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2

PCI_REQ#2
PCI_REQ#3
TP76
BOOT_BLOCK#
TP73
PCI_REQ#5
PCI_GNT#5
PCI_REQ#6
PCI_GNT#6

?CHECK SATA PRESENT

RN17
SRN10KJ-4-GP
1
8SATA0_R2
2
7SATA0_R3
3
6SATA0_R0
4
5SATA0_R1

24
24
28
28
22
22

TP72

TPAD28

26 ACZ_SPKR
29 PM_SUS_STAT#

R450 1

22,24,28
22,24,28
22,24,28
22,24,28

DBRESET#
7 PM_BMBUSY#
PCI_IRDY# 22,24,28
29 ECSCI#_1
PCI_PAR 22,24,28
29 ECSMI#
PCIRST1# 22,24,28

210R2J-2-GP
PCI_DEVSEL# 22,24,28
PCI_PERR# 22,24,28

PCI_LOCK#

PCI_SERR# 22,24,28
PCI_STOP# 22,24,28
PCI_TRDY# 22,24,28

C595
SC22P50V2JN-4GP

TP71 TPAD28

GPI[7]
GPI[8]
SMBALERT#/GPI[11]

M2
R6

GPI[12]
GPI[13]

K25
K24
J27
J26

PERn[3]
PERp[3]
PETn[3]
PETp[3]

M25
M24
L27
L26

PERn[4]
PERp[4]
PETn[4]
PETp[4]

P24
P23
N27
N26

DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

T25
T24
R27
R26

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

7
7
7
7

DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

V25
V24
U27
U26

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

7
7
7
7

DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

Y25
Y24
W27
W26

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

7
7
7
7

DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

AB24
AB23
AA27
AA26

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

7
7
7
7

DMI_CLKN
DMI_CLKP

AD25
AC25

CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3

Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.

PLT_RST1# 7,18,25,29,31,42,47
3,34 PM_STPCPU#

TP63 TPAD28

RESERVED

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
TP[3]

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

D9
C7
C6
M3

TPAD28
TPAD28
TPAD28
TPAD28

AD9
AF8
AG8
U3

29 KBC_SLP_WAKE

INT_PIRQE# 22
INT_PIRQF# 28
INT_PIRQG# 24

22,24,28,29 PM_CLKRUN#

10
9
8
7
6

1
2
3
4
5

PCI_FRAME#
PCI_STOP#
PCI_TRDY#
PCI_PERR#

R204
PM_BATLOW#_R
R205
ECSMI#
R207
ECSWI#
R209

10
9
8
7
6

1
2
3
4
5

3D3V_S0

1KR2J-1-GP
2
8K2R2J-3-GP

1
1
1

DY
DY

2
100KR2J-1-GP
2
100KR2J-1-GP

ECSCI#_1

ICH_GPIO33
ICH_GPIO34

1
R191

8
7
6
5

THRM#

7,32 VGATE_PWRGD

SRN10KJ-4-GP
2
100KR2J-1-GP

PM_SLP_S5#

THRM#

AF21

VRMPWRGD

V6

SUSCLK

T4
T5
T6

SLP_S3#
SLP_S4#
SLP_S5#

AA1

19 PWROK

2
R192
100R2J-2-GP

PM_DPRSLPVR_RAE20
PM_BATLOW#_R
PM_PWRBTN#

LAN_RST#

PM_SLP_S3# 18,29,32,36,37,41,52
R213
100KR2J-1-GP

PM_DPRSLPVR_R

2
R193
100KR2J-1-GP

29,32 RSMRST#_KBC

DY

R201
100KR2J-1-GP

PWROK
DPRSLPVR

V2

BATLOW#

U1

PWRBTN#

V5

LAN_RST#

Y3

RSMRST#

DY

1D5V_S0

Place within 500 mils of ICH

DMI_ZCOMP

F24

F23

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

C23
D23
C25
C24

OC[0]#
OC[1]#
OC[2]#
OC[3]#

C27
B27
B26
C26

USB_OC#0 21
USB_OC#1 21

USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

USBPN0
USBPP0
USBPN6
USBPP6
USBPN7
USBPP7
USBPN4
USBPP4

USBRBIAS#
USBRBIAS

A22
B22

DMI_IRCOMP_R

3D3V_S5
SRN10KJ-4-GP

MYALL SB

USB_OC#3

USB_OC#3
USB_OC#1
USB_OC#6
USB_OC#0

USB_OC#6 21

4
3
2
1

5
6
7
8
RN39

MYALL SB
21
21
21
21
21
21
21
21

3D3V_S0

R7F9
1
R223

2
DY 1KR2J-1-GP

USB_RBIAS_PN

1 R228

ACZ_SPKR

R7F8

TPAD28 TP75
TPAD28 TP79
USBPN3 25
USBPP3 25
USBPN1 21
USBPP1 21
USBPN2 21
USBPP2 21

1KR2J-1-GP
R225 1
2

PCI_GNT#6

1KR2J-1-GP
R227 1
2

PCI_GNT#5

100KR2J-1-GP
R428 1
2

PWROK

DY

R7F7

DY

DY

22D6R2F-L1-GP
Place within 500 mils of ICH

ICH6-M Strapping Options

FUNCTION

DEFAULT

OPTIONAL OVERRIDE

R7F9

No Reboot

NO_STUFF

STUFF

R7F8

A16 Swap
Override

NO_STUFF

STUFF

R7F7

Boot BIOS

NO_STUFF

STUFF

REF

SRN10KJ-L3-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH6-M (2 of 4)
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

A

R224
24D9R2F-L-GP

DMI_IRCOMP

R203
10KR2J-3-GP

3D3V_S5
DBRESET#
PM_RI#
CHK_PW#

AC20

CLK48

29 PM_PWRBTN#

2 0R0603-PAD

SERIRQ

A27

TP68 TPAD28

1 R214

AB20

3 CLK48_ICH

29,37 PM_SLP_S4#

PM_SLP_S3#_ICH

WAKE#

CLK14

PM_SLP_S3#_ICH

34 PM_DPRSLPVR

U5

GPIO[25]
GPIO[27]
GPIO[28]
CLKRUN#
GPIO[33]
GPIO[34]

3 CLK_ICH14

18 PM_SUS_CLK

Need to check what power we will use

P5
R3
T3
AF19
AF20
AC18

E10

3D3V_S0
INT_SERIRQ
THRM#
MCH_SYNC#
INT_PIRQB#

RN24

10
9
8
7
6

1
2
3
4

3D3V_S0
PCI_REQ#3
INT_PIRQE#
PM_CLKRUN#
PCI_REQ#2

SRN10KJ-L3-GP

1
2
3
4
5

PCI_REQ#1
PCI_REQ#6
BOOT_BLOCK#

1 MYALL DIS 0206

10
9
8
7
6

R215

ICH6_WAKE#

3D3V_S5

STP_CPU#

GPIO[24]

CHK_PW#

24,28,29 INT_SERIRQ
3D3V_S0
19 THRM#

AD22

V3

TP58 TPAD28
TP62 TPAD28

GPO[19]

GPO[21]
GPO[23]

10KR2J-3-GP 1

TP61
TP56
TP55
TP67

STP_PCI#

AB21

ICH_GPO21
AD20
KBC_SLP_WAKE AD21

31 PCB_VER1
31 PCB_VER0
31 CHK_PW#

AC21

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#/GPI[4]
PIRQ[H]#/GPI[5]

ICH_GPO19

1
2
3
4
5

SRN10KJ-L3-GP
RN29

3D3V_S5

BMBUSY#

AE19
R1

PERn[2]
PERp[2]
PETn[2]
PETp[2]

AC5
AD5
AF4
AG4
AC9

SRN10KJ-L3-GP
RN40

SMLINK1
SMLINK0
SMB_ALERT#
SMB_LINK_ALERT#

AD19

CLOCKS

TPAD28
TPAD28
TPAD28
TPAD28
TPAD28

PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#

ICH6_WAKE#

3D3V_S0

SYS_RESET#

POWER MGT
USB

N2
L2
M1
L3

RN32

PCI_REQ#0
INT_PIRQH#
INT_PIRQC#
INT_PIRQA#

SUS_STAT#/LPCPD#

U2

H25
H24
G27
G26

FRAME#

1 R211
247R2J-2-GP
CLK_ICHPCI 3
ICH_PME# 22 Int. PH

RN85

3D3V_S0

W3

ICH_GPI12

3 PM_STPPCI#

TP66 TPAD28

PLT_RST1#_1

ICH6 Pullups

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

ICH_PCIE_RXN
1
ICH_PCIE_RXP
1
ICH_PCIE_TXN
1
ICH_PCIE_TXP
1

PERn[1]
PERp[1]
PETn[1]
PETp[1]

TP64
TP60
TP59
TP57
TP65

PCI_LOCK#
INT_PIRQG#
PCI_DEVSEL#
PCI_IRDY#

SATA[0]GP/GPI[26]
SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

W6

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

24 INT_PIRQB#

3D3V_S0

RI#

SMB_ALERT#

29 ECSWI#

Interrupt I/F

INT_PIRQD#
INT_PIRQF#
PCI_REQ#5
PCI_SERR#

Y4
W5
SMB_LINK_ALERT# Y5
SMLINK0
W4
SMLINK1
U6
MCH_SYNC# AG21
F8

TPAD28

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

AF17
AE18
AF18
AG18

www.kythuatvitinh.com
J3

22,24,28 PCI_FRAME#

T2

SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3

18,25 SMB_CLK
18,25 SMB_DATA

TPAD28

PM_RI#

PCI-EXPRESS

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1

Direct Media Interface

AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

GPIO

3D3V_S0

U61B

22,24,28 PCI_AD[31..0]

Sheet
E

16

of

52

Layout Note:
IDE decoupling

C321
1D5V_S0

SCD1U16V2ZY-2GP

3D3V_S0

Layout Note:
Place near pin AA19

EC32
SCD1U16V2ZY-2GP

C289
SCD1U16V2ZY-2GP

2
1
2

1
2

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

EC35
SCD1U16V2ZY-2GP

AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9

Place within 100

mils of ICH pin

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B

AA22
AA23
AA24
AA25
AB25
AB26
AB27
F25
F26
F27
G22
G23
G24
G25
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22

CORE

DY

SCD1U16V2ZY-2GP

C281

TC4
ST220U2D5VBM-2GP

EC36
SCD1U16V2ZY-2GP

U61E
1D5V_S0

EC37
SCD1U16V2ZY-2GP

Layout Note:
Place above caps within
100 mils of ICH near F27, P27, AB27

C296
SCD1U16V2ZY-2GP

1D5V_S0

ALL NO_STUFF Caps do

not have layout
requirements but if
layout allows then place
next to ICH6

3D3V_S0

C324

1
1

1
1

2
1D5V_ICH_S0

C273
SCD1U16V2ZY-2GP

1D05V_S0

RTC_AUX_S5

Place within 100

mils of ICH
pin G10

1
2

C300

SC1U10V3ZY-6GP

1D5V_INT_S5

DY

Place within 100

mils of ICH
C621
SCD1U16V2ZY-2GP

VOUT
VIN
GND

Layout Note:
Place near AB3
C267
SCD1U16V2ZY-2GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

C323
SCD1U16V2ZY-2GP

DY
C

DY

APL5308-15AC-GP

Place within 100

mils of ICH
pin A17

ICH6-M (3 of 4)
Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

B

C301

1
C314
SCD1U16V2ZY-2GP

2
1

<Core Design>

Layout Note:
Place near AG23

Place within 100

mils of ICH
pin V7

1D5V_INT_S5

3D3V_S5

DY
U8

3D3V_S5
Place within 100
mils of ICH
C620
SCD01U16V2KX-3GP

3D3V_S5

C284
SCD1U16V2ZY-2GP

2
1

2
Layout Note:
Place near AB18

C269
SCD1U16V2ZY-2GP

C17
SC1U10V3ZY-6GP

1
C303

AG23
AD26
AB22

10R2J-2-GP
R230

2D5V_S0

DY

1
2
0R3J-3-GP

AB3

G16
G15
F16
F15
E16
D16
C16

5V_S5

C312
SCD1U16V2ZY-2GP

G11
G10

C332
SC1U10V3ZY-6GP

1
A25
A24

R188

2
1

USB

2
V5REF_SUS
VCCUSBPLL
VCCSUS3_3

VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCRTC
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCSUS3_3
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

IDE
PCI

1
V2D5S_PCI_IDE

AB18
P7

10R2J-2-GP
R231

RB751V-40-1-GP
D9

Place both
within 100 mils
of ICH near D27

C297
SCD1U16V2ZY-2GP
AA18
A8
V5REF_S0
V5REF_S5
F21

V5REF
V5REF

Layout Note:
Place near ICH6

C304
SCD1U16V2ZY-2GP

V5REF_S5

1
2

DY
A

VCCSATAPLL
VCC3_3

VCC2_5
VCC2_5

C317
SCD1U16V2ZY-2GP

3D3V_S5

1
2

C286
SC10U10V5ZY-1GP

Place within 100

mils of ICH
pin A13

EC34
SCD1U16V2ZY-2GP

1D5V_S0

G8

1D5V_S0

AE1
AG10

A17
B17
C17
F18
G17
G18

SCD1U16V2ZY-2GP

3D3V_S5

VCC1_5_A

3D3V_S5

1
C264
SCD1U16V2ZY-2GP

Place within 100

mils of ICH
pin AG10

VCCDMIPLL
VCC3_3

A11
U4
V1
V7
W2
Y7

G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

C329
SCD1U16V2ZY-2GP

C287 C290
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP

C579
SCD1U16V2ZY-2GP

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

V5REF_S0

1D5V_INT_S5

Place within 100

mils of ICH
pin AE1

3D3V_S0

AC27
E26

A13
F14
G13
G14

1 R425
2
0R0603-PAD

VCCSUS1_5

G19

RB751V-40-1-GP
D10

1D5V_INT_S5

1D5V_ICH_S0

C313
SCD1U16V2ZY-2GP

1D5V_S0

Place within 100

mils of ICH
near E26, E27

U7
R7

5V_S0

SC2D2U6D3V3MX-1-GP

3D3V_S0

VCCSUS1_5
VCCSUS1_5

3D3V_S0

C302
SCD1U16V2ZY-2GP

C581
SCD01U16V2KX-3GP

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

*Within a given well, 5VREF needs to be up before the

corresponding 3.3V rail

3D3V_S0

2
1

1
C578
SC10U10V5ZY-1GP

Place within 100

mils of ICH

1 R431
2
0R0603-PAD

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

C282
SCD1U16V2ZY-2GP

Layout Note:
Distribute in PCI section
near pin A2-A6 near D1-H1

C283
1D5V_GPLL_ICH_S0

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

1D5V_S0
2

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

SCD1U16V2ZY-2GP

1D5V_S0
Place within 100
mils of ICH
near pin AG9

SCD1U16V2ZY-2GP

C266

SCD1U16V2ZY-2GP

Place within 100

mils of ICH
near pin AG5

1D5V_S0

USB CORE

PCI/IDE
REF

Layout Note:
PCI decoupling

SATA

DY

PCIE

www.kythuatvitinh.com
EC33
SCD1U16V2ZY-2GP

SA
Sheet
E

17

of

52

U61D

E27
Y6
Y27
Y26
Y23
W7
W25
W24
W23
W1
V4
V27
V26
V23
U25
U24
U23
U15
U13
T7
T27
T26
T23
T16
T15
T14
T13
T12
T1
R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N7
N17
N16
N15
N14
N13
N12
N11
N1
M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13
K7
K27
K26
K23
K1
J4
J25
J24
J23
H27
H26
H23
G9
G7
G21
G12
G1

3D3V_S5

32K suspend clock output

U10

1
2
3

16,29,32,36,37,41,52 PM_SLP_S3#
16 PM_SUS_CLK

OE
A
GND

VCC

R218
32KHZ

G791_32K 19

10R2J-2-GP

NC7SZ126P5X-GP
RUN_POWER_ON

DY

2
S

R217
240KR2J-1-GP

2N7002W-7-GP
Q15

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

10

14

U1C

R8

PLT_RST1#

TSAHCT125PW-GP

1
R10

2
0R2J-L1-GP

RSTDRV#_5 20

R9
10KR2J-3-GP

C4
SC100P50V2JN-3GP

7,16,25,29,31,42,47

PCIRST# 3V to 5V level shift for HDD & CDROM

3D3V_S0

8
7
6
5

3D3V_S5

1
2
3
4

RN18
SRN10KJ-4-GP

3D3V_S0

2005/11/14 From 5V_S0 Change to 3D3V_S0

SMBUS

VSS

www.kythuatvitinh.com
5V_S0

33R2J-2-GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SMBC_ICH 3,11

2
S

16,25 SMB_DATA

<Core Design>

Q94 & Q95 connect SMLINK and

SMBUS in S) for SMBus 2.0
compliance

Q14
2N7002PT-U

16,25 SMB_CLK

Wistron Corporation

SMBD_ICH 3,11

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Q13
2N7002PT-U

Title

ICH6-M (4 of 4)
Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet
E

18

of

52

FAN1_VCC

C206 put near

FAN1 / 5V_S0 add
0.1u near FAN by
EMI request

C30
SCD1U16V3KX-3GP

DY

R39
10KR2J-3-GP

D27
BAT54-4-GP

DY

5V_S0

C592
SC2200P50V2KX-2GP

C593
SC10U10V5ZY-1GP

C32

SCD1U16V2ZY-2GP

*Layout* 15 mil

C206 put
near FAN1 /
5V_S0 add
0.1u near
FAN by EMI
request

1
2
R432

*Layout* 15 mil

C28
SC100P50V2JN-3GP

4
ACES-CON3-1-GP
20.F0735.003
<CONNECTOR>

2nd source: 20.F0736.003

U60

*Layout* 30 mil

www.kythuatvitinh.com

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree

Place near chip as close

as possible

R433
10KR2J-3-GP

DCBATOUT

1
2

1
2

PMBS3904-1-GP

Hardware shutdown
H_THERMDA 4
H_THERMDC 4

5V_S5_G913

PMBS3904-1-GP

Q36
C611 1

System Sensor

G792_RESET#

2
4K7R2J-2-GP
R441

Q26
1

C493

G73

DY
5

VCC

HTH
GND
RESET#/RESET LTH

1
2
3

0R2J-GP

INTRUDER#

15

DY
RSMRST# 29

R461
110KR2F-GP

DY

2004/11/10 CHANGE

D26
BAT54-4-GP

DY

R446
10KR2J-3-GP

R445

DY

R462

Output type:
Open-Drain RESET#

15KR2F-GP

D29

DY

HTH

G680LT1F-GP

D28
BAS16-7-F-GP
BAW56PT-U

3D3V_AUX_S5

LOW3_OFF

U64

DY

T8_HW_SHUT#

R463
1MR2J-1-GP

1
2

C600
SCD1U16V2ZY-2GP

47 OVERT#

DY
1

(dummy, KBC already delay)

C596
SCD1U16V2ZY-2GP

DY
SC MYALL CHANGE TO DY 2006.01.11

<Core Design>

Wistron Corporation
2

1KR2J-1-GP
C588
SCD1U16V2ZY-2GP

Q34
PMBT2222A-1GP

B
E

4,15 H_PWRGD

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

R442

Title

Thermal/Fan Controllor

DY

Size
Custom

DY

GAP-CLOSE
1
2

G68

C585
SC2200P50V2KX-2GP
THRM# 16

G792_DXN3

G792SFUF-GP

16 PWROK
R457
10KR2J-3-GP

G792_DXN2

V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC

SGND1
SGND2
SGND3

H_THERMDC

SC470P50V2KX-3GP

SC470P50V2KX-3GP

R440
49K9R2F-L-GP

8
10
12

H_THERMDA
G792_DXP3
G792_DXP2

C589
SC2200P50V2KX-2GP

ALERT#
THERM#
THERM_SET
RESET#

5
17

C590
SC2200P50V2KX-2GP

15
13
3
2

DGND
DGND

G791_32K 18
SMB_DATA_W 29
SMB_CLK_W 29

DXP1
DXP2
DXP3

7
9
11

FAN1
FG1
CLK
SDA
SCL
NC#19

C607
SC2200P50V2KX-2GP
2
1

THRM#
T8_HW_SHUT#
V_DEGREE

VCC
DVCC

1
4
14
16
18
19

C605

C604
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2
1

SC4D7U10V5ZY-3GP
2

C608

Setting T8 as
100 Degree

R439
4K99R2F-L-GP

1
2

C584
SCD1U16V2ZY-2GP

200R2F-L-GP

6
20

GAP-CLOSE
1
2

5V_G791_S0

3D3V_S0

3
2
1

FAN1_VCC

5V_S0
5V_S0

<2nd>
FAN1

PM_THRMTRIP-I# 4,7,15

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet

19

of

52

5V_S0

3D3V_S0

8
7
6
5

CD-ROM Connector

RN41
SRN4K7J-6-GP

TC27

1
2
3
4

ST100U6D3VDM-5

K
A

DYD31
SSM22LLPT-GP

C334

IDE_PDIORDY
IDE_PDDACK#
INT_IRQ14

ODD1

HDD1

TPAD30 TP78
5V_S0

1A
2A
3A

V33
V33
V33

7A
8A
9A

V5
V5
V5

13A
14A
15A

V12
V12
V12

KEY
CSEL
PDIAG#
RESET#
DASP#
INTRQ
IORDY
DIOR#
DIOW#
DMARQ
DMACK#

20
28
34
1
39
31
27
25
23
21
29

R234
HDDCSEL
PDIAG
RSTDRV#_5

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ
IDE_PDIOR#

2
1
470R2J-2-GP

INT_IRQ14
IDE_PDIORDY
IDE_PDIOR#
IDE_PDIOW#
IDE_PDDREQ
IDE_PDDACK#

RSTDRV#_5 18
IDE_LED# 13
INT_IRQ14 15
IDE_PDIORDY 15
IDE_PDIOR# 15
IDE_PDIOW# 15
IDE_PDDREQ 15
IDE_PDDACK# 15

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
52

RSTDRV#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

1
2

10KR2J-2-GP

12
1
2
3
4
5
6
7
8
9
10
11
14

15 SATA_TXP0
15 SATA_TXN0

15 SATA_RXN0
15 SATA_RXP0

TC5
ST100U4VBM-10-GP

5V_S0

DY

R51
0R2J-GP

DY

1
2

TC26

PWR TRACE 100mil

SATA1

5V_S0

R52

CSEL

5V_S0

SATA Connector

C617
SCD1U16V2ZY-2GP

R38
10KR2J-3-GP

ODD_LED# 13

SPD-CONN50-4R-17GP-U

D30
B240LA-13F-GP

3D3V_S0

IDE_PDIOW#
IDE_PDIORDY
INT_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#

For HDD & SATA both

CON44+15P+S7-GP

TC33 CLOSE
BETWEEN
HDD1 AND
SATA1
CONNECTOR.

C34

5V_S0

HDD Connector

C33

SCD1U16V2ZY-2GP

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C38
SC10U10V5ZY-1GP

ST100U6D3VDM-5

NP1
NP2

SATA_TXN1
SATA_TXP1

NP1
NP2

S3
S2

DA0
DA1
DA2
CS0#
CS1#

AA+

5V_S0

35
33
36
37
38

B+
B-

SATA_RXP1
SATA_RXN1

SCD1U16V2ZY-2GP

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_PDCS1#
IDE_PDCS3#

10KR2J-3-GP

S6
S5

40
30
26
24
22
43
19
45
46
2
S1
S4
S7
4A
5A
6A
10A
12A

PDIAG
IDE_PDA2
IDE_PDCS3#

DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0

18
16
14
12
10
8
6
4
3
5
7
9
11
13
15
17

5V_S0

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_PDCS1#
IDE_PDCS3#

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

IDE_PDDACK#

R37

44
32
11A

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

RESERVED#44
RESERVED#32
RESERVED#11A

15
15
15
15
15

+5V_MOTOR
+5V_LOGIC

www.kythuatvitinh.com
TPAD30 TP80

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

42
41

51
1

SCD1U16V2ZY-2GP

C336

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

C337

C335
SCD1U25V3ZY-3GP

Put near SATA2 Connector

SATA1
FCI-CON11-GP-U
13

15

SATA1

SATA_TXP0
SATA_TXN0

2
1

SRN0J-6-GP
SATA_RXN0
2
SATA_RXP0
1

SATA2

MYALL SB RELOAD SYMBOL ADD PIN 12~15

3
4

SATA_TXP1
SATA_TXN1

RN30

3
4

<Core Design>

SATA_RXN1
SATA_RXP1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Dummy when use IDE

Title

HDD and CDROM

RN31

? 0 Ohms closae to SATA2 Connector

SATA2
SRN0J-6-GP

ME : 20.F0777.022

Size
A3

Document Number

Rev

SA

MYALL

Date: Monday, February 13, 2006

Sheet

20

of

52

5V_USB0_S0

100 mil

5V_S5

USB PORT

5V_USB2_S0

U53

SRN0J-6-GP

5V_USB0_S0

AG1-910-SB

USB3

29 USB_PWR_EN#

GND
OC1#
IN
OUT1
EN1/EN1# OUT2
EN2/EN2# OC2#

2
1

8
7
6
5

3
4

USB_OC#0 16
USB_OC#6 16

7
5

AG1-910-01
1

RN68

RN62

SC1000P50V3JN-GP

4
3

16 USBPN6
16 USBPP6

?Check
resistance
value

USB_0USB_0+

USB_6USB_6+

1
2

2
3
4
6
8

EC63

68.00201.141

SKT-USB-105-GP-U

DY

L16

AG1-910-SB

DLW21HN900SQ2LGP

DY DY

SCD1U16V2ZY-2GP

SRN0J-6-GP
EC62

C548
G546A2P1UF-GP
SCD1U16V3KX-3GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

EC24

1
2
3
4

EC25

DY

TC15
SE100U10VM-4GP

5V_USB0_S0

Right side
5V_USB2_S0

USB4

7
5
1

5V_USB1_S0

100 mil

5V_USB1_S0

5V_USB2_S0

SKT-USB-105-GP-U

68.00201.141

3
2

L17

DY

AG1-A-SA

DLW21HN900SQ2LGP

6
8

USB_7USB_7+

1
2

DY

DLW21HN900SQ2LGP

1
2

68.00201.141

L2

USBPN4 16
USBPP4 16

RN25
3D3V_BT_S0

ACES-CON4-1-GP
BLUE1

SRN0J-6-GP
2
1

4
3

16 USBPN7
16 USBPP7

SRN0J-6-GP

3
4

2
3
4

RN63
USB_2USB_2+

RN42

4
3
2

1
USB_7USB_7+

SRN0J-6-GP
2
1

DY

L18

AG1-A-SA

EC38 put near

BLUE1 / all
USB put one
choke near
connector by
EMI request

7
5

DY

DLW21HN900SQ2LGP

AAT4250IGV-T1-GP

3
4

16 USBPN2
16 USBPP2

5V_USB2_S0

USB5

BLUETOOTH_EN 29

L15

DY

AG1-910-SB

68.00201.141

SCD1U16V2ZY-2GP

C263
SC4D7U10V5ZY-3GP
2
DLW21HN900SQ2LGP

EC31

OUT
IN
GND
NC#3 ON/OFF#

68.00201.141

EC48

1
2
3

USB_OC#1 16

1 MYALL DIS 0206

3D3V_BT_S0

3D3V_S0

74.04250.A3F

6
8

C356
G528P1UF-GP
SCD1U16V3KX-3GP

SCD1U16V2ZY-2GP

U7

2
3
4

SKT-USB-105-GP-U

2 0R0603-PAD

1 R268

3D3V_BT_S0

USB_6USB_6+

RN60

8
7
6
5

OUT
OUT
OUT
FLG

USB_0+
USB_0-

29 USB_PWR_EN#

GND
IN
IN
EN#/EN

1
2
3
4

EC30

1
2

1
2

DY

SC1000P50V3JN-GP

TC22
SE150U6D3VDM-GP

EC60
SCD1U16V2ZY-2GP

SC1000P50V3JN-GP

SCD1U16V2ZY-2GP

SE100U10VM-4GP

EC5

DY

EC4

3
4

16 USBPP0
16 USBPN0

U14

5V_S5

BLUETOOTH MODULE

DY

SRN0J-6-GP
2
1

www.kythuatvitinh.com
2

FROM 150U.

100 mil

TC30

TC6
SE100U10VM-4GP

MYALL SB CHANGE TO 100U*2

5V_USB1_S0

5V_USB1_S0

1st source: 20.D0197.104

SCD47U10V3ZY-GP

1
10R2J-2-GP

USB_1USB_1+

USB_2USB_2+

2
3
4
5

2
3
4
5

SKT-USB-97-UGP

SKT-USB-97-UGP

RN1

Rear side

R283

C376
DUMMY-C2

L21

DY
AG1-910-01

DLW21HN900SQ2LGP

C375

<Core Design>
ACZ_BTCLK_MDC 15

68.00201.141

2nd source: 20.F0604.012

R20

1 C13

SRN0J-6-GP
2
1

DY

DY
2

AMP-CONN12A-GP
<CONNECTOR>
20.F0582.012

USB1

6
1

3D3V_S5

C14
SC22P50V2JN-4GP

TP83 TPAD28

100KR2J-1-GP

39R2J-L-GP
1

3
4

4
6
8
10
12
17
18

3
5
ACZ_SYNC
7
ACSDATAIN1_A 9
2 R23
ACZ_RST#
11
MH2
16

USB_1USB_1+

16 USBPN1
16 USBPP1

TP82 TPAD28

SC4D7U10V5ZY-3GP

15,26 ACZ_SYNC
15 ACZ_SDATAIN1
15,26 ACZ_RST#

MDC1

13
MH1
1

<2nd>
15
14
2

R21
0R0603-PAD
ACZ_SDATAOUT
1
2

15,26 ACZ_SDATAOUT

CHANGE TO AZ

1 MYALL DIS 0206

USB2

6
1

MDC 1.5 CONNECTOR

EC38 put near

BLUE1 / all
USB put one
choke near
connector by
EMI request

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

USB / MDC / BLUETOOTH

Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

SA
Sheet

21

of

52

TGP0

TGP1

16,24,28 PCI_AD[31..0]

3
4

LAN_X2

1
2

SC MYALL CHANGE

2006.01.11

C387
SCD01U50V3KX-4GP

XTAL-25MHZ-67GP
LAN_X1

C390
SCD01U50V3KX-4GP

C382
X2 SC15P50V3JN-GP

MID1X

MID0X

16,24,28 PCI_C/BE#[3..0]

RN50
SRN49D9F-GP

3
4

RN49
SRN49D9F-GP

CLOSE TO
LAN CHIP
2
1

TGN1

2
1

TGN0

C383
SC15P50V3JN-GP
3D3V_LAN_S5
U23

LAN_X2
ACT_LED#
LDVDD
RTL_LED1#

CS
SK
DI
DO

VCC
DC
ORG
GND

8
7
6
5

C392

AT93C46-10SU-1GP

EEPROM LED OPTION USE '01'

(DEFINED IN SPEC)
=> LED0 : ACT
=> LED1 : LINK
(BOTH 10/100 AND GIGA CHIP)

ACT_LED# 23

1
2
3
4

LAN_EECS_3
LAN_EESK
LAN_EEDI
LAN_EEDO

1 R292
2 10KR2J-2-GP
1
2
R291
3K6R3-GP

SCD1U16V2ZY-2GP

3D3V_LAN_S5
3D3V_LAN_S5

DY
LAN_X1

www.kythuatvitinh.com
LAN_EESK
LDVDD
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
LAN_EECS_3

R290

3D3V_LAN_S5

3D3V_LAN_S5

PCI_AD0
PCI_AD1

5K6R2F-2-GP
RSET

1
2

C45

1
2

XTAL1

XTAL2

VSS

VSS

CTRL18

AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LANWAKE
PCIAD0
PCIAD1

C384

PCI_PAR 16,24,28
PCI_SERR# 16,24,28

3D3V_LAN_S5

PCI_PERR#
PCI_STOP#
PCI_DEVSEL#
PCI_TRDY#
PM_CLKRUN#

R58
0R0603-PAD

PCI_PERR# 16,24,28
PCI_STOP# 16,24,28
PCI_DEVSEL# 16,24,28
PCI_TRDY# 16,24,28

1
2

PCI_AD27
PCI_AD26
3D3V_LAN_S5

R319
PCI_AD23

100R2F-L1-GP-U

LAN_IDSEL

PCI_AD19
LDVDD
PCI_AD20

PCI_IRDY# 16,24,28
PCI_FRAME# 16,24,28

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

G18

3D3V_LAN_S5
3D3V_S5

RTL8100CL

3D3V_LAN_S5
Size
A3

GAP-CLOSE-PWR-2U

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SCD1U16V2ZY-2GP

<Core Design>

LDVDD
PCI_IRDY#
PCI_FRAME#
PCI_C/BE#2
PCI_AD16
PCI_AD17
PCI_AD18

PCI_AD25
PCI_AD24
PCI_C/BE#3
LDVDD
LAN_IDSEL
PCI_AD23
PCI_AD22
PCI_AD21

C388

C396
SC1U10V3ZY-6GP

GIGALAN: RTL8110SBL
10/100 LAN:RTL8100C

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

RTL8100CL-U
<CHANGE>

LAVDDL

PM_CLKRUN# 16,24,28,29

PCIAD27
PCIAD26
VDD33
PCIAD25
PCIAD24
CBEB3
VDD18
IDSEL
PCIAD23
GND
PCIAD22
PCIAD21
VSSPST
GND
PCIAD20
VDD18
PCIAD19
VDD33
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAME#
GND
IRDY#
VDD18

PCI_AD29
PCI_AD28

PCI_AD15
LDVDD
PCI_C/BE#1
PCI_PAR
PCI_SERR#

C408

LDVDD
PCI_AD31
PCI_AD30

PCI_AD13
PCI_AD14

C400

PCI_GNT#2
PCI_REQ#2

C389

PCI_AD10
PCI_AD11
PCI_AD12

16 INT_PIRQE#
3D3V_LAN_S5
16,24,28 PCIRST1#
3 PCLK_LAN
16 PCI_GNT#2
16 PCI_REQ#2
16 ICH_PME#

LDVDD

PCI_AD8
PCI_AD9

ISOLATE#
LDVDD

1
2
R306 15KR2F-GP

PCI_AD7
PCI_C/BE#0

SCD1U16V2ZY-2GP

LAVDDL

BCP69T1-1-GP
Q23

SCD1U16V2ZY-2GP

CTRL25

SCD1U16V2ZY-2GP

LAVDDL

3 1 R305
2
1KR2J-1-GP

LDVDD
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6

SCD1U16V2ZY-2GP

3D3V_LAN_S5

PCI_AD2

LDVDD

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

D21
BAT54-4-GP

PCIAD2
VSSPST
GND
VDD18
PCIAD3
PCIAD4
PCIAD5
PCIAD6
VDD33
PCIAD7
CBEB0
VSSPST
PCIAD8
PCIAD9
M66EN
PCIAD10
PCIAD11
PCIAD12
VDD33
PCIAD13
PCIAD14
VSSPST
GND
PCIAD15
VDD18
CBEB1
PAR
SERR#
NC
GND
NC
VDD33
PERR#
STOP#
DEVSEL#
TRDY#
VSSPST
CLKRUN#

TGP1
TGN1
LAVDDL
CTRL25

MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATE#
VDD18
INTA#
VDD33
PCIRST#
PCICLK
GNT#
REQ#
PME#
VDD18
PCIAD31
PCIAD30
GND
PCIAD29
PCIAD28
VSSPST

23 TGP1
23 TGN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

TGP0
TGN0
LAVDDL

SC10U10V5ZY-1GP

3D3V_S0

23 TGP0
23 TGN0

AVDD18

VSS
RSET

SCD1U16V2ZY-2GP

C407

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

121

122

123

124

125

126

U25

128
127

RTL_LED1# 23

SA
Sheet
E

22

of

52

10/100M Lan Transformer

<2nd>

U15
22 TGP0
22 TGN0

XRF_TDC
C365
SCD1U16V2ZY-2GP

DY

C366
SCD1U16V2ZY-2GP
2
1

XRF_RDC

7
8

TD+
TD-

6
14
11
3

CT
CT
CT
CT

TX+
TX-

10
9

RD+
RD-

1
2

RX+
RX-

16
15

TDP_RJ45-1
TDN_RJ45-2
TGP1 22
TGN1 22
RDP_RJ45-3
RDN_RJ45-6

RJ45_78

4
3
2
1

www.kythuatvitinh.com
RJ45_45

RN46
SRN75J-1-GP

5
6
7
8

C354

LAN_TERMINAL 1

SC1KP2KV8KX-LGP

C355

SCD01U50V3KX-4GP

DY

LAN Connector

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

ACT_LED#
22 ACT_LED#
C2
SCD1U16V3KX-3GP
2
1
R6
CONN_PWR_B2
2
1
3D3V_S5
470R2J-2-GP
LAN1
9
B1
MH1
TDP_RJ45-1
RJ45_1
B2

TDN_RJ45-2
RDP_RJ45-3
RJ45_45
RDN_RJ45-6
RJ45_78
TIP1

3
1
2
4

TIP_MDC
RING_MDC

L3

2 0R0603-PAD

TIP

L4

2 0R0603-PAD

RING

RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
A1
A2
A3
RJ11_1
RJ11_2
RJ11_3
RJ11_4
MH2
10

TIP
RING

ACES-CON2-1-GP

RJ45-75-GP
RTL_LED1#

22 RTL_LED1#
C3

3D3V_S5
1

SCD1U16V3KX-3GP
1

2 R7
1 CONN_PWR
470R2J-2-GP

<Core Design>

B2:YELLOW

Wistron Corporation

A1:ORANGE

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

A3:GREEN
Title

LAN CONN
3D3V_S5 add 0.1u near LAN1 by EMI request

Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet
E

23

of

52

CBB_D[0..15]
CBB_A[0..25]

3D3V_S0

25
25

1
2

C625
SCD1U16V2ZY-2GP

R472
4K7R2J-2-GP

C632
SCD1U16V2ZY-2GP

3D3V_S0
RN87
CB_MFUNC5
CB_MFUNC4
INT_SERIRQ
CB_MFUNC2

1
2

C629
SC1000P50V3JN-GP

3D3V_S0

CB1410_GBRST#

3D3V_S0

3D3V_S0

C634
SCD1U16V2ZY-2GP

1
2
3
4

8
7
6
5

SRN10KJ-4-GP
3D3V_S0

90
126

8
7
6
5
RN86
SRN47KJ-1-GP

REG#/CCBE3#
A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RFU
A17/CAD16
A16/CCLK#
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12
A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RFU
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RFU
D1/CAD29
D0/CAD27
OE#/CAD11
WE#/CGNT#
IORD#/CAD13
IOW#/CAD15
WP/IOIS16/CCLKRUN#
INPACK#/CREQ#
RDY_IREQ#/CINT#
WAIT#/CSERR#
CD2/CCD2#
CD1/CCD1#
CE2/CAD10
CE1#/CCBE0#
RESET/CRST#
BVD2/SPKR/LED/AUDIO
BVD1/STSCHG/RI/CSTSCHG
VS2/CVS2
VS1/CVS1

125
116
113
111
109
107
105
103
100
98
108
110
104
101
112
95
89
97
99
115
118
120
121
124
127
128
129
87
84
82
80
77
144
142
140
85
83
81
79
76
143
141
139
92
106
93
96
136
123
132
133
137
75
91
88
119
134
135
117
131

CBB_REG#
CBB_A25
CBB_A24
CBB_A23
CBB_A22
CBB_A21
CBB_A20
CBB_A19
CBB_A18
CBB_A17
A_CCLKXX
CBB_A15
CBB_A14
CBB_A13
CBB_A12
CBB_A11
CBB_A10
CBB_A9
CBB_A8
CBB_A7
CBB_A6
CBB_A5
CBB_A4
CBB_A3
CBB_A2
CBB_A1
CBB_A0
CBB_D15
CBB_D14
CBB_D13
CBB_D12
CBB_D11
CBB_D10
CBB_D9
CBB_D8
CBB_D7
CBB_D6
CBB_D5
CBB_D4
CBB_D3

CBB_REG# 25
CBB_A25 25
CBB_RESET
CBB_A24 25
CBB_OE#
CBB_A23 25
CBB_CE2#
CBB_A22 25
CBB_CE1#
CBB_A21 25
CBB_A20 25
CBB_A19 25
CBB_A18 25
CBB_A17 25
1
2 33R2J-2-GP
CBB_A15 25
CBB_A14 25
CBB_A13 25
CBB_A12 25
CBB_A11 25
CBB_A10 25
CBB_A9 25
CBB_A8 25
CBB_A7 25
CBB_A6 25
CBB_A5 25
CBB_A4 25
CBB_A3 25
CBB_A2 25
CBB_A1 25
CBB_A0 25
CBB_D15 25
CBB_D14 25
CBB_D13 25
CBB_D12 25
CBB_D11 25
CBB_D10 25
CBB_D9 25
CBB_D8 25
CBB_D7 25
CBB_D6 25
CBB_D5 25
CBB_D4 25 VCC_ASKT_S0

1
2
3
4

63
AUX_VCC

14
66
86
102
122
138

C626
SCD1U16V2ZY-2GP

U65

SOCKET_VCC
SOCKET_VCC

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

GRST# CORE_VCC

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

GND
GND
GND
GND
GND
GND
GND
GND

16,22,28 PCI_AD[31..0]

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

18
30
44
50

6
22
42
58
78
94
114
130

C615
SC1000P50V3JN-GP

C623
SCD1U16V2ZY-2GP

C618
SCD1U16V2ZY-2GP

1
2

C616
SC1000P50V3JN-GP

VCC_ASKT_S0

PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR

3 PCLK_PCM

16,22,28 PCIRST1#

TP104 16 PCI_GNT#0
16 PCI_REQ#0

C627
SC22P50V2JN-4GP

DY

DY

CLK33_PCM12

R469
10R2J-2-GP

C628
SC10P50V2JN-4GP

25
25
25
25

VCCD1#
VCCD0#
VPPD1
VPPD0
3D3V_S0

1
R471

2
10KR2J-3-GP

CBB_IORD#
CBB_IOWR#

CBB_D3 25
CBB_D2 25
CBB_D1 25
CBB_D0 25
CBB_OE# 25
CBB_WE# 25
CBB_IORD# 25
CBB_IOWR# 25

CBB_D1
CBB_D0
CBB_OE#

R464
10KR2J-3-GP

CBB_WP 25
CBB_INPACK# 25
CBB_RDY 25
CBB_WAIT# 25
CBB_CD2# 25
CBB_CD1# 25
CBB_CE2# 25
CBB_CE1# 25
CBB_RESET 25
CBB_BVD2# 25
CBB_BVD1# 25
CBB_VS2# 25
CBB_VS1# 25

CBB_CE2#
CBB_CE1#

CB-1410-U
Reduce start up noise
RC1

1
CB_MFUNC2

43KR2F-GP
2

DY

CB_SPKR 26
INT_PIRQG# 16
INT_PIRQB# 16

R473
47KR2J-2-GP

INT_SERIRQ 16,28,29

CB_MFUNC4
CB_MFUNC5

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PM_CLKRUN# 16,22,28,29
Title

CardBus_ENE CB1410
Size
A3

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#

C_BE3#
C_BE2#
C_BE1#
C_BE0#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
PAR
PCI_CLK
RST#
RI_OUT#/PME#
GNT#
REQ#

CBB_A16 25

12
27
37
48
28
29
31
33
CARD_IDESL 13
32
34
35
36
21
20
59
2
1

R465

16,22,28
16,22,28
16,22,28
16,22,28
PCI_AD25
R468
1
2
100R2F-L1-GP-U
16,22,28
16,22,28
16,22,28
16,22,28

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

74
73
72
71
CBUS_SUSPEND70
69
68
67
65
64
61
60
62

16,22,28 PCI_C/BE#[3..0]

VCCD1#/SMBCLK/SCLK
VCCD0#/SMBDATA/SDATA
VPPD1
VPPD0/SLATCH
SUSPEND
O2MF6
O2MF5
O2MF4
O2MF3
O2MF2
O2MF1
O2MF0
SPKR_OUT#

www.kythuatvitinh.com

SA
Sheet
E

24

of

52

CBB_CD1#

24 CBB_CD1#
CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14

CBB_CE1#
CBB_D15
CBB_A10
CBB_CE2#
CBB_OE#
CBB_VS1#

VCC_ASKT_S0
CBB_A11
SCD1U16V2ZY-2GP

1
TPAD28

24 VCCD0#
24 VCCD1#

3
4
5
6
9

3.3V
3.3V
5V
5V
12V

1
2

VCCD0#
VCCD1#

15
14

24 VPPD0
24 VPPD1

2211_SHDN#

SHDN#

16

AVCC
AVCC
AVCC

13
12
11

VCC_ASKT_S0

10

VPP_ASKT_S0

AVPP

VPPD0
VPPD1

CBB_VS1# 24
CBB_VS2# 24

OC#

GND

TPS2211AIDBR-1GP

CBB_WAIT#
CBB_A3
CBB_INPACK#
CBB_A2
CBB_REG#
CBB_A1
CBB_BVD2#
CBB_A0
CBB_BVD1#

CBB_WP
CBB_CD2#

24 CBB_CD2#

VCC_ASKT_S0

CARDBUS-SKT42

21.H0056.011

+1.5V
+1.5V

52

+3.3V

24

MINICARD

C397
C405
SC1U10V3ZY-6GP SC1U10V3ZY-6GP

28
48

C386

UIM
28,29 WIRELESS_EN

PERN0
PERP0

23
25

PETN0
PETP0

31
33

USB_DUSB_D+

36
38

USBPN3 16
USBPP3 16

SMB_CLK
SMB_DATA

30
32

SMB_CLK 16,18
SMB_DATA 16,18

WAKE#
CLKREQ#
PERST#

1
7
22

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

4
9
15
18
21
26
27
29
34
35
40
50
53
54

+3.3VAUX

SC1U10V3ZY-6GP

3 RESERVED#3
5 RESERVED#5
8 RESERVED#8
10 RESERVED#10
12 RESERVED#12
14 RESERVED#14
16 RESERVED#16
17 RESERVED#17
19 RESERVED#19
20 RESERVED#20
37 RESERVED#37
39
R300 41 RESERVED#39
RESERVED#41
10KR2J-2-GP
43 RESERVED#43
45 RESERVED#45
47 RESERVED#47
49 RESERVED#49
51 RESERVED#51

MINICARD
13,28 WLAN_LED#

42
44
46

WLAN_LED#

LED_WWAN#
LED_WLAN#
LED_WPAN#

MINICARD

CARDBUS68P-11-GP

SKT-MINI52P-3-GP
R208
DUMMY-R2

R74

CLK_PCIE_MINI1 3
CLK_PCIE_MINI1# 3

3D3V_S0

1D5V_S0

47K

PCIE_TXN1 16
PCIE_TXP1 16

PLT_RST1# 7,16,18,29,31,42,47

3D3V_S5

C401
SC1U10V2ZY

MINICARD
Place near MINIC1

<Core Design>

C391

C385

1
2

C291
SCD01U16V2KX-3GP

C402
SC1U10V2ZY

SCD1U16V2ZY-2GP

MINICARD

MINICARD

C394
SCD1U16V2ZY-2GP

MINICARD

MINICARD

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCMCIA /PCIE MINI CARD

Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

A

PCIE_RXN1 16
PCIE_RXP1 16

62.10043.331

Clock AC termination
33MHz clock for 32-bit
Cardbus card I/F

3.3V

20R0603-PAD
2
0R0603-PAD

13
11

CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10

R73

1
1

REFCLK+
REFCLK-

SCD1U16V2ZY-2GP

C603
DUMMY-C2

1.5V

NP1
NP2

Place close to pin 19.

NP1
NP2

CBB_A4

CBB_RESET

1 MYALL DIS 0206

MINIC1

CBB_VS2#
CBB_A5

1D5V_S0

SKT1

C609
SCD1U16V2ZY-2GP

Mini Card Connector

3D3V_S0

CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6

3D3V_S5

MINICARD

1
2

C606
SC1U10V3ZY-6GP

TP101
CBB_CE1# 24
CBB_CE2# 24
CBB_BVD1# 24
CBB_BVD2# 24

CBB_WE#

CBB_A20

CBB_RDY

CBB_A16

C602
SCD1U16V2ZY-2GP

C612
SC1000P50V3JN-GP

VPP_ASKT_S0

4K7R2J-2-GP
R452

U62

MINICARD

C610

CBB_IOWR#

CBB_A8
CBB_A17
CBB_A13
CBB_A18
CBB_A14
CBB_A19

CBB_A21

C601
SCD1U16V2ZY-2GP

www.kythuatvitinh.com
1

DY

C613

SC10U10V5ZY-1GP
2
1

CBB_IORD#
CBB_A9

C599
SC1U10V3ZY-6GP

CBB_D3

5V_S0

CBB_IORD# 24
CBB_IOWR# 24
CBB_OE# 24
CBB_WE# 24
CBB_REG# 24
CBB_RDY 24
CBB_WP 24
CBB_RESET 24
CBB_WAIT# 24
CBB_INPACK# 24

CN1

NP1
1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68
NP2

24
24

3D3V_S0

CBB_D[0..15]
CBB_A[0..25]

Power switch

Cardbus I/F

3D3V_S0

PCMCIA Socket

Sheet
E

25

of

52

5VA_S0

5V_S0

R488
28K7R2F-GP

C651
SC22P50V2JN-4GP
U68

SHDN# SET

GND

IN

5VA_SET

R490
10KR2F-2-GP

G923-330T1UF-GP
C649
SC1U10V3KX-3GP

C646
SC10U10V5ZY-1GP

5VA_S0

OUT

www.kythuatvitinh.com
5VA_S0

3D3V_S0

24 CB_SPKR

2 C636

1
SCD47U10V3ZY-GP

"VAUX" Pull high to enable standby mode

1
SCD47U10V3ZY-GP

2 C633

SRN47KJ-1-GP

R470
1KR2J-1-GP

1
2

C652

C637

C638

C645
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

C630
SC100P50V3JN-2GP

SC1U10V3ZY-6GP
SC1U10V3ZY-6GP

29
31

LINE1-VREFO
LINE2-VREFO

21
22
16
17

MIC1-L
MIC1-R
MIC2-L
MIC2-R

32
28
30

MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO

34
13
SENSE_B
SENSE_A

44
43
LFE-OUT
CEN-OUT

ACZ_RST# 15,21
ACZ_SYNC 15,21
ACZ_BITCLK 15
1
10KR2J-3-GP

SDATA-OUT
SDATA-IN

5
8

SPDIFO
SPDIFI/EAPD

48
47

SIDESURR-OUT-L
SIDESURR-OUT-R

45
46

SURR-OUT-L
SURR-OUT-R

39
41

FRONT-OUT-L
FRONT-OUT-R

35
36

ACZ_SDATAOUT 15,21
ACZ_SDATAIN0 15

AC97_DATIN
1 R474
2
39R2J-L-GP

SPDIF 27
G1421_MUTE 27

LINE1-L
LINE1-R
LINE2-L
LINE2-R

AUD_LOL 27
AUD_LOR 27

CD-L
CD-R
CD-GND
18
20
19

GPIO0
GPIO1
2
3

JDREF
PIN37_VREFO

VREF

40
37

R476
4K7R2J-2-GP

71.00883.A0G

0R2J-GP
1 R475
TP105 TPAD30

SYS_LOUT_IN#

27

TP106 TPAD30
R486
4K99R2F-L-GP

27

ALC883-1-GP
C647
C643
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP

MIC1V_R
MIC1V_L

1 R487
2
1 R485
2
2K2R2J-2-GP
2K2R2J-2-GP

ALC 883

1ALC883_MIC1_L
1ALC_883MIC1_R

2
2

1 MYALL 2006/02/10

23
24
14
15

27 AUD_MICIN_R

ALC861_LINE_IN_L
ALC861_LINE_IN_R

SC1U10V3ZY-6GP
SC1U10V3ZY-6GP

AVSS1
AVSS2
DVSS1
DVSS2

C343
R243 C644
0R2J-GP

27 AUD_MICIN_L

C648
C650
1
1

26
42
4
7

2
2

27 LINE_IN_L
27 LINE_IN_R

PCBEEP
RESET#
SYNC
BIT-CLK
VAUX

DVDD1
DVDD2
AVDD1
AVDD2

1
9
25
38

12
11
10
6
33

R4892

U67

2AUDIP_PC_BEEP

SC1U10V3KX-3GP

29 KBC_BEEP

C635
1

AUDIO_BEEP

5
6
7
8

CB_SPKR_1 4
1
2 C631
3
SCD47U10V3ZY-GP
KBC_BEEP_1 2
SPKR_SB_1 1

16 ACZ_SPKR

RN88

C654
SCD47U10V3ZY-GP

C653
SCD47U25V5KX-2GP

DY
MYALL SB
1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AZALIA CODEC - ALC883

Size
Document Number
Custom
Date:
A

Rev

SA

MYALL

Friday, February 10, 2006

Sheet
E

26

of

52

MYALL SB

I/P signal level

need +5V level
R250
1
2
0R0603-PAD

C348

C342
SC1U10V3ZY-6GP

DY

1
5

20
4
15

LIN1
LIN2
LOUT+
LOUT-

6
8
23

NC#6
NC#8
NC#23

IN1#/IN2

1
2
24
7

10KR2J-2-GP
SC1U10V3ZY-6GP
C350
1

R247
RIN1
RIN2
ROUT+
ROUT-

LBYPASS
RBYPBASS

SOUND_R_OP1

18
17
19
12

SPKR_R+
SPKR_R-

SOUND_R2 2

3
16

AUD_LOR 26

SOUND_R_OP1

R242
10KR2J-2-GP
2
1

DY

C344
SC1U10V3ZY-6GP

R501

2
2

SC2D2U16V5ZY-2GP

KBC_MUTE_GPIO8

LINE OUT

LIN1

SYS_LOUT_IN

3
2
1

5V_SPDIF_S0

C352
2

1 GND
R2
DTC114EUA-1-GP

SPKR_LSPKR_L+
SPKR_R+

4
3
2

SPKR_R-

ACES-CON4-1-GP
SPKR1

AAT4250IGV-T1-GP
5

3 OUT

R1

ON/OFF# NC#3
GND
IN
OUT

1
2

Q16

SCD1U16V2ZY-2GP
1
2
3
4

2
IN

C641

Internal Speaker

U13

R244
10KR2J-2-GP

R249
10KR2J-2-GP

SYS_LOUT_IN#

C642

5VA_OP_S0

R481 2 AUD_LINE_R
1KR2J-1-GP
R483 2 AUD_LINE_L
1KR2J-1-GP

26 LINE_IN_L

NP2
NP1
5
4
3
6
2
1

SC100P50V2JN-U

26 LINE_IN_R

Q38
2N3906-3-GP

PHONE-JK234-GP

C340

LINE IN

R241
100KR2J-1-GP

RB731U-1GP-U
R239
10KR2J-3-GP

G1432_LBYPASS 1
2
49K9R2F-L-GP

SC2D2U16V5ZY-2GP

R237
10KR2J-3-GP

R505

CHANGE TO CLOSE GAP

SYS_LOUT_IN

C351
SC4D7U10V5ZY-3GP

MYALL SB

MUTE_5

SC100P50V2JN-U

GAP-CLOSE-PWR

G9

1
1

5VA_OP_S0

10KR2J-3-GP R482
10KR2J-3-GP R480

26 G1421_MUTE

Q37
2N3906-3-GP

R506

R503

29 KBC_MUTE

2
49K9R2F-L-GP

C349

5VA_OP_S0

R502

G1432_RBYPASS

G1432Q5U-GP

100KR2J-1-GP 100KR2J-1-GP

GND
GND

GND/HS
GND/HS
GND/HS
GND/HS

14
25

11

DY

9
10
21
22

MUTE

www.kythuatvitinh.com
R240
0R2J-GP

D11

MYALL SC ADDED

5VA_OP_S0
1

SPKR_L+
SPKR_L-

100KR2J-1-GP 100KR2J-1-GP
R504
1

SOUND_L_OP1

VOL
LVDD
RVDD

R238
10KR2J-2-GP
SC1U10V3ZY-6GP
10KR2J-2-GP
C338
R236
1
2 SOUND_L2 1
2 SOUND_L_OP1

R235
10KR2J-2-GP
2

TP81
TPAD28

SHUTDOWN

DY

13

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

C347

1
2

SCD1U16V2ZY-2GP

1
2

SC10U10V5ZY-1GP

C341

U12

DELETE GAP

AMP_SHUTDOWN 29
C339

5V_S0

AUDIO OP AMPLIFIER

5V_S0

26 AUD_LOL

5V_S0

8
7
6
5

SRC100P50V-2-GP
ERC11

1st source: 20.D0197.104

LOUT1

EC
MYALL SC CHANGE TO 22U FROM 68U

MIC IN

26 SPDIF

AUD_LOR

GND
VCC
VIN

<Core Design>

Wistron Corporation

EC38

EC39

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

2
SC330P50V2KX-3GP

C345

2
SC330P50V2KX-3GP

C346

R248

PHONE-JK237-GP

SC680P50V2KX-2GP

1 MYALL DIS 0206

SPKR_L_A1
2
22R2J-2-GP
SPKR_R_A1
2
22R2J-2-GP

TC29 SC10U6D3V6MX-2GP
R251

MIC1

1 R245
1

SPKR_R+1
1

1KR2J-1-GP

SC100P50V2JN-U

1
2

C639

26 SYS_LOUT_IN#
SC10U6D3V6MX-2GP
SPKR_L+1
2
1 R246

SC680P50V2KX-2GP
2

R484;R477 CHANGE TO DY
DY DY

C640

TC28
AUD_LOL
1

AUD_MIC_L
0R2J-GP

10KR2J-3-GP R477

2
1
10KR2J-3-GP R484

1 R479

AUD_MIC_R

SC100P50V2JN-U

26 AUD_MICIN_R
13 INT_MIC
26 AUD_MICIN_L

2 0R2J-GP

NP2
NP1
5
4
3
6
2
1

1KR2J-1-GP
2

MYALL SB
R478;R479 CHANGE TO 0 Ohm FROM 1K
1 R478

9
8
7
16
6
5
4
2
3
1

PHONE-JK233-GP

Title

AUDIO AMP AND JACK

Size

Document Number

Rev

SA

MYALL
Date: Friday, February 10, 2006
D

Sheet
E

27

of

52

C168
SCD1U16V2ZY-2GP

1
2

C167
SCD1U16V2ZY-2GP

16,22,24 PCI_AD[31..0]

2
4

C151
SCD1U16V2ZY-2GP

3D3V_S0

MINI1

125
2

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122

123

124
126

3D3V_S0

www.kythuatvitinh.com
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2

16,22,24 PCI_C/BE#2
16,22,24 PCI_IRDY#
16,22,24,29 PM_CLKRUN#
16,22,24 PCI_SERR#
16,22,24 PCI_PERR#
16,22,24 PCI_C/BE#1

PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10

PCI_AD1

2 PCI_AD21
R105
100R2J-2-GP

MINI-PCI

PCI_PAR 16,22,24

PCI_AD18
PCI_AD16

WIRELESS_EN

2N7002PT-U
Q12

1
G

PCI_FRAME# 16,22,24
PCI_TRDY# 16,22,24
PCI_STOP# 16,22,24

PCI_DEVSEL# 16,22,24
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C/BE#0

PCI_C/BE#0 16,22,24

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

R2

PCI_AD3
5V_S0

80211_ACTIVE

2N7002PT-U
Q11

R1

PCI_AD5

PCI_AD22
PCI_AD20

TPAD28 TP93

C150
SC22P50V2JN-4GP

OUT

PCI_AD8
PCI_AD7

PCI_AD28
PCI_AD26
PCI_AD24
MOD_IDSEL

TP92

PCI_C/BE#3
PCI_AD23

TPAD28

PME#_MINI
BT_COEX1
PCI_AD30

Q17
CHDTC124EU-1GP

INT_SERIRQ 16,24,29

BT_COEX2

16,22,24 PCI_C/BE#3

TP98

PCI_AD27
PCI_AD25

TPAD28

PCI_GNT#1 16

PCI_AD31
PCI_AD29

PCIRST1# 16,22,24

3D3V_S0

16 PCI_REQ#1

WLAN_LED# 13,25

3 PCLK_MINI

INT_PIRQF# 16

TP99 TPAD28

R116
100KR2J-1-GP

5V_S0

INT_PIRQF#

3D3V_S0

PIN 3-16 : LAN RESERVE

80211_ACTIVE

25,29 WIRELESS_EN

GND

IN

29 WLAN_TEST_LED

PCISLT124-4-GP
<CONNECTOR>
62.10032.061

MINI-PCI
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI-PCI
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet
E

28

of

52

SC MYALL

3D3V_AUX_S5

C39

5V_S0

KBC_XO
KCOL[1..18] 30
KROW[1..8] 30

SC12P50V3JN-GP

1
2
3
4
1

LPC

2
S

GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A

41
28
27
25
24
23

SMB_CLK_W 19
SMB_DATA_W 19
3D3V_AUX_S5

MATRIXID2# 31
MATRIXID1# 31
PRE_CHG 38
BLT_BTN# 13
CHG_ON# 38
AD_OFF 39

155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3

2
Q9
2N7002PT-U

Q10
2N7002PT-U

GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00

R34

KB Matrix

160
158

KBC_SCL2
KBC_SDA2

XCLKO
XCLKI

SCL1
SDA1
SCL2
SDA2

BAT_SCL
BAT_SDA
KBC_SCL2
KBC_SDA2

163
164
169
170

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

71
72
73
74
77
78
79
80
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KCOL18

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

161

C37
SC15P50V2JN-2-GP
U3

100KR2J-1-GP

LFRAME#
LCLK
SERIRQ

KBC_XI

100KR2J-1-GP

9
18
7

LAD0
LAD1
LAD2
LAD3

3D3V_S0

R31

15
14
13
10

VCCBAT

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

RN5

8
7
6
5
5V_S0

1
2
3
4

117
116
115
114
111
110

PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1

30 TDATA_5
30 TCLK_5

PS/2

16
16,32
35
13
16,18,32,36,37,41,52
30
38
30
16

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
81
82
83
84
87
88
89
90

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
99
100
101
102
1
42
47
174

3
4

BAT_IN# 39
SRN8K2J-3-GP

WLAN_TEST_LED 28
ECSMI# 16
WIRELESS_EN 25,28
PM_CLKRUN# 16,22,24,28
FPBACK 13
NUM_LED# 13

ECSMI#

PLT_RST1# 7,16,18,25,31,42,47
3D3V_S5

BLUETOOTH_EN 21
DC_BATFULL# 13
BLT_LED#_1 13
BLT_LED#_2 13
MAIL_LED# 30
CHARGE_LED# 13

KBC_SLP_WAKE 2
1
R59
10KR2J-2-GP
PRE_CHG
2
1
R44
10KR2J-2-GP

DY
DY

R57
100KR2J-1-GP

VCC3VSB
AMP_SHUTDOWN
2
0R2J-L1-GP

KBC_PCIRST#1
KBC_BL_ONR56

27

C58
SC1U10V3ZY-6GP

C43
SC150P50V2JN-3GP
2

UMA
KB3910SF-2-GP

1
R54

2
0R2J-L1-GP

BL_ON 7

1
R53

2
0R2J-L1-GP

NV_BL_ON 47

G72

3D3V_AUX_S5
SRN10KJ-5-GP

PM_PWRBTN#
RSMRST#_KBC
S5_ENABLE
BRIGHTNESS

2
GAP-OPEN
G1

PM_SLP_S3#
KBC_PWRBTN#
AC_IN#
KBC_LID#
KBC_SLP_WAKE

RN7

2
1

39 BAT_SCL
39 BAT_SDA

KBC_SLP_WAKE

C29

2
1

CH3906PT-GP
Q5

3
4

RSMRST# 19

S5_ENABLE

RN6

R62
100KR2F-L1-GP

168
175
171
165
162
156

GMODULE_RST# 42

2
8K2R2J-3-GP

R120

16 ECSWI#
A1

R30
10KR2J-3-GP

GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A

KEY4# 30

EC_RST#
ECSCI#

26 KBC_BEEP

KBC_BB_ENABLE#

RSMRST#_KBC

SRN10KJ-5-GP

BRIGHTNESS

43
40
39
38
37
36
33
32

4
3

TCLK_5
TDATA_5

GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7

RN4

2
26
29
30
44
76
172
176

PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0

SRN10KJ-4-GP

1
2

98
97
94
93
92
91

13

3D3V_AUX_S5

8K2R2J-3-GP
2

5V_S0

GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A

WIRELESS_BTN#

KBRCIN#
KA20GATE

CH731UPT-GP

PM_PWRBTN#

R491

ECSCI#

SCD1U16V2ZY-2GP

KBRCIN#

R63
10KR2J-3-GP

KBC_MUTE 27
KEY5# 30

GND
GND
GND
GND
GND
GND

17
35
46
122
137
167

KB3910

AGND
BATGND

16 ECSCI#_1

KA20GATE

96
159

15 KBRCIN#_1

ECRST#
ECSCI#

X-bus
ROM

124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

19
31

D3

INTERNET# 30
MAIL# 30
PM_SLP_S4# 16,37
CHG_3S_4S# 38
PM_SUS_STAT# 16
CRT_DEC 14
CAP_LED# 13
FRONT_PWRLED# 13

D0
D1
D2
D3
D4
D5
D6
D7

3D3V_S5

KBC_BB_ENABLE#

138
139
140
141
144
145
146
147

STDBY_LED# 13

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

31 KBC_D[0..7]

TP1

E51CS#

RD#
WR#
MEMCS#
IOCS#

E51TXD

150
151
173
152

KBCBIOS_RD#
KBCBIOS_WE#
KBCBIOS_CS#

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31 KBCBIOS_RD#
31 KBCBIOS_WE#
31 KBCBIOS_CS#

C19
SCD1U16V2ZY-2GP

2
16
34
45
123
136
157
166
95

C26

SCD1U16V2ZY-2GP

0R0603-PAD

15,31 LPC_LFRAME#
3 PCLK_KBC
16,24,28 INT_SERIRQ

15 KA20GATE_1

3D3V_KBC_AUX_S5

RN8
SRN10KJ-4-GP

X1
RESO-32D768KHZ-GP

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

1 L5

15,31 LPC_LAD[0..3]

1
2

C18
SCD1U16V2ZY-2GP

1
C72

C53

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_AUX_S5

8
7
6
5

3D3V_AUX_S5

Place near K/B Connector (TOP side)

A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable
A4 for DMRP==>High=Disable,Low=Enable
1

A5 for EMWB==>High=Enable,Low=Disable
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)
GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)

21 USB_PWR_EN#

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

KBC ENE
Size
Document Number
Custom
Date:
A

Rev

SA

MYALL

Friday, February 10, 2006

Sheet
E

29

of

52

Cover Up Switch

3D3V_AUX_S5

3D3V_S5

R270
10KR2J-3-GP

LAUNCH BD CONN

RN3

1
2
3
4

LID1

MAIL_LED#

1
2

5V_S0

20.K0174.012
<CONNECTOR>

<2nd>

C191

EC20
SCD1U16V2ZY-2GP

RN11
SRN10KJ-5-GP

DY

KBC_PWRBTN# 29

ACES-CON12-GP
SC1U10V3ZY-6GP
13
1

www.kythuatvitinh.com
5
6
7
8

LED2
LED-G-62-GP

2nd source: 20.K0185.012

LED1
LED-Y-47-GP

2
4

2 2
1

C7

5
3

R18
120R2F-GP

MAIL LED
FOR
BUTTON
SIDE

SC MYALL

TP_SCROLL_LEFT
SCRL2 2

SW-TACT-59-GP-U1

EC19

TP_RIGHT
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN
TP_LEFT

TP_SCROLL_RIGHT
SCRL3 2

TPAD1

SW-TACT-59-GP-U1

MAIL_LED# 29

SCD1U16V2ZY-2GP

SW-TACT-59-GP-U1

R17
120R2F-GP

2 K

Program Button

POWER LED
FOR BUTTON
SIDE

EC18

TP_SCROLL_UP
SCRL1 2

2
3
4
5
6
7
8
9
10
11
12
14

TP_DATA
TP_CLK

3
4

RN10

5V_S0

5V_S0

Power Button

SW1

2
1

SC47P50V2JN

SRN100J-3-GP

29 TDATA_5
29 TCLK_5

SRC100P50V-2-GP
ERC12

SW-TACT-59-GP-U1

DY

SW-TACT-59-GP-U1
SCD1U16V2ZY-2GP

C6
SCD1U16V2ZY-2GP

R12
470R2J-2-GP

SC47P50V2JN

C10

SRN470J-3-GP
RN2

SW5

PWRBTN#

MAIL# 29
INTERNET# 29
KEY4# 29
KEY5# 29

R11
10KR2J-3-GP

8
7
6
5

4
3
2
1

SW4

1
2
3
4

5V_S0

TOUCH PAD

SW-TACT-59-GP-U1

SW-TACT-59-GP-U1
MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1

KBC_LID# 29

C353
SCD22U16V3ZY-GP

3D3V_AUX_S5

2 SC100P50V2JN-3GP

KBC_LID#

100R2F-L1-GP-U

2
4
ACES-CON2-1-GP

SCD1U16V2ZY-2GP

EC6

4
3

SCD1U16V2ZY-2GP

COVER_SW#

C8

C9

5
3

SW2

1
1

SW3

R269

3
1

SRN10KJ-4-GP

8
7
6
5

MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1

Mail Button

Internet Button

4
SW-TACT-59-GP-U1

TP_SCROLL_DOWN
SCRL4 2

TP_LEFT
LEFT1 2

TP_RIGHT
RIGHT1 2

SC MYALL
5

E-Button

2nd source: 62.40009.341

SW-TACT-59-GP-U1

SW-TACT-59-GP-U1

SW-TACT-59-GP-U1

EMI Bypass cap.

KROW[1..8] 29
KCOL[1..18] 29

ERC10

1
2
3
4

1
KROW8

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KCOL18

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

KB1
ETY-CON26-2-GP

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

8
7
6
5

1
2
3
4

KCOL5
KCOL6
KCOL7
KCOL8

1
2
3
4

SRC100P50V-2-GP
ERC4
8
7
6
5

KCOL1
KCOL2
KCOL3
KCOL4

1
2
3
4

SRC100P50V-2-GP
ERC3
8
7
6
5

KROW1
KROW2
KROW3
KROW4

1
2
3
4

SRC100P50V-2-GP
ERC7
8
7
6
5

KROW5
KROW6
KROW7
KROW8

1
2
3
4

SRC100P50V-2-GP
ERC8
8
7
6
5

1
2
3
4

SRC100P50V-2-GP
ERC6
8
7
6
5

ERC1
KCOL17
KCOL18

1
1

2
2
ERC2
SC100P50V2JN-3GP
SC100P50V2JN-3GP

Internal KeyBoard CONN

25

KCOL13
KCOL14
KCOL15
KCOL16

........
CHECK KB SPEC. AND PIN DEFINE

ERC9
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN
TP_LEFT

1
2
3
4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BUTTONs / KB / TOUCHPAD
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

B

8
7
6
5
SRC100P50V-2-GP

SRC100P50V-2-GP
A

8
7
6
5
SRC100P50V-2-GP

27

28

KCOL9
KCOL10
KCOL11
KCOL12

TP_DATA
TP_CLK
TP_RIGHT
TP_SCROLL_RIGHT

ERC5

Sheet
E

30

of

52

KBC_D[0..7]

29

TOP VIEW
29 KBCBIOS_WE#
29 KBCBIOS_RD#
29 KBCBIOS_CS#

1
30
2

22
24
31

A18
A17
A16

CE#
OE#
WE#

32
VDD
13
14
15
17
18
19
20
21

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A15
A14
A13
A12
A11
A10
A9
A8
VSS

29
29
29
29
29
29
29
29

3
29
28
4
25
23
26
27

A15 29
A14 29
A13 29
A12 29
A11 29
A10 29
A9 29
A8 29

A2

(B14)

A1

(B15)

(BOTTOM VIEW)

GOLDEN FINGER FOR DEBUG BOARD

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16

12
11
10
9
8
7
6
5

A0
A1
A2
A3
A4
A5
A6
A7

NEED PUT SOCKET

P/N AND FLASH
ROM P/N IN BOM

MYALL SB DELETE BIOS SOCKET

5V_S0

5V_S0

U63

GF_RST#
GF_LPC_LFRAME#

72.39040.H03 FOR LEAD FREE

A0
A1
A2
A3
A4
A5
A6
A7

GF_PCLK_FWH
GF_FWH_INIT#

ROM SIZE MAX. 512KBYTE

GF_LPC_LAD3
GF_LPC_LAD2
GF_LPC_LAD1
GF_LPC_LAD0
EXT_FWH#

TPAD30
1

TP100

PLCC32 Socket P/N:

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

GF_RST#
GF_LPC_LFRAME#
GF_PCLK_FWH

GF_FWH_INIT#

GF_LPC_LAD3
GF_LPC_LAD2
GF_LPC_LAD1
GF_LPC_LAD0
EXT_FWH#
TP102
TPAD30
1
3D3V_S0

3D3V_S0
FOX-GF30
ZZ.GF030.XXX

15,29 LPC_LAD[0:3]
3D3V_S0

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

U2762.10054.051SOCKET
PLT_RST1#
LPC_LFRAME#
PCLK_FWH
FWH_INIT#

SRN10KJ-5-GP
RN15

PLT_RST1#
LPC_LFRAME#
PCLK_FWH
FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

1
1
1
1
1
1
1
1

DY
DY
DY

Boot Device must have ID[3:0] = 0000

Has internal pull-down resistors
All may be left floated
FPET7 Elec. P3-46

GF_RST#
GF_LPC_LFRAME#
GF_PCLK_FWH
GF_FWH_INIT#
GF_LPC_LAD3
GF_LPC_LAD2
GF_LPC_LAD1
GF_LPC_LAD0

3D3V_S0
B

2
GAP-OPEN
G2

C619

C614

PH at ICH6M

20R2J-2-GP
20R2J-2-GP
20R2J-2-GP
20R2J-2-GP
20R2J-2-GP
20R2J-2-GP
20R2J-2-GP
20R2J-2-GP

3
4

Plz put G12 close SW1

R460
R459
R458
DY
R456
DY
R455
DY
R454
DY
R453
DY
R451

C594

2
1

7,16,18,25,29,42,47
15,29
3
15

29
29
29
29
29
29
29
29

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

(B2)

U66

C333
SCD1U16V2ZY-2GP

(B1)

A14

....

A15

....

A18 29
A17 29
A16 29

3D3V_AUX_S5

SW6

1
2
3
4

16 CHK_PW#
29 MATRIXID1#
29 MATRIXID2#

SCD1U16V

5
6
7
8

SC10U6D3V5MX

SCD1U16V

DY

DY

DY

EC23
SC1000P50V3JN-GP

Board ID

Keyboard matrix ( from vendor )

16 PCB_VER0
16 PCB_VER1

Eur

R443
10KR2J-3-GP

DY

DY

PCB_VER0
PCB_VER1

Other

MATRIXID1#

High Bit

MATRIXID2#

Low Bit

Jap

R212
10KR2J-3-GP

US

3D3V_S0

DY

R216
10KR2J-3-GP

R447
10KR2J-3-GP

DY

DY

SW-DIP-4-2-U2-GP

Planar ID(2,1,0)
SA:
SB:
-1 :

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BIOS ROM
Size
A3

Document Number

Date: Friday, February 10, 2006

5

Rev

SA

MYALL
Sheet
1

31

of

52

Run Power

SC MYALL

5V_S0
Q24
TP0610K-T1-GP

C461
1

RUN_POWER_ON

1
2
3
4

SCD1U16V2ZY-2GP
RUN_POWER_ON

330KR2J-L1-GP

S
S
S
G

D
D
D
D

3D3V_S0

8
7
6
5

K
A

D22
MMGZ5242BPT-GP

2RUN_POWER2

R362
330KR2J-L1-GP

R371

SCD1U50V3ZY-GP

C480

RUN_POWER1
2 20KR2F-L-GP

R372 1

PWRGD for NB and SB

5V_S5
U33

S
S
S
G

D
D
D
D

R186
1KR2J-1-GP

3D3V_S5

U32

1
2
3
4

8
7
6
5

1 R194

3,34 6218_PGOOD

VGATE_PWRGD 7,16

0R0603-PAD

AO4422-1-GP

PM_SLP_S3 2

R370
1KR2J-1-GP

AO4422-1-GP
3D3V_S0

DCBATOUT

1D8V_S0

1D8V_S3

1 MYALL DIS 0206

PWRGD to Turn on CPU_Core_Power

U54

www.kythuatvitinh.com
OUT

1
2
3
4

S
S
S
G

D
D
D
D

AO4422-1-GP

R2

R1

GND

IN

16,18,29,36,37,41,52

PM_SLP_S3#

G72

TC34
ST330U2D5VDM-9GP

G72
MYALL SC

Q25
CHDTC124EU-1GP

8
7
6
5

5V_S5

SC MYALL

R376
10KR2J-3-GP

SC MYALL
0R3-0-U-GP1 R512

Aux Power

1 MYALL DIS 0206

DY

1 MYALL DIS 0206

16,29 RSMRST#_KBC

3D3V_AUX_S5

CH3906PT-GP
Q28

1 MYALL DIS 0206

5V_S5

DY

3D3V_AUX

3D3V_AUX_S5

3D3V_AUX_S5

0R3J-3-GP

DY

U6

D6

C519
SC1U50V5ZY-1-GP

G913CF-GP
C257
SC10U10V5ZY-1GP

OUT

3D3V_G913_SET

1
2

1
2

DUMMY-C3

2
1

1
C518

C252

C254

R175
16K5R2F-1-GP

Output = 3.3V
output=1.25(1+(Rx/Ry))

R177
10KR2F-2-GP

DY

Ry

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

LP2951CDR2G-GP

DUMMY-C5

1
2

1
2

2
1

R513

OUTPUT
INPUT
SENSE
FEEDBACK
SHUTDOWN
VO TAP
100mA
GND
ERROR# OUTPUT

8
7
6

C247
SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

C534
SCD1U16V2ZY-2GP

1
2
3
4

SC10U10V5ZY-1GP

U44 SCD1U16V2ZY-2GP
C535

C244

DCBATOUT

C532
1
2

SET

SC1U10V3ZY-6GP

C249

DY

SHDN#
GND
IN

SC1U10V3ZY-6GP

CH521S-30-GP-U

1
2
3

2
1

Rx

C255

0R3J-3-GP

DY R553

1
2

5V_AUX_S5

5V_S5_G913

DY R554

5V_AUX

2
CH521S-30-GP-U

D7

DY

SC22P50V2JN-4GP
2
1

R378
10KR2J-3-GP

Title
0R2J-GP

RUN POWER and 3D3V_AUX_S5

Size
A3

Document Number

Rev

SA

MYALL

Date: Tuesday, February 14, 2006

Sheet

32

of

52

CPU_CORE

Output Signal
PGOOD(OD / 3.3V)

VID1(I / 1.05V)

H_VID2

Input Signal

H_VID3

TPS51120_EN1_5

VID3(I / 1.05V)
Output Power

VID4(I / 1.05V)

H_VID5

VID5(I / 1.05V)

VCC_CORE(O)

Output Signal

6218_PGOOD

VID2(I / 1.05V)

H_VID4

TPS51120
5V/3D3V

VID0(I / 1.05V)

H_VID1

ISL6218CV

VID Setting

H_VID0

TPS51120_EN2_3D3

PGOOD1(OD / 5V)

CPUCORE_ON

PGOOD2(OD / 5V)

CPUCORE_ON

EN1
Output Power
EN2

VCC_CORE (27A)

5V_DC_S5 (5A)

5V(O)

Input Signal

3D3V(O)

Input Power

3D3V_DC_S5 (5A)

www.kythuatvitinh.com

CPUCORE_ON

EN(I / 3.3V)

PM_DPRSLPVR

DRSEN(I / 3.3V)

PM_STPCPU#

DSEN# (I / 3.3V)

DCBATOUT_TPS51120

2D5V_S0

3D3V_S0

Voltage Sense

VCC_CORE_S0

5V_S0

VCC(I)

FAN5234_VGA_Core
1D0V or 1D20V

1D5V_S0

1D8V_S0

VIN

Input Power

VOUT

Input Power
VCC(I)

VOUT

VIN

APL5308-25AC

VSEN(I / 1.55V / 1.35V)

DCBATOUT

VIN

VCNTL

5V_S5

Output Power

VCC

DCBATOUT

1D0V (O)

1D0V (7.5A)

VIN

APL5331KAC

1D2V_S0
1D8V_S0

5V_S5
2

CHG_ON#/OFF

EN (I / 3.3V)

BAT_IN#

THM (I / 3.3V)

EN

VOUT
VCNTL

Output Signal

ACPRN (O / 3.3V)
XTAL2/PB4 (O/5V)

AC_IN

Adapter

1D05V_S0
1D8V_S3

CHARGE_LED#

VIN
VOUT

AD_OFF

Input Signal

CHG_I_PRE_SEL

CHLIM (IO / 5V)

Output Power
VCC (O)

Input Power

VCC (O)

AC_IN

AD_JK
DCBATOUT

1D8V_S0

PB0/MOSI/AIN0

PM_SLP_S3#
Input Power

AD+

5V_AUX_S5

0D9V_S3
5V_S5

BT+

DCIN (I)

PM_SLP_S5#

DC_IN+

(O)

VCNTL

APL5331KAC
SDA (IO / 5V)

Output Signal

(I)

SCL (IO / 5V)

KBC_SDA0

APL5331KAC

Output Signal

5V_S5
KBC_SCL0

PM_SLP_S3#

PG

Charger_ISL6255
Input Signal

Input Signal

VIN

Output Power
AD+

VCC(O)

VCC(I)
VCC(I)

VIN
VTT

VLDOIN

<Core Design>

S3

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

VTTREF
S5

Title

Power Diagram
Size
A3

TPS51100

Document Number

Rev

MYALL

Date: Friday, February 10, 2006

A

SA
Sheet

33
E

of

52

1
2

1
2

5
6
7
8

AO4422-1-GP

U46

VCC_CORE_S0

4
3
2
1

4
3
2
1

C553
SCD22U16V3KX-2-GP

AO4422-1-GP

1
1

1 MYALL DIS 0206

5
6
7
8

U47

CORE_AGND
1K21R2F-2-GP

SC10U25V0KX-3GP

2
1
2

1
2

SC10U25V0KX-3GP
1

R397
0R0603-PAD

U56

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

VDD
DACOUT
DSV
FSET
NC#5
EN
DRSEN
DSEN#
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT

L33

VBAT
ISEN1
PHASE1
UG1
BOOT1
VSSP1
LG1
VDDP
NC#31
NC#29
NC#28
NC#27
NC#26
NC#25
VSEN
DRSV
STV
OCSET
VSS

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

R392

3K83R2F-GP
2

www.kythuatvitinh.com
5
6
7
8

6217_DRSV
6217_STV
6217_OCSET

4
3
2
1

1 MYALL
DIS REMOVE
TO REAR
SIDE FOR
TC47

TC18
TC17
TC19
SE680U2D5VM-GP-U
SE680U2D5VM-GP-U
SE680U2D5VM-GP-U
SE680U2D5VM-GP-U

TC20

U49

NIPPON 680uF 2.5V

ESR=13m

4
3
2
1

U48

C2_SB:Change R100 to
debug Core power

AO4430-1-GP

5
6
7
8

6217_LG1

R406
1K8R3F-GP

6217_EA+
6217_COMP
6217_FB
6217_SOFT

L-D56UH-2-GP

S
S
S
G

3,32 6218_PGOOD

D
D
D
D

2
2
2
2
2

6217_ISEN1
6217_PHASE1
6217_UG1
6217_BOOT1

S
S
S
G

6217_DAC
6217_DSV
243KR2F-GP
6217_FSET
0R0603-PAD
6217_PWRCH
R398
6217_EN#
6217_DRSEN
6217_DSEN#
6218_H_VID0
1 R415
2
6218_H_VID1
1 R416
2
R417
6218_H_VID2
1
2
6218_H_VID3
1 R418
2
6218_H_VID4
1 R420
2
6218_H_VID5
1 R421
2

D
D
D
D

36,52 CPUCORE_ON
16 PM_DPRSLPVR
3,16 PM_STPCPU#
5 H_VID0
MYALL
5 H_VID1
SB
CHANGE 5 H_VID2
5 H_VID3
VID 0
Ohm TO 5 H_VID4
5 H_VID5 PH 10K P.45
0 Ohm
PAD BY
Pingi

1 R389
2
1
100KR2F-L1-GP
1 R395
R396
1
1KR2J-1-GP 1
0R0603-PAD
1 R403
0R0603-PAD
1 R404
0R0603-PAD
0R0603-PAD
0R0603-PAD
0R0603-PAD
0R0603-PAD
0R0603-PAD

AO4430-1-GP

CORE_AGND

CORE_AGND

1 MYALL DIS 0208 REMOVE C543 C544 ADD TC45,TC46

BAT54-4-GP
D25

CORE_AGND

C550
SC1U10V3ZY-6GP

R390

R409
6K04R2F-GP

ISL6218CVZ-TGP
C573
SCD022U16V2KX-3GP

G67

GAP-CLOSE
CORE_AGND
CORE_AGND

46K4R3F-1-GP
54K9R2F-L-GP

1 MYALL DIS 2006/02/10

1
2

3K57R3F-L-GP

2
1

12.4uA/0.87/0.5 = 28.54uA

C564
SC1U10V3ZY-6GP

C576

Rds(on) *Io = Isen * Rsen

(5m/2)*25A=28.54uA*Rsen

R33 = 2.18K ~ 2.15K

CORE_AGND

CORE_AGND

R426
2K21R3F-L-GP

VCC_CORE_S0

2
75KR2F-GP

C569

R423
820KR2F-GP

2
1
2

R424

DY

SC680P50V2KX-2GP

C577
SCD015U50V3KX-GP

R405

C572
SC2200P50V2KX-2GP

R410

SC1800P50V3KX-GP

IMVP IV
Load Line Slope :3mR
25A*3mV/A=> 75mV
Idroop = 75mV / 6.04K = 12.4uA

R414

1 2

R412
15KR3F-GP

1
C575
DUMMY-C3

SC470P50V2KX-3GP

DY
2

C567

1 2

DY

C551
SCD1U50V3ZY-GP

EC61

S
S
S
G

C552

6217_VDD

C246

S
S
S
G

1 MYALL DIS 0206

R388
4D7R3J-L1-GP

6217_VBAT

GAP-CLOSE-PWR

SCD027U50V3KX-GP
1

C561
SC4D7U10V5ZY-3GP

1
R387
10R3J-3-GP

GAP-CLOSE-PWR
G54
2

TC45

C245

D
D
D
D

GAP-CLOSE-PWR
G51
2

TC46

5V_S0

D
D
D
D

5V_S0

SC10U25V0KX-3GP

TC47
SE100U25VM-7GPU

GAP-CLOSE-PWR
G55
2

SCD1U50V3ZY-GP

DCBATOUT_6218

GAP-CLOSE-PWR
G52
2

1 MYALL DIS 0206

2

DCBATOUT_6218

G53

1 MYALL
DIS REMOVE
TO REAR
SIDE FOR
TC47

DCBATOUT_6218

SC10U25V0KX-3GP

DCBATOUT

VCC_CORE_S0

VCC_CORE_S0

DY

1
TC11

1
2

TC7
TC8
SE330U2VDM-4-GP

DY

SE330U2VDM-4-GP
2
1

1. U12,U14:AO4422 84.04422.037
U13,U15:AO4430 84.04430.B37
R100:3K83R2F
2. U12,U14:IRF7413 84.07413.037
U13,U15:IRF7832-U 84.07832.037
R100:2K43R2F

DY
TC10

DY

SE330U2VDM-4-GP
SE330U2VDM-4-GP

<Core Design>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1 MYALL DIS 0206

Title

VCC_CORE
Size
A3

Document Number

Date: Friday, February 10, 2006

A

Rev

SA

MYALL
Sheet
E

34

of

52

DCBATOUT_51120

G37

GAP-CLOSE-PWR
G31
2

GAP-CLOSE-PWR
G28
2

GAP-CLOSE-PWR
G25
2

GAP-CLOSE-PWR
G22
2

GAP-CLOSE-PWR
G20
2

51120_V5FILT

SCD1U50V3ZY-GP

SC10U10V5KX-2GP

51120_VFB1

R183

R174
30KR2F-GP

TC3

TC13
SE220U6D3VM-4GP

5V_S5

GAP-CLOSE-PWR
G19
2

www.kythuatvitinh.com
1

290k/CH1
440k/CH2

VFB1

N/A

not use

ADJ.

VFB2

N/A

not use

ADJ.

5V
Fixed Output
3.3V
Fixed Output

EN1,EN2 Switcher OFF

not use

Swithchr ON

Switcher ON

EN3,EN5

not use

LDO ON

LDO OFF

1
2

C262

DY

VREG3 on

51120_GND

3D3V Iomax=5A
OCP>10A

1
2

1
1

TC2

TC12
SE220U6D3VM-4GP

DY
G8

SANYO 220uF ESR=25mohm

Iripple=2.4A

2
GAP-CLOSE-PWR

51120_GND

2
1

C261

DY
DY

51120_GND

For TPS51120,
Vout=5V
1. If you use
2. If you use
3. If you use
Vout=3.3V
1. If you use
2. If you use
3. If you use

<Core Design>

a 6.8uH inductor, the minimum ESR is 70m ohm.

a 4.7uH inductor, the minimum ESR is 48m ohm.
a 3.3uH inductor, the minimum ESR is 34m ohm.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

a 4.7uH inductor, the minimum ESR is 51m ohm.

a 3.3uH inductor, the minimum ESR is 36m ohm.
a 2.5uH inductor, the minimum ESR is 27m ohm.

TPS51120 / 3D3V / 5V
Size
A3

Document Number

Date: Friday, February 10, 2006

5

GAP-CLOSE-PWR
G36
2

Vout=1V*(R1+R2)/R2

180k/CH1
280k/CH2

380k/CH1
590k/CH2

DY

220k/CH1
330k/CH2

TONSEL

D-Cap
MODE

CURRENT
MODE

N/A

51120_GND

SC680P50V3JN-GP

N/A

C258

DY

GAP-CLOSE-PWR
G33
2

3D3V_S5

DY

R184
22KR2F-GP

51120_COMP2_PL

COMP

PWM

SC390P50V3JN-GP

PWM

SC1000P50V3JN-GP

AUTOSKIP
/FAULTS
OFF

SC390P50V3JN-GP

AUTOSKIP

51120_COMP1_PL

C259

SKIPSEL

R176
13KR2F-GP

DY

V5FILT

DY
R172

G
S
S
S

4
3
2
1

DY

51120_COMP2

R179
30KR2F-GP

GAP-CLOSE-PWR
G30
2

NIPPON 220uF ESR=15mohm

1

IND-4D7UH-85-GP

51120_DRVL2

FLOAT

GAP-CLOSE-PWR
G27
2

51120_VFB2

VREF2

SC10U25V0KX-3GP

3D3V_PWR

SC33P50V3JN-GP

U42
AO4702-1-GP

51120_GND

GND

GAP-CLOSE-PWR

L28

51120_DRVH2
51120_LL2

251120_VREF2
R173
0R0603-PAD

C253

51120_COMP1

C529

51120_TONSEL 1

R178
0R0603-PAD

51120_CS2

C528

23
18

51120_GND
51120_CS1

U39
AO4422-1-GP

GAP-CLOSE-PWR
G24
2

DCBATOUT_51120

51120_DRVH1
51120_DRVH2

3D3V_PWR

27
14

DY

DY

2
0R2J-GP
2
0R2J-GP

DRVH1
DRVH2

DY

ST220U6D3VDM-13GP
30K9R3F-GP

251120_SKIPSEL 32
31

CS1
CS2

PGND1
PGND2
GND
GND
24
17
5
33

DRVL1
DRVL2

25
16

51120_PGD1
1
51120_PGD2 R1701
R171
51120_DRVL1
51120_DRVL2

100KR2J-1-GP

S
S
S
G

1 R163
2
12KR2F-L-GP

30
11

VREF2

TPS51120RHBR-GPU1

112KR2F-L-GP
2
B

PGOOD1
PGOOD2

VO1
VO2

U5

R164

51120_LL2
51120_LL1

D
D
D
D

SC1000P50V3JN-GP

51120_V5FILT

7
2

20
22

V5FILT
VIN

VBST1
VBST2

VFB2
VFB1

C260

51120_GND

15
26

SC10U25V0KX-3GP

R169

LL2
LL1

5
6
7
8

51120_VREF2

GAP-CLOSE-PWR

SANYO 220uF ESR=25mohm

Iripple=2.4A

51120_GND

4
3
2
1

1
8

G21

EN1
EN2
EN3
EN5

5V_PWR
3D3V_PWR

3D3V_S0

5
6
7
8

6
3

NIPPON 220uF ESR=15mohm

R185
7K5R2F-1-GP

DY

1 MYALL DIS 0206

COMP2
COMP1

19
21

28
13

VREG3
VREG5

29
12
10
9

51120_VFB2
51120_VFB1

51120_DRVL1

0R0603-PAD

D
D
D
D

R182 2
1
1 0R0603-PAD
2
R181
0R0603-PAD

51120_V5FILT

51120_EN1
51120_EN2

DY

TP53 TPAD30
TP54 TPAD30

R167
1 0R0603-PAD
2
R168 2
1
0R0603-PAD

51120_COMP1
1 R180

SKIPSEL
TONSEL

29 S5_ENABLE

C242

1
2

C241

51120_COMP2 10R0603-PAD
2

3D3V_AUX
51120_VREG3

1 MYALL DIS 0206

SC10U10V5KX-2GP

1
2

C256

5V_PWR

DY
2

C243
SCD1U50V3ZY-GP
G
S
S
S

51120_VREG50R0603-PAD

251120_VBST1

DY

C250

251120_LL1_1 1

IND-4D7UH-85-GP

U41
AO4702-1-GP

SCD1U50V3ZY-GP

R165
51120_LL1 1

SC10U25V0KX-3GP

DCBATOUT_51120

251120_VBST2

5V Iomax=5A
OCP>10A

SC33P50V3JN-GP

0R0603-PAD

C251

251120_LL2_1 1

5V_PWR

L29

51120_DRVH1
51120_LL1

4
3
2
1

R166
51120_LL2 1

4
3
2
1

C536
51120_GND

5
6
7
8

1 MYALL DIS 0206

C523
SCD1U50V3ZY-GP

D
D
D
D

51120_VREG5 1
2
5D1R3F-GP

GAP-CLOSE-PWR

5V_AUX

5
6
7
8

R384

C531

ST220U6D3VDM-13GP

GAP-CLOSE-PWR
G3
2

C530

GAP-CLOSE-PWR
G34
2

GAP-CLOSE-PWR
G4
2

U40
AO4422-1-GP

S
S
S
G

GAP-CLOSE-PWR
G5
2

51120_V5FILT

D
D
D
D

GAP-CLOSE-PWR
G6
2

SC1U10V3KX-3GP

DCBATOUT_51120

DCBATOUT

SC10U25V0KX-3GP

G7

Rev

SC

MYALL
Sheet
1

35

of

52

1D8V_S3

SC10U10V5ZY-1GP
C524

G41

GAP-CLOSE-PWR
G44
2

3
1

SE330U4VM-1GP

2D5V_S0

U57

GAP-CLOSE-PWR

C512

3D3V_S0

C562

VOUT

GND

VIN

C563

C566

GAP-CLOSE-PWR
G42
2

C570

NC7S14M5X-GP
C547
DUMMY-C2

DY

Q30

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC2D2U16V5ZY-2GP

2
1

R373

C501
SCD22U16V3ZY-GP

VCC

DY

2 0R0603-PAD

NC#1
A
GND

10KR3F-L-GP

1
2
3

R382 2

5331_VREF_1D05V

5V_S5_G913

DY

SB

APL5308-25AC-1GPU

SC1U10V3ZY-6GP

R374
7K15R2F-L-GP

U51

PM_SLP_S3#

VIN
GND
VREF
VOUT

TC21

C230

GND

NC#8
NC#7
VCNTL
NC#5

1
2
3
4

2N7002TPT-GP

SC1U10V3ZY-6GP

www.kythuatvitinh.com
8
7
6
5

1 MYALL DIS 0206

16,18,29,32,37,41,52

1
SC10U10V5ZY-1GP
APL5331KAC-TRLGP
U37

5331_VREF_1D05V
5331_VOUT_1D05V

2
GAP-CLOSE-PWR
G43
2

1
C238

VIN
GND
VREF
VOUT

1
2
3
4

SC1U10V3ZY-6GP

NC#8
NC#7
VCNTL
NC#5

GND

1
8
7
6
5

5V_S5

1D05V_S0
APL5331KAC-TRLGP
U43

R377

SB
5V_S5_G913

2
210KR2F-GP

5V_S5

1D8V_S3

C657
SC1U6D3V2KX-GP

C658
SC4D7U10V5ZY-3GP

C656
SC1U6D3V2KX-GP

3D3V_S0

1D5V

21KR2F-GP

Q29
CH3904PT-GP

SC

R380
1D5V_S0

1D5VLDO

1D5VLDO

U69

C660

GND

FB

R510

APL5912-KAC-GP

1D5VLDO
Add 10K PL for
solve EN pin issue

SO-8-P
1D5VLDO
R511
2K26R3F-GP

1D5VLDO

1D5VLDO

1
2

10KR2J-3-GP

2KR2F-3-GP
2

TC31

DY

ST100U6D3VBML1GP

1D5VLDO
1D5VLDO

VOUT
VOUT

EN

R509

5912_VOUT_1D5V

SC330P50V3JN-GP

C659
10KR2J-3-GP
SCD1U16V

3
4
1

5
9

VIN
VIN

PM_SLP_S3#

16,18,29,32,37,41,52

POK

1D5VLDO

R508

VCNTL

34,52 CPUCORE_ON

G69
R507
1D5VLDO
1KR2J-1-GP

2
GAP-CLOSE-PWR
G71
2

1D5VLDO

GAP-CLOSE-PWR
G70
2
1D5V_S0
1D5VLDO
GAP-CLOSE-PWR
G72
2

1D5VLDO

GAP-CLOSE-PWR

KEMET
1D5VLDO
100uF, 6V, B2 Size
ESR=40mohm

Vo=0.8*(1+(R1/R2))

1D5VLDO

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D5V / 1D05V / 2D5V

Size
A3

Document Number

Date: Friday, February 10, 2006

5

Rev

SA

MYALL
Sheet
1

36

of

52

3D3V_S5

Ioc = 40uA*Roc/Rds

G65

Roc close high side MOS Drain pin

2
GAP-CLOSE-PWR

3D3V_S5

G63

2
GAP-CLOSE-PWR

MYALL SB
1

DY

DY

U55
FDS6612A-1-GP

GAP-CLOSE-PWR
C549

1
C546

1
C545

1
C559

1
C560

7057_PHASE
SCD1U25V3ZY-3GP

7057_OCSET

2
D

G
G

NC7S14M5X-GP

5
6
7
8

Q27

SCD1U25V3ZY-3GP

G59
3D3V_7057_S5
SC10U10V5ZY-1GP

VCC

C522
SC10U10V5ZY-1GP

NC#1
A
GND

D24
BAT54PT-GP

SC10U10V5ZY-1GP

U45

1
2
3

16,29 PM_SLP_S4#

2
GAP-CLOSE-PWR

SC10U10V5ZY-1GP
D
D
D
D

5V_S5_G913

SC1U10V3ZY-6GP

2N7002TPT-GP

SB

5V_S5
C533
SC470P50V2KX-3GP

R386
12KR2F-L-GP

1D8V_S3

G56

4D7R3J-L1-GP

BOOT
UGATE
GND
LGATE

1
2
3
4

7057_BOOT 1
7057_UGATE

7057_LGATE

4
3
2
1

L34

G57

1D8V_PWR

IND-3D3UH-57GP

GAP-CLOSE-PWR
G58
2

SE330U4VM-1GP

4
3
2
1

TC24

GAP-CLOSE-PWR
G62
2

GAP-CLOSE-PWR
G66
2

GAP-CLOSE-PWR
G64
2

TC23

S
S
S
G

Vout = 0.8V(1+Rout/Rgnd)

DY

U52
FDS6690DS-GP

GAP-CLOSE-PWR
G60
2

U50
C537
SC1U10V3ZY-6GP

SE330U4VM-1GP

SCD1U25V3ZY-3GP

PHASE
OCSET
FB
VCC

D
D
D
D

C538
1

R379
2K4R2F-GP

7057_VCC

8
7
6
5

GAP-CLOSE-PWR

3KR2F-GP

R381

5
6
7
8

7057_FB
1
5V_S5

C525

APW7057KC-TR-GP

S
S
S
G

www.kythuatvitinh.com
R385

1D8V_PWR

G61

GAP-CLOSE-PWR

0D9V
5V_S5

C315
SC10U10V5ZY-1GP
C322
SC10U10V5ZY-1GP

1 MYALL DIS 0206

16,29 PM_SLP_S4#

1 R219

2 0R0603-PAD

1 R220

2 0R0603-PAD

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS

1
2

C331
SC10U10V5ZY-1GP

TPS51100DGQ-1-GP

DDR_VREF_S3

C316
SCD1U16V2ZY-2GP

DDR_VREF

1
2
3
4
5

GND

PM_SLP_S3#

U11

10
9
8
7
6

11

16,18,29,32,36,41,52

1D8V_S3

C330
SC10U10V5ZY-1GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

APW7057 / 1D8V/0D9V
Size
A3

Document Number

Date: Friday, February 10, 2006

A

Rev

SA

MYALL
Sheet
E

37

of

52

D17
DCBATOUT

EC49
SCD1U50V3ZY-GP

G14
GAP-CLOSE

G15

U21
S
S
S
G

D
D
D
D

8
7
6
5

BT+

AO4407-1-GP

For EMI

EC56

ID = 10A @
VGS = 10V

GAP-CLOSE

C359
SCD015U50V3KX-GP

C357
SC1U50V5ZY-1-GP

AO4411-1-GP

D02R3720F-2-GP

1
2
3
4

AD+_TO_SYS

1
2
3
4
1

D
D
D
D

R271

SCD1U50V3ZY-GP

U16
S
S
S
G

8
7
6
5

EC50

1
SSM34PT

AD+

DY
DY

SCD1U50V3ZY-GP

DY

ISL6255_CSIN_1

R36
226R3F-GP
ISL6255_SGATE

DCSET

ACLIM

3S

29 CHG_3S_4S#

GND

Float

2S

2N7002PT-U

Q6

1
2

C374
SC10U35V0ZY-GP

C373
SC10U35V0ZY-GP

C377
SCD1U50V3ZY-GP

1
2

1
2

1
2

5
6
7
8

Cell voltage
4.41V/cell

Float

4.20V/cell

GND

3.99V/cell

R29

Page update by David 11/21/2005

24K3R2F-1-GP

2
1

C20

R25

DY

delete 3S2P_I circuit

2
<Core Design>

1K74R2F-GP

1
2
1

DY

Wistron Corporation

Q4

R28
100KR3F-GP

100KR2J-1-GP

4S

VADJ
VREF

ISOURCE_MAX = (((ACLIM/VREF)*0.05+0.05)/Rsense)
Adaptor is 65W/19V : I_LIMIT = 2.9A ( 85% )

SCD1U16V2ZY-2GP

R43

ICHG : 3S2P = 3.2A

IPRE_CHG = 200mA

ISL6255_VREF

R33
100R2F-L1-GP-U

ISL6255_CELLS

Operate Mode
2

VDD

2N7002PT-U
2

S
R50
150KR2J-GP

DY
CELLS

3
29 CHG_ON#

C22
SC100P50V2JN-3GP

R42

100KR2J-1-GP

R35
10KR2J-2-GP SCD01U16V2KX-3GP
C23

Q7

DY

ISL6255_ICM
ISL6255_VCOMP

3D3V_AUX_S5

C16
SC2700P50V3KX-1GP

ISL6255_VDD

R40

R41
100KR2J-1-GP

R26
20KR3F-GP

DY

ISL6255_CHLIM
C24

ISL6255_EN

4
3
2
1

1
CHLIM

VREF

ICM

VCOMP

EN

R27
15K8R3F-GP

DY
SC6800P25V2KX-1GP

SC680P50V2KX-2GP
ISL6255_VDD
C25
100KR2J-1-GP
1
2

DY

DY

GND
ICOMP

29

Near ISL6255
Pin 26

CELLS

1
2

C36

SC1U10V3ZY-6GP

1
R49
15K4R2F-GP

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

PRE_CHG 29
G

Title

28

R285
R284
20KR3F-GP
80K6R3F-1-GP

C380
SC10U25V0KX-3GP

VADJ

C379
SC10U25V0KX-3GP

ACSET

27

C378
SC10U25V0KX-3GP

10

C381
SC1000P100V3KX-GP

DY

4
3
2
1

GND

VDD

C372

26

AO4422-1-GP

5
6
7
8

U20

S
S
S
G

200KR2F-L-GP

ISL6255_VREF

2ISL6255_ACSET

D03R3720F-1-GP

11

Near ISL6255 Pin 13

BT+

PGND

ISL6255_LGATE SC1U10V3ZY-6GP

1 R282

SCD1U50V3ZY-GP

12

LGATE

G17
GAP-CLOSE

R289

DCPRN

DY
L22
1
2 CHG_PWR-3
IND-15UH-41-GP

24

R24

1
2ISL6255_VDD
2R3J-2-GP
C15
ISL6255_VDDP 1
2

13

CHG_PWR-2

AO4422-1-GP

VDDP

1
2
2

UGATE

ACPRN

DCIN

16

15

PHASE

17

BGATE

18

23

G16
GAP-CLOSE

D
D
D
D

ISL6255_VDD

ACSET Threshold 1.27V typ.

ACSET > 1.29V Max. --> AC
DETECT

SGATE

14

25

1 R48

ISL6255_CSIP

BOOT

1 MYALL DIS 0206

AD+

CSIN

CSOP
CSON

DY

2N7002PT-U

ISL6255_ACPRN#

R32 D2
2D2R3J-2-GP
BAT54-4-GP

SCD1U50V3ZY-GP
C35
1
2
22

U2
ISL6255HRZ

U19

2D2R3J-L1-GP

29 AC_IN#

R46
0R0603-PAD
AC_IN# 1
2

19

21

R45
100KR2J-1-GP

EC

R22
10KR2F-2-GP
C21
SCD1U50V3ZY-GP

S
S
S
G

C31
SC1U50V5ZY-1-GP

ISL6255_UGATE

CSIP

Q8

ISL6255_CSIN

20

R47
2R3J-2-GP

D
D
D
D

ISL6255_VDD

DCBATOUT

D
BSS84LT1G-GP

www.kythuatvitinh.com
5V_S5_G913

ISL6255_BGATE

SCD1U50V3ZY-GP
C27
1
2

CHARGER ISL6225

(Power Team)

Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet

38

of

52

DY

Adaptor in to generate DCBATOUT

D18
PZM24NB1

2
3
1

AD+

DC1
AD_JK

C362
SCD1U50V3ZY-GP

E
C

D
D
D
D

8
7
6
5

U17
S
S
S
G

C368
SCD1U50V3ZY-GP

AO4411-1-GP

ID = -10A/70deg
Rds(ON) = 24mohm
SO-8

R1

R2

DC-JACK115-GP

100KR2J-1-GP
2

5
6
MH1

R272

C369
SC1U50V5ZY-1-GP

AD+_2

OUT

www.kythuatvitinh.com
3

PDTA124EU-1-GP
Q3

R273
56KR3F-GP

R1

SC MYALL CHANGE ME RALPH 2..6.01.11

GND

IN

29 AD_OFF

R2

Q2
CHDTC124EU-1GP

1
2
3
4

R19
1KR2J-1-GP

3D3V_AUX_S5

3D3V_AUX_S5

BATTERY CONNECTOR
D19
BAV99PT-GP-U

DY

29 BAT_SDA
29 BAT_SCL
29 BAT_IN#

2
3
4
5
6
7
9

BATA_SDA_1
2
27R3F-GPBATA_SCL_1

1
R288
2
27R3F-GP

1
R287

BAT1

8
1

DY

R286
1MR2J-1-GP

D20
BAV99PT-GP-U

1
2

1
2

1
2

DY

EC55

EC53
SC10P50V2JN-4GP

EC59

SC1000P50V3JN-GP

EC58
SCD1U50V3ZY-GP

SC1000P50V3JN-GP

EC57
SCD1U50V3ZY-GP

SC10P50V2JN-4GP

EC54

DY

BT+
2

SYN-CON7-16-GP-U

Page update by David 11/21/2005

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AD/BATT CONN
Size
A3

Document Number

Rev

SA

MYALL

Date: Friday, February 10, 2006

Sheet
E

39

of

52

H34
<Geometry>

<CHANGE>

34.4A904.001

<CHANGE>

H41
HOLE

H32
HOLE

34.4A905.001

34.4A906.001

H29
HOLE

1D8V_S3

H25
HOLE

GND10
SPRING-29-GP SPRING-18-U

H22
HOLE

GND9

H42
HOLE

H27
HOLE

<CHANGE>

GND8

H28
H11
<Geometry> HOLE

H3
HOLE

G72

1 MYALL DIS 0206

GND7

H21
HOLE

<CHANGE>

MINICARD

MINICARD

H17
HOLE

H14
HOLE

H12
HOLE

H5
HOLE

G72

H18
<Geometry>

www.kythuatvitinh.com
1

H35
H7
H8
<Geometry> <Geometry> HOLE

H19
HOLE

DY

SPRING-18-U SPRING-9-GP SPRING-9-GP

H38
HOLE

H23
HOLE

34.4A908.001

GND6

SC 0103

H16
HOLE

<CHANGE> <CHANGE>

<CHANGE>

H15
HOLE

H39
HOLE

H37
HOLE

H36
HOLE

H31
H33
H40
<Geometry> <Geometry> HOLE

<CHANGE>

H13
H10
<Geometry> HOLE

34.4A902.001

D
H30
HOLE

H6
HOLE

<CHANGE>

3
H9
HOLE

H4
HOLE

34.4A908.001

34.4A902.001

<CHANGE>

<CHANGE>

H2
HOLE

H1
HOLE

34.4A905.001

H24
HOLE

<CHANGE>

H26
HOLE

34.4A903.001

5
H20
HOLE

EC66
EC67
EC68
EC69
EC70
EC71
EC72
EC73
EC74
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP

NVVDD_S0

GND2
SPRING-19

GND3
SPRING-19

GND4
SPRING-23-GP

GND5
SPRING-23-GP

EC17
SCD1U50V3ZY-GP

GND1
SPRING-19

MYALL SB

EC26
SCD1U50V3ZY-GP

DCBATOUT

DDR_VREF

34.41Y19.001

EC27

Page 40 of the EMI of

capacitor and spring, can
delete first by EMI request

EC75
EC76
EC77
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP

EC29

EC12

1
EC11

EC14

EC22

EC28

34.42T14.001 34.42T14.001

34.41Y19.001 34.41Y19.001

MYALL SB

B
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP

EC8

EC7

EC80
EC81
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP

SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP

3D3V_S0

1
EC9

EC10

EC13

EC16

1
2

EC15

1D8V_S0

DCBATOUT

MYALL SB

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
EC78
EC79
EC82
EC83
EC84
EC85
EC86
EC87
EC88
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP

MYALL SB

Title
Size
A3

EMI
Document Number

Date: Friday, February 10, 2006

Rev

MYALL

Sheet

SA
40

of

52

DCBATOUT

DCBATOUT_51124

1D2V_PWR
G75

51124_DRVH1
51124_LL1

GAP-CLOSE-PWR
G79
1
2

1D2V Iomax=5A
OCP>12A
1D2V_PWR

1
IND-4D7UH-88-GP

GAP-CLOSE-PWR
G83
1
2

4
3
2
1

51124_VFB1

EC

G72

S
S
S
G

R521

DY
C663

R522
18KR3-GP

G72

SC33P50V3JN-GP

3D3V_S0

D
D
D
D

U71
FDS6690DS-GP

GAP-CLOSE-PWR

GAP-CLOSE-PWR
G81
1
2

Voutsetting=1.2V

L35

5
6
7
8

GAP-CLOSE-PWR
G82
1
2

G72

GAP-CLOSE-PWR
G77
1
2

1 MYALL DIS 0207

4
3
2
1

EC

SC10U25V0KX-3GP

S
S
S
G

GAP-CLOSE-PWR
G80
1
2

C662

G72

G72

5
6
7
8

C661

D
D
D
D

U70
FDS6612A-1-GP

GAP-CLOSE-PWR
G78
1
2

1
SC10U25V0KX-3GP

GAP-CLOSE-PWR
G76
1
2

1D2V_S0

DCBATOUT_51124

G74

TC40
ST220U4VDM-L6-GP

GAP-CLOSE-PWR
G84
1
2
GAP-CLOSE-PWR

51124_PGD1
51124_PGD2

G72

51124_VFB2

51124_DRVL2

R535

G72
251124_LL2_1 1
2 C672
0R3J-3-GP
SCD1U50V3ZY-GP

51124_VBST2

G72
G72

R533

TC43
TC42
SE330U2VDM-4-GP
SE330U2VDM-4-GP

G72

NIPPON 680uF 2.5V

ESR=13m

GAP-CLOSE-PWR
G92
1
2

51124_GND

Panasonic V Size 330uF 2V

ESR=9mohm, Iripple=3.0A

G93

GAP-CLOSE-PWR
G90
1
2
GAP-CLOSE-PWR
G91
1
2

G72

Vout=0.75V*(R1+R2)/R2

G72

GAP-CLOSE-PWR
G89
1
2

DY

4
3
2
1

51124_VBST1
251124_LL1_1 1
2C671
0R3J-3-GP
SCD1U50V3ZY-GP

GAP-CLOSE-PWR
G88
1
2

G72

51124_GND

C670

GAP-CLOSE-PWR
G87
1
2

G72

75KR3F-GP

51124_LL2 1
R536

1D05V_PWR

U74
FDS6690DS-GP

G72

GAP-CLOSE-PWR
G86
1
2

Voutsetting=1.051V

2
IND-2D2UH-46-GP

51124_DRVL1
R532
20KR3F-GP

NVVDD_S0
G85

L36

51124_DRVH2
51124_LL2

30K1R3F-GP

G72

1D05V_PWR

1D05V Iomax=7A
OCP>14A

51124_DRVL2

S
S
S
G

51124_LL1 1
R534

G72

G72
51124_GND

C669

SC10U25V0KX-3GP

G72

C668

U73
FDS6612A-1-GP

51124_GND

DCBATOUT_51124

DY

SC10U25V0KX-3GP

G72

DRVL1
DRVL2

VBST1
VBST2

51124_V5FILT

SC33P50V3JN-GP

R530 10KR2F-2-GP
0R2J-2-GP

D
D
D
D

20KR3F-GP

51124_GND

18
13
25
3

51124_DRVH1
51124_DRVH2

51124_TRIP2

G72
R531

PGND1
PGND2
GND
GND

51124_TRIP1

21
10

19
12

22
9

TPS51124RGER-GPU1

DRVH1
DRVH2

51124_TONSEL

S
S
S
G

DY
51124_GND

R528

5
6
7
8

G72
TRIP1
TRIP2

1
2

LL1
LL2

C666
C667
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP

DY
51124_GND

EN1
EN2

20
11

Vout=0.75V*(R1+R2)/R2

D
D
D
D

51124_LL1
51124_LL2

G72

51124_GND

G72

5
6
7
8

R527

23
8

17
14

0R2J-2-GP

51124_EN1_1
51124_EN2_1

2
2

TPAD30

0R2J-2-GP

TONSEL

PM_SLP_S3#
PM_SLP_S3#

G72

V5FILT
V5IN

16,18,29,32,36,37,52
16,18,29,32,36,37,52

0R2J-2-GP
1
1

G72

4
3
2
1

15
16

1 MYALL DIS 0206

51124_V5FILT

TP110

VFB1
VFB2

51124_GND

R529

NIPPON 220uF ESR=15mohm

R523

G72

R526

PGOOD1
PGOOD2

U72

VO1
VO2

C665
SC1U10V3ZY-6GP

1
6

G72

G72

51124_DRVL1

24
7

1D05V_PWR
1D2V_PWR
51124_VFB2
51124_VFB1

C664

SC4D7U10V5ZY-3GP

G72

R524
3D3R3J-L-GP

G72

2
5

R525

0R2J-2-GP
1

DY

1KR3F-GP

30K1R3F-GP

www.kythuatvitinh.com
5V_S5

GAP-CLOSE-PWR

GAP-CLOSE-PWR

51124_GND
<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

TONSEL

GND

OPEN

V5FILT

230k/CH1
283k/CH2

283k/CH1
346k/CH2

346k/CH1
423k/CH2

TPS51124 / NVDD/1D2V
Size
A3

Document Number

Date: Friday, February 10, 2006

4

Rev

SC

MYALL
Sheet
1

41

of

52

R519 DY
0R2J-2-GP
1
2

U27A
1D2V_S0

1 OF 14

1
2

SCD1U16V2ZY-2GP

G72

G72

G72

C165

MYALL SC
C108

TC37
ST330U2D5VDM-9GP

C46

BLM18BB221SN1D-GP

DY

1
2

C93

C130

1
P20
T20
T23
U20
U23
W20

G72

G72
2004/11/10 ADD

C148

SCD1U10V2MX-3GP

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5

1D2V_S0

SC4D7U6D3V3KX-GP

U13
U14
U15
U18
U19
V16
V17
W13
W14
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20

1D2V_S0

SC4D7U6D3V3KX-GP

G72

G72

G72
PEG_TXP6 G72

7
7 PEG_TXN6
1
1

7 PEG_RXP7
7 PEG_RXN7

2 C179
2 C178

G72

7 PEG_TXP7 G72
7 PEG_TXN7
1
1

7 PEG_RXP8
7 PEG_RXN8

2 C434
2 C435

G72
PEG_TXP8 G72

7
7 PEG_TXN8
1
1

7 PEG_RXP9
7 PEG_RXN9

2 C176
2 C177

G72

7 PEG_TXP9 G72
7 PEG_TXN9
1
1

7 PEG_RXP10
7 PEG_RXN10

2 C436
2 C437

G72

7 PEG_TXP10G72
7 PEG_TXN10
1
1

7 PEG_RXP11
7 PEG_RXN11

2 C175
2 C174

G72

7 PEG_TXP11G72
7 PEG_TXN11
1
1

7 PEG_RXP12
7 PEG_RXN12

2 C439
2 C438

G72
PEG_TXP12G72

7
7 PEG_TXN12
1
1

7 PEG_RXP13
7 PEG_RXN13

2 C173
2 C172

G72

7 PEG_TXP13G72
7 PEG_TXN13
1
1

7 PEG_RXP14
7 PEG_RXN14

2 C440
2 C441

G72

7 PEG_TXP14G72
7 PEG_TXN14
1
1

7 PEG_RXP15
7 PEG_RXN15

2 C171
2 C170

G72
PEG_TXP15G72

7
7 PEG_TXN15

AM18
AM19

PEX_RX5
PEX_RX5#

SCD1U10V2KX-5GP
PEX_TX6
PEX_TX6#
SCD1U10V2KX-5GP
PEG_TXP6
PEG_TXN6

AG20
AH20

PEX_TX6
PEX_TX6#

AK19
AK20

PEX_RX6
PEX_RX6#

SCD1U10V2KX-5GP
PEX_TX7
PEX_TX7#
SCD1U10V2KX-5GP
PEG_TXP7
PEG_TXN7

AG21
AH21

PEX_TX7
PEX_TX7#

AL20
AL21

PEX_RX7
PEX_RX7#

SCD1U10V2KX-5GP
PEX_TX8
PEX_TX8#
SCD1U10V2KX-5GP
PEG_TXP8
PEG_TXN8

AK21
AJ21

PEX_TX8
PEX_TX8#

AM21
AM22

PEX_RX8
PEX_RX8#

SCD1U10V2KX-5GP
PEX_TX9
PEX_TX9#
SCD1U10V2KX-5GP
PEG_TXP9
PEG_TXN9

AJ22
AH22

PEX_TX9
PEX_TX9#

AK22
AK23

PEX_RX9
PEX_RX9#

SCD1U10V2KX-5GP
PEX_TX10
PEX_TX10#
SCD1U10V2KX-5GP
PEG_TXP10
PEG_TXN10

AG23
AH23

PEX_TX10
PEX_TX10#

AL23
AL24

PEX_RX10
PEX_RX10#

SCD1U10V2KX-5GP
PEX_TX11
PEX_TX11#
SCD1U10V2KX-5GP
PEG_TXP11
PEG_TXN11

AK24
AJ24

PEX_TX11
PEX_TX11#

AM24
AM25

PEX_RX11
PEX_RX11#

SCD1U10V2KX-5GP
PEX_TX12
PEX_TX12#
SCD1U10V2KX-5GP
PEG_TXP12
PEG_TXN12

AJ25
AH25

PEX_TX12
PEX_TX12#

AK25
AK26

PEX_RX12
PEX_RX12#

SCD1U10V2KX-5GP
PEX_TX13
PEX_TX13#
SCD1U10V2KX-5GP
PEG_TXP13
PEG_TXN13

AH26
AG26

PEX_TX13
PEX_TX13#

AL26
AL27

PEX_RX13
PEX_RX13#

SCD1U10V2KX-5GP
PEX_TX14
PEX_TX14#
SCD1U10V2KX-5GP
PEG_TXP14
PEG_TXN14

AK27
AJ27

PEX_TX14
PEX_TX14#

AM27
AM28

PEX_RX14
PEX_RX14#

AJ28
AH27

PEX_TX15
PEX_TX15#

AL28
AL29

PEX_RX15
PEX_RX15#

SCD1U10V2KX-5GP
PEX_TX15
PEX_TX15#
SCD1U10V2KX-5GP
PEG_TXP15
PEG_TXN15

G72

PEX_PLLAVDD
PEX_PLLDVDD
PEX_PLLGND

AF15
AE15
AE16

1
2

1
2

1
2

MYALL SC
1

1
2

C97
SCD01U25V2KX-3GP

C110
SCD01U25V2KX-3GP

G72

C134

C136

SCD1U10V2MX-3GP SC1U10V3ZY

G72

G72

TC38
ST330U2D5VDM-9GP

G72

3D3V_S0

PLACE NEAR GPU

AC11
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
L10
L7
L8
M10

G72

G72

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12

1
2

C103
SCD01U25V2KX-3GP

SC1U10V3ZY

G72

C90
SC4700P50V3KX-1GP

G72

C112
2004/11/10
SCD022U16V2KX-3GP

CHANGE
D1U*1 / 4700P *1 /
D022U*1 / 1U*1

G72
1

C197
SC1U10V3ZY

G72

C153
SCD01U25V2KX-3GP

G72

G72

2
BLM18BB221SN1D-GP

G72

C198
C192
SCD1U10V2MX-3GP SC4D7U6D3V3KX-GP

G72
1D2V_S0

L13
1
C194
SC1U10V3ZY

G72

C140
SCD01U25V2KX-3GP

G72

G72

PLACE NEAR BALLS

NC#AM10
NC#AM8
NC#AM9
NC#B32
NC#J6

1D2V_S0
L12

2 C432
2 C433

C128
SCD01U25V2KX-3GP

G72

2004/11/10 CHANGE
220P*6 / 0.1U*4 /
1U*2 / 100P*3

C91

SC1U10V3ZY

1
1

7 PEG_RXP6
7 PEG_RXN6

G72

C113

G72

7 PEG_TXP5 G72
7 PEG_TXN5

PEX_TX5
PEX_TX5#

AJ19
AH19

G72

SCD1U10V2KX-5GP
PEX_TX5
PEX_TX5#
SCD1U10V2KX-5GP
PEG_TXP5
PEG_TXN5

G72

BLM18BB221SN1D-GP

2 C181
2 C180

G72

SC100P50V2JN-U

1
1

7 PEG_RXP5
7 PEG_RXN5

C125

PEX_RX4
PEX_RX4#

C221

PEX_TX4
PEX_TX4#

AL17
AL18

AK18
AJ18

SCD1U10V2KX-5GP
PEX_TX4
PEX_TX4#
SCD1U10V2KX-5GP
PEG_TXP4
PEG_TXN4

G72

SC100P50V2JN-U

2 C430
2 C431

7 PEG_TXP4 G72
7 PEG_TXN4

SC100P50V2JN-U

1
1

7 PEG_RXP4
7 PEG_RXN4

PEX_RX3
PEX_RX3#

C123

AK16
AK17

C114

SC220P50V2KX-3GP

SC220P50V2KX-3GP

C96

G72

7 PEG_TXP3 G72
7 PEG_TXN3

C104

PEX_TX3
PEX_TX3#

PEX_RX2
PEX_RX2#

AG18
AH18

AL15
AL16

SCD1U10V2KX-5GP
PEX_TX3
PEX_TX3#
SCD1U10V2KX-5GP
PEG_TXP3
PEG_TXN3

2005/11/11 change that base on demo circuit

G72SC220P50V2KX-3GP
G72

2 C183
2 C182

C122

G72SC220P50V2KX-3GP
G72

G72

1
1

G72

NVVDD_S0

SC220P50V2KX-3GP

7
7 PEG_TXN2

7 PEG_RXP3
7 PEG_RXN3

C115

SC220P50V2KX-3GP

G72
PEG_TXP2 G72

C105

PEX_TX2
PEX_TX2#

AG17
AH17

SCD1U10V2KX-5GP
PEX_TX2
PEX_TX2#
SCD1U10V2KX-5GP
PEG_TXP2
PEG_TXN2

2 C428
2 C429

1
1

7 PEG_RXP2
7 PEG_RXN2

PEX_RX1
PEX_RX1#

AM14
AM15

PEG_TXP1
PEG_TXN1

7 PEG_TXP1 G72
7 PEG_TXN1

G72

PLACE NEAR BALLS

PEX_TX1
PEX_TX1#

AH16
AG16

PEX_RX0
PEX_RX0#

SCD1U10V2KX-5GP
PEX_TX1
PEX_TX1#
SCD1U10V2KX-5GP

PEX_TX0
PEX_TX0#

AK13
AK14

AJ15
AK15

SCD1U10V2KX-5GP
PEX_TX0
PEX_TX0#
SCD1U10V2KX-5GP
PEG_TXP0
PEG_TXN0

G72

PEX_REFCLK
PEX_REFCLK#

2 C185
2 C184

AH14
AJ14

1
1

CLK_PCIE_PEG
CLK_PCIE_PEG#

G72

7 PEG_RXP1
7 PEG_RXN1

VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37

C144
C229
SCD47U25V5KX-2GP

SCD1U10V2MX-3GP

2 C426
2 C427

7 PEG_TXP0 G72
7 PEG_TXN0

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

K16
K17
N13
N14
N16
N17
N19
N20
P13
P14
P16
P17
P19
R16
R17
T13
T14
T15
T18
T19

G72

www.kythuatvitinh.com
1
1

7 PEG_RXP0
7 PEG_RXN0

AM12
AM11

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19

TC35
ST330U2D5VDM-9GP

L6

SCD1U10V2MX-3GP

DY

SCD1U16V
R332
100R2F-L1-GP-U
C424
R331
100R2F-L1-GP-U
1
2G72_PEX_TSCLK_OUT
1
2 PEX_TSTCLK
1
2 PEX_TSTCLK#

DY

3 CLK_PCIE_PEG
3 CLK_PCIE_PEG#

RFU0
RFU1

G72

PLACE NEAR BALLS

SC1U16V3KX-2GP

1D2V_S0

AG12
AH13

G72

C132

SC10U10V6ZY-U

SC MYALL
DY

PEX_RST#

G72

PEX_RST# AH15

G72

R516 DY
0R2J-2-GP
1
2

G72

C166

SC4D7U6D3V3KX-GP

R111 DY
0R2J-2-GP
1
2

29 GMODULE_RST#

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

C131

SC1U16V3KX-2GP

KBC GPIO5

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10

C147
SCD1U10V2MX-3GP

R514 G72
10KR2J-3-GP

PLACE NEAR GPU

MYALL SC
C152
SCD1U10V2MX-3GP

U1D
5K1R2F-2-GP
TSAHCT125PW-GP

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

G72

11

R515
12

AD23
AF23
AF24
AF25
AG24
AG25

13

R112 G72
0R2J-2-GP
1
2

PLT_RST1#

PLACE NEAR BALLS

7,16,18,25,29,31,47

14

5V_S0

G72

C195
C186
SCD1U10V2MX-3GP SC4D7U6D3V3KX-GP

G72
PLACE NEAR GPU

AM10
AM8
AM9
B32
J6

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

G72M

G72

Size
Document Number
Custom

Rev

MYALL

SA

Date: Friday, February 10, 2006

5

Sheet
1

42

of

52

3D3V_S0

L11
BLM18BB221SN1D-GP

G72

2004/11/10 ADD 220 Ohm at 100MHz

C135

1
1

C149

6 OF 14

U27F

C139

AD10

DACA_VDD

DACA_VREF

AH10

DACA_VREF

AH9

DACA_RSET

C419
SCD01U25V2KX-3GP

SC4700P50V2KX

SC4D7U6D3V3KX-GP

DACA_VDD

SC470P50V2KX

DACA_RSET

I2CA_SCL
I2CA_SDA 1
R68

K2
J3

I2CA_SCL
I2CA_SDA

G72

AF10
AK10

DACA_HSYNC
DACA_VSYNC

G72_CRT_EDID_CLK
G72_CRT_EDID_DAT

14
14

G72

HSYNC 14
VSYNC 14

DACA_RED

AH11

CRT_RED 14

DACA_GREEN

AJ12

CRT_GREEN 14

DACA_BLUE

AH12

CRT_BLUE 14

CRT

R115
R113
R114
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP

50 ohm trace to filter

AG9

DACA_IDUMP

MYALL SB DELETE R326 FROM DY

G72

G72

G72

R327
124R2F-U-GP

www.kythuatvitinh.com
G72

G72

1
2
R70 2 33R2J-L1-GP
33R2J-L1-GP

G72

37.5 ohm trace to 150R resistor G72

G72

G72
CLOSE TO G72

2004/11/10 CHANGE TO 3D3V_S0

7 OF 14

R104 G72
10KR2F-2-GP
1
2

8 OF 14

U27H

AD7

DACC_VDD

AH4

DACC_VREF

AF5

DACC_RSET

I2CB_SCL
I2CB_SDA

R84

H4
J4

DACC_HSYNC
DACC_VSYNC

AG7
AG5

DACC_RED

AF6

DACC_GREEN

AG6

DACC_BLUE

AE5

DACC_IDUMP

AG4

G72

V8 DACB_VDD
2 10KR2F-2-GP
R5

DACB_VREF

R7

DACB_RSET

DACB_RED

R6

DACB_GREEN

T5

DACB_BLUE

T6

DACB_IDUMP

V7

G72

2D5V_S0

13 OF 14
2004/11/10 ADD 220 Ohm at 100MHz
L10

G72

PLLGND

PLACE R308 CLOSE TO G72 MYALL SB

MYALL SB CAANGE
T1

XTALSSIN

XTALOUTBUFF

BXTALOUT

R308
2
22R2J-2-GP

XTALIN

XTALOUT

G72

U2 XTALOUT

DY
1
C403
SC12P50V3JN-GP

10MIL_G2G_20MIL

G72

SC

2004/11/10 ADD

XTAL-27MHZ-16-GP

G72

G72

C48
SC4700P50V3KX-1GP

G72

SB CHANGE

10MIL_G2G_20MIL

1
2

C116

1
2

C47

G72
MYALL

X3

BLM18BB221SN1D-GP

G72

XTALOUTBUFF 48

R309
10KR2J-2-GP

G72

2004/11/10 ADD 220 Ohm at 100MHz

L7

T2

XTALIN U1

R311
10KR2J-2-GP

2D5V_S0

PLLVDD
DISP_PLLVDD

G72

G72

48 SSFOUT

G72

T9
T10
U10

C106
SC1U6D3V2KX-GP
SC4700P50V2KX
SCD1U10V2MX-3GP

SC1U6D3V2KX-GP

G72

C109

C111

DISP_PLLVDD

G72

G72

U27M

2
C117
BLM18BB221SN1D-GP

SC4D7U6D3V3KX-GP

1
C102

U27G

C406
SC12P50V3JN-GP

SC
<Core Design>

SCD1U10V2MX-3GP
SC4D7U6D3V3KX-GP

The R784 (XTALSSIN 10K

pull-down) should be NO
STUFF when spread chips
is used.
Dummy R784

G72

G72

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT,TV OUT
Size
Document Number
Custom

Rev

MYALL

Date: Friday, February 10, 2006

5

SA
Sheet
1

43

of

52

U27I

9 OF 14
C418

AM4

2
SCD01U16V2KX-3GP

2D5V_S0
2005/11/10 CHANGE TO 220 Ohms at 100MHz

IFPABPLLVDD

2
1

C141
SC4700P50V2KX

SC4D7U6D3V3KX-GP

G72
SC4D7U6D3V3KX-GP

C412 BLM18BB221SN1D-GPC411

C410

AC9

G72

AJ9

LVDS_TXACLK-

25MIL

LVDS_TXACLK- 13

IFPA_TXC

AK9

LVDS_TXACLK+

25MIL

LVDS_TXACLK+ 13

IFPA_TXD0#
IFPA_TXD0

AJ6
AH6

LVDS_TXAOUT0LVDS_TXAOUT0+

25MIL
25MIL

LVDS_TXAOUT0- 13
LVDS_TXAOUT0+ 13

IFPA_TXD1#
IFPA_TXD1

AH7
AH8

LVDS_TXAOUT1LVDS_TXAOUT1+

25MIL
25MIL

LVDS_TXAOUT1- 13
LVDS_TXAOUT1+ 13

IFPA_TXD2#
IFPA_TXD2

AK8
AJ8

LVDS_TXAOUT2LVDS_TXAOUT2+

25MIL
25MIL

LVDS_TXAOUT2- 13
LVDS_TXAOUT2+ 13

IFPAB_RSET

IFPAB_PLLVDD

AL5

G72

L23

IFPA_TXC#
IFPAB_VPROBE

R325
1KR2F-3-GP

SC470P50V2KX

www.kythuatvitinh.com
AD9

G72

G72

G72

IFPAB_PLLGND

G72

1D8V_S0

IFPA_TXD3#
IFPA_TXD3

AH5
AJ5

IFPB_TXC#
IFPB_TXC

AL4
AK4

LVDS_TXBCLKLVDS_TXBCLK+

25MIL
25MIL

LVDS_TXBCLK- 13
LVDS_TXBCLK+ 13

IFPB_TXD4#
IFPB_TXD4

AM5
AM6

LVDS_TXBOUT0LVDS_TXBOUT0+

25MIL
25MIL

LVDS_TXBOUT0- 13
LVDS_TXBOUT0+ 13

IFPB_TXD5#
IFPB_TXD5

AL7
AM7

LVDS_TXBOUT1LVDS_TXBOUT1+

25MIL
25MIL

LVDS_TXBOUT1- 13
LVDS_TXBOUT1+ 13

IFPB_TXD6#
IFPB_TXD6

AK5
AK6

LVDS_TXBOUT2LVDS_TXBOUT2+

25MIL
25MIL

LVDS_TXBOUT2- 13
LVDS_TXBOUT2+ 13

IFPB_TXD7#
IFPB_TXD7

AL8
AK7

IFPC_TXC#
IFPC_TXC

AM3
AM2

IFPC_TXD0#
IFPC_TXD0

AE1
AE2

IFPC_TXD1#
IFPC_TXD1

AF2
AF1

IFPC_TXD2#
IFPC_TXD2

AH1
AG1

IFPD_TXC#
IFPD_TXC

AH2
AG3

IFPD_TXD4#
IFPD_TXD4

AJ1
AK1

IFPD_TXD5#
IFPD_TXD5

AL1
AL2

IFPD_TXD6#
IFPD_TXD6

AJ3
AJ2

L24

1
2

SB

C415

C95

SC4700P50V2KX
SC4D7U6D3V3KX-GP

G72

C413

AF9

IFPA_IOVDD

AF8

IFPB_IOVDD

SC470P50V2KX

G72

G72

G72

SC4700P50V2KX

G72

1
2

C154

SC4D7U6D3V3KX-GP

G72

C414

BLM18BB221SN1D-GP
2005/11/10 CHANGE TO 220 Ohms at 100MHz

IFPAIOVDD

C94

SC470P50V2KX

G72

G72

2005/11/10 ADD

U27J

AK3

IFPCD_VPROBE

AH3

IFPCD_RSET

10 OF 14

AA10

IFPCD_PLLVDD

8
7
6
5

G72_PLLVDD

RN9
SRN10KJ-4-GP

2005/11/10 ADD

1
2
3
4

G72

AB10

IFPCD_PLLGND

G72_IFPC_IOVDD

AD6

IFPC_IOVDD

G72_IFPD_IOVDD

AE7

IFPD_IOVDD

G72
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LVDS,TMDS
Size
Document Number
Custom
Date:
5

Rev

MYALL

SA

Friday, February 10, 2006

Sheet
1

44

of

52

U22
U26
FBA_BA0
FBA_BA1

46,50 FBA_BA0
46,50 FBA_BA1
46,50 FBA_A[12..0]

FBA_A12
FBA_A11
FBA_A10
FBA_A9
FBA_A8
FBA_A7
FBA_A6
FBA_A5
FBA_A4
FBA_A3
FBA_A2
FBA_A1
FBA_A0

G72_64MB

L2
L3

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBAD15
FBAD14
FBAD13
FBAD12
FBAD11
FBAD10
FBAD9
FBAD8
FBAD7
FBAD6
FBAD5
FBAD4
FBAD3
FBAD2
FBAD1
FBAD0

46,50

FBA_BA0
FBA_BA1

46,50 FBA_BA0
46,50 FBA_BA1

L2
L3

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

CK
CK

K2

CKE

FBA_CS0#

L8

CS

FBA_WE#

K3

WE

FBA_RAS#

K7

RAS

46,50 FBA_A[12..0]

FBA_A12
FBA_A11
FBA_A10
FBA_A9
FBA_A8
FBA_A7
FBA_A6
FBA_A5
FBA_A4
FBA_A3
FBA_A2
FBA_A1
FBA_A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

FBAD31
FBAD30
FBAD29
FBAD28
FBAD27
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD21
FBAD20
FBAD19
FBAD18
FBAD17
FBAD16

FBAD[63..0]

46,50

www.kythuatvitinh.com

* "Place the
differential
termination
resistor at the
end of the
transmission
line"

50 FBACLK0#
50 FBACLK0

FBA_CKE

46,50 FBA_CKE

G72

46,50 FBA_CS0#

R69
1
10KR2J-3-GP
FBA_CS0#
FBA_WE#

46,50 FBA_WE#

46,50 FBA_RAS#
46,50 FBA_CAS#

K2

CKE

L8

CS

WE

FBA_RAS#

K7

RAS

FBA_CAS#

L7

CAS

F3
B3

ODT

LDM
UDM

K9

ODT

50 FBADQSP0
50 FBADQSN0

F7
E8

LDQS
LDQS

R75
50 FBADQSP1
1KR2F-3-GP
50 FBADQSN1

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

46,50 ODT

1D8V_S0

FBAREF0

1
R77
1KR2F-3-GP

C55

G72_64MB

CK
CK

K3

50 FBADQM0
50 FBADQM1

G72_64MB

K8
J8

SCD047U16V3KX-GP

G72_64MB

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBA_CKE

46,50 FBA_CKE

46,50 FBA_CS0#

46,50 FBA_WE#

46,50 FBA_RAS#

A1
E1
J9
M9
R1

J1
J7

FBACLK0#
FBACLK0

50 FBACLK0#
50 FBACLK0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDDL
VSSDL

1D8V_S0

1D8V_S0

FBA_CAS#

L7

CAS

F3
B3

LDM
UDM

K9

ODT

50 FBADQSP2
50 FBADQSN2

F7
E8

LDQS
LDQS

50 FBADQSP3
50 FBADQSN3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

46,50 FBA_CAS#
50 FBADQM2
50 FBADQM3

G72

46,50 ODT

ODT

FBAREF0

G72

MYALL SC

C101
SCD047U16V3KX-GP

G72_64MB

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBACLK0#

TC39
ST330U2D5VDM-9GP

120R2F-GP

R55

FBACLK0

FBAD[63..0]

G72

HY5PS561621A-33GP
HY5PS561621A-33GP

Decoupling for left MEMORY

Place around the MEM

Decoupling for right MEMORY

Place around the MEM

1D8V_S0

1
C56
SCD01U25V2KX-3GP

C40
SCD1U16V2KX-3GP
2

C54
SCD1U16V2KX-3GP
2

C42
SCD1U16V2KX-3GP
2

1
2

G72_64MB

G72_64MB

C57
SCD1U16V2KX-3GP
2

G72_64MB

G72_64MB
G72_64MB

C41
SCD1U16V2KX-3GP
2

G72_64MB

C60
SC4D7U6D3V3KX-GP
2

C74
SCD01U25V2KX-3GP

1
C87
SCD01U25V2KX-3GP
2

1
C75
SCD01U25V2KX-3GP
2

1
C88
SCD1U16V2KX-3GP
2

1
C77
SCD1U16V2KX-3GP
2

C85
SCD1U16V2KX-3GP
2

C59
SC4D7U6D3V3KX-GP
2

1D8V_S0

G72_64MB

G72_64MB

G72_64MB

G72_64MB

G72_64MB

G72_64MB G72_64MB
G72_64MB
G72_64MB G72_64MB

1
2

SC100P50V2JN-3GP

G72_64MB

G72_64MB

G72_64MB

<Core Design>
C67
SC1KP16V2KX-GP

1
C156

C81

SC1KP16V2KX-GP

C76

SC100P50V2JN-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

G72_64MB
Title

VRAM (1ST 1/2)

Size
Document Number
Custom
Date:

Rev

MYALL

SA

Friday, February 10, 2006

Sheet
1

45

of

52

U30
U29
FBA_BA0
FBA_BA1

45,50 FBA_BA0
45,50 FBA_BA1
45,50 FBA_A[12..0]

FBA_A12
FBA_A11
FBA_A10
FBA_A9
FBA_A8
FBA_A7
FBA_A6
FBB_A5
FBB_A4
FBB_A3
FBB_A2
FBA_A1
FBA_A0

50 FBB_A[5..2]

G72_128MB
R110
FBACLK1

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

FBAD55
FBAD54
FBAD53
FBAD52
FBAD51
FBAD50
FBAD49
FBAD48
FBAD39
FBAD38
FBAD37
FBAD36
FBAD35
FBAD34
FBAD33
FBAD32

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBAD[63..0]

45,50

FBA_BA0
FBA_BA1

L2
L3

BA0
BA1

FBA_A12
FBA_A11
FBA_A10
FBA_A9
FBA_A8
FBA_A7
FBA_A6
FBB_A5
FBB_A4
FBB_A3
FBB_A2
FBA_A1
FBA_A0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

45,50 FBA_BA0
45,50 FBA_BA1
45,50 FBA_A[12..0]

50 FBB_A[5..2]

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBAD63
FBAD62
FBAD61
FBAD60
FBAD59
FBAD58
FBAD57
FBAD56
FBAD47
FBAD46
FBAD45
FBAD44
FBAD43
FBAD42
FBAD41
FBAD40

FBAD[63..0]

45,50

1D8V_S0

1D8V_S0

www.kythuatvitinh.com
50 FBACLK1#
50 FBACLK1

FBA_CKE

45,50 FBA_CKE

45,50 FBA_RAS#
45,50 FBA_CAS#

CKE

L8

CS

K3

WE

FBA_RAS#

K7

RAS

FBA_CAS#

L7

CAS

F3
B3

LDM
UDM

50 FBADQM4
50 FBADQM6

ODT

K9

ODT

50 FBADQSP4
50 FBADQSN4

F7
E8

LDQS
LDQS

R118
50 FBADQSP6
1KR2F-3-GP
50 FBADQSN6

B7
A8

UDQS
UDQS

45,50 ODT

1D8V_S0

CK
CK

K2

FBA_WE#

45,50 FBA_CS0#

45,50 FBA_WE#

K8
J8

G72_128MB

FBAREF1

VREF
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

R119
1KR2F-3-GP

C138

G72_128MB

J2
A2
E2
L1
R3
R7
R8

SCD047U16V3KX-GP

G72_128MB

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBACLK1#
FBACLK1

50 FBACLK1#
50 FBACLK1

FBA_CKE

45,50 FBA_CKE

K8
J8

CK
CK

K2

CKE

L8

CS

FBA_WE#

K3

WE

FBA_RAS#

K7

RAS

FBA_CAS#

L7

CAS

F3
B3

LDM
UDM

K9

ODT

50 FBADQSP5
50 FBADQSN5

F7
E8

LDQS
LDQS

50 FBADQSP7
50 FBADQSN7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

45,50 FBA_CS0#

45,50 FBA_WE#

45,50 FBA_RAS#
45,50 FBA_CAS#
50 FBADQM5
50 FBADQM7

ODT

45,50 ODT

FBAREF1

FBAREF1

FBACLK1#
FBACLK1

C196

120R2F-GP

* "Place the
differential
termination
resistor at the
end of the
transmission
line"
C

FBACLK1#

L2
L3

SCD047U16V3KX-GP

G72_128MB

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

HY5PS561621A-33GP
HY5PS561621A-33GP

G72_128MB

G72_128MB
B

Decoupling for left MEMORY

Place around the MEM

Decoupling for right MEMORY

Place around the MEM

1D8V_S0

G72_128MB

G72_128MB

G72_128MB

C70
C73
SC100P50V2JN-3GP
SC100P50V2JN-3GP

1
C69
C68
SC1KP16V2KX-GP
SC1KP16V2KX-GP

G72_128MB G72_128MB G72_128MB G72_128MB

G72_128MB G72_128MB G72_128MB

1
C133
C71
SC1KP16V2KX-GP
SC1KP16V2KX-GP

1
2

1
2

G72_128MB

G72_128MB G72_128MB G72_128MB

C66
C161
C188
C160
C187
C163
C169
C44
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD01U25V2KX-3GP
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
SCD01U25V2KX-3GP
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
G72_128MB

C86

G72_128MB G72_128MB G72_128MB G72_128MB

C79
C193
SC100P50V2JN-3GP
SC100P50V2JN-3GP

C145
C121
C124
C137
C120
C142
C143
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP

1D8V_S0

G72_128MB G72_128MB G72_128MB G72_128MB

<Core Design>

G72_128MB

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VRAM (1ST 2/2)

Size
Document Number
Custom
Date:
5

Rev

MYALL

SA

Friday, February 10, 2006

Sheet
1

46

of

52

U27K

3D3V_S0

3D3V_S0

U27N

11 OF 14

G72

G72

L1

MIOACAL_PD_VDDQ

L3

L2

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

AA8
AB7
AB8
AC6
AC7

MIOA_D0 49
C129
SC1U6D3V2KX-GP

MIOA_D1 49

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11

MIOA_D6 49

C100
SC1U6D3V2KX-GP

MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4

C92
SC1U6D3V2KX-GP

14 OF 14

M7
M8
R8
T8
U9

MIOA_D8 49
MIOA_D9 49

G72

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4

C126
SC1U6D3V2KX-GP

G72

Y1

MIOBCAL_PD_VDDQ

MIOACAL_PU_GND

Y3

MIOBCAL_PU_GND

MIOA_VREF

Y2

MIOB_VREF

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
RFU13
RFU14
RFU15
RFU16

MYALL SB DELETE TESTPAD

MYALL SB DELETE TESTPAD

TP108

R3
R1
P1
P3

MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
MIOA_CTL3

TPAD30

RFU17
RFU18
RFU19
RFU20

G72

MIOB_VSYNC
MIOB_HSYNC
MIOB_DE
MIOB_CTL3

R4
P4
M5

MIOB_D0
MIOB_D1

AC3
AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5
W3
V1
Y5
W1

MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11

MIOB_D0 49
MIOB_D1 49
MIOB_D3 49
MIOB_D4 49
MIOB_D5 49
MIOB_D7 49
MIOB_D8 49
MIOB_D9 49
MIOB_D10 49
MIOB_D11 49

W4
W5
V5
Y6
AE3
AF3
AD1
AD3

2005/11/10 ADD

AD4
AD5
AE4

www.kythuatvitinh.com
1

MIOB_CLKOUT
MIOB_CLKOUT#
MIOB_CLKIN

MIOA_CLKOUT
MIOA_CLKOUT#
MIOA_CLKIN

R72
10KR2J-2-GP

G72

G72

G72

R322
10KR2J-2-GP

G72

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

CLAMP

F6

I2CC_SCL
I2CC_SDA

G2
G1

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12

K3
H1
K5
G5
E2
J5
G6
K6
E1
D2
H5
F4
E3

4
3
RN48
SRN2K2J-1-GP

DY

R307
10KR2J-2-GP

G72
1

DY

12 OF 14

U27L

DY

J1

THERMDN

THERMDP

K1

THERMDP

C399
SC2200P50V2KX-2GP
TP35 TPAD30

G72

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

G72
R333
10KR2J-2-GP

DY

R328
10KR2J-2-GP

AJ11
AK11
AK12
AL12
AL13

G72

I2CC_SCL
I2CC_SDA

G72

C398

1
2
3
4

13

1
G72
2K2R2J-2-GP

2
3D3V_S0

G72

G72

I2CC_SCL
I2CC_SDA

VCC
DXP
DXN
OVERT#

SCLK
SDA
ALERT#
GND

8
7
6
5

G72_ALERT-

VGA_THERM_SHDN#

13
13

R294
100KR2J-1-GP

U24

G72

G72_LCD_EDID_CLK
G72_LCD_EDID_DAT

NV_LCDVDD_ON#
NV_BL_ON 29

R295

R302
10KR2J-3-GP

CHECK I2C FOR LCD

2005/11/10 ADD

2
R301
200R2F-L-GP

2 33R2J-L1-GP
2 33R2J-L1-GP

G72
G72

3D3V_S0

SCD1U10V2MX-3GP

R296 1
R298 1

THERMDN

1
2

Please close to the GPU

R329
10KR2J-2-GP

DY

R330
10KR2J-2-GP

R61
10KR2J-2-GP

SB

G72
MAX6649MUA-1-GP

G72
CLOSE TO KBC ?

Q22
2N7002PT-U

R303
VGA_THERM_SHDN#
2
0R2J-L1-GP

19 OVERT#

<Core Design>

G72

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

G72

ROM , Spread Specturm

PLT_RST1# 7,16,18,25,29,31,42

Size
Document Number
Custom
Date:

Rev

MYALL

SA

Friday, February 10, 2006

Sheet
1

47

of

52

U27D

4 OF 14

AA12
AA2
AA21
AA31
AB27
AB6
AC10
AC23
AC29
AC4
AD16
AD17
AD2
AD31
AE17
AE27
AE6
AF11
AF26
AF29

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119

K10
K23
K29
K4
L27
L6
M12
M2
M21
M31
N15
N18
N29
N4
P15
P18
P27
P6
R13
R14

AF4
AF7
AG10
AG11
AG14
AG15
AG19
AG2
AG22
AG31
AG8
AH24
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ26
AJ29

GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39

GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139

R15
R18
R19
R2
R20
R31
T16
T17
T24
T29
T4
U16
U17
U24
U29
U8
V13
V14
V15
V18

AJ4
AJ7
AK2
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AL3
AL6
AL9
AM13
AM16
AM17
AM20
AM23
AM26
AM29

GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59

GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151

V19
V2
V20
V31
W15
W18
W27
W6
Y15
Y18
Y29
Y4

B12
B15
B18
B21
B24
B27
B3
B30
B6
B9
C2
C31
D10
D13
D16
D17
D20
D23
D26
D29

GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79

www.kythuatvitinh.com
AA4

ROM_SO
ROM_SI
ROM_SCLK

AA6
W2
AA7

I2CH_SCL
I2CH_SDA

U3
V3
U6
U5
U4
V4
V6

RFU6
RFU7
RFU8
RFU9
RFU10
RFU11
RFU12

G3
H3

BUFRST#

F3

STEREO

T3

SWAPRDY_A
TESTMEMCLK
TESTMODE
MCG0
MCG1

3D3V_S0

M6

1
R71

A26
H2
AL10
AG13

G72

2
10KR2J-2-GP
G72_TESTMBMCLK

TESTMODE

MEMSTRAPSEL0
MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3

AE26
AD26
AH31
AH32

MYALL SB DELETE

ROMCS#

STRAP

2005/11/10 ADD
R293
10KR2J-2-GP

G72

R304
10KR2J-2-GP

G72

G72

Spread Specturm
U28
ASM3P2872AF-060R-GP

GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

1
2
3

43 XTALOUTBUFF

REFOUT
VSS
XOUT
MODOUT
XIN/CLKIN
VDD

3D3V_S0

SC
R517

6
5
4

SSFOUT 43

G72

22R2J-2-GP

C409
SCD1U16V

G72
2

D4
D7
F11
F14
F19
F2
F22
F25
F31
F8
G26
G29
G4
G7
H27
H6
J16
J17
J2
J31

F1

5 OF 14

U27E

G72

C404
SCD1U16V

G72

R518

2
0R2J-L1-GP

DY
1 MYALL 2006/02/10
G72

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ROM , Spread Specturm

Size
Document Number
Custom
Date:
5

Rev

MYALL

SA

Friday, February 10, 2006

Sheet
1

48

of

52

STRAPS, Mechanical Parts

www.kythuatvitinh.com
3D3V_S0

Bit Signal

Values

R312

MIOA_D1

MIOA_D1 47

G72

2KR2-GP

MIOA_D1:

SUB_VENDOR

MIOB_D0

1
R106

2
10KR2J-2-GP

MIOB_D0:

RAM_CFG_0

2
10KR2J-2-GP

MIOB_D1

1
R103

2
G7210KR2J-2-GP

MIOB_D1:

RAM_CFG_1

1
R324

DY
2
G7210KR2J-2-GP

MIOB_D8

1
R107

2
10KR2J-2-GP

MIOB_D8:

RAM_CFG_2

1
R320

2
10KR2J-2-GP

MIOB_D9

1
R101

2
10KR2J-2-GP

MIOB_D9:

RAM_CFG_3

MIOB_D2:

CRYSTAL_0

MIOB_D6:

CRYSTAL_1

MIOA_D7:

TV_MODE_0

MIOA_D10:

TV_MODE_1

MIOB_D4:

PCI_DEVID_0

2
10KR2J-2-GP

G72_128MB_S

DY

0000 RFU
0001 8Mx32 BGA 1.8V
0010 RFU
0011 RFU
0100 4Mx32 BGA 1.8V
0101 RFU
0110 RFU
0111 RFU
0011 16MX16

47 MIOA_D6
47 MIOA_D8

47 MIOB_D5

MIOB_D4

MIOB_D5

MIOB_D3

47 MIOB_D3

MIOB_D11

47 MIOB_D0
47 MIOB_D1

00 13.500 MHz
01 14.31818 MHz
10 27.000 MHz
11 UNKNOWN

00 SECAM
01 NTSC
10 PAL
11 CRT

R97
47 MIOB_D4

1000 RFU
1001 RFU
1010 RFU
1011 RFU
1100 RFU
1101 RFU
1110 RFU
1111 RFU

G72_64MB_S

SB

47 MIOA_D9

0 NO_BIOS
1 READ FROM BIOS

G72_HYNIX

1
R321

1
R323

G72_INFINEON

2
G72
R86
2KR2-GP
2
G72
R87
2KR2-GP
1
2
G72
R82
2KR2-GP
1
2

MIOB_D5:

PCI_DEVID_1

MIOB_D3:

PCI_DEVID_2

MIOB_D11:

PCI_DEVID_3

1000 (default 0x00FC)

0111 G72MV

DY
2KR2-GP
R78

MIOA_D0

47 MIOA_D0
47 MIOB_D8
47 MIOB_D9

SB

2KR2-GP
R80

47 MIOB_D11

MIOA_D6

SC CHANGE 001

G72

R314

G72

2
2KR2-GP

MIOA_D8

MIOA_D9

G72

R79

MIOA_D0:

PEX_PLL_EN_TERM100

MIOA_D6:

3GIO_PADCFG_LUT_ADDR[0]

MIOA_D8:

3GIO_PADCFG_LUT_ADDR[1]

MIOA_D9:

3GIO_PADCFG_LUT_ADDR[2]

MIOB_D7:

MOBILE_GPIO

2
2KR2-GP

2
DY
R76
2KR2-GP
2
DY 2KR2-GP

R83

MIOB_D7

47 MIOB_D7
R318

DY

DY

2KR2-GP

MIOB_D10
2005/11/10 ADD

2KR2-GP

0 ENABLED
1 DISABLED

MIOB_D10 47

0 DESKTOP
1 MOBILE

SC CHANGE 001
010 DEFAULT

0 GPIO_PULLDN
1 GPIO_FLOAT

For MEM strapping, Please use below table,

RAM_CFG[3:0]
Config
FB Bus Width
Definitions
0000
16Mx16 DDR2
64-bit
Elpida
0001
16Mx16 DDR2
64-bit
Samsung
0010
16Mx16 DDR2
64-bit
Infineon
0011
16Mx16 DDR2
64-bit
Hynix

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ROM,Spread Specturn
Size
Document Number
Custom

Rev

MYALL

Date: Friday, February 10, 2006

5

SA
Sheet
1

49

of

52

FBADQSN0
FBADQSN1
FBADQSN2
FBADQSN3
FBADQSN4
FBADQSN5
FBADQSN6
FBADQSN7

M28
K32
G31
G27
AA28
AL31
AF31
AH29

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

C83
C119
SCD1U10V2MX-3GP
SC1U10V3ZY

C157
C146
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP

C118
SC4D7U6D3V3KX-GP

L28
K31
G32
G28
AB28
AL32
AF32
AH30

FBADQSP0
FBADQSP1
FBADQSP2
FBADQSP3
FBADQSP4
FBADQSP5
FBADQSP6
FBADQSP7

1D8V_S0

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

PLACE BELOW GPU

M29
M30
G30
F29
AA29
AK30
AC30
AG30

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23

AA25
AA26
AB25
AB26
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
M26
R25
R26
V25
V26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

A12
A15
A18
A21
A24
A27
A3
A30
A6
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32
V32

www.kythuatvitinh.com
FBADQSN0
FBADQSN1
FBADQSN2
FBADQSN3
FBADQSN4
FBADQSN5
FBADQSN6
FBADQSN7

RFU2
RFU3

Y30
AC26
AC27

FBA_REFCLK
FBA_REFCLKN

D32
D31

FBA_PLLVDD

G23

FBB_A[5..2]

1
2

1
2

G72

C162

C189

C107

G72

G72

C84

1
2

G72

C64
SCD1U10V2MX-3GP

C127

G72

G72

SCD1U10V2MX-3GP
SC4700P50V3KX-1GP SC4700P50V3KX-1GP
SC4700P50V3KX-1GP SC4700P50V3KX-1GP

46

MYALL
G72

FBA_WE# 45,46
FBA_BA0 45,46
FBA_CKE 45,46

FBB_A2
FBA_A12
FBA_RAS#
FBA_A11
FBA_A10
FBA_BA1
FBA_A8
FBA_A9
FBA_A6
FBA_A5
FBA_A7
FBA_A4
FBA_CAS#

FBA_CS0# 45,46
ODT 45,46

FBA_RAS# 45,46

R85
10KR2J-3-GP

FBA_BA1 45,46

G72
B

FBA_CAS# 45,46

FBACLK0
FBACLK0#
FBACLK1
FBACLK1#

FBACLK0
FBACLK0#
FBACLK1
FBACLK1#

45
45
46
46

FBA_PLLAVDD

G25

FBA_PLLGND

G24

TPAD30 TP16G72

MYALL SB DELETE TESTPAD

TPAD30 TP107

1D2V_S0

L9

G72
1

C80
SCD01U25V2KX-3GP

C49
SC1U10V3ZY

C50

BLM18BB221SN1D-GP
SC4D7U6D3V3KX-GP
G72

<Core Design>

FBVREF1 E32

G72

G72

FB_VREF1

PLACE NEAR BALLS

G72

G72

PLACE NEAR GPU

Wistron Corporation

R299
1KR2F-3-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
G72

Title

MEMORY IF 1
Size
Document Number
Custom

G72

Date:
5

G72

G72

TPAD30 TP109
SC

1
FBA_WE#
FBA_BA0
FBA_CKE

G72

1
2

1
2

SCD022U16V2KXLGP

G72

G72

FBA_A3
FBA_A0
FBA_A2
FBA_A1
FBB_A3
FBB_A4
FBB_A5

1
1

R297
1KR2F-3-GP

C395
SCD1U10V2MX-3GP

C63

DY

SC4D7U6D3V3KX-GP

MYALL SB ADD TESTPAD

1D8V_S0

C393
SCD1U10V2MX-3GP

C99

CHECK NC?

FBA_DEBUG

1
2

P28
R28
Y27
AA27

G72

G72

1
2

FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#

45,46

45
45
45
45
46
46
46
46

C62
SCD1U10V2MX-3GP

FBADQSP0
FBADQSP1
FBADQSP2
FBADQSP3
FBADQSP4
FBADQSP5
FBADQSP6
FBADQSP7

C89
C98
SCD1U10V2MX-3GP
SC1U10V3ZY

45
45
45
45
46
46
46
46

C61
C78
SCD022U16V2KXLGP
SCD022U16V2KXLGP
SCD1U10V2MX-3GP

G72

G72

G72

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32

G72

G72

FBA_A[12..0]

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

C65

G72

45
45
45
45
46
46
46
46

G72

FBVDD_0
FBVDD_1
FBVDD_2
FBVDD_3
FBVDD_4
FBVDD_5
FBVDD_6
FBVDD_7
FBVDD_8
FBVDD_9
FBVDD_10
FBVDD_11
FBVDD_12
FBVDD_13
FBVDD_14
FBVDD_15
FBVDD_16
FBVDD_17
FBVDD_18
FBVDD_19

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

N27
M27
N28
L29
K27
K28
J29
J28
P30
N31
N30
N32
L31
L30
J30
L32
H30
K30
H31
F30
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
E28
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
AM30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

2 OF 14

U27B

45,46 FBAD[63..0]

Rev

MYALL

Friday, February 10, 2006

SA
Sheet
1

50

of

52

3 OF 14
U27C

B7
A7
C7
A2
B2
C4
A5
B5
F9
F10
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
D3
E4
C3
B4
C10
B10
C8
A10
C11
C12
A11
B11
B28
C27
C26
B26
C30
B31
C29
A31
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C25
C23
A22
C22
C21
B22
E22
D22
D21
E21
E18
D19
D18
E19

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

A4
E11
F5
C9
C28
F24
C24
E20

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

C5
E10
E5
B8
A29
D25
B25
F20

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

C6
E9
E6
A8
B29
E25
A25
F21

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
FBVTT_10
FBVTT_11
FBVTT_12
FBVTT_13
FBVTT_14
FBVTT_15
FBVTT_16
FBVTT_17

AA23
AB23
H16
H17
J10
J23
J24
J9
K11
K12
K21
K22
K24
K9
L23
M23
T25
U25

1D8V_S0
R496

1
0R3-0-U-GP

DY

www.kythuatvitinh.com

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20

FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#

E13
F13
F18
E17

RFU4
RFU5

C20
D1

FBC_DEBUG

F12

FBC_REFCLK
FBC_REFCLKN

B1
C1

FBC_PLLVDD

G8

FBC_PLLAVDD

G10

1D8V_S0

FBC_PLLGND

G9

G72

<Core Design>

FB_VREF2

FBCAL_PD_VDDQ

K26

FBCAL_PU_GND

H26

FBCAL_TERM_GND

J26

Wistron Corporation

G72

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

A28

R493
40D2R2F-GP

1 R494

Title

R495
30R2J-1-GP

MEMORY IF 2

G72

Size
Document Number
Custom

60D4R3D-1-GP

DY
SC MYALL CHANGE
5

Date:

Vaule 2006.01.11
3

Rev

SA

MYALL

Friday, February 10, 2006

Sheet
1

51

of

52

5V_S5
DCBATOUT_6269

1D5V_PWR

G94

5
6
7
8

1D5VSW
6269_FSET

GAP-CLOSE-PWR
G100
2

GAP-CLOSE-PWR
G102
2

R541
73K2R2F-GP

1D5VSW

C679
SCD01U50V2KX-1GP

GAP-CLOSE-PWR
G103
2

4
3
2
1

6269_EN

1
C678

1D5VSW 1D5VSW
1D5VSW

6269_VCC

PM_SLP_S3#

U75
FDS6612A-1-GP

C676

C674
SC2D2U16V3KX-GP

SC2D2U16V3KX-GP

16,18,29,32,36,37,41

C675

1D5VSW

SC10U25V0KX-3GP

1D5VSW

1
1

C677

R539

6269_LG

11
14
15
3

L37

6269_UG

6269_PHASE

1D5VSW

U77
FDS6690DS-GP

DY

TC44
ST220U4VDM-L6-GP

1D5VSW

1KR3F-GP

1D5VSW
C682
1

R549

2 1

1D5VSW

SC2200P50V2KX-2GP

1D5VSW

NIPPON 220uF ESR=15mohm

4
3
2
1

SC15P50V3JN-GP
C681
1
2 6269_COMP

1D5VSW

R548

5
6
7
8

R546
0R2J-2-GP

ISL6269CRZ-GP

1D5VSW

IND-4D7UH-88-GP

GND

17

PGND

FSET
EN

7
4

GAP-CLOSE-PWR

1D5VSW

1D5V_PWR

LG
UG
PHASE
FCCM

10

BOOT
ISEN
VO
FB

12

VIN

6269_FB

1D5VSW

R547
0R2J-2-GP
1

13
9
8
6

R545
1K5R3F-GP

6269_BOOT

1D5VSW

S
S
S
G

34,36 CPUCORE_ON

4K42R3F-GP

1
2

1KR3F-GP

R5431D5VSW
1
2
1D5V_PWR

1D5VSW
0R2J-2-GP

D
D
D
D

R544

1D5VSW

3D3V_S0

1D5VSW

PVCC

1D5VSW

1 MYALL DIS 2006/02/10

U76

VCC

16
5

2D2R2J-GP

R542

1D5VSW

6269_PHASE

R540

1KR3F-GP

PGOOD
COMP

C680
SCD1U25V3KX-GP

www.kythuatvitinh.com
GAP-CLOSE-PWR

R538
6269_PVCC1
2
2D2R2J-GP

1D5VSW

GAP-CLOSE-PWR
G101
2

GAP-CLOSE-PWR
G98
2

C673
SCD1U25V3KX-GP

Close to pin1

2
GAP-CLOSE-PWR
G99
2

DY

SCD1U25V3ZY-3GP

S
S
S
G

GAP-CLOSE-PWR
G97
2

G95

R537
0R2J-2-GP

D
D
D
D

GAP-CLOSE-PWR
G96
2

1D5V_S0

DCBATOUT_6269

DCBATOUT_6269

1D5VSW

SC10U25V0KX-3GP
2
1

DCBATOUT

Vref = 0.6V
Vo = (1+R8/R9)*0.6V =1.5V

1 MYALL DIS 0204

71K5R2F-1-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ISL6269/1D5V
Size
A3

Document Number

Date: Friday, February 10, 2006

A

Rev

SC

MYALL
Sheet
E

52

of

52