Compaq Presario Cq40 - Compal La-4101p

A
www.kythuatvitinh.com
Compal confidential
2
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic
3
Digitally signed by dd
2008-01-01
DN: cn=dd, o=dd, ou=dd,
email=dddd@yahoo.com,
c=US
Date: 2009.11.12 09:03:29
+07'00'
Compal Secret Data
Security Classification
2007/08/28
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Compal Electronics, Inc.

Cover Sheet
Size Do c ument Number

Cu s tom Montevina B lade
Da te:
Rev
0.3
UMA LA 4101P
Sheet
S aturday, January 05, 2008

E
of
46
Compal confidential
Montevina Consumer 14" UMA

CK505
Mobile Penryn
Thermal Sensor
E MC1402
72QFN
Clock Generator
SLG8SP553V
uFCPGA-478 CPU
P06
P17
P6, 7, 8
Fan conn
P06
H_A#(3. .35)
FSB
667/800/1066 MHz 1.05V
H_D#(0. .63)
LVDS Panel
Interface
DDR2 667MHz 1.8V

P19
DDR2 SO-DIMM X2
BANK 0, 1, 2, 3
P15, 16
CRT
Intel Cantiga MCH
Support V1.3
HDMI
Dual Channel
FCBGA 1329
P18
USB conn x1
P9,10, 11, 12, 13, 14
USB2.0 X12
DMI X4
BT Conn
C-Link
USB Camera
PCI-E BUS*5
RTL8102EL
(10/100M)
P25
Mini-Card
Mini-Card
WLAN
TV-tuner or
Robson
P26
P26
P30
P19
Azalia
Intel ICH9-M
PCIE
CardReader
JMB385 P27
P30
P35
SATA Master-1
Finger print
New Card
P30
SATA Slave
mBGA-676
SATA Slave
P20,21,22,23
Audio CKT
P26
AMP & Audio Jack
Codec_IDT9271B7
TPA6017A2
P28
5 in1 Slot
RJ45/11 CONN
LPC BUS
P25
P33
M DC
P29
P29
SATA HDD Connector
P24
RTC CKT.
ENE
KB926
LED
P21
P32
SATA ODD Connector
P24
SPI
P33
ACCELEROMETER-1
P24
ST
P30
USB Board Conn

USB conn x2
P32
P33
Dock
e-SATA Connector
Int.KBD
Touch Pad CONN.
P30
USB2.0*1
ACCELEROMETER-2
P24
BOSCH
4
RGB
SPI ROM
25LF080A
RJ45
Audio board
CIR Conn
P31
P29
SPDIF
CIR
K/B backlight Conn
Capsense switch Conn
MIC*1
P33
P33
LINE-OUT*1
Compal Secret Data
DC/DC Interface CKT.

P36
2006/02/13
Issued Date
2006/03/10
Deciphered Date
P34
B
Title

Block Diagram

Da te:
Rev
0.3
UMA LA 4101P
Sheet

E
of
46
Symbol Note :
Voltage Rails
MEANS ON
USB assignment:
X MEANS OFF
: means Digital Ground
USB-0 Right side

USB-1 Right side
USB-2 Left side(with ESATA)
: means Analog Ground
USB-3 Dock
power
plane
USB-4
+1.8V
+5VALW
+B
+5VS
+3VALW
45@ : means need be mounted when 45 level assy or rework stage.
+1.5VS
+0.9V
+2.5VS
USB-11 X
ESATA @ : means just reserve for ESATA
PCIe assignment:
PCIe-1
GS @ : means just reserve for G sensor
S3
MiniCard(WWAN/TV)
CONN@ : means ME part
+1.8VS
S1
Finger Printer
USB-8
USB-10 X
BATT @ : means need be mounted when 45 level assy or rework stage.
+CPU_CORE
USB-7
USB-9 Express card
DEBUG@ : means just reserve for debug.
+VCCP
State
USB-6 Bluetooth
@ : means just reserve , no build
+3VS
S0
Camera
USB-5 WLAN
PCIe-3 WLAN
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
TV /WWAN/Robeson
PCIe-2 X
FP @ : means just reserve for Finger Print
PCIe-4
GLAN (Realtek)
PCIe-5
Card reader
PCIe-6
New Card
DOCK@ : means just reserve for Docking
S5 S4/AC
Main@ : means just reserve for Main stream
S5 S4/ Battery only
OPP@ : means just reserve for OPP
S5 S4/AC & Battery

don't exist
2MiniC@ : means just reserve for 2nd Mini card slot
SMBUS Control Table

SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT
KB926
I2C / SMBUS ADDRESSING
INVERTER
BATT
SERIAL
EEPROM
Thermal
Sensor
SODIMM
CLK CHIP
MINI CARD
LCD
Cap sensor
board
NEW CARD
G sensor
KB926
ICH9
Cantiga
ADDRESS
A0
1 0 100000
DDR SO-DIMM 1
A4
1 0 100100
CLOCK GENERATOR (EXT.)
D2
1 1 010010
Compal Secret Data
DA600007100 --->Main
DAZ03V00100 --->OPP
HEX
DDR SO-DIMM 0
43154432L01 UMA GM PA FF (SI-1)

43154432L02 UMA GM PR FF (SI-1)
43154432L03 UMA GL PR FF43154432L04 UMA GM OPP (SI-1)
43154432L05 U MA GL OPP
Cantiga GM45 B0(QR32) SA00001P930
ICH9M A2 ES2 Base
SA00002AN10
43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP @/ESATA@/GS@/Multi@/2MiniC@

43154432L02 Main@/DEBUG@/DOCK@/NewC @/FP@/ESATA@/GS@/2MiniC@
43154432L03 Main@/DEBUG@/DOC K@/NewC@/FP@/2MiniC@
43154432L04 OP P@/DEBUG@
43154432L05 OP P@/DEBUG@
2007/08/28
Issued Date
DEVICE
Deciphered Date
2006/03/10
A
Title

Notes List

Da te:
Rev
0 .3
UMA LA 4101P
S a turday, January 05, 2008
Sheet
of
46
50mA
177mA
1A
D
+V_BATTERY
ICH9
INVPWR_B+
1A
+3VALW_EC
10mA
VIN
35mA
+3VAUX_BT
20mA
LVDS CON
25mA
LAN
60mA
AC
PC Camera
Dock con
300mA
0.3A
50mA
Finger printer
278mA
SPI ROM
+3VS_DVDD
ALC268
MDC 1.5
New card
ICH9
1.7A
2A
+3VALW
5.89A
3.39A
550mA
B++
+3VS
1.5A
250mA
657mA
0.3A
+1.5VS
0.58A
+5VALW
2.2A
1.56A
+LCDVDD
LVDS CON
JMB385
ICH_VCC1_5
ICH9
1A
ICH9
1A
35mA
1.3A
+5VS
+3VS_CK505
Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)
+VDDA
IDT 9271B7
B+
10mA
7A
1.8A
700mA
B
3.7A
3.7 X 3=11.1V
DC
BATT
1.9A
B+++
12.11A
8 A
+1.8V
50mA
1.05V_B+
1.8A
DDR2
800Mhz
CPU_B+
10mA
+VCC_CORE
Muti Bay
+0.9V
1.26A
+VCCP
34A/1.025V
SATA
4G x2
2.3A
2A
ODD
MCH
1.17A
4.7A
+5VAMP
ICH9
MCH
CPU
CPU
Compal Secret Data
Issued Date
2007/08/28
Deciphered Date
2006/03/10
5
Title

Power delivery
Size
C
Da te:
Do cu me n t Number
Rev
0.3
Mo n tevina Blade UMA LA4101P

Sa tu r d a y, Ja n u ary 05, 2008
1
Sheet
of
46
1
Compal Secret Data
2007/08/28
Issued Date
Deciphered Date
2006/03/10
A
Title

Power sequence

Da te:
Rev
0 .3
UMA LA 4101P
Sheet
of
46
+3VS
@ R1
ITP-XDP Connector
XDP_DBRESET#_R
1K_0402_5%
+ VCCP
Change value in 5/02

JP1
XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
<9> H_ A#[3..16]
J CPU1A
K3
H2
K2
J3
L1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
CONTROL
H _REQ#0
H _REQ#1
H _REQ#2
H _REQ#3
H _REQ#4
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
ADDR GROUP_0
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H1
E2
G5
H _ADS#
H_ B NR#
H_ BPRI#
H5
F21
E1
H_ D EFER#
H_ DRDY #
H_ DBSY#
F1
H _BR0#
D20
B3
H_ IE RR#
H_ INIT#
H4
H _LOCK#
C1
F3
F4
G3
G2
H_RESET#
H _RS#0
H _RS#1
H _RS#2
H_ T RDY#
G6
E4
H _HIT#
H _HITM#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_ADS# <9>
H_ BNR# <9>
H_ BPRI# <9>
H_ DEFER# <9>
H_ DRDY # <9>
H_ DBSY# <9>
R9
1K_0402_5%
2
1H_ P W RG OOD_R
XDP_HOOK1
<7,21> H_ P W RGOOD
H_BR0# <9>
T1
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
R2
54.9_0402_1%
XDP_TMS
R3
54.9_0402_1%
XDP_TDO
R4
54.9_0402_1%
XDP_BPM#5
R5
54.9_0402_1%
XDP_HOOK1 @ R 6
54.9_0402_1%
XDP_TRST#
R7
54.9_0402_1%
XDP_TCK
R8
54.9_0402_1%
This shall place near CPU
CLK_CPU_XDP
CLK_CPU_XDP#
CLK_CPU_XDP <17>
CLK_CPU_XDP# <17>
H_STPCLK#
H_ INTR
H_ NMI
H_SMI#
H_A20M#
H_ F ERR#
H_ IG NNE#
A6
A5
C4
H_STPCLK#
H_ I NTR
H_ N MI
H_SMI#
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
HIT#
HITM#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
THERMAL
ICH
<21> H_A20M#
<21> H_ F ERR#
<21> H_ IGNNE#
LOCK#
H_LOCK# <9>
2
C1
Place TP with a
GND 0.1" away
1
0.1U_0402_16V4Z
Removed at 5/30.(Follow
Chimay)
XDP_TCK
H_RESET# <9>
H_RS#0 <9>
H_RS#1 <9>
H_RS#2 <9>
H_ T RDY# <9>
H_ THERMDA_R
H_ T H ERMDC_R
C7
H_THERMTRIP#
A22
A21
C LK_CPU_BCLK
C LK_CPU_BCLK#
H_RESET#_R
R10
XDP_DBRESET#_R R11
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
SAMTE_BSH-030-01-L-D-A
C ONN@
H_HIT# <9>
H_HITM# <9>
H_ P ROCHOT#
D21
A24
B25
H CLK
BCLK[0]
BCLK[1]
H_ INIT# <21>
+ VCCP
1
2
+ V CCP
2 1K_0402_1%
1 200_0402_1%
H_RESET#
XDP_DBRESET#
R12
0_0402_5%
2
Place R191 within 200ps (~1") to CPU
+3VS
0.1U_0402_16V4Z
<9> H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
ADDR GROUP_1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
IERR#
INIT#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
XDP/ITP SIGNALS
<9> H_REQ#0
<9> H_REQ#1
<9> H_REQ#2
<9> H_REQ#3
<9> H_REQ#4
<9> H_A#[17..35]
XDP_DBRESET# <22>
R13
R14
R15
1
1
1
2 49.9_0402_1%
2 100_0402_5%
2 100_0402_5%
+ V CCP
H_ THERMDA
H_ T H ERMDC
C3
1
H_THERMTRIP# <9,21>
+3VS
CLK_CPU_BCLK <17>
CLK_CPU_BCLK# <17>
1
C2
U1
2
1
H_ THERMDA
H_ T H ERMDC
2
2200P_0402_50V7K
THERM#
For Merom, R14 and R15 are 0ohm

For Penryn, R14 and R15 are 100ohm.
VDD
R16
1
2
10K_0402_5%
SMCLK
DP
SMDATA
DN
ALERT#
THERM#
GND
SMB_EC_CK2
SMB_EC_DA2
SMB_EC_CK2 <32>
SMB_EC_DA2 <32>
6
5
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
H_THERMDA, H_THERMDC routing together,

T race w idth / Spacing = 10 / 10 mil
RESERVED
<9> H_ADSTB#0
<21>
<21>
<21>
<21>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
XDP_TDI
PWM Fan Control circuit

+5VS
11/01 update
P enryn
JP2
1
2
+ V CCP
RB751V_SOD323
@
R17
56_0402_5%
C4
4.7U_0805_10V4Z
C5
0.1U_0402_16V4Z
3
4
1
2
GND
GND
ACES_88231-02001
C ONN@
D1
D Q2
@ D2
OCP# <22>
RLZ5.1B_LL34
<32> F AN_PWM
SI3456BDV-T1-E3_TSOP6
Change PCB Footprint from

ACES_85204-02001_2P to
ACES_88231-02001_2P
O CP#
3
1
@ Q1
MMBT3904_NL_SOT23-3
H_ P ROCHOT#
1
2
5
6
2 2
+ FAN
+ V CCP
A
R18
56_0402_5%
Compal Secret Data
H_ IE RR#
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title

Penryn(1/3)-AGTL+/ITP-XDP

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
of
46
+ V CC_CORE
<9> H_ D# [0..15]
H_DSTBN#0
H_DSTBP#0
H_ DINV#0
H_ D#[16..31]
DATA GRP 2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
H _D#32
H _D#33
H _D#34
H _D#35
H _D#36
H _D#37
H _D#38
H _D#39
H _D#40
H _D#41
H _D#42
H _D#43
H _D#44
H _D#45
H _D#46
H _D#47
H_DSTBN#2
H_DSTBP#2
H_ D INV#2
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H _D#48
H _D#49
H _D#50
H _D#51
H _D#52
H _D#53
H _D#54
H _D#55
H _D#56
H _D#57
H _D#58
H _D#59
H _D#60
H _D#61
H _D#62
H _D#63
H_DSTBN#3
H_DSTBP#3
H_ D INV#3
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
H_ DP WR#
H_ P W R GOOD
H _CPUSLP#
H_PSI#
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
* Route the TEST3 and TEST5 signals through

a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
CPU_BSEL2
CPU_BSEL1
200
266
R23
R24
R25
R26
Resistor placed within 0.5"

of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
CPU_BSEL0
166
H_DPRSTP# <9,21,43>
H_DPSLP# <21>
H_ DP WR# <9>
H_ P W RGOOD <6,21>
H_CPUSLP# <9>
H_PSI# <43>
1
1
2
2
R20
0_0402_5%
0_0402_5%
+ C6
330U_D2E_2.5VM_R7
B26
C26
VCCA[01]
VCCA[02]
+1.5VS
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
CP U_VID0
CP U_VID1
CP U_VID2
CP U_VID3
CP U_VID4
CP U_VID5
CP U_VID6
<43>
<43>
<43>
<43>
<43>
<43>
<43>
AF7
V CCSENSE
V CCSENSE <43>
AE7
VSSSENSE
VSSSENSE <43>
1
C7
2
0.01U_0402_16V7K
MISC
+ VCCP
R19
G21 + VCCPA
+ VCCPB
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
10U_0805_6.3V6M
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
27.4_0402_1%
2
1
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
H_DSTBN#3 <9>
H_DSTBP#3 <9>
H_ DINV#3 <9>
54.9_0402_1%
2
1
+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
Penryn
CPU_BSEL
H_DSTBN#2 <9>
H_DSTBP#2 <9>
H_ DINV#2 <9>
H_ D#[48..63] <9>
27.4_0402_1%
2
1
T2
T3
T4
T5
T6
<17> CPU_BSEL0
<17> CPU_BSEL1
<17> CPU_BSEL2
J CP U1C
54.9_0402_1%
2
1
2 1K_0402_5%
2 1K_0402_5%
1
1
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
<9> H_DSTBN#1
<9> H_DSTBP#1
<9> H_ DINV#1
@ R21
@ R22
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
DATA GRP 1
H _D#16
H _D#17
H _D#18
H _D#19
H _D#20
H _D#21
H _D#22
H _D#23
H _D#24
H _D#25
H _D#26
H _D#27
H _D#28
H _D#29
H _D#30
H _D#31
H_DSTBN#1
H_DSTBP#1
H_ D INV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DATA GRP 3
<9>
<9>
<9>
<9>
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 0
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
+ V CC_CORE
H_ D#[32..47] <9>
J CPU1B
H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H _D#10
H _D#11
H _D#12
H _D#13
H _D#14
H _D#15
H_DSTBN#0
H_DSTBP#0
H_ D INV#0
1
C8
2
Near pin B26

B
Penryn
.
Length match within 25 mils.

The trace width/space/other is 20/7/25.
1
+ V CCP
R27
1K_0402_1%
2
+ V CC_CORE
+V_CPU_GTLREF
R28
2 100_0402_1%
V CCSENSE
R30
2 100_0402_1%
VSSSENSE
R29
2K_0402_1%
Close to CPU pin within

500mils.
Close to CPU pin AD26

within 500mils.
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title


Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
of
46
+ V CC_CORE
5
Place these capacitors on
L8 (North side,Secondary
Layer)
C9
10U_0805_6.3V6M
C10
10U_0805_6.3V6M
C11
10U_0805_6.3V6M
C1 2
10U_0805_6.3V6M
C13
10U_0805_6.3V6M
C14
10U_0805_6.3V6M
C15
10U_0805_6.3V6M
C16
10U_0805_6.3V6M
+ V CC_CORE
J CP U1D
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

Layer)
5
1
C17
10U_0805_6.3V6M
C18
10U_0805_6.3V6M
C19
10U_0805_6.3V6M
C2 0
10U_0805_6.3V6M
C21
10U_0805_6.3V6M
C22
10U_0805_6.3V6M
C23
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
+ V CC_CORE

Layer)
5
1
C25
10U_0805_6.3V6M
C26
10U_0805_6.3V6M
C27
10U_0805_6.3V6M
C2 8
10U_0805_6.3V6M
C29
10U_0805_6.3V6M
C30
10U_0805_6.3V6M
C31
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
+ V CC_CORE

Layer)
C33
10U_0805_6.3V6M
C34
10U_0805_6.3V6M
C35
10U_0805_6.3V6M
C3 6
10U_0805_6.3V6M
C37
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
Mid Frequence Decoupling
ESR <= 1.5m ohm

Capacitor > 1980uF
Near CPU CORE regulator
@
C42
1
+
2
1
+
C43
1
+
C44
330U_D2_2VY_R7M
330U_D2_2VY_R7M
1
C41
330U_D2_2VY_R7M
+ V CC_CORE
330U_D2_2VY_R7M
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
11/21 Change ESR=7m ohm
+ V CCP
Inside CPU center cavity in 2 rows

5
C45
0.1U_0402_10V6K
C46
0.1U_0402_10V6K
C47
0.1U_0402_10V6K
C48
0.1U_0402_10V6K
C49
0.1U_0402_10V6K
C50
0.1U_0402_10V6K
P enryn
.
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title


Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
of
46
H _ADS#
H_ADSTB#0
H_ADSTB#1
H_ B NR#
H_ BPRI#
H _BR0#
H_ D EFER#
H_ DBSY#
C LK_MCH_BCLK
CLK_MCH_BCLK#
H_ DP WR#
H_ DRDY #
H _HIT#
H _HITM#
H _LOCK#
H_ T RDY#
J8
L3
Y13
Y1
H_ D INV#0
H_ D INV#1
H_ D INV#2
H_ D INV#3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
B15
K13
F13
B13
B14
H _REQ#0
H _REQ#1
H _REQ#2
H _REQ#3
H _REQ#4
B6
F12
C8
H _RS#0
H _RS#1
H _RS#2
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
+1.8V
R31
1K_0402_1%
2
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
C52
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
2.2U_0603_6.3V4Z
C51
S MRCOMP_VOH
80% of 1.8V VCC_SM
R32
3.01K_0402_1%
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
T21
T22
T23
B31
B2
M1
T24
AY21
T25
T26
T27
T28
BG23
BF23
BH18
BF18
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
C5 4
RESERVED
RESERVED
RESERVED
RESERVED
R33
1K_0402_1%
2
SMRCOMP_VOL
RESERVED
RESERVED
RESERVED
RESERVED
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
AP24
AT21
AV24
AU20
M _ CLK_DDR0
M _ CLK_DDR1
M _ CLK_DDR2
M _ CLK_DDR3
AR24
AR21
AU24
AV20
M _ CLK_DDR#0
M _ CLK_DDR#1
M _ CLK_DDR#2
M _ CLK_DDR#3
BC28
AY28
AY36
BB36
DDR _CKE0_DIMMA
DDR _CKE1_DIMMA
DDR _CKE2_DIMMB
DDR _CKE3_DIMMB
BA17
AY16
AV16
AR13
DDR _CS0_DIMMA#
DDR _CS1_DIMMA#
DDR _CS2_DIMMB#
DDR _CS3_DIMMB#
BD17
AY17
BF15
AY13
M_ODT0
M_ODT1
M_ODT2
M_ODT3
BG22
BH21
S MRCOMP
SMRCOMP#
BF28
BH28
S MRCOMP_VOH
SMRCOMP_VOL
AV42
AR36
BF17
BC36
V _ DDR _MCH_REF
SM_PWROK
SM_REXT
TP_SM_DRAMRST#
B38
A38
E41
F41
CL K _ MCH_DREFCLK
CL K _MCH_DREFCLK#
M CH_ SSCDREFCLK
M CH_ SSCDREFCLK#
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
AE41
AE37
AE47
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AE35
AE43
AE46
AH42
D MI_RXN0
D MI_RXN1
D MI_RXN2
D MI_RXN3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M _ CLK_DDR0
M _ CLK_DDR1
M _ CLK_DDR2
M _ CLK_DDR3
<15>
<15>
<16>
<16>
M _ CLK_DDR#0
M _ CLK_DDR#1
M _ CLK_DDR#2
M _ CLK_DDR#3
<15>
<15>
<16>
<16>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<15>
<15>
<16>
<16>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<15>
<15>
<16>
<16>
M_ODT0
M_ODT1
M_ODT2
M_ODT3
R34
R35
<15>
<15>
<16>
<16>
+1.8V
2 80.6_0402_1%
2 80.6_0402_1%
1
1
Follow Design Guide

For Cantiga: 80.6ohm
+ H_VREF
A11
B11
2 10K_0402_5%
H_RS#0 <6>
H_RS#1 <6>
H_RS#2 <6>
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18
CF G19
CF G20
0.1U_0402_16V4Z
<22> PM_BMBUSY#
<7,21,43> H_DPRSTP#
<15> PM_EXTTS#0
<16> PM_EXTTS#1
<22,32> PM_PWROK
R41
1
2
R42
1
2 100_0402_5%
0_0402_5%
Layout Note: V_DDR_MCH_REF

trace width and spacing is 20/20.
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
THERMTRIP#
DP RSLPVR
1 @
C55
2
+1.8V
1
2
R55
C59
2
1
221_0603_1%
2
1
+ H_ SWNG
V _ DDR _MCH_REF
R48
1K_0402_1%
C57
2
R54
<15,16> V _ DDR_MCH_REF
0.1U_0402_16V4Z
C58
R47
0.1U_0402_16V4Z
H_ R COMP
100_0402_1%
2
1
R52
0.1U_0402_16V4Z
+ H_VREF
24.9_0402_1%
2
1
1K_0402_1%
1
2K_0402_1%
2
1
R46
R45
1K_0402_1%
R29
B7
N33
P32
AT40
AT11
T20
R32
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
B33
B32
G33
F33
E33
T30
T31
T32
T33
T34
C34
T35
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
<22>
<22>
<22>
<22>
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
<22>
<22>
<22>
<22>
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
<22>
<22>
<22>
<22>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
<22>
<22>
<22>
<22>
+ V CCP
AH37
AH36
AN36
AJ35
AH34
C L_CLK0
CL_DATA0
M _PWROK
CL_RST#
+ CL_VREF
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
N28
M28
G36
E36
K36
H36
T36
T37
HDM ICLK_NB
HD MIDAT_NB
CLKREQ#_7
M CH_ ICH _SYNC#
B12 TSATN#
R43
1K_0402_1%
CL_CLK0 <22>
CL_DATA0 <22>
M _PWROK <22,32>
CL_RST# <22>
0621 add CLK and DAT for DVI

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
Near B3 pin
1 R737
B28
B30
B29 HDA _ SDIN2_NB
C29
A28
C5 6
0.1U_0402_16V4Z
R44
499_0402_1%
2
HDM ICLK_NB <35>
HDMIDAT_NB <35>
CLKREQ#_7 <17>
M CH_ ICH_SYNC# <22>
2 56_0402_5% + VCCP
TSATN# <32>
*R44*Follow Intel
feedback
HDA_BITCLK_NB <21>
R210
HDA_RST#_NB <21>
1
2
HDA _SDOUT_NB <21>
33_0402_5%
HDA _ S YNC_NB <21>
HDA _ SDIN2 <21> A
0830 Add pull-up and pull-down resistor.
Compal Secret Data

2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
CLK_MCH_3GPLL <17>
CLK_MCH_3GPLL# <17>
CANTIGA ES_FCBGA1329
within 100 mils from NB
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
NC
+V_DDR_MCH_REF generated by DC-DC
+ VCCP
PEG_CLK
PEG_CLK#
DMI
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
PM
PLT_RST#
+ V CCP
CLK
<6>
<6>
<6>
<6>
<6>
<20,25,26,27> PLT_RST#
<6,21> H_THERMTRIP#
<22,43> DPRSLPVR
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
R40
<11> CF G5
<11> CF G6
<11> CF G7
<11> CF G8
<11> CF G9
<11> CF G10
<11> CF G11
<11> CF G12
<11> CF G13
<11> CF G14
<11> CF G15
<11> CF G16
<11> CF G17
<11> CF G18
<11> CF G19
<11> CF G20
Route H_SCOMP and H_SCOMP# with trace

width, spacing and impedance (55 ohm) same as
FSB data traces
CLKREQ#_7
<17> MCH_CLKSEL0
<17> MCH_CLKSEL1
<17> MCH_CLKSEL2
H_AVREF
H_DVREF
Layout note:
2 10K_0402_5%
H_RS#_0
H_RS#_1
H_RS#_2
CL K _ MCH_DREFCLK <17>
CL K _MCH_DREFCLK# <17>
M CH_ SSCDREFCLK <17>
M CH_ SSCDREFCLK# <17>
H_CPURST#
H_CPUSLP#
H_ REQ#0
H_ REQ#1
H_ REQ#2
H_ REQ#3
H_ REQ#4
R39
2 0_0402_5%
2 499_0402_1%
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
<7>
<7>
<7>
<7>
PM_EXTTS#1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
R36
1
R37
1
T29 P AD
H_SWING
H_RCOMP
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
2 10K_0402_5%
GRAPHICS VID
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
<7>
<7>
<7>
<7>
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
<7>
<7>
<7>
<7>
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
R38
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
ME
C12
E11
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_ DINV#0
H_ DINV#1
H_ DINV#2
H_ DINV#3
+3VS
PM_EXTTS#0
MISC
H_RESET#
H _CPUSLP#
<6> H_RESET#
<7> H_CPUSLP#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_ADS# <6>
H_ADSTB#0 <6>
H_ADSTB#1 <6>
H_ B NR# <6>
H_ BPRI# <6>
H_BR0# <6>
H_ DEFER# <6>
H_ DBSY# <6>
CLK_MCH_BCLK <17>
CLK_MCH_BCLK# <17>
H_ DP WR# <7>
H_ DRDY # <6>
H_ HIT# <6>
H_HITM# <6>
H_ LOCK# <6>
H_ T RDY# <6>
HDA
C5
E3
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
CFG
+ H_ SWNG
H_ R COMP
HOST
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
20% of 1.8V VCC_SM

0.01U_0402_25V7K
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
2.2U_0603_6.3V4Z
C5 3
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
RSVD
H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H _D#10
H _D#11
H _D#12
H _D#13
H _D#14
H _D#15
H _D#16
H _D#17
H _D#18
H _D#19
H _D#20
H _D#21
H _D#22
H _D#23
H _D#24
H _D#25
H _D#26
H _D#27
H _D#28
H _D#29
H _D#30
H _D#31
H _D#32
H _D#33
H _D#34
H _D#35
H _D#36
H _D#37
H _D#38
H _D#39
H _D#40
H _D#41
H _D#42
H _D#43
H _D#44
H _D#45
H _D#46
H _D#47
H _D#48
H _D#49
H _D#50
H _D#51
H _D#52
H _D#53
H _D#54
H _D#55
H _D#56
H _D#57
H _D#58
H _D#59
H _D#60
H _D#61
H _D#62
H _D#63
0.01U_0402_25V7K
U2A
<7> H_ D#[0..63]
U2B
H_ A#[3..35] <6>
DDR CLK/ CONTROL/COMPENSATION
Title

Cantiga(1/6)-AGTL/DMI/DDR

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
of
46
<15> DDR_ A _D[0..63]

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR _A_D10
DDR _A_D11
DDR _A_D12
DDR _A_D13
DDR _A_D14
DDR _A_D15
DDR _A_D16
DDR _A_D17
DDR _A_D18
DDR _A_D19
DDR _A_D20
DDR _A_D21
DDR _A_D22
DDR _A_D23
DDR _A_D24
DDR _A_D25
DDR _A_D26
DDR _A_D27
DDR _A_D28
DDR _A_D29
DDR _A_D30
DDR _A_D31
DDR _A_D32
DDR _A_D33
DDR _A_D34
DDR _A_D35
DDR _A_D36
DDR _A_D37
DDR _A_D38
DDR _A_D39
DDR _A_D40
DDR _A_D41
DDR _A_D42
DDR _A_D43
DDR _A_D44
DDR _A_D45
DDR _A_D46
DDR _A_D47
DDR _A_D48
DDR _A_D49
DDR _A_D50
DDR _A_D51
DDR _A_D52
DDR _A_D53
DDR _A_D54
DDR _A_D55
DDR _A_D56
DDR _A_D57
DDR _A_D58
DDR _A_D59
DDR _A_D60
DDR _A_D61
DDR _A_D62
DDR _A_D63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
BD21
BG18
AT25
D DR_A_BS0
D DR_A_BS1
D DR_A_BS2
BB20
BD20
AY20
DD R_A_RAS#
DD R_A_CAS#
DDR _A_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDR _A_DM0
DDR _A_DM1
DDR _A_DM2
DDR _A_DM3
DDR _A_DM4
DDR _A_DM5
DDR _A_DM6
DDR _A_DM7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
DDR _A_DQS0
DDR _A_DQS1
DDR _A_DQS2
DDR _A_DQS3
DDR _A_DQS4
DDR _A_DQS5
DDR _A_DQS6
DDR _A_DQS7
DDR _A_DQS#0
DDR _A_DQS#1
DDR _A_DQS#2
DDR _A_DQS#3
DDR _A_DQS#4
DDR _A_DQS#5
DDR _A_DQS#6
DDR _A_DQS#7
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
D DR_A_MA0
D DR_A_MA1
D DR_A_MA2
D DR_A_MA3
D DR_A_MA4
D DR_A_MA5
D DR_A_MA6
D DR_A_MA7
D DR_A_MA8
D DR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
U2E
DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR _B_D10
DDR _B_D11
DDR _B_D12
DDR _B_D13
DDR _B_D14
DDR _B_D15
DDR _B_D16
DDR _B_D17
DDR _B_D18
DDR _B_D19
DDR _B_D20
DDR _B_D21
DDR _B_D22
DDR _B_D23
DDR _B_D24
DDR _B_D25
DDR _B_D26
DDR _B_D27
DDR _B_D28
DDR _B_D29
DDR _B_D30
DDR _B_D31
DDR _B_D32
DDR _B_D33
DDR _B_D34
DDR _B_D35
DDR _B_D36
DDR _B_D37
DDR _B_D38
DDR _B_D39
DDR _B_D40
DDR _B_D41
DDR _B_D42
DDR _B_D43
DDR _B_D44
DDR _B_D45
DDR _B_D46
DDR _B_D47
DDR _B_D48
DDR _B_D49
DDR _B_D50
DDR _B_D51
DDR _B_D52
DDR _B_D53
DDR _B_D54
DDR _B_D55
DDR _B_D56
DDR _B_D57
DDR _B_D58
DDR _B_D59
DDR _B_D60
DDR _B_D61
DDR _B_D62
DDR _B_D63
DDR_A_BS0 <15>
DDR_A_BS1 <15>
DDR_A_BS2 <15>
DDR_A_RAS# <15>
DDR_A_CAS# <15>
DDR_A_WE# <15>
DDR_ A _DM[0..7] <15>
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
BC16
BB17
BB33
DDR_B_BS0
D DR_B_BS1
D DR_B_BS2
AU17
BG16
BF14
DD R_B_RAS#
DD R_B_CAS#
DDR _B_WE#
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDR _B_DM0
DDR _B_DM1
DDR _B_DM2
DDR _B_DM3
DDR _B_DM4
DDR _B_DM5
DDR _B_DM6
DDR _B_DM7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
DDR _B_DQS0
DDR _B_DQS1
DDR _B_DQS2
DDR _B_DQS3
DDR _B_DQS4
DDR _B_DQS5
DDR _B_DQS6
DDR _B_DQS7
DDR _B_DQS#0
DDR _B_DQS#1
DDR _B_DQS#2
DDR _B_DQS#3
DDR _B_DQS#4
DDR _B_DQS#5
DDR _B_DQS#6
DDR _B_DQS#7
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
D DR_B_MA0
D DR_B_MA1
D DR_B_MA2
D DR_B_MA3
D DR_B_MA4
D DR_B_MA5
D DR_B_MA6
D DR_B_MA7
D DR_B_MA8
D DR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS0 <16>
DDR_B_BS1 <16>
DDR_B_BS2 <16>
DDR_B_RAS# <16>
DDR_B_CAS# <16>
DDR_B_WE# <16>
DDR_ B _DM[0..7] <16>
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR_ A _DQS#[0..7] <15>
DDR_A_MA[0..14] <15>
B
MEMORY
DDR_ A _DQS[0..7] <15>
SYSTEM
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
DDR
SYSTEM
MEMORY
DDR
<16> DDR_ B _D[0..63]
U 2D
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR_ B _DQS[0..7] <16>
DDR_ B _DQS#[0..7] <16>
DDR_B_MA[0..14] <16>
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title

Cantiga(2/6)-DDR2 A/B CH

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
10
of
46
100K_0402_5%
ENBKL
<32> ENBKL
+3VS
R58
2 10K_0402_5%
R59 1
DDC2 _CLK
DD C2_DATA
<19> DDC2 _CLK

<19> DDC2_DATA
2 2.37K_0402_1%
LVDS_ACLKLVDS_ACLK+
LVDS_BCLKLVDS_BCLK+
T38
T39
T72
T73
T74
T40
L32
G32
M32
Strap Pin Table
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
B37
A37
LVDS_A0LVDS_A1LVDS_A2LVDS_A3-
H47
E46
G40
A40
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+
H48
D45
F40
B40
LVDS_B0LVDS_B1LVDS_B2LVDS_B3-
A41
H38
G37
J37
LVDS_B0+
LVDS_B1+
LVDS_B2+
LVDS_B3+
TV_COMPS
TV_LUMA
TV_CRMA
B42
G38
F37
K37
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
PEG_COMPI
PEG_COMPO
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
LVDS
Follow Intel DG &

Checklist
T80
T81
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
+VCC_PEG
R57
1
2
49.9_0402_1%
T37
T36
000 = FSB 1066MHz

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
CFG[2:0] FSB Freq

select
PEGCOMP trace width

and spacing is 20/25 mils.
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
CFG[4:3]
Reserved
CFG5 (DMI select)
0 = DMI x 2
1 = DMI x 4
CFG6
1 = T he iT PM Host Interface is disable
CFG7 (Intel Management

Engine Crypto strap)
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
TMDS_B_HPD#
TMDS_B_HPD# <35>
0 = T he iT PM Host Interface is enable
0 =(T LS)chiper suite with no confidentiality

1 =(T LS)chiper suite with confidentiality
CFG8
Reserved
CFG9 (PCIE Graphics

Lane Reversal)
0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in
order
11/10 Disable TV out
E28
G28
J28
G29
<18> 3 V DDCCL
<18> 3 V DDCDA
<18> CRT _ HS YNC
H S Y NC
V S Y NC
H32
J32
J29
E29
L29
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
<18> CRT _ VSYNC
3 V DD CCL
3 V DD CDA
CRT _ HS YNCR68 1
30.1_0402_1%
CRT _ VSYNC R69 1
30.1_0402_1%
TV_DCONSEL_0
TV_DCONSEL_1
R70
1.02K_0402_1%
VGA
R67
150_0402_1%
R66
150_0402_1%
R65
150_0402_1%
Follow Intel DG &

Checklist
C31
E32
2.2K_0402_5%
0_0402_5%
2
2
1
1
<18> M_BLUE
<18> M _GREEN
<18> M _ RED
@ R64
R406
M_BLUE
M _GREEN
M _RED
+3VS
TV_RTN
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
0 = Enable
CFG10 (PCIE
Lookback
enable)
CFG11
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK
C274
C275
C276
C277
1
1
1
1
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
TMDS_B_DATA2# <35>
TMDS_B_DATA1# <35>
TMDS_B_DATA0# <35>
TMDS_B_CLK# <35>
1 = Disable
Reserved
CFG[13:12] (XOR/ALLZ)
00
01
10
11
=
=
=
=
CFG[15:14]
Reserved
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation
(Default)
CFG16 (FSB Dynamic ODT) 0 = Disabled

1 = Enabled
Reserved
CFG[18:17]
CFG19 (DMI Lane Reversal) 0 = Normal Operation

C278
C279
C280
C281
1
1
1
1
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
(Lane number in Order)
TMDS_B_DATA2 <35>
TMDS_B_DATA1 <35>
TMDS_B_DATA0 <35>
TMDS_B_CLK <35>
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
CFG20 (PCIE/SDVO
concurrent)
1 = PCIE/SDVO are operating simu.
+3VS
H24
PCI-EXPRESS
R63
TVA_DAC
TVB_DAC
TVC_DAC
TV
R62
75_0402_1%
R61
75_0402_1%
75_0402_1%
Follow Intel DG &

Checklist
F25
H25
K25
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
T48
T49
T50
T75
T77
T79
T41
2 10K_0402_5%
E NA VDD
R60 1
<19> E NA VDD
D
ENBKL
GRAPHICS
U 2C
R148
+3VS
R71
4.02K_0402_1%
B
CF G5
<9> CF G16
<9> CF G5
@
R74
2.21K_0402_1%
<9> CF G19
1
2
4.02K_0402_1%
@ R73
1
2
4.02K_0402_1%
@R75
1
2
4.02K_0402_1%
@R76
1
2
2.21K_0402_1%
R77
1
2
2.21K_0402_1%
<9> CF G20
R72
Solve 3G WWAN issue

<19> LVDS_ACLK+
LVDS_ACLK+
<19> LVDS_ACLK<19> LVDS_A0+
LVDS_ACLKLVDS_A0+
<19> LVDS_A0<19> LVDS_A1+
LVDS_A0LVDS_A1+
<19> LVDS_A1<19> LVDS_A2+
LVDS_A1LVDS_A2+
<19> LVDS_A2-
LVDS_A2-
<9> CF G11
1
2
1
2
1
2
1
<9> CF G12
@
C60
0.1U_0402_10V6K
<9> CF G13
@
C61
0.1U_0402_10V6K
<9> CF G6
<9> CF G7
@
C62
0.1U_0402_10V6K
<9> CF G8
@
C63
0.1U_0402_10V6K
<9> CF G9
<9> CF G10
2007/08/28
2006/03/10
Deciphered Date
5
R81
1
2
2.21K_0402_1%
1
2
2.21K_0402_1%
<9> CF G14
<9> CF G15
@R83
1
2
2.21K_0402_1%
@R84
1
2
2.21K_0402_1%
<9> CF G17
@R86
1
2
2.21K_0402_1%
<9> CF G18
Compal Secret Data
Issued Date
@R79
Title
R78
1
2
2.21K_0402_1%
@R80
1
2
2.21K_0402_1%
@R82
1
2
2.21K_0402_1%
@R85
1
2
2.21K_0402_1%
@R87
1
2
2.21K_0402_1%

Cantiga(3/6)-VGA/LVDS/TV

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
11
of
46
VTT
C81
CRT
PLL
C82
+1.8V_SM_CK
+1.05VS_DPLLB
+ 1.8V
+ VCCP
R 95
R 94
10U_FLC-453232-100K_0.25A_10%
A PEG
0_0603_5%
50mA
A SM
VCCD_PEG_PLL
VCCD_LVDS
VCCD_LVDS
60.31mA
VCC_HV
VCC_HV
VCC_HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
AXF
SM CK
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
+1.05VS_PEGPLL
+ 1.05VS_DMI
+ VCCP
+ VCCP
L1
+ 3VS_HV
C35
B35
A35
R 104
BLM18PG121SN1D_0603
V48
U48
V47
U47
U46
+VCC_PEG
AH48
AF48
AH47
AG47
+ 1.05VS_DMI
0_0603_5%
2
2
+ VCCP_D
456mA
VTTLF
VTTLF
VTTLF
D3
A8
L1
AB2
0.47U_0603_10V7K
C112
0.47U_0603_10V7K
C111
R 105
+ VCCP
0.47U_0603_10V7K
C110
C ANTIGA ES_FCBGA1329
PEG
HV
50mA
DMI
+1.8V_LVDS
M38
L37
157.2mA
VTTLF
AA47
1732mA
48.363mA
+1.8V_TXLVDS
10U_0805_10V4Z
0.1U_0402_16V4Z
C109
+1.05VS_PEGPLL
VCCD_HPLL
K47
+
C100
C108
VCCD_QDAC
AF1
+1.8V_SM_CK
118.8mA
VCC_TX_LVDS
105.3mA
58.67mA
BF21
BH20
BG20
BF20
10U_0805_10V4Z
VCCD_TVDAC
L28
+ 1.5VS_QDAC
+ 1.05VS_HPLL
50mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
C107
M25
+ 1.5VS_TVDAC
B
VCC_HDA
C 99
124mA
R 106
10_0402_5%
CH751H-40PT_SOD323-2
+ 3VS_HV
0_0402_5%
+3VS
+ 1.8V_LVDS
40 mils
+1.8V_TXLVDS
1
2
1
2
+ 1.8V
1 @
+
C115
0_0603_5%
C116
1
220U_D2_4VM
0_0603_5%
1000P_0402_50V7K
@ R110
+ 1.8V
2
A
Compal Secret Data
S e c urity Classification
2007/08/28
Issued Date
2006/03/10
Deciphered Date
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5
R 108
0_0603_5%
C114
C113
1U_0603_10V4Z
1 @
C121
220U_D2_4VM
C120
100_0603_1%
0.1U_0402_16V4Z
0.022U_0402_16V7K
0_0603_5%
C119
@ R114
C118
0_0603_5%
R 112
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
C117
0_0603_5%
@ R113
0.022U_0402_16V7K
10U_0805_10V4Z
+1.5VS
R 111
@ R109
+ 1.5VS_QDAC
+3VS
R 107
+ 3VS_TVDAC
0_0805_5%
MBK2012121YZF_0805
C106
A32
R 102
+V1.05VS_AXF
0.1U_0402_16V4Z
+1.5VS
Check Again!!!
B22
B21
A21
0. 1U_0402_16V4Z
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
VCCA_TV_DAC
VCCA_TV_DAC
VCC_AXF
VCC_AXF
VCC_AXF
0.1U_0402_16V4Z
+3VS_TVDAC
B24
A24
+ VCCP
10U_0805_10V4Z
+ VCCP
C101
R 101
C98
C105
C104
C103
1U_0603_10V4Z
10U_0805_10V4Z
C 102
0.1U_0402_16V4Z
0_0603_5%
1U_0603_10V4Z
220U_D2_4VM
+1.05VS_A_SM_CK
R 103
VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
+1.05VS_MPLL
321.35mA
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
+VCC_PEG
1U_0603_10V4Z
A CK
0_0805_5%
TV
4. 7U_0805_10V4Z
C 97
HDA
0.1U_0402_16V4Z
C 96
C93
220U_D2_4VM
0.022U_0402_16V7K
C95
C94
POWER
C92
0_0805_5%
10U_0805_10V4Z
720mA
+ 1.5VS
R 99
MBK2012121YZF_0805
C91
+1.05VS_A_SM
R 100
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
+ 1.5VS_TVDAC
+ VCCP
R 98
10U_0805_10V4Z
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
+ 1.05VS_HPLL
C90
+VCCP
0. 1U_0402_16V4Z
VCCA_PEG_PLL
0.1U_0402_16V4Z
AA48
+1.05VS_PEGPLL
C 89
LVDS
0_0805_5%
C85
A LVDS
2
D TV/CRT
C79
VCCA_PEG_BG
R 97
+1.5VS
0_0603_5%
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
AD48
+1.5VS_PEG_BG
C78
VSSA_LVDS
414uA
0_0603_5%
VCCA_LVDS
J47
C84
C 88
1000P_0402_50V7K
10U_0805_10V4Z
+1.8V_TXLVDS
R 96
C83
139.2mA
VCCA_MPLL
13.2mA
+3VS
VCCA_HPLL
J48
1
24mA
10U_0805_10V4Z
AE1
64.8mA
10U_0805_10V4Z
+1.05VS_MPLL
VCCA_DPLLB
C87
AD1
C86
L48
+1.05VS_HPLL
R 93
R 90
10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
+1.05VS_DPLLB
64.8mA
2.2U_0805_16V4Z
BLM18PG181SN1D_0603
VCCA_DPLLA
4.7U_0805_10V4Z
F47
+1.05VS_DPLLA
0.47U_0603_10V7K
C76
0.1U_0402_16V4Z
R92
0.022U_0402_16V7K
C75
0_0603_5%
10U_0805_10V4Z
R 91
1 @
C74
+3VS
0.1U_0402_16V4Z
+ 3VS_DAC_CRT
1
+
C77
VCCA_DAC_BG
VSSA_DAC_BG
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
C73
2.68mA
A25
B25
+ 3VS_DAC_BG
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
+VCCP
+ V1.05VS_AXF
C72
+ 3VS_DAC_CRT
VCCA_CRT_DAC
VCCA_CRT_DAC
+VCCP
1
220U_D2_4VM
852mA
73mA
B27
A26
+1.05VS_DPLLA
4.7U_0805_10V4Z
+ VCCP
C71
2
BLM18PG181SN1D_0603
220U_6.3V_M
10U_0805_10V4Z
C69
C70
0.1U_0402_16V4Z
C68
R89
0_0603_5%
0.022U_0402_16V7K
R 88
**RED Mark: Means UMA & dis@ Power select**

~It check by INTEL Graphics Disable
Guidelines~
U2 H
+3VS
C80
+ 3VS_DAC_BG
Title

Cantiga(4/6)-PWR
Size D ocument Number

C ustom M o n te v ina Blade
D ate:
R ev
0.3
UMA LA4101P
Sheet
Sat ur day, January 05, 2008

1
12
of
46
+ V CCP
U2 G
3000mA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0317 change value
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
POWER
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
VCC CORE
C123
0.01U_0402_16V7K
C130
10U_0805_10V4Z
C122
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
10U_0805_10V4Z
C126
C125
0.1U_0402_16V4Z
C133
0.22U_0402_10V4Z
C132
0.22U_0402_10V4Z
C124
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
0.1U_0402_16V4Z
1
4.7U_0603_6.3V6M
1
C127
C128
C129
D
0.22U_0402_10V4Z
6326.84mA
1
C134
1U_0603_10V4Z
1
C136
1
C137
1
C138
+ C135
2
10U_0805_10V4Z
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title
1U_0603_10V4Z
1U_0603_10V4Z
C145
0.47U_0402_6.3V6K
C144
C143
0.22U_0603_10V7K
0.22U_0603_10V7K
C142
C141
VCC_AXG_SENSE
VSS_AXG_SENSE
AV44
BA37
AM40
AV21
AY5
AM10
BB13
C140 0.1U_0402_16V4Z
AJ14
AH14
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
C139 0.1U_0402_16V4Z
P AD T42
P AD T43
VCC SM LF
+ VCCP
10U_0805_10V4Z 0.1U_0402_16V4Z
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
VCC GFX NCTF
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
330U_D2E_2.5VM_R7
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC GFX
VCC
VCC NCTF
T32
BA36
BB24
BD16
BB21
AW16
AW13
AT13
+ V CCP
POWER
+
2
10U_0805_10V4Z
C131
220U_D2_4VM
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
330U_D2E_2.5VM_R7
+ VCCP
+1.8V
VCC SM
Extnal Graphic: 1210.34mA

integrated Graphic: 1930.4mA
U2 F

Cantiga(5/6)-PWR/GND

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
13
of
46
U2 J
U2 I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS NCTF
BA16
VSS SCB
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title

Cantiga(6/6)-PWR/GND

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
14
of
46
+1.8V
+1.8V
V _ DDR _MCH_REF
<10> DDR_ A_DQS#[0..7]
DDR_ A_D2
DDR_ A_D3
Layout Note:
Place near
JP3
DDR_ A_D8
DDR_ A_D9
DDR _A_DQS#1
DDR _A_DQS1
DDR _A_D11
DDR _A_D10
+1.8V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR _A_D16
DDR _A_D17
1
C150
C157
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
C149
0.1U_0402_16V4Z
C148
C156
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C155
C154
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C153
2.2U_0805_16V4Z
C147
2.2U_0805_16V4Z
C152
DDR _A_DQS#2
DDR _A_DQS2
DDR _A_D26
DDR _A_D27
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
<9> DDR_CKE0_DIMMA
<10> DDR_A_BS2
<10> DDR_A_BS0
<10> DDR_A_WE#
1
<10> DDR_A_CAS#
<9> DDR_CS1_DIMMA#
DDR_A_MA10
D DR_A_BS0
DDR _A_WE#
DD R_A_CAS#
DDR _CS1_DIMMA#
M_ODT1
<9> M_ODT1
2
DDR _A_D37
DDR _A_D36
C170
C169
C168
C167
C166
C165
C164
C163
C162
C161
C160
C159
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
D DR_A_BS2
D DR_A_MA5
D DR_A_MA3
D DR_A_MA1
DDR _CKE0_DIMMA
DDR_A_MA12
D DR_A_MA9
DDR_A_MA8
+0.9V
0.1U_0402_16V4Z
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_ A_D6
DDR_ A_D7
DDR _A_D13
DDR _A_D12
DDR _A_DM1
M _ CLK_DDR0
M _ CLK_DDR#0
M _ CLK_DDR0 <9>
M _CLK_DDR#0 <9>
DDR _A_D15
DDR _A_D14
DDR _A_D20
DDR _A_D21
PM_EXTTS#0 <9>
DDR _A_DM2
DDR _A_DQS#4
DDR _A_DQS4
DDR _A_D39
DDR _A_D38
DDR _A_D45
DDR _A_D44
DDR _A_DM5
+0.9V
56_0404_4P2R_5%
RP1
DDR_A_MA8
1
D DR_A_MA5
2
4
3
4
3
RP2
56_0404_4P2R_5%
RP3
D DR_A_MA1
1
D DR_A_MA3
2
4
3
4
3
RP4
56_0404_4P2R_5%
RP5
DD R_A_RAS#
1
DDR _CS0_DIMMA# 2
4
3
4
3
56_0404_4P2R_5%
RP7
D DR_A_BS0
1
DDR_A_MA10
2
4
3
4
3
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
56_0404_4P2R_5%
1 D DR_A_BS2
2 DDR _CKE0_DIMMA
DDR _A_D47
DDR _A_D46
DDR _A_D49
DDR _A_D48
56_0404_4P2R_5%
1 D DR_A_MA7
2 DDR_A_MA6
RP6
56_0404_4P2R_5%
1 DDR_A_MA12
2 D DR_A_MA9
RP8
56_0404_4P2R_5%
1 D DR_A_MA4
2 D DR_A_MA2
DDR _A_DQS#6
DDR _A_DQS6
DDR _A_D54
DDR _A_D50
DDR _A_D61
DDR _A_D60
DDR _A_DM7
DDR _A_D59
DDR _A_D58
4
3
RP10
56_0404_4P2R_5%
RP11
DDR _CS1_DIMMA# 2
M_ODT1
1
3
4
4
3
RP12
RP13
DDR_A_MA11
4
3
56_0404_4P2R_5%
1 D DR_A_MA0
2 D DR_A_BS1
<16,17> CLK_SMBDATA
<16,17> CLK_SMBCLK
+3VS
CLK_SMBDATA
CLK_SMBCLK
56_0404_4P2R_5%
1 M_ODT0
2 DDR_A_MA13
56_0404_4P2R_5%
1 DDR _CKE1_DIMMA
2 DDR_A_MA14
R117 56_0402_5%
1
C171 C172
FOX_ASOA426-M4R-TR
C ONN@
SO-DIMM A
DDR _A_D28
DDR _A_D25
DDR _A_DQS#3
DDR _A_DQS3
DDR _A_D31
DDR _A_D30
DDR _CKE1_DIMMA
2006/02/13
DDR_A_MA11
D DR_A_MA7
DDR_A_MA6
D DR_A_MA4
D DR_A_MA2
D DR_A_MA0
D DR_A_BS1
DD R_A_RAS#
DDR _CS0_DIMMA#
M_ODT0
DDR_A_MA13
M_ODT0 <9>
DDR _A_DM4
DDR _A_D34
DDR _A_D35
DDR _A_D40
DDR _A_D41
B
DDR _A_DQS#5
DDR _A_DQS5
DDR _A_D43
DDR _A_D42
DDR _A_D52
DDR _A_D53
M _ CLK_DDR1
M _ CLK_DDR#1
M _ CLK_DDR1 <9>
M _CLK_DDR#1 <9>
DDR _A_DM6
DDR _A_D51
DDR _A_D55
DDR _A_D57
DDR _A_D56
DDR _A_DQS#7
DDR _A_DQS7
DDR _A_D62
DDR _A_D63
5
DDR_A_BS1 <10>
DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9>
DDR _A_D32
DDR _A_D33
2006/03/10
Deciphered Date
DDR_CKE1_DIMMA <9>
DDR_A_MA14
Compal Secret Data
Issued Date
0.1U_0402_16V4Z
4
3
2.2U_0603_6.3V4Z
56_0404_4P2R_5%
RP9
DD R_A_CAS#
1
DDR _A_WE#
2
DDR _A_D23
DDR _A_D22
R116
10K_0402_5%
2
1
DDR _A_DM3
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
DDR _A_DM0
DDR _A_D18
DDR _A_D19
DDR _A_D29
DDR _A_D24
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_ A_D5
DDR_ A_D0
R115
10K_0402_5%
2
1
2.2U_0805_16V4Z
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C151
DDR _A_DQS#0
DDR _A_DQS0
<10> DDR_A_MA[0..14]
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C146
DDR_ A_D4
DDR_ A_D1
<10> DDR_ A _DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
<10> DDR_ A _DM[0..7]
V _ DDR_MCH_REF <9,16>
J DIMM1
<10> DDR_ A _D[0..63]
Title

DDRII-SODIMM SLOT1

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
15
of
46
+1.8V
+1.8V
<10> DDR_ B _DQS#[0..7]
J DIMM2
<10> DDR_ B _DQS[0..7]
DDR _B_DQS#0
DDR _B_DQS0
D
DDR_ B_D2
DDR_ B_D3
Layout Note:
Place near
JP10
DDR_ B_D8
DDR_ B_D9
DDR _B_DQS#1
DDR _B_DQS1
DDR _B_D10
DDR _B_D11
+1.8V
V _ DDR_MCH_REF <9,15>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
DDR_ B_D5
DDR_ B_D4
DDR _B_DM0
DDR_ B_D6
DDR_ B_D7
C182
DDR_ B_D0
DDR_ B_D1
<10> DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C173
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0.1U_0402_16V4Z
V _ DDR _MCH_REF
<10> DDR_ B _DM[0..7]
2.2U_0805_16V4Z
<10> DDR_ B _D[0..63]
DDR _B_D12
DDR _B_D13
DDR _B_DM1
M _ CLK_DDR2
M _ CLK_DDR#2
M _ CLK_DDR2 <9>
M _CLK_DDR#2 <9>
DDR _B_D14
DDR _B_D15
5
1
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR _B_D21
DDR _B_D20
C181
C180
0.1U_0402_16V4Z
C179
0.1U_0402_16V4Z
C178
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C177
C183
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C176
2.2U_0805_16V4Z
DDR _B_DQS#2
DDR _B_DQS2
DDR _B_D19
DDR _B_D18
DDR _B_D30
DDR _B_D31
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
DDR _CKE2_DIMMB
<9> DDR_CKE2_DIMMB
D DR_B_BS2
<10> DDR_B_BS2
DDR_B_MA12
D DR_B_MA9
DDR_B_MA8
D DR_B_MA5
D DR_B_MA3
D DR_B_MA1
+0.9V
DDR_B_MA10
D DR_B_BS0
DDR _B_WE#
<10> DDR_B_BS0
<10> DDR_B_WE#
DD R_B_CAS#
DDR _CS3_DIMMB#
<10> DDR_B_CAS#
<9> DDR_CS3_DIMMB#
2
C196
C195
C194
C193
C192
C191
C190
C189
C188
C187
C186
C185
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C184
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M_ODT3
<9> M_ODT3
DDR _B_D32
DDR _B_D37
DDR _B_DQS#4
DDR _B_DQS4
DDR _B_D34
DDR _B_D35
+0.9V
56_0404_4P2R_5%
RP14
D DR_B_MA3
1
D DR_B_MA1
2
RP15
4
3
4
3
56_0404_4P2R_5%
RP16
D DR_B_BS0
1
DDR_B_MA10
2
4
3
4
3
RP17
56_0404_4P2R_5%
RP18
D DR_B_MA0
1
D DR_B_BS1
2
4
3
4
3
56_0404_4P2R_5%
RP20
DDR _CS2_DIMMB# 1
DD R_B_RAS#
2
4
3
4
3
56_0404_4P2R_5%
DDR_B_MA12
1
D DR_B_MA9
2
DDR _B_D40
DDR _B_D41
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
DDR _B_DM5
DDR _B_D42
DDR _B_D43
DDR _B_D48
DDR _B_D49
56_0404_4P2R_5%
DDR_B_MA11
1
DDR_B_MA14
2
RP19
56_0404_4P2R_5%
D DR_B_MA5
1
DDR_B_MA8
2
RP21
56_0404_4P2R_5%
DDR_B_MA6
1
D DR_B_MA7
2
DDR _B_DQS#6
DDR _B_DQS6
DDR _B_D54
DDR _B_D55
DDR _B_D60
DDR _B_D61
DDR _B_DM7
DDR _B_D63
DDR _B_D58
PM_EXTTS#1 <9>
DDR _B_DM2
RP25
4
3
RP26
DDR _CKE3_DIMMB 1
R120
2
56_0402_5%
4
3
CLK_SMBDATA
CLK_SMBCLK
<15,17> CLK_SMBDATA
<15,17> CLK_SMBCLK
+3VS
56_0404_4P2R_5%
DDR_B_MA13
1
M_ODT2
2
56_0404_4P2R_5%
DDR _CKE2_DIMMB
1
D DR_B_BS2
2
1
C197
DDR _B_DQS#3
DDR _B_DQS3
DDR _B_D26
DDR _B_D27
DDR _CKE3_DIMMB
DDR_B_MA14
2006/02/13
0612 add
DDR_B_MA11
D DR_B_MA7
DDR_B_MA6
D DR_B_MA4
D DR_B_MA2
D DR_B_MA0
D DR_B_BS1
DD R_B_RAS#
DDR _CS2_DIMMB#
DDR_B_BS1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>
M_ODT2
DDR_B_MA13
M_ODT2 <9>
DDR _B_D36
DDR _B_D33
DDR _B_DM4
DDR _B_D39
DDR _B_D38
DDR _B_D44
DDR _B_D45
DDR _B_DQS#5
DDR _B_DQS5
DDR _B_D46
DDR _B_D47
DDR _B_D52
DDR _B_D53
M _ CLK_DDR3
M _ CLK_DDR#3
M _ CLK_DDR3 <9>
M _CLK_DDR#3 <9>
DDR _B_DM6
DDR _B_D50
DDR _B_D51
DDR _B_D56
DDR _B_D57
DDR _B_DQS#7
DDR _B_DQS7
DDR _B_D59
DDR _B_D62
FOX_AS0A426-N8RN-7F
C ONN@
SO-DIMM B
2006/03/10
Deciphered Date
5
DDR_CKE3_DIMMB <9>
R118
1
+3VS
10K_0402_5%
A
Compal Secret Data
Issued Date
C198
DDR _B_D29
DDR _B_D24
R119
3
4
56_0404_4P2R_5%
D DR_B_MA2
1
D DR_B_MA4
2
0.1U_0402_16V4Z
4
3
DDR _B_D22
DDR _B_D23
10K_0402_5%
56_0404_4P2R_5%
RP24
DDR _CS3_DIMMB# 2
M_ODT3
1
RP23
4
3
2.2U_0603_6.3V4Z
56_0404_4P2R_5%
RP22
DD R_B_CAS#
1
DDR _B_WE#
2
DDR _B_D16
DDR _B_D17
DDR _B_DM3
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
2
DDR _B_D28
DDR _B_D25
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
C175
C174
2.2U_0805_16V4Z
2.2U_0805_16V4Z
Title

DDRII-SODIMM SLOT2
Size
Do c ument Number
Rev
0.3
Montevina B lade UMA LA 4101P

Da te:
Sheet
1
16
of
46
FSC
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
DOT_96
MHz
+3VS
USB
MHz
R121
1
266
100
33.3
14.318
96.0
48.0
2
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
166
100
33.3
14.318
96.0
48.0
C199
10U_0805_10V4Z
Routing the trace at least 10mil
333
100
33.3
14.318
96.0
0.1U_0402_16V4Z
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
48.0
C201
0.1U_0402_16V4Z
C202
0.1U_0402_16V4Z
C203
0.1U_0402_16V4Z
C204
0.1U_0402_16V4Z
C205
0.1U_0402_16V4Z
+1.05VS_CK505
+ V CCP
CLK_XTAL_OUT
CLK_XTAL_IN
48.0
C200
Place close to U51
R122
1
2
0_0805_5%
Y1
0_0805_5%
+3VS_CK505
0.1U_0402_16V4Z
1
C206
C207
10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C209
C210
C211
C208
C212
14.318MHZ_16PF_7A14300083
2
10U_0805_10V4Z
C213
18P_0402_50V8J
Reserved
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C214
18P_0402_50V8J
Vendor suggests 22pF
+1.05VS_CK505
+3VS_CK505
R123
1
+ V CCP
56_0402_5%
CL RP1
NO S HORT PADS
R _CPU_XDP
R_CPU_XDP#
R _MCH_3GPLL
R_MCH_3GPLL#
R _CLKREQ#_6
R_ C LK_PCIE_MCARD2
R_ CLK_PCIE_MCARD2#
R124
R125
R127
R131
R133
R135
R137
1
1
1
1
1
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
475_0402_1%
0_0402_5%
0_0402_5%
2
2
2
2
2
2
2
XDP/ITP
MCH_CLKSEL0 <9>
NB
CPU
2
2
2
2
2
475_0402_1%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
@
R143
1K_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
1
1
1
R_ CK P WRGD
FSB
R147
T44
MCH_CLKSEL1 <9><15,16> CLK_SMBDATA

<15,16> CLK_SMBCLK
R393 1
R155 1
R158
1
<26> CLK_DEBUG_PORT_1
<32> CL K_PCI_EC
@
R157
0_0402_5%
2 33_0402_1%
1
1
2
R150
1K_0402_5%
R161
FSC
R EF1
CLK_SMBDATA
CLK_SMBCLK
2 39_0402_1% P CI2_1
2 39_0402_1% PCI2_TME
2 33_0402_1% 27_SEL
P CI_CLK3
2 33_0402_1% ITP_EN
<20> CL K _ PCI_ICH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK_XTAL_OUT
CLK_XTAL_IN
No Debug port anymore
<7> CPU_BSEL1
1
2
R165
1K_0402_5%
MCH_CLKSEL2 <9>
R167 1
<22> CLK_48M_ICH
2 39_0402_1%
FSA
R _CLK_48M_CRUSB
T76
+1.05VS_CK505
@
R174
0_0402_5%
1
1
2 0_0402_5%
2 0_0402_5%
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
H_STP_PCI#
H_STP_CPU#
2MiniC@
2MiniC@
2MiniC@
2 0_0402_5%
CLK_PCIE_MCARD0# <26>
2 0_0402_5%
CL K_PCIE_MCARD0 <26>
2 475_0402_1%
CLKREQ#_10 <26>
0_0402_5%
CLK_SRC11 <27>
0_0402_5%
CLK_SRC11# <27>
H_STP_PCI# <22>
H_STP_CPU# <22>
R_ CLK_PCIE_MCARD0# R144
R_ C LK_PCIE_MCARD0
R145
R_CLKREQ#_10
R146
R_ CLK_SRC11 R725 1
R _CLK_SRC11# R726 1
1
1
1
2
2
R _CLK_PCIE_LAN#
R _CLK_PCIE_LAN
R _CLKREQ#_9
R152
R153
R738
1
1
1
2 0_0402_5%
2 0_0402_5%
2 475_0402_1%
CLK_PCIE_LAN# <25>
CLK_PCIE_LAN <25>
CLKREQ#_9 <25>
R _CLKREQ#_4
R_ CL K _PCIE_NCARD#
R_ CL K _PCIE_NCARD
R156
R159
R160
1
1
1
2 475_0402_1%
2 0_0402_5%
2 0_0402_5%
CLKREQ#_4 <26>
CL K _ PCIE_NCARD# <26>
CL K _ PCIE_NCARD <26>
R_ C LKREQ#_C
R162
2 475_0402_1%
CL KREQ#_C <22>
MiniCard_0
LAN
New Card
Ne wC@
Ne wC@
Ne wC@
R_PCIE_SATA#
R_PCIE_SATA
R166
R168
1
1
2
2
0_0402_5%
0_0402_5%
R_ P C IE_ICH#
R_ P CI E_ICH
R170
R172
1
1
2
2
0_0402_5%
0_0402_5%
R176
R177
1
1
2
2
0_0402_5%
0_0402_5%
CLK_PCIE_SATA# <21>
CLK_PCIE_SATA <21>
SATA
CL K _ PCIE_ICH# <22>
CL K _ PCIE_ICH <22>
ICH
M CH_ SSCDREFCLK# <9>

M CH_ S SCDREFCLK <9>
NB_SSC (UMA)
+1.05VS_CK505
R_ M CH _DREFCLK
R_ M C H_DREFCLK#
S S C DREFCLK#
S S C DREFCLK
NB (UMA)
<9> CL K _ MCH_DREFCLK
<9> CL K _ MCH_DREFCLK#
R173
R175
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#
SLG8SP553VTR_QFN72_10x10
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
<7> CPU_BSEL2
FSC
+3VS_CK505
R164
1
2
10K_0402_5%
R171
1
2
0_0402_5%
Change 33M and 48M damping to 39M by EMI request
@
R163
1K_0402_5%
CKPWRGD/PD#
FS_B/TEST_MODE
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF_0/FS_C/TEST_
REF_1
SDA
SCL
NC
VDD_PCI
PCI_1
PCI_2
PCI_3
PCI_4/SEL_LCDCL
PCIF_5/ITP_EN
VSS_PCI
+ VCCP
MiniCard_2(WLAN)
+1.05VS_CK505
VDD_48
USB_0/FS_A
USB_1/CLKREQ_A#
VSS_48
VDD_IO
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO
VDD_PLL3
LCDCLK/27M
LCDCLK#/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRC_2
SRC_2#
VSS_SRC
SRC_3
SRC_3#
@ R141
@ R142
R140
<22,43> VGATE
<43> CLK_ENABLE#
<22> CK _ P WRGD
<22> CLK_14M_ICH
R154
1
2
0_0402_5%
3G_PLL
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
U3
+3VS_CK505
+ VCCP
FSB
CLK_CPU_XDP <6>
CLK_CPU_XDP# <6>
CLK_MCH_3GPLL <9>
CLK_MCH_3GPLL# <9>
CLKREQ#_6 <26>
CL K_PCIE_MCARD2 <26>
CLK_PCIE_MCARD2# <26>
+3VS_CK505
@
R139
1K_0402_5%
R _CLKREQ#_7
R_ MCH_BCLK#
R_ MCH_BCLK
R_ CPU_BCLK#
R_ CPU_BCLK
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_IO
SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
VDD_SRC
<7> CPU_BSEL0
1
2
R129
1K_0402_5%
1
1
1
1
1
FSA
R128
1
2
2.2K_0402_5%
R138
1
2
0_0402_5%
R126
R130
R132
R134
R136
<9> CLKREQ#_7
<9> CLK_MCH_BCLK#
<9> CLK_MCH_BCLK
<6> CLK_CPU_BCLK#
<6> CLK_CPU_BCLK
+3VS
+3VS
+3VS
+3VS
R178
2.2K_0402_5%
Q3A
SB, MINI PCI

1
<22,24,26> ICH_SMBDATA
+3VS
R180
10K_0402_5%
@
R181
10K_0402_5%
<22,24,26> ICH_SMBCLK
Q3B
3
R179
2.2K_0402_5%
@ C215
2
5P_0402_50V8C
@ C216
2
4.7P_0402_50V8C
@ C217
2
4.7P_0402_50V8C
@ C218
2
4.7P_0402_50V8C
@ C219
2
5P_0402_50V8C
PCI_CLK3
0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable SRC0 & 27MHz(DIS)
ITP_EN
CLK_SMBDATA
2N7002DW-7-F_SOT363-6
CLK_SMBCLK
2N7002DW-7-F_SOT363-6
C LK_48M_ICH
C LK_14M_ICH
CL K _ PCI_ICH
CL K_PCI_EC
CLK_DEBUG_PORT_0
P CI_CLK3
1
ITP_EN
@
R182
10K_0402_5%
<BOM Structure>
R183
10K_0402_5%
2007/08/28
2006/03/10
Deciphered Date
Title
5

Clock Generator CK505
Issued Date
2
Compal Secret Data
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
17
of
46
BLUE
GR EEN
R ED
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
R ED
<34> R E D
GR EEN
<34> GREEN
<34> D_ HS Y NC
<34> BLUE
BLUE
1
3
+ CRTVDD
<34> D_ V S YNC
+5VS
R185
R186
2.2K_0402_5%
2.2K_0402_5%
V S YNC_G_A
2 0_0603_5%
D_ V S YNC
D_ DD CDATA
U5
SN74AHCT1G125GW_SOT353-5
1 @
C223
2
1
1
1 @
C224
5P_0402_50V8C
R187
2.2K_0402_5%
2
2
D_ HS Y NC
Q5A
5P_0402_50V8C
2N7002DW-7-F_SOT363-6
3
D_ DDC CLK
R188
2.2K_0402_5%
3 V DD CDA
3 V DDCDA <11>
R189
1
2 0_0603_5%
5
1
CRT _ VSYNC
<11> CRT _VSYNC
R184
1
+3VS
+3VS
+ CRTVDD
16
17
SUYIN_070546FR015S263ZR
C ONN@
U4
SN74AHCT1G125GW_SOT353-5
HS Y N C_G_A
4
Y
P
OE#
CRT _ HS YNC
C222
0.1U_0402_16V4Z
1
2
+ CRTVDD
<11> CRT _ HSYNC
P
OE#
5
1
C221
0.1U_0402_16V4Z
1
2
+5VS
Place close to
JCRT1
1
0.1U_0402_16V4Z
2
C220
J CRT1
W=40mils
1 .1A_6VDC_FUSE
@ D7
DAN217T146_SC59-3
1
RB491D_SC59-3
CRT Connector
F1
1
@ D6
D4
@ D5
+ CRT VDD
DAN217T146_SC59-3
+ RCRT_VCC
+5VS
DAN217T146_SC59-3
3 V DD CCL
3 V DDCCL <11>
Q5B
2N7002DW-7-F_SOT363-6
D_ DDCDATA <34>
D_ DDCCLK <34>
CRT Termination/EMI Filter
11/07 Change CRT lounting NB-->Docking-->CRT connector
<11> M _ RED
<11> M _GREEN
1
2
HLC0603CSCCR11JT_0603
GR EEN
L4
1
2
BLUE
@ C225 @ C226 @ C227
10P_0402_50V8J
150_0402_1%
L3
10P_0402_50V8J
150_0402_1%
R197
2
1
C_ GRN
C_ BLU
10P_0402_50V8J
R ED
22P_0402_50V8J
R195
1
2
22P_0402_50V8J
L2
22P_0402_50V8J
150_0402_1%
R196
2
1
<11> M_BLUE
C_ R ED
C228 C229 C230
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
A
Title

CRT Connector
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
E
18
of
46
C237
LVDS CONN & USB Camera + Dig Mic
+3VS
+3VS
Q7
SI2301BDS-T1-E3_SOT23-3
3
LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ACLK- <11>
LVDS_ACLK+ <11>
C231
0.1U_0402_16V4Z
R198
100_0402_5%
0.1U_0402_16V4Z
C233
4.7U_0805_10V4Z
1
C234
2
R200
2
11/07 Change R727 to 0805 size

DM IC_DAT
DM I C_CLK
+3V_LOGO
I NV_PWM
BKOFF#
DA C_ BRIG
R199
1M_0402_5%
C232
2
G
LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+
2
1
2
4
3
4
6
5
6
8
7
8
10
9
10
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
42
GND GND
ACES_88242-4001
C ONN@
2N7002DW-7-F_SOT363-6
Q8A
4.7U_0805_10V4Z
J LVDS1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
+5VALW
1
+ L CDVDD
680P_0402_50V7K
680P_0402_50V7K
1
2
680P_0402_50V7K
+ L CDVDD
+ L CDVDD
USB20_P4
USB20_N4
<22> USB20_P4
<22> USB20_N4
C235 C236
INV PWR_B+
6 2
+ L CDVDD
+3VS
100K_0402_5%
C238
3
0.047U_0402_16V7K
Limited Current < 1A
+USB_CAM
DDC2 _CLK <11>

DDC2_DATA <11>
<11> E NA VDD
01/03 Change to 0.047u to meet T1 timing
Q8B
2N7002DW-7-F_SOT363-6
R201
100K_0402_5%
DDC2 _CLK
DD C2_DATA
DM IC_DAT <28>
DM IC_CLK <28>
+5VS
INV_PWM <32>
BKOFF# <32>
DA C_ BRIG <32>
11/17 Delete LVDS B
R727
1
470_0805_5%
C435
680P_0402_50V7K
C434
680P_0402_50V7K
Avoid Panel display garbage after power on.
0308_Install all cap for EMI

request.
B+
INVPWR_B+
@
L5
Must close JLVDS1pin 24

26
+3VS
0_0805_5%
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
R202
2.2K_0402_5%
DDC2 _CLK
DD C2_DATA
L6
1
2
FBMA-L11-201209-221LMA30T_0805
DM IC_DAT
2
2
2
2
R203
2.2K_0402_5%
@ C302
220P_0402_25V8J
@ C1399 1
@ C1400 1
@ C1401 1
@ C1402 1
LVDS_ACLK+
LVDS_ACLKDDC2 _CLK
DD C2_DATA
DM I C_CLK
0308_Reserve L10 and install L11.
@ C303
220P_0402_25V8J
0831 EMI request

11/09 EMI reserver
B
USB Camera
IN
SHDN
BYP
G916-390T1UF_SOT23-5
2
R440
0_0402_5%
C1391
10U_0805_6.3V6M
2
R1093
100K_0402_1%
R1091
215K_0603_1%
2
3
C1392
10U_0805_6.3V6M
OUT
GND
U42
PJP5
P A D-OPEN 2x2m
@ PJP6
P A D-OPEN 2x2m
+USB_CAM
+5VS
+5VALW
<22> GPIO20
@ R441 1
2 0_0402_5%
11/07 Change U42 to 3.9V LDO(Adjustable)
11/07 Change R1091 to 215K

R1093 to 100K
11/08 Change C1391
C1392 to 0805 size
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm
+USB_CAM=1.25(1+R1091/R1093)
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title

LCD CONN.
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
19
of
46
+3VS
PCI_DEVSEL#
2 8.2K_0402_5%
PCI_STOP#
R274 1
2 8.2K_0402_5%
P CI _TRDY#
R275 1
2 8.2K_0402_5%
P CI_FRAME#
R276 1
2 8.2K_0402_5%
P CI_PLOCK#
R277 1
2 8.2K_0402_5%
U12B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
P CI_ IR DY#
R278 1
2 8.2K_0402_5%
P C I_SERR#
R279 1
2 8.2K_0402_5%
P C I_PERR#
+3VS
R281 1
2 8.2K_0402_5%
P C I_PIRQA#
R282 1
2 8.2K_0402_5%
P C I_PIRQB#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PCI
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
F1
G4
B6
A7
F13
F12
E6
F6
P CI_REQ0#
P CI_GNT0#
P CI_REQ1#
P CI_REQ2#
P CI_REQ3#
P CI_GNT3#
D8
B4
D6
A5
Place closely pin D4

CL K _ PCI_ICH
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
P CI_ IR DY#
2 8.2K_0402_5%
R273 1
PCI_RST#
PCI_DEVSEL#
P C I_PERR#
P CI_PLOCK#
P C I_SERR#
PCI_STOP#
P CI _TRDY#
P CI_FRAME#
P CI_RST# <31,32>
@
R280
10_0402_5%
R272 1
P CI_SERR# <32>
R283 1
2 8.2K_0402_5%
P CI_ PIRQC#
R284 1
2 8.2K_0402_5%
P CI_ PIRQD#
R285 1
2 8.2K_0402_5%
P C I_PIRQE#
R286 1
2 8.2K_0402_5%
P CI _PIRQF#
R287 1
2 8.2K_0402_5%
P CI _PIRQG#
R288 2
1 8.2K_0402_5%
P CI_ PIRQH#
R289 1
2 8.2K_0402_5%
P CI_REQ0#
R290 1
2 8.2K_0402_5%
P CI_REQ1#
R292 1
2 8.2K_0402_5%
P CI_REQ2#
R293 1
2 8.2K_0402_5%
P CI_REQ3#
A16 swap override Strap

B
PCI_GNT3#
P CI_GNT3#
Low= A16 swap override Enble

High= Default *
@R294
1
P C I_PIRQA#
P C I_PIRQB#
P CI_ PIRQC#
P CI_ PIRQD#
J5
E1
J6
C4
PLTRST#
PCICLK
PME#
C14
D4
R2
PLT_RST#
CL K _ PCI_ICH
PCI_PME#
@
C425
8.2P_0402_50V
PLT_RST# <9,25,26,27>
CL K _ P CI_ICH <17>
PCI_PME# <32>
3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
H4
K6
F2
G2
P C I_PIRQE#
P CI _PIRQF#
P CI _PIRQG#
P CI_ PIRQH#
1
R291
GS@
2
0_0402_5%
A CCEL_INT <24>
Boot BIOS Strap

PCI_GNT0#
SPI_CS#1
Boot BIOS Location
SPI
PCI
LPC
2
1K_0402_5%
*
+3VALW
<22> SPI_CS1#_R
SPI_CS1#_R
@ R295
1
P CI_GNT0#
@ R296
1
2
1K_0402_5%
2
1K_0402_5%
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
Title

ICH9(1/4)-PCI/INT
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
20
of
46
R300
1
R302
LAN100_SLP
+3VS
GATEA20
R298
1
2
10K_0402_5%
KB_RST#
R301
1
2
10K_0402_5%
ICH_ INTVRMEN
ICH8M LAN100 SLP Strap

(Internal VR for VccLAN1.05 and VccCL1.05)
IC H_SRTCRST#
C426
0.1U_0402_16V4Z
@
R303
@
R304
+ VCCP
ICH_LAN100_SLP
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
CLRP2
S HORT PADS
A25
F20
C22
ICH_ INTVRMEN
LAN100_SLP
B22
A22
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
LAN100_SLP
FWH4/LFRAME#
LPC
1U_0603_10V4Z
C427
ICH _RTCRST#
IC H_SRTCRST#
S M _ INTRUDER#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LDRQ0#
LDRQ1#/GPIO23
K5
K4
L6
K2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
K3
E25
H_DPSLP#
@ R306
1
2
56_0402_5%
LPC_FRAME#
GLAN_CLK
A20GATE
A20M#
LPC_FRAME# <26,31,32>
+ V CCP
J3
J1
T54
+ RT CVCC
RTCX1
RTCX2
RTC
R307
1
2
20K_0402_5%
C23
C24
@ R305
1
2
56_0402_5%
L P C_AD[0..3] <26,31,32>
U12A
I CH_RTCX1
I CH_RTCX2
H_DPRSTP#
N7
AJ27
GATEA20
H_A20M#
AJ25
AE23
H _DPRSTP_R#
H_DPSLP#
R309
AJ26
R_ H_ FERR#
R310
AD22
H_ P W R GOOD
AF25
H_ IG NNE#
AE22
AG25
L3
H_ INIT#
H_ I NTR
KB_RST#
AF23
AF24
H_ N MI
H_SMI#
AH27
H_STPCLK#
AG26
T HR MTRIP_ICH#
P AD
0_0402_5%
2
1
1
R299
S M _ INTRUDER#
0_0402_5%
2
1
R297
2
1M_0402_5%
2
330K_0402_5%
2
330K_0402_5%
2
180K_0402_5%
ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5,
VccCL1.5)
ICH_INTVRMEN
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
+ RT CVCC
GATEA20 <32>
H_A20M# <6>
R308
56_0402_5%
R312
R313
R207
R316
R314
R208
R317
R318
R209
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
<29> HDA _ SDOUT_MDC

<28> HDA _ S DOUT_CODEC
<9> HDA _SDOUT_NB
1
1
1
1
1
1
1
1
1
R320
R321
R204
2
2
2
2
2
2
2
2
2
B10
B28
B27
33_0402_5%
33_0402_5%
33_0402_5%
1
1
1
2
2
2
P AD T55
P AD T56
H DA_BITCLK
HDA _ S YNC
AF6
AH4
H DARST#
AE7
HDA _ SDIN0
HDA _ SDIN1
HDA _ SDIN2
AF4
AG4
AH3
AE5
HDA _SDOUT
AG5
SATA_LED#
P- HDD
<24>
<24>
<24>
<24>
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0
SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1
SATA_TXP1
SATA_TXN0
SATA_TXP0
0.01U_0402_50V7K
C431
1
2
C433
1
2
SATA_TXN1
SATA_TXP1
0.01U_0402_50V7K
0.01U_0402_50V7K
C820
1
2 Multi@
C821
1
2 Multi@
GLAN_COMPI
GLAN_COMPO
SATA_TXN0_C
SATA_TXP0_C
SATA_TXN1_C
SATA_TXP1_C
IGNNE#
INIT#
INTR
RCIN#
NMI
SMI#
HDA_BIT_CLK
HDA_SYNC
STPCLK#
HDA_RST#
THRMTRIP#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
TP12
HDA_SDOUT
AG7
AE8
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
<33> SATA_LED#
<24>
<24>
<24>
<24>
GPIO56
FERR#
CPUPWRGD
IHDA
HDA _ BITCLK_CODEC
HDA_BITCLK_MDC
HDA_BITCLK_NB
HDA _ S Y NC_CODEC
HDA _ S Y NC_MDC
HDA _ S YNC_NB
HDA _ RST#_CODEC
HDA_RST#_MDC
HDA_RST#_NB
<28> HDA _ SDIN0
<29> HDA _ SDIN1
<9> HDA _ SDIN2
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
SATALED#
AJ16
AH16
AF17
AG17
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AH13
AJ13
AG14
AF14
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
0.01U_0402_50V7K
H_DPRSTP# <7,9,43>
H_DPSLP# <7>
H_ F ERR#
2
56_0402_5%
H_ P W RGOOD <6,7>
H_ F ERR# <6>
3/28 add 56ohm
H_ IGNNE# <6>
within 2" from R379
H_ INIT# <6>
H_ INTR <6>
KB_RST# <32>
+ V CCP
H_ NMI <6>
H_SMI# <6>
R315
56_0402_5%
H_STPCLK# <6>
R319
2 54.9_0402_1%
H_THERMTRIP# <6,9>
placed within 2"

from ICH9M
AG27
AH11
AJ11
AG12
AF12
0.01U_0402_50V7K
2
1 C428
2
1 C429
SATA_TXN4_C
SATA_TXP4_C
SATA_RXN4_C <24>
SATA_RXP4_C <24>
SATA_TXN4 <24>
SATA_TXP4 <24>
SATA_TXN4
SATA_TXP4
ODD
AH9
AJ9
AE10
AF10
AH18
AJ18
AJ7
AH7
SATA_TXN5_C
SATA_TXP5_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
R322
2
2
ESATA@
ESATA@
SATA_RXN5_C <30>
SATA_RXP5_C <30>
SATA_TXN5 <30>
SATA_TXP5 <30>
0.01U_0402_50V7K
SATA_TXN5
1 C430
SATA_TXP5
1 C432
0.01U_0402_50V7K
e-SATA
De-feature disable
CLK_PCIE_SATA# <17>
CLK_PCIE_SATA <17>
1
2
24.9_0402_1%
Within 500 mils
ICH9-M ES_FCBGA676
H_DPRSTP#
2
0_0402_5%
0.01U_0402_50V7K
SATA
<28>
<29>
<9>
<28>
<29>
<9>
<28,32>
<29>
<9>
G LAN_COMP
LAN / GLAN
D13
D12
E13
+1.5VS
R311
24.9_0402_1%
1
2
LAN_RXD0
LAN_RXD1
LAN_RXD2
CPU
F14
G13
D14
DPRSTP#
DPSLP#
LAN_RSTSYNC
C13
Add 12p on HDA_SDOUT and HDA_SDOUT

XOR CHAIN ENTRANCE STRAP:RSVD
+3VS
@ R325
1
HDA _ SDOUT_MDC
C311 1
12P_0402_50V8J
HDA _ S DOUT_CODEC
C312 1
12P_0402_50V8J
BATT1
HDA _ S DOUT_CODEC
2
1K_0402_5%
@
ICH_ R SVD
2
1K_0402_5%
+ RT CVCC
0821 Change C528 and C516 to 15PF
ICH_ RSVD <22>
I CH_RTCX1
R328
1
HDA_SDOUT_CODEC
C436
15P_0402_50V8J
D8
R329
1
2
1
C437
15P_0402_50V8J
2
@
C439
10P_0402_25V8K
3
W=20mils
R330
1
JBATT1
2
1
2
3
4
W=20mils
1K_0402_5%
DAN202U_SC70
C438
2.2U_0603_6.3V4Z
1
2
GND
GND
ACES_85205-02001
C ONN@
Place near ICH9
Y2
1
32.768KHZ_12.5P_MC-146
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
0_0402_5%
1
W=20mils
W=20mils
10M_0402_5%
ICH_RSVD
BATT1.1
@
R327
10_0402_5%
I CH_RTCX2
CR2032 RTC BATTERY
+3VL
H DA_BITCLK
1
@ R326
1
Title

ICH9(2/4)_LAN,HD,IDE,LPC

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
21
of
46
R331 1
R332 1
+3VALW
+3VS
2 2.2K_0402_5%
2 2.2K_0402_5%
U1 2C
R374
R375
R376
R377
R378
R379
R373
R380
B
R381
@ R339
10K_0402_5%
@ R340
<9> PM_BMBUSY#
10K_0402_5%
E C _SCI#
2
<17> H_STP_PCI#
<17> H_STP_CPU#
C R_WAKE#
R345
2 0_0402_5%
M6
E C_LID_OUT#
A17
H_STP_PCI#
R_STP_CPU#
A14
E19
P M _CLKRUN#
L4
GPIO18
IC H_PCIE_WAKE# E20
S I RQ
M5
T HERM_SCI#
AJ23
<25,26> ICH_PCIE_WAKE#
<32> S IRQ
<32> T HERM_SCI#
HD DHALT_LED#
GPIO20
VGATE
<17,43> VGATE
GPIO21
R353
GPIO36
1
2
100K_0402_5%
D21
A20
P AD T59
O CP#
AG19
CR _CPPE#
AH21
EC_SCI#_SB
R225
1
2 0_0402_5%
AG21
EC_SMI#
A21
@ R226
0_0402_5%
E
C_SCI#_GPIO12
1
2
C12
C21
P AD T46
17/14
AE18
GPIO18
K1
GPIO20
AF8
<19> GPIO20
C R_WAKE#
AJ22
<27> CR_WAKE#
DIS /UMA
A9
D19
P AD T47
CL KREQ#_C
L1
<17> CL KREQ#_C
GPIO38
1
2
AE19
+3VS
R364
8.2K_0402_5%
GPIO39
AG22
R739 1
GPIO48
2
AF21
<26> EXP_CPPE#
0_0402_5%
GPIO49
AH24
GPIO57
A8
@ R366 1
2 1K_0402_5%
+3VS
SB_SPKR
M7
<28> SB_SPKR
M CH_ ICH _SYNC# AJ24
<9> M CH_ ICH_SYNC#
ICH_ R SVD
B21
<21> ICH_ RSVD
AH20
AJ20
AJ21
R366
<6> OCP#
GPIO37
<27> CR_CPPE#
<32> E C_SCI#
<32> EC_SMI#
SUS_STAT#/LPCPD#
SYS_RESET#
CLK14
CLK48
SUSCLK
PMSYNC#/GPIO0
SLP_S3#
SLP_S4#
SLP_S5#
SMBALERT#/GPIO11
STP_PCI#
STP_CPU#
CLKRUN#
WAKE#
SERIRQ
THRM#
S4_STATE#/GPIO26
PWROK
VRMPWRGD
TP11
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
C LK_14M_ICH
C LK_48M_ICH
P1
ICH_ SUSCLK
C16
E16
G17
SLP_S3#
SLP_S4#
SLP_S5#
C10
S4_STATE#
Place closely pin

AF3
CLK_14M_ICH <17>
CLK_48M_ICH <17>
PM_PWROK
R348 1
B13
ICH_LOW_BAT#
R3
PWRBTN_OUT#
@ R342
@ R343
10_0402_5%
10_0402_5%
T58 P AD
1
M2
C LK_14M_ICH
HDDHALT_LED# <33>
SLP_S3# <32>
SLP_S4# <32>
SLP_S5# <32>
G20
Place closely pin

H1
C LK_48M_ICH
1
H1
AF3
11/09 Change Gsensor control from SB
@ C440
@ C441
D
4.7P_0402_50V8C
4.7P_0402_50V8C
R346
10K_0402_5%
1
2
DP RSLPVR <9,43>
PM_PWROK <9,32>
2 0_0402_5%
PWRBTN_OUT# <32>
D20
R_EC_RSMRST# <39>
D22
R_EC_RSMRST#
R5
CK _ P WRGD
R6
M _PWROK
R354 1
R355 1
CK _ P WRGD <17>
11/17 Add +3VALW GD to EC_RSMRST#

to fix Battery mode can't boot issue
2 100_0402_5%
2 10K_0402_5%
EC_RSMRST# <32>
LINKALERT#
ICH_ R I#
TV Tuner
XDP_DBRESET#
<26>
<26>
<26>
<26>
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
C445 1
C444 1
2MiniC@
2MiniC@
S4_STATE#
ME_EC_CLK1
WLAN
<26>
<26>
<26>
<26>
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
C448 1
C449 1
PCIE_RXN3
PCIE_RXP3
2 0.1U_0402_16V4Z PCIE_C_TXN3
2 0.1U_0402_16V4Z PCIE_C_TXP3
J29
J28
K27
K26
LAN
<25>
<25>
<25>
<25>
GLAN_RXN
GLAN_RXP
GLAN_TXN
GLAN_TXP
C452 1
C453 1
2
2
G LAN_RXN
GLAN_RXP
0.1U_0402_16V4Z GLAN_TXN_C
0.1U_0402_16V4Z GLAN_TXP_C
G29
G28
H27
H26
Card Reader
<27>
<27>
<27>
<27>
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
C816 1
C817 1
PCIE_RXN5
PCIE_RXP5
2 0.1U_0402_16V4Z PCIE_C_TXN5
2 0.1U_0402_16V4Z PCIE_C_TXP5
E29
E28
F27
F26
New Card
<26>
<26>
<26>
<26>
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
PCIE_RXN4
PCIE_RXP4
2 0.1U_0402_16V4Z PCIE_C_TXN4
2 0.1U_0402_16V4Z PCIE_C_TXP4
C29
C28
D27
D26
GPIO10
E C_LID_OUT#
EC_SMI#
GPIO14
Board ID
<31,32> SPI_CLK
<31> SPI_SB_CS#
<20> SPI_CS1#_R
1
2
17/14
C450 1
C451 1
Ne wC@
Ne wC@
R417 1
2 15_0402_5%
SPI_CS1#_R
SPI_SI
SPI_SO_R
R416 1
2 15_0402_5%
<31> SPI_SI
<31> SPI_SO_R
SPI_CLK
SPI_SB_CS#
11/20 Add HDCP ROM for ICH9M

<30> BT_OFF
RP27
U SB_OC#6
U SB_OC#1
U SB_OC#2
U SB_OC#4
4
3
2
1
5
6
7
8
R383 1
2 0_0402_5%
<26> WXMIT_OFF#
+3VALW
10K_1206_8P4R_5%
RP28
5
6
7
8
10K_1206_8P4R_5%
RP29
WXMIT_OFF#
U SB_OC#5
USB_OC#10
USB_OC#11
4
3
2
1
5
6
7
8
10K_1206_8P4R_5%
+3VS
U SB_OC#0
U SB_OC#1
U SB_OC#2
WXMIT_OFF#
U SB_OC#4
U SB_OC#5
U SB_OC#6
U SB_OC#7
U SB_OC#8
U SB_OC#9
USB_OC#10
USB_OC#11
U SBRBIAS
4
3
2
1
C25
A19
CL _ VREF0_ICH
CL _ VREF1_ICH
F21
D18
CL_RST#
A16
C18
C11
C20
XMIT_OFF
GPIO10
GPIO14
L AN_WOL_EN
C442
CL_RST# <9>
3.24K_0402_1%
R363
453_0402_1%
CL_DATA0 <9>
NA lead free
+3VALW
R367
XMIT_OFF <26>
C443
R370
+3VALW
100K_0402_5%
3.24K_0402_1%
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
CL_DATA0
R368
453_0402_1%
1
R399
2SPI_SB_CS#
10K_0402_5%
1
R429
2 SPI_SI
10K_0402_5%
1
R430
2 SPI_SO_R
10K_0402_5%
Within 500 mils
D23
D24
F23
D25
E23
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
AG2
AG1
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
SPI
SPI_MOSI
SPI_MISO
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
V27
V26
U29
U28
D MI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>
Y27
Y26
W29
W28
D MI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>
AB27
AB26
AA29
AA28
D MI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>
AD27
AD26
AC29
AC28
D MI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_RXN3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>
T26
T25
CL K _PCIE_ICH#
CL K _ PCIE_ICH
AF29
AF28
DM I_ IRCOMP
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
CL K _PCIE_ICH# <17>
CL K _ PCIE_ICH <17>
R382
1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
24.9_0402_1%
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
<30>
<30>
<30>
<30>
<30>
<30>
<34>
<34>
<19>
<19>
<26>
<26>
<30>
<30>
<30>
<30>
<26>
<26>
<26>
<26>
Within 500 mils

+1.5VS
USB-0 Right side

USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USBRBIAS
USBRBIAS#
ICH9-M ES_FCBGA676
R384
22.6_0402_1%
2
U SB_OC#7
U SB_OC#8
U SB_OC#9
U SB_OC#0
N29
N28
P27
P26
L29
L28
M27
M26
11/17 Swap PCIE LAN and New card
R748
10K_0402_5%
PCIE_RXN1
PCIE_RXP1
2 0.1U_0402_16V4Z PCIE_C_TXN1
2 0.1U_0402_16V4Z PCIE_C_TXP1
ME_EC_DATA1
R746
10K_0402_5%
CL_RST0#
CL_RST1#
F22
C19
R360
CL_CLK0 <9>
U1 2D
@ R747
10K_0402_5%
DIS /UMA
CL_VREF0
CL_VREF1
C L_CLK0
ICH9-M ES_FCBGA676
IC H_PCIE_WAKE#
+3VS
Low -->default
High -->No boot
ICH_LOW_BAT#
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
CL_DATA0
CL_DATA1
+3VS
F24
B19
GPIO49
CL_CLK0
CL_CLK1
M _PWROK <9,32>
B16
0.1U_0402_16V4Z
GPIO57
SLP_M#
0.1U_0402_16V4Z
GPIO48
CLPWROK
MISC
GPIO
Controller Link
GPIO39
@ R745
10K_0402_5%
SATA
GPIO
R4
G19
PM_BMBUSY#
<32> E C_LID_OUT#
CR _CPPE#
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
1K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
+3VS
SUS_STAT#
XDP_DBRESET#
clocks
RI#
Direct Media Interface
R372
PM_BMBUSY#
T57
<6> XDP_DBRESET#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
GPIO21
HD DHALT_LED#
GPIO36
GPIO37
P AD
CL KREQ#_C
SMB
PCI - Express
R371
F19
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
AH23
AF19
AE21
AD20
+3VALW
R369
ICH_ R I#
T HERM_SCI#
1
2
@ R365 10K_0402_5%
+3VS
G16
A13
E17
C17
B18
SYS / GPIO
O CP#
P M _CLKRUN#
IC H_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
Power MGT
S I RQ
1
2
10K_0402_5%
1
2
R334
8.2K_0402_5%
1
2
R335
10K_0402_5%
1
2
@ R336 8.2K_0402_5%
1
2
@ R337 10K_0402_5%
1
2
@ R338 8.2K_0402_5%
1
2
R341
8.2K_0402_5%
1
2
R344
8.2K_0402_5%
1
2
R356
8.2K_0402_5%
1
2
R349
8.2K_0402_5%
1
2
R350
8.2K_0402_5%
1
2
R351
8.2K_0402_5%
1
2
R352
8.2K_0402_5%
1
2
R357
8.2K_0402_5%
1
2
R358
8.2K_0402_5%
1
2
R359
10K_0402_5%
1
2
R361
8.2K_0402_5%
1
2
R362
8.2K_0402_5%
R333
Compal Secret Data
2007/08/28
Issued Date
01/03 Change HDCP ROM to +3VS
2006/03/10
Deciphered Date
4
Title

ICH9(3/4)_DMI,USB,GPIO,PCIE

Da te:
Rev
0.3
UMA LA 4101P
Sheet
1
22
of
46
+ RT CVCC
+ V CCP
U12E
+3VS
R386
C458
220U_D2_4VM
+5VS
A23
ICH_ V 5 REF_RUN
A6
ICH _V5REF_SUS
AE1
C460
C456
10U_0805_10V4Z
2
2.2U_0603_6.3V4Z
D9
C464
2
+ V CCP
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
G10
G9
C483
0.1U_0402_16V4Z
C484
0.1U_0402_16V4Z
V CC_LAN1_05_INT_ICH_1
V CC_LAN1_05_INT_ICH_2
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
2.2U_0603_6.3V4Z
10U_0805_10V4Z
C487
A27
4.7U_0805_10V4Z
2
D28
+1.5VS
D29
CHB1608U301_0603
E26
1
C488
E27
1
VCCGLANPLL
R391
1
C489
0316 change design
+3VS
2
80mA
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
1mA
A26
VCCGLAN3_3
ICH9-M ES_FCBGA676
GLAN POWER
CHB1608U301_0603
2
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL1_05
VCCCL1_5
VCCLAN3_3[1]
19/78/78mA
VCCLAN3_3[2]
23mA
C473
R212 @
0_0402_5%
0.1U_0402_16V4Z
AC8
F17
T65
T66
AD8 V CC SUS1_5_ICH_1
A18
D16
D17
E22
R740
2 180_0402_1%
0.1U_0402_16V4Z
1
+3VALW
+1.5VS
C474
AJ3
R741
150_0402_1%
+1.5VALW
T67
V CC SUS1_5_ICH_2
T68
0.1U_0402_16V4Z
1
VCCSUS3_3[05]
VCC1_5_A[21]
A12
B12
R390
1
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
(DMI)
AJ4
F18
+1.5VS
212mA
USB CORE
T69
T70
VCCSUS1_5[2]
VCC1_5_A[22]
11mA
11mA
AA7
AB6
AB7
AC6
AC7
+3VS
VCCSUS1_5[1]
VCC1_5_A[20]
AJ5
VCCHDA
VCCSUSHDA
VCC1_5_A[18]
VCC1_5_A[19]
AC12
AC13
AC14
+1.5VS
2
+3VALW
AF1
VCC1_5_A[17]
AC21
1342mA
AC9
AC18
AC19
+1.5VS
0.1U_0402_16V4Z
C480
+3VS
0.1U_0402_16V4Z
C479
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
B9
F9
G3
G6
J2
J7
K7
C475
ATX
C481
1U_0603_10V4Z
+1.5VS
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
AD19
AF20
AG24
AC20
308mA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCPSUS
C478
1U_0603_10V4Z
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCCPUSB
C477
10U_0805_10V4Z
+3VS
AG29
AJ6
AC10
VCCSATAPLL
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
+1.5VS
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
11mA
ARX
1U_0603_10V4Z
C476
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
AB23
AC23
C468
+ VCCP
1
C467
W23
Y23
10U_0805_10V4Z
0.1U_0402_16V4Z
R29
C463
C466
0.1U_0402_16V4Z
AJ19
+1.5VS
0.1U_0402_16V4Z
C461
+1.5VS
4.7U_0603_6.3V6M
2mA
11mA
C471
0316 change design
C485
0.1U_0402_16V4Z
0.1U_0402_10V6K
48mA V_CPU_IO[1]
V_CPU_IO[2]
47mA
R385
1
2
CHB1608U301_0603
0.01U_0402_16V7K
C470
C472
R389
1
2
CHB1608U301_0603
+1.5VS
C469
ICH _V5REF_SUS
20 mils
0.1U_0402_16V4Z
CH751H-40_SC76
VCCDMIPLL
23mA VCC_DMI[1]
VCC_DMI[2]
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
C457
C455
0.1U_0402_16V4Z
D10
10_0402_5%
C
646mA
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
0.1U_0402_10V6K
+5VALW +3VALW
R388
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
2mA
VCCP_CORE
20 mils
C465
V5REF_SUS
PCI
ICH_ V 5 REF_RUN
1
1634mA VCC1_05[01]
VCC1_05[02]
2mA
22U_0805_6.3VAM
CH751H-40_SC76
G3: 6uA
VCCA3GP
100_0402_5%
V5REF
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
10U_0805_10V4Z
C459
VCCRTC
CORE
R387
1
2
40 mils
CHB1608U301_0603
1
+1.5VS
C454
0.1U_0402_16V4Z
C462
0.1U_0402_16V4Z
U12F
20 mils
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
G22
G23
+3VALW
V CCC L1_05_ICH
C482
4.7U_0603_6.3V6M
T71
19/73/73mA
VCCCL3_3[1]
VCCCL3_3[2]
A24
B24
1 @
C486
1U_0603_10V4Z
+3VS
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH9-M ES_FCBGA676
A
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
Title

ICH9(4/4)_POWER&GND

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
23
of
46
C493
+3VS
+3VS_ACL
+3VS_ACL_IO
GS@ D23
2
GS@ R564
0_0603_5%
1
2
Near CONN side.

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+ 3VS_HDD1
Pleace near HDD CONN

IC H_SMBCLK
@ C497
@ C498
VDDIO absolute man

rating is VDD+0.1
1
+3VS_ACL_IO
GS@ R568
0_0402_5%
1
2
Vdd_IO
ICH_SMBCLK <17,22,26>
14
U29 GS@
SCL / SPC
@ C496
1U_0603_10V4Z
+ 3VS_HDD1
+3VS
+5VS
@ R392
1
2
0_0805_5%
0011101b
SDA / SDI / SDO
13
ICH_SMBDATA
12
R570 GS@
0_0402_5%
1
2
ICH_SMBDATA <17,22,26>
GND
SUYIN_127072FR022G523_RV
C ONN@
+3VS_ACL
SDO
Reserved
4
5
11
Reserved
GND
GND
GND
INT 2
Vdd
INT 1
CD-ROM Connector
10
9
8
A CCEL_INT <20>
CS
C714
10U_0805_6.3V6M
SATA_RXN0_C <21>
SATA_RXP0_C <21>
C492
C713
C490
SATA_TXP0 <21>
SATA_TXN0 <21>
+3VS_ACL
GS@
1 C494 SATA_RXN0_C
1 C495 SATA_RXP0_C
C491
ACCELEROMETER (ST)
0.1U_0402_16V4Z
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K
0.1U_0402_16V4Z
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
SATA_TXP0
SATA_TXN0
1000P_0402_50V7K
1
2
3
4
5
6
7
10U_0805_10V4Z
J P3
GND
A+
AGND
BB+
GND
Pleace near HDD CONN (JP3)
+5VS
0.1U_0402_16V4Z
HDD Connector
GS@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LIS302DLTR_LGA14_3x5
+5VS
1 C510 SATA_RXN4_C
1 C511 SATA_RXP4_C
SATA_TXP4 <21>
SATA_TXN4 <21>
SATA_RXN4_C <21>
SATA_RXP4_C <21>
Near CONN side.

6
5
4
3
2
1
C512
C513
C514
C515
1
10K_0402_5%
M ust be placed in the center of the system.
10U_0805_10V4Z
SATA_TXP4
SATA_TXN4
0.01U_0402_16V7K
SATA_RXN4
2
SATA_RXP4
2
0.01U_0402_16V7K
10U_0805_10V4Z
DP
V5
V5
MD
GND
GND
13
12
11
10
9
8
7
1U_0603_10V4Z
GND
A+
AGND
BB+
GND
2
GS@ R569
Placea caps. near ODD CONN.
0.1U_0402_16V4Z
J P5
ACCELEROMETER (Bosch)
+5VS
SUYIN_127382FR013GX09ZR
C ONN@
U14 @
BMA150
Multi Bay
A CCEL_INT
+3VS_ACL
+5VS
+5VS
JP12
1
R571
2 G _CS#
10K_0402_5%
ICH_SMBDATA
SATA_RXN1 C822 2
SATA_RXP1 C823 2
IC H_SMBCLK
SATA_TXP1 <21>
SATA_TXN1 <21>
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
Multi@
Multi@
SATA_RXN1_C
SATA_RXP1_C
SATA_RXN1_C <21>
SATA_RXP1_C <21>
C297
Multi@
17
C298
Multi@
C299
Multi@
C300
Multi@
5
6
7
10U_0805_10V4Z
GND GND
TYCO_2023087
C ONN@
SATA_TXP1
SATA_TXN1
10U_0805_10V4Z
GND
TX+
TXGND
RXRX+
GND
GND
1U_0603_10V4Z
18
VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND
1
2
3
4
5
6
7
8
0.1U_0402_16V4Z
16
15
14
13
12
11
10
9
Placea caps. near Multi Bay CONN.
INT
VDDIO
VDD
CSB
GND
SCK
RSVD
RSVD
9
2
+3VS_ACL_IO
+3VS_ACL
3
1
10
SDO
SDI
RSVD
RSVD
11
12
BMA150_LGA12
Z ZZ2
2007/08/28
Issued Date
PCB-MB
5
Compal Secret Data
2006/03/10
Deciphered Date
3
Title

HDD & CDROM

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
24
of
46
LAN Conn.
J RJ45
Place Close to Chip
U44
LAN_ACTIVITY#
<22> GLAN_RXP
C240 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_P2
20
<22> GLAN_RXN
C241 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N2
21
<22> GLAN_TXP
15
<22> GLAN_TXN
16
17
18
<17> CLK_PCIE_LAN
<17> CLK_PCIE_LAN#
<17> CLKREQ#_9
25
<9,20,26,27> PLT_RST#
27
R688 1
2 2.49K_0402_1%
+3VS
46
ISOLATEB
26
28
LAN_X1
LAN_X2
41
42
HSOP
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
HSON
HSIP
LED0
HSIN
RTL8102EL
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
REFCLK_P
REFCLK_M
CLKREQB
PERSTB
RSET
NC
LANWAKEB
ISOLATEB
VCTRL12A
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
33
34
35
32
L A N_DO
L A N_DI
LAN_SK_LAN_LINK#
L AN_CS
38
LAN_ACTIVITY#
2
3
5
6
8
9
11
12
L AN_MDI0+
L AN_MDI0L AN_MDI1+
L AN_MDI1-
R697
1 300_0402_5%
14
1
8
2
C268
@ 68P_0402_50V8K
7
RJ 45_MIDI1-
6
5
4
RJ 45_MIDI1+
RJ 45_MIDI0-
RJ 45_MIDI0+
4
48
VCTRL12
LAN_SK_LAN_LINK#
19
30
36
13
10
@ C269
+3V_LAN
68P_0402_50V8K
1 R698
2
1 300_0402_5%
11
12
+ EVDD12
+ LAN_VDD12
Yellow LED+
Yellow LEDSHLD1
PR4DETECT PIN1
16
D
PR4+
PR2PR3PR3+
PR2+
PR1DETCET PIN2
PR1+
SHLD1
10
15
Green LED+
Green LEDFOX_JM36113-P1122-7F
C ONN@
CKXTAL1
CKXTAL2
R215
1K_0402_1%
13
+3V_LAN
NC
23
24
Check??
ISOLATEB
7
14
31
47
R216
15K_0402_5%
22
NC
NC
NC
VCTRL12D
GND
GND
GND
GND
VDD33
VDD33
AVDD33
NC
NC
GNDTX
L A NG ND
39
44
45
+ LAN_VDD12
29
37
C271
0.1U_0402_16V4Z
C272
4.7U_0805_10V4Z
+3V_LAN
1
40
43
RTL8102EL-GR_LQFP48_7X7
U46
10/29 update
C247 1
2 0.01U_0402_16V7K
L AN_MDI0+
L AN_MDI0LAN_CT0
1
2
3
4
5
6
7
8
PJP4
1
+3VALW
2
C248 1
2 0.01U_0402_16V7K
P AD-OPEN 4x4m
S
40 mils
1
1
R218
2
10K_0402_5%
RJ45_MIDI0+ <34>
RJ45_MIDI0- <34>
C257 1
C258 1
2 0.01U_0603_100V7-M R J45_CT0_C
2 0.01U_0603_100V7-M R J45_CT1_C
RJ45_CT1
RJ 45_MIDI1+
RJ 45_MIDI1-
RJ45_MIDI1+ <34>
RJ45_MIDI1- <34>
1
1
R693
75_0402_1%
2
2
RJ 4 5 _GND
R694
75_0402_1%
C259
1000P_1206_2KV7K
+3V_LAN
LEF8423A-R
2
2
1
<32> L A N_POWER_OFF
RJ 45_MIDI0+
RJ 45_MIDI0RJ45_CT0
16
15
14
13
12
11
10
9
RX+
RXCT
NC
NC
CT
TX+
TX-
@
C255
LAN_CT1
L AN_MDI1+
L AN_MDI1-
RD+
RDCT
NC
NC
CT
TD+
TD-
Q19
0.1U_0402_16V4Z
1
R695
2
+3V_LAN
3.6K_0402_5%
U45
+ LAN_VDD12
Close to Pin10,13,30,36
L A N_DO
L A N_DI
LAN_SK_LAN_LINK#
L AN_CS
+3V_LAN
Close to Pin1,37,29
4
3
2
1
DO
DI
SK
CS
5
6
7
8
GND
NC
NC
VCC
C256
0.1U_0402_16V4Z
+3V_LAN
C253
C254
C261
0.1U_0402_16V4Z
C252
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C251
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C250
0.1U_0402_16V4Z
C249
0.1U_0402_16V4Z
AT93C46-10SI-2.7_SO8
2
R696
1
10K_0402_5%
Y3
Close to Pin19
Close to Pin45
+EVDD12
LAN_X1
Close to Pin48
+LAN_VDD12
@ 1
C262
2
C263
0.1U_0402_16V4Z
1
10U_0805_10V4Z
C264
@
C265
10U_0805_10V4Z
0.1U_0402_16V4Z
C267
0.1U_0402_16V4Z
1U_0402_6.3V4Z
C266
A
LAN_X2
25MHz_20pF_6X25000017
VCTRL12
C244
27P_0402_50V8J
2 27P_0402_50V8J
2
10/09 update
C245
Change the PCB Footprint from

Y_KDS_1BX25000CK1A_2P to
Y_6X25000017_2P
A
Compal Secret Data
Issued Date
2007/08/28
2007/06/30
Deciphered Date
5
Title

RTL8102EL LAN

Cu s tom
Montevina Blade UMA LA4101P
Da te:
Rev
0.3
Sheet
Saturday, January 05, 2008

1
25
of
46
Mini Card 0--TV tuner/WWAN/Robson
Mini Card 2---WLAN
SIM card Connector
+3VS_WLAN
+3VALW
+3VALW
+1.5VS_WLAN
+ 3VS_WWAN
JP4
0.1U_0402_16V4Z
0.01U_0402_16V7K 4.7U_0805_10V4Z
C572
2MiniC@
C573
2MiniC@
C574
2MiniC@
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
UIM _PWR
UIM_DATA
UI M_CLK
U IM_RST
UIM_VPP
C575
2MiniC@
0.1U_0402_16V4Z
1
2
3
4
5
6
7
1
2
3
4
5
6
7
G1
G2
C566
2
4.7U_0805_10V4Z
8
9
C567
C568
4.7U_0805_10V4Z
1
C569
C570
C571
+1.5VS
R431 1
0_0805_5%
+1.5VS_WLAN
+3VS
R432 1
0_0805_5%
+3VS_WLAN
2
2
0.1U_0402_16V4Z
ACES_88266-07001
C ONN@
+ 3VS_WWAN
J P6
IC H_PCIE_WAKE#
C H_DATA
CH_ CLK
CLKREQ#_10
<17> CLKREQ#_10
<17> CLK_PCIE_MCARD0#
<17> CL K_PCIE_MCARD0
2MiniC@
2MiniC@
R419 1
1
R421
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
J P7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+1.5VS_WLAN
UIM _PWR
UIM_DATA
UI M_CLK
U IM_RST
UIM_VPP
M_WXMIT_OFF#
PLT_RST#
@R420
1
R422
1
2MiniC@
IC H_SMBCLK
ICH_SMBDATA
CL K_PCIE_MCARD2#
CL K_PCIE_MCARD2
<17> CLK_PCIE_MCARD2#
<17> CL K_PCIE_MCARD2
PLT_RST#
2 0_0402_5%
+3VALW
2 0_0402_5%
+ 3VS_WWAN
+1.5VS_WLAN
R423 1
R425 1
P CIE_C_RXN3
PCIE_C_RXP3
2 0_0402_5%
2 0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WLAN
+1.5VS_WLAN
1
2
1
2
1
2
1
2
1
2
R699
R700
R701
R702
R703
XMIT_OFF#
PLT_RST#
R424 1
@ R426 1
0_0402_5% DE BUG@
0_0402_5% DE BUG@
0_0402_5% DE BUG@
0_0402_5% DE BUG@
0_0402_5% DE BUG@
2 0_0402_5%
2 0_0402_5%
LPC_FRAME# <21,31,32>
LPC_AD3 <21,31,32>
LPC_AD2 <21,31,32>
LPC_AD1 <21,31,32>
LPC_AD0 <21,31,32>
GND1
GND2
W W _LED# <33>
+3VS_WLAN
+1.5VS_WLAN
11/17 Reserve UIM_DATA

PU to UIM_PWR
+ 3VS_WWAN
54
53
+3VS_WWAN
AP2305GN
D
@
R434
100K_0402_5%
2
+3VALW
UI M_CLK
1
Q52
2MiniC@
3
M_WXMIT_OFF#
54
GND2
C824 @
18P_0402_50V8J
<22> XMIT_OFF
2
G
Express Card Power Switch

U16
12
14
+3VS
C579 1
C580 1
Ne wC@
2 0.1U_0402_16V4Z
Ne wC@
2 0.1U_0402_16V4Z
2
4
17
+3VALW
<9,20,25,27> PLT_RST#
<32,33,36,41> S Y S ON
<28,32,36,38,40,41> SUSP#
+3VALW
<22> EXP_CPPE#
PLT_RST#
S Y SON
20
SUSP#
R439 1
2 100K_0402_5%
10
EXP_CPPE#
9
18
<22> USB20_N9
<22> USB20_P9
Ne wC@
1.5Vin
1.5Vin
1.5Vout
1.5Vout
3.3Vin
3.3Vin
3.3Vout
3.3Vout
AUX_IN
SYSRST#
SHDN#
AUX_OUT
OC#
PERST#
STBY#
NC
CPPE#
GND
11
13
R436
R437
2 0_0402_5%
2 0_0402_5%
1
1
Ne wC@
USB9USB9+
EXP_CPPE#
+1.5VS_PEC
IC H_SMBCLK
ICH_SMBDATA
3
5
+3VS_PEC
15
+3V_PEC
R438
1
2
0_0402_5%
Ne wC@
19
8
+3VS_PEC
+1.5VS_PEC
+1.5VS_PEC
+3V_PEC
PCIE_PME#_R
PERST#
+3VS_PEC
PERST#
CLKREQ#_4
EXP_CPPE#
<17> CLKREQ#_4
16
<17> CL K _ PCIE_NCARD#
<17> CL K _ PCIE_NCARD
<22> PCIE_RXN4
<22> PCIE_RXP4
CPUSB#
<22> PCIE_TXN4
<22> PCIE_TXP4
RCLKEN
R5538D001-TR-F_QFN20_4X4~D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
internal pull high to 3.3Vaux-in

EC need setting at Hi-Z & output Low
JEXP1
Ne wC@
+1.5VS
C576
Ne wC@
1
2 0.1U_0402_16V4Z
Near to Express Card slot.
Close to
JEXP
New Card
@
Q10
2N7002_SOT23-3
R435
1
2
0_0402_5%
01/03 Prevent WLAN leakage
<32> W W A N_POWER_OFF
XMIT_OFF#
D
2
G
CH751H-40_SC76
CH751H-40_SC76
2MiniC@
D19
1
+3VS_WLAN
@ R433
10K_0402_5%
@ R418
1
2
0_1206_5%
0811 Pins 37 and 43 connect to GND and remove +1.5VS

2
GND1
WL_LED# <33>
+1.5VS_WLAN
FOX_AS0B226-S40N-7F
C ONN@
+3VALW
0821 Change +3VS to +3VS_WWAN

D1 1
1
@ R750
1
2 UIM_DATA
47K_0402_5%
UIM _PWR
FOX_AS0B226-S40N-7F
C ONN@
USB20_N5 <22>
USB20_P5 <22>
53
PCIE_TXN3
PCIE_TXP3
<22> PCIE_TXN3
<22> PCIE_TXP3
USB20_N8 <22>
USB20_P8 <22>
0_0603_5%
2
2
0_0603_5%
+3VALW
+3VS_WLAN
+1.5VS_WLAN
IC H_SMBCLK
ICH_SMBDATA
R427
1
1
R428
2MiniC@
2MiniC@
<22> PCIE_RXN3
<22> PCIE_RXP3
+3VS_WWAN
<22> WXMIT_OFF#
IC H_PCIE_WAKE#
C H_DATA
CH_ CLK
CLKREQ#_6
<30> CH_DATA
<30> CH_ CLK
<17> CLKREQ#_6
PCIE_TXN1
PCIE_TXP1
<22> PCIE_TXN1
<22> PCIE_TXP1
0_0402_5%
2 P CIE_C_RXN1
2 PCIE_C_RXP1
0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<22> PCIE_RXN1
<22> PCIE_RXP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
C577
0.1U_0402_16V4Z
Ne wC@
C578
4.7U_0805_10V4Z
2 Ne wC@
+1.5VS_PEC
C581
0.1U_0402_16V4Z
Ne wC@
C582
4.7U_0805_10V4Z
2 Ne wC@
+3V_PEC
GND
GND
29
30
SANTA_130801-5_LT
C ONN@
C583
0.1U_0402_16V4Z
Ne wC@
C584
4.7U_0805_10V4Z
Ne wC@
01/03 New card PTH connector GND

Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
A
Title

WLAN, WWAN, New Card
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
E
26
of
46
09/26 (JMicron)recommend C1328/1000pF close to U36 pin5

09/26 (JMicron)recommend place C1329/0.1uF near by C1328
+ 1 . 8VS_CR
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)
+ 3VS
X D C D 0 # _SDCD#
X D C D 1 #_MSCD#
C 1326
1 0U_0805_10V4Z
09/26 (JMicron)recommend
width/length: 12mil /
<250mil for PREXT signal
(pin 7)
+ V C C _4IN1
R 1044
R 1043
1 10K_0402_5%
1 10K_0402_5%
2
2
X D W P # _ SDWP#
X D _RB#
R 7 09 1
2 10K_0603_5%
X D _CLE
3
4
R 1048 1
2 10K_0603_5%
X D_ALE
9
8
<22> P C IE_TXN5
<22> P CIE_TXP5
C 1321 2
C 1322 2
<22> P C I E_RXN5
<22> P C I E_RXP5
X D _RE#
R 1046
+ 3VS
2 200K_0402_5%
1 0 .1U_0402_16V4Z
1 0 .1U_0402_16V4Z
R 402 1
11/07 Change to 8.2K(vender)
01/03 Change Cardreader LED control
R 972
2 C 1328
+ V C C _ OUT
C 1329
0 .1U_0402_16V4Z
+ V C C _4IN1
R 704
0_0603_5%
1000P_0402_50V7K
P C I E _ C_RXN5
P C I E _C_RXP5
11
12
2 8.2K_0402_5%P REXT
2 10K_0402_5%
X IN
38
39
C 1324
10U_0805_10V4Z
APCLKN
APCLKP
APVDD
APV18
TAV33
APRXN
APRXP
DV33
DV33
DV33
DV18
DV18
APTXN
APTXP
APREXT
PCIES_EN
PCIES
JMB385
09/26 (JMicron)recommend add a

test point for pin 13 1 4
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
5
10
30
C 1336
C 1334
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
19
20
44
18
37
C 1325
0.1U_0805_50V7M
C 1335
0 .1U_0402_16V4Z
Use 0603 type and over 20

mils trace width on both side
+ 1 . 8VS_CR
09/26 (JMicron)recommend change to 0805 Size

X D _ SD_MS_D0
C 1332
X D _ SD_MS_D1
X D _ SD_MS_D2
0 .1U_0402_16V4Z
X D _ SD_MS_D3
S D C M D _ M S BS_XDWE#
S D C L K _ MSCLK_XDCE#
X D W P # _ SDWP#
X D _CLE
X D_D4
X D_D5
X D_D6
X D_D7
X D _RE#
X D _RB#
X D_ALE
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
C 1333
0 .1U_0402_16V4Z
09/26 (JMicron)recommend +VCC_OUT >30mil
1
@ R 706
100_0402_5%
SDCLK
@ R 707
100_0402_5%
M S C LK
@ R 708
100_0402_5%
R 404 1
<22> C R _ C P PE#
@ C 789
100P_0402_25V8K
D18
@ C 790
100P_0402_25V8K
<22> C R _ W A KE#
R 710
R 711
R 712
2 22_0402_5%
2 22_0402_5%
2 22_0402_5%
1
1
1
SDCLK
M S C LK
X D CE#
0_0402_5%
13
14
T78
X D C D 1 #_MSCD#
X D C D 0 # _SDCD#
2
C H 751H-40PT_SOD323-2
11/09 Add D18 for cardreader wake up
S D C L K _ MSCLK_XDCE#
1
2
<9,20,25,26> P L T_RST#
@ C 788
100P_0402_25V8K
15
16
17
+ V C C _OUT
use for PWR_EN#

C R _ L ED#
21
8mA sink current
XRSTN
XTEST
SEEDAT
SEECLK
NC
NC
NC
CR1_CD1N
CR1_CD0N
APGND
CR1_PCTLN
GND
GND
GND
GND
CR1_LEDN
+ V C C _OUT
40mil
+ 3VS
C 1330
0 .1U_0402_16V4Z
IN
EN
OUT
OUT
1
5
GND
G5250C2T1U_SOT23-5
C 1331 2
1 U_0603_10V4Z
24
31
32
33
@ R 1050
150K_0402_5%
reserved power circuit
11/07 Change U37 correct PCBFootprint SOT23

11/07 BOM delete for JMB385 internal LDO
D41
X D C D 0 # _SDCD#
@ U37
3
4
34
35
36
J MB3 8 5 -L G EZ 0 A_ L Q F P4 8 _ 7 X7
XDCD1#_MSCD#
+ V C C _4IN1
X D CE#
2
C 1327
0 .1U_0402_16V4Z
11/07 Stuff for JMB385 internal LDO
+ 3VS
U 36
11/07 Change to 10K(vender)
+ 3VS
<17> C L K _ SRC11#
<17> C L K _ SRC11
+ 3VS
2 4.7K_0402_5%
2 4.7K_0402_5%
1
R 1042 1
R 1041 1
1
D A N 2 0 2U_SC70
X D _ CD#
C 1047
270P_0402_50V7K
09/26 Must change P mos FET

+ 1 . 8VS_CR
+ 1.8VS
Card Reader Connector

JREAD1
+ V C C _4IN1
B
White LED: VF=3V, IF = 5mA, Res = 56ohm

11/09 don't support DIM function
+ 5VS
R 719
470_0402_5%
D 15 W hite
H T - F 1 96BP5_WHITE
32
10
9
8
7
6
5
4
X D W P # _ SDWP#
X D_ALE
X D _ CD#
X D _RB#
X D _RE#
X D CE#
X D _CLE
34
33
35
40
39
38
37
36
11
31
1 1
@ R 7 05
XD-VCC
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
SD-VCC
MS-VCC
7 IN 1 CONN
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
41
42
R 194
4.7K_0402_5%
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
SD-WP-SW
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
7IN1 GND
7IN1 GND
C R _ L ED#
2
G
Q101
2N7002_SOT23-3
X D _ SD_MS_D0
X D _ SD_MS_D1
X D _ SD_MS_D2
X D _ SD_MS_D3
X D_D4
X D_D5
X D_D6
X D_D7
21
28
+ V C C _4IN1
2
0_0805_5%
B
20
14
12
30
29
27
23
18
16
25
1
SDCLK
X D _ SD_MS_D0
X D _ SD_MS_D1
X D _ SD_MS_D2
X D _ SD_MS_D3
X D_D4
X D_D5
X D_D6
X D_D7
X D C D 0 # _SDCD#
X D W P # _ SDWP#
26
17
15
19
24
22
13
M S C LK
X D _ SD_MS_D0
X D _ SD_MS_D1
X D _ SD_MS_D2
X D _ SD_MS_D3
X D C D 1 #_MSCD#
11/07 Don't stuff for JMB385 internal LDO
7IN1 GND
7IN1 GND
T A I T W _ R 0 1 5 - B 1 0 - LM
CONN@
11/17 Update CIS library

A
01/03 Change Cardreader LED control
Compal Secret Data
S ecurity Classification
Issued Date
2007/08/28
Deciphered Date
2006/10/06
5
Title

USB CardReader&CONN
Size
D o c u m ent Number
C u s t om
Mo n te v in a
D a te:

1
Rev
0 .3
Bla d e UMA LA4 1 0 1P

Sheet
27
of
46
CODEC POWER
+1.5VS_HDA
(4.75V(4.56~4.94V))
300mA
+1.5VS
+5VALW
W=40Mil
R1053
1
2
0_0603_5%
C1341
+ V DDA_CODEC
2
0.1U_0402_16V4Z
<26,32,36,38,40,41> SUSP#
+ V DDA_CODEC
U39
1
IN
OUT
5
1
GND
SHDN
BYP
G9191-475T1U_SOT23-5 1
11/07 Change to 4.75V LDO

2
C1343
C1340
1U_0603_10V4Z
+ V DDA _CODEC_R
C1339
0.1U_0402_16V4Z
C1338
0.1U_0402_16V4Z
C1337
1U_0603_10V4Z
C1342
0.1U_0402_16V4Z
+ 3 V DD_CODEC
R1052
1
2
BLM18BD601SN1D_0603
1
+3VS
C1344
2.2U_0805_16V4Z
R1051
1
2
BLM18BD601SN1D_0603
0.1U_0402_16V4Z
U38
9
+ 3 V DD_CODEC
DVDD_CORE*
EAPD/ SPDIF OUT 0 or 1 / GPIO 0
38
VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2
AVDD1*
GPIO 3
AVDD2**
VREFOUT-E / GPIO 4
<21> HDA _ BITCLK_CODEC

<21> HDA _ S DOUT_CODEC
R1055 1
<21> HDA _ SDIN0
<21> HDA _ S Y NC_CODEC
@ R445
47K_0402_5%
EC_BEEP 1
2
<32> EC_BEEP
<21,32> HDA _RST#_CODEC
R1060 1
R1061 1
2 10K_0402_5%
C1349
@ C1358
1
2
0.1U_0402_16V4Z
2 HDA _ S DI N0_CODEC
33_0402_5%
HDA _ S Y NC _CODEC
10
HDA _RST#_CODEC
11
R1058
<19> DM IC_CLK
<22> SB_SPKR
HDA _ S DOUT_CODEC
47K_0402_5%
2 22_0402_5%
1
C1347
1
C1348
R1062 1
R1063 1
2 5.1K_0402_1%
2 39.2K_0402_1%
SENSEB#
SPDIF OUT0
43
44
45
S PDIF_OUT
S PDIF_OUT <34>
01/03 Change SPDIF to SPDIF1
48
SDO
SDI_CODEC
VREFOUT-B
SYNC
VREFOUT-C
28
VREFOUT_B
VREFOUT_B <29>
+ V DDA _CODEC_R
29
RESET#
SENSE_A
R1056
R1057
R1059
R683
C1346
13
SENSE
41
HP _OUTR
39
HP_OUTL
22
MIC_EXTR
21
MIC_EXTL
DMIC_CLK
PORTA_R
PORTA_L
1
2 5.1K_0402_1%
1
2 20K_0402_1%
1
2 39.2K_0402_1%
1
2 10K_0402_1%
0.1U_0402_16V4Z
1
2
HP _OUTR <29>
37
C1353
0.1U_0402_16V4Z
18
19
20
C1355
10U_0805_10V4Z
V C_REFA
1
2
27
42
7
2
0_1206_5%
PORTB_R
NC / OTP
PORTB_L
SENSE_B / NC
NC
PORTC_R
NC
PORTC_L
NC
PORTD_R
NC
PORTD_L
26
2
0_0402_5%
VREFFILT
PORTE_R
AVSS1*
PORTE_L
AVSS2**
PORTF_R
DVSS**
PORTF_L
2
0_1206_5%
GND
EXTMIC_DET# <29>
JACK_DET# <29,34>
INTMIC_DET# <29>
11/07 Change R1059 39.2K
HP Jack & Dock
HP_OUTL <29>
24
1
C1350
1
C1351
MIC_EXT_R <29>
1U_0603_10V6K
2
1U_0603_10V6K
M IC_ I NR
@ R1064
0_0603_5%
23
M IC _INL
36
L I NE_OUT_R
35
LINE_OUT_L
15
DOCK _ MICR
14
DOC K_MICL
M IC_ IN_R <29>
11/08 Change C1352 C1354 (recommend)

Internal MIC
1
C1354
L INE_OUT_R <29>
LINE_OUT_L <29> Internal

1
C1356
1
C1357
DOCK _ M ICR_C
1U_0603_10V6K
DOCK _MICL_C
2
1U_0603_10V6K
17
R735
1.21K_0402_1%
16
2
0.022U_0402_16V7K
M IC_IN_L <29>
SPKR.
R733 1
2 10K_0402_5%
DOCK _MIC_R <34>
R734 1
2 10K_0402_5%
DOCK_MIC_L <34>
DOCK MIC
R736
1.21K_0402_1%
92HD71B7X5NLGXA1X8_QFN48_7X7
GNDA <29,34>
Jack MIC
MIC_EXT_L <29>
1
2
C1352
0.022U_0402_16V7K
R596
1
34
@ C1361
1
2
0.1U_0402_16V4Z
R1065
1
BITCLK
1
33
1U_0603_10V4Z CAP2
M ONO_ INR
2
12
PCBEEP
0.1U_0402_16V4Z
40
+ V DDA _CODEC_R
<34> SENSE_B#
SPDIF OUT1 / GPIO 7
@ C1360
1
2
0.1U_0402_16V4Z
C1362
1
46
GPIO 6
2 0.1U_0402_16V4Z
@ C1359
1
2
0.1U_0402_16V4Z
MONO_OUT
31
11/09 reserve EC_BEEP
GPIO 5
30
HDA _BITCLK_CODEC
DVDD_IO
DM IC_DAT <19>
E A P D_CODEC <32>
@
C1345
33P_0402_50V8K
+1.5VS_HDA
32
E A P D_CODEC
HDA _BITCLK_CODEC
@
R1054
47_0402_5%
47
25
+ V DDA _CODEC_R
DVDD_CORE
1/10*Vin
need close to
Codec
GNDA
11/07 Stuff 0 Ohm for AGND and GND
SENSE A
SENSE B
Port
Resistor
Port
Resistor
39.2K
39.2K
20K
20K
10K
10K
2007/08/28
Issued Date
5.11K
Compal Secret Data
5.11K
2006/07/26
Deciphered Date
Title
Codec_IDT9271B7
D

Cu s tom
Da te:
M ontevina Blade UMA LA4101P

Sheet

E
28
of
46
Rev
0.3
GAIN0
GAIN1
6dB
10dB
15.6dB
21.6dB
Av(inv)
SPEAKER
+5VAMP
+5VS
JP60
1
1
RIN-
GAIN1
ROUT+
ROUT-
2 0.022U_0603_25V7K 9
2
0.022U_0402_16V7K
LIN+
2 0.022U_0603_25V7K 5
2
0.022U_0402_16V7K
LIN-
1
2
3
4
11/07Change JP60 PCB

Footprint from
ACES_85204-04001_4P to
ACES_88231-04001_4P
GND1
GND2
E&T_3806-F04N-02R
C ONN@
@ D55
PSOT24C_SOT23-3
R396
100K_0402_5%
8/31EMI request
1
2
3
4
5
6
3
C1375
100P_0402_50V8J
C1376
C1377
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
3
18
SPKR+
14
SPKR-
D56 @
PSOT24C_SOT23-3
2 0.022U_0603_25V7K17
2
0.022U_0402_16V7K
GAIN0
100P_0402_50V8J
1
@ R395
100K_0402_5%
2
RIN+
2
2
2
2
R397
100K_0402_5%
@ R398
100K_0402_5%
2
C289
2 0.022U_0603_25V7K 7
2
0.022U_0402_16V7K
11/17 Change to15.6 dB
C287 1
1
C288
<28> L INE_OUT_R
+5VS
15.6 dB
1
1
C286
0_1206_5%
2
2
0.1U_0402_16V4Z
VDD
PVDD1
PVDD2
U40
C285
100P_0402_50V8J
C284
C1378
16
15
6
10U_0805_10V4Z
C283
R1105 1
R1104 1
R1103 1
R1102 1
SPKRSPKR+
SPKLSPKL+
C282
100P_0402_50V8J
R394
0.1U_0402_16V4Z
Audio/B & CIR
SPKL-
+3VALW
Q16B
DOCK@
5
11/07 Add 10K PU
HP _OUT_R
HP_OUT_L
<28> EXTMIC_DET#
EXTMIC_DET#
HP_DET#
<32,34> CIR_ IN
CIR_ IN
2
G
Q46
D 2N7002_SOT23-3
DOCK@
+5VL
C270
0.01U_0402_25V7K
DOCK@
Q17B
DOCK@
3
Q17A
DOCK@
C295
1
DOCK@
R409 1
2
150U_B_6.3VM_R40M DOCK@
2 47_0402_5%
DOCK_LOUT_R <34>
1
DOCK@
R410 1
2
150U_B_6.3VM_R40M DOCK@
2 47_0402_5%
DOCK_LOUT_L <34>
2N7002DW-7-F_SOT363-6
HP OUT For Docking
<28> MIC_EXT_L
HP_OUT_L
2
150U_B_6.3VM_R40M
2
3
MIC_EXT_L
HP _OUT_R
2
150U_B_6.3VM_R40M
4.7K_0402_5%
C786 1
MIC_EXT_R
C785 1
4.7K_0402_5%
<28> MIC_EXT_R
11/07 Add Capacitor avoid DC lever to Docking audio
R686
R685
2N7002DW-7-F_SOT363-6
1U_0603_10V4Z
2
1
0_0402_5%
<28> VREFOUT_B
<28> HP_OUTL
HP OUT
C296
C787 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_87213-1400G
C ONN@
<28> HP _OUTR
R684
1
2
3
4
5
6
7
8
9
10
11
12
13
14
12/18 Shut down pop noise
R678
330K_0402_5%
DOCK@
TPA6017A2_TSSOP20
JP49
MIC_EXT_R
MIC_EXT_L
Q16A
DOCK@
2
HP_DET#
C293
1U_0805_25V6K
R401
10K_0402_5%
Keep 10 mil width
10
12
21
20
13
11
1
BYPASS
2N7002DW-7-F_SOT363-6
SHUTDOWN
GND1
GND2
GND3
GND4
<32> EC_MUTE#
19
EC_MUTE#
THERMAL PAD
NC
R676
10K_0402_5%
DOCK@
+3VALW
B+
<28,34> JACK_DET#
SPKL+
LOUT-
C291 1
1
C292
<28> LINE_OUT_L
LOUT+
2N7002DW-7-F_SOT363-6
C290
HP OUT For M/B
EXTMIC IN
JACK_DET#
OPP@
R192
2
HP_DET#
0_0402_5%
+ V DDA_CODEC
C1379
1U_0603_10V4Z
1
2
1
2
@ C618
10P_0402_25V8K
@C621
+3VS
Connector for MDC Rev1.5

C ONN@
MDC Standoff
2007/08/28
2006/07/26
Deciphered Date
5
6
GND1
GND2
ACES_88231-04001
C ONN@
Q18B
Title
AM P & Audio Jack
B
Q18A
1
2
3
4
Compal Secret Data
1
10K_0402_5%
<28> INTMIC_DET#
ACES_88018-124G
Issued Date
2
R681
<32> ANA_MIC_DET
2N7002DW-7-F_SOT363-6
4
3
2
@ R478
10_0402_5%
4.7U_0805_10V4Z
HDA_BITCLK_MDC <21>
C620
+3VS
JP51
1
2
3
4
<28> M IC_IN_L
<28> M IC_ IN_R
2N7002DW-7-F_SOT363-6
1
6
13
14
15
16
17
18
+3VS
C619
2
4
6
8
10
12
RES0
RES1
3.3V
GND3
GND4
IAC_BITCLK
GND
GND
GND
GND
GND
GND
HDA _ S Y NC_MDC
2 HDA _ S DIN1_MDC
33_0402_5%
H14
HOLEA
H12
HOLEA
1
R477
GND1
IAC_SDATA_OUT
GND2
IAC_SYNC
IAC_SDATA_IN
IAC_RESET#
0.1U_0402_16V4Z
<21> HDA _ S Y NC_MDC

<21> HDA _ SDIN1
<21> HDA_RST#_MDC
1
3
5
7
9
11
R951
10K_0402_5%
+1.5VS
1000P_0402_50V7K
HDA _ SDOUT_MDC
2
0_0603_5%
2
0_0603_5%
+3VS
1
R475
@ 1
R476
R1079
4.7K_0402_5%
Main@
2
R1078
4.7K_0402_5%
JP8
<21> HDA _ SDOUT_MDC
MDC 1.5 Conn.
INTMIC IN
R1077
0_0402_5%
2
1
+ V DDA _CODEC

Cu s tom
Da te:

Sheet

E
29
of
46
Rev
0.3
Left side USB Connector
Left side ESATA/USB combination Connector
+5VALW
US B _VCCC
US B _VCCC
U4 1
USB_EN#
JP53
W=100mils
8
7
6
5
TPS2061IDGNR_MSOP8
2
1
+
2
C1383
1000P_0402_50V7K
C1381
OUT
OUT
OUT
OC#
C1382
0.1U_0402_16V4Z
GND
IN
IN
EN#
C1380
150U_D_6.3VM
1
2
3
4
4.7U_0805_10V4Z
R1080 1
R1081 1
<22> USB20_N2
<22> USB20_P2
2 10K_0402_5%
1
2
3
4
U SB20_N2_R
USB20_P2_R
C1385 2
C1384 2
ESATA@
ESATA@
+5VALW
1 0.01U_0402_16V7KSATA_RXN5
1 0.01U_0402_16V7KSATA_RXP5
USB
VBUS
DD+
GND
5
6
7
8
9
10
11
SATA_TXP5
SATA_TXN5
<21> SATA_TXP5
<21> SATA_TXN5
<21> SATA_RXN5_C
<21> SATA_RXP5_C
R1083
2 0_0402_5%
2 0_0402_5%
GND
A+
ESATA
AGND
BB+
GND
12
13
14
15
GND
GND
GND
GND
TYCO_1759576-1
C ONN@
D45
4
+5VALW
USB20_P2
VIN
USB20_N2
IO1
D46
IO2 GND
+5VALW
@ PRTR5V0U2X_SOT143-4
SATA_TXN5
VIN
IO1
IO2 GND
SATA_TXP5
Finger printer
BT Connector
Need change to New version
JP57
1
2
3
4
5
6
7
8
GND1
GND2
F P@
2 0_0603_5%
+3VS
20070209 Add for FPR

S
2
0_0603_5%
C756 FP@
0.1U_0402_16V4Z
2
2 0_0402_5%
2 0_0402_5%
FP@
FP@
JP24
U SB20_N7_R
USB20_P7_R
2
R634 1
R635 1
@ Q31
SI2301BDS_SOT23
<22> USB20_N7
<22> USB20_P7
G
USB_EN#
+3VALW
@ R628
@ R405
1
2
0_0402_5%
@ D30
PACDN042_SOT23-3~D
+3VAUX_BT
USB20_P6_R
U SB20_N6_R
R1084
R1085
@ R1086 1
@ R1087 1
1 0_0402_5%
1 0_0402_5%
2
2
1
2
3
4
5
6
GND
GND
USB20_P6 <22>
USB20_N6 <22>
BT_LED <33>
CH_DATA <26>
CH_ CLK <26>
1K_0402_5%
1K_0402_5%
2
2
0612 no install
D4 7
ACES_88231-08001
C ONN@
+5VALW
U SB20_N6_R
+3VS
VIN
IO1
IO2 GND
USB20_P6_R
R235
1
+3VALW
2
+3VAUX_BT
0_0603_5%
Q105
C1386
1U_0603_10V4Z
R1090
100K_0402_5%
C1387
C1388
C1389
0.1U_0402_16V4Z
2
0_0603_5%
11/07 Change PCB Footprint

to ACES_85201-06051_6P
SI2301BDS_SOT23
R236
S
@
1
ACES_85201-06051
C ONN@
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
R627
0.01U_0402_16V7K
USB cable connector for Right side
<22> BT_OFF
R1092
1
4.7U_0805_10V4Z
C1390
1
2
0.1U_0402_16V4Z
2
47K_0402_5%
JP55
+5VALW
<32> USB_EN#
<22> USB20_N0
<22> USB20_P0
<22> USB20_N1
<22> USB20_P1
USB_EN#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
01/03 Change BT power to +3VS
GND1
GND2
ACES_87213-1000G
C ONN@
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title

USB, BT, eSATA
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
30
of
46
SPI ROM
+3VL
U27
20mils
C712
0.1U_0402_16V4Z
8
3
SPI_FSEL#
2
0_0402_5%
S PI_CLK_R
2
0_0402_5%
S P I_FWR#
2
0_0402_5%
<32> FSEL#
<22,32> SPI_CLK
<32> F W R#
VSS
LPC Debug Port
2
1
R553
1
R554
1
R556
VCC
HOLD
Change from +3VL to +3VS. 6/9
SPI_SO 1
R555
F RD#
2
0_0402_5%
Removed +3VS. 6/13

F RD# <32>
W IESON G6179 8P SPI
15P_0402_50V8J
33_0402_5%
@ R232
S P I_FWR# 2
JP18
<21,26,32> LPC_FRAME#
C308
2
11/16 Change TO +3VALW
15P_0402_50V8J
33_0402_5%
C309
2
+3VALW
<20,32> P CI_RST#
<21,26,32>
<21,26,32>
<21,26,32>
<21,26,32>
+3VALW
@ R231
S PI_CLK_R 2
C307
2
15P_0402_50V8J
C711
0.1U_0402_16V4Z
12/27EMI request
L PC_AD0
L PC_AD1
L PC_AD2
L PC_AD3
ON/ OFFBTNLED#
R552
100K_0402_5%
U28
8
7
6
5
<32,33,37> SMB_EC_CK1
<32,33,37> SMB_EC_DA1
33_0402_5%
B+
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH

WIESO_G6179-100000_8P
@ R230
SPI_FSEL# 2
VCC
WP
SCL
SDA
A0
A1
A2
GND
Connect pin3 & 23

together and pin 24
to GND in 6/29.
1
2
3
4
V CC1 P WRGD
SPI_CLK_JP18
SPI_CS#_JP18
SPI_SI_JP18
SPI_SO_JP18
SPI_HOLD#_0
Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved
AT24C16AN-10SI-2.7_SO8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R557
100K_0402_5%
2
ACES_87216-2404_24P
C ONN@
+3VS
+3VS
+3VALW
1
R411 1
R412 1
+3VS
2 SPI_WP#
3.3K_0402_5%
2S PI_HOLD#
3.3K_0402_5%
C304
0.1U_0402_16V4Z
U6
8
@ R413
1K_0402_5%
R414
<22> SPI_SB_CS#
SPI_SB_CS# 1
SPI_CLK
<22> SPI_SI
R561 1
SPI_WP#
S PI_HOLD#
15_0402_5%
SPI_SI
VCC
VSS
4
<32,33> ON/OFFBTN_LED#
W
HOLD
<32> V CC1 _PWRGD
S
C
R415
SPI_SO_L 1
2
2
D
Q
SST25LF080A_SO8-200mil
15_0402_5%
SPI_SO_R
SPI_CLK
2
0_0402_5%
SPI_CLK_JP18
FSEL#
2
0_0402_5%
SPI_CS#_JP18
2
0_0402_5%
SPI_SI_JP18
2
0_0402_5%
SPI_HOLD#_0
2
0_0402_5%
SPI_SO_JP18
2
0_0402_5%
ON/ OFFBTNLED#
2
0_0402_5%
V CC1 P WRGD
1
R558
DE B UG@
1
R559
DE B UG@
F W R#
1
R560
DE B UG@
HOL D#
2
1
3.3K_0402_5%
R562
DE B UG@
F RD#
1
R563
DE B UG@
ON /OFFBTN_LED#
1
R565
DE B UG@
V CC1 _ PWRGD
1
R566
DE B UG@
11/07 Add 0 Ohm for debug port

SPI_SO_R <22>
11/17 Add SB HDCP ROM

01/03 Change HDCP ROM to +3VS
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title

BIOS ROM
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
31
of
46
C301
+3VL_EC
BATT_OVP
C718
+3VL
C719
2
+3VL_EC
R572
1
+5VL
+3VS
1
1
1
1
2
2
2
2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ C722
1
<21> GATEA20
<21> KB_RST#
<22> S IRQ
<21,26,31> LPC_FRAME#
<21,26,31> L PC_AD3
<21,26,31> L PC_AD2
<21,26,31> L PC_AD1
<21,26,31> L PC_AD0
@ R576
2
33_0402_5%
15P_0402_50V8J
<17> CLK_PCI_EC
1
<20,31> P CI_RST#
2
47K_0402_5%
R578
2
C721
1
0.1U_0402_16V4Z
<22> E C_SCI#
<21,28> HDA _ RST#_CODEC
1
+3VL
R403 1
J1
11/09 Delete CLKRUN#
J OPEN
11/09 Add HDA_RST# to EC
1
2
3
4
5
7
8
10
CL K_PCI_EC
PCI_RST#
ECRST#
12
13
37
20
2 0_0402_5% 38
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
I NV_PWM
F AN_PWM
EC_BEEP
A C OFF
63
64
65
66
75
76
BATT_TEMP
BATT_OVP
A DP_I
A D P_ID
TP_BTN#
ANA_MIC_DET
68
70
71
72
DA C_ BRIG
V CTRL
IRE F
AC_SET
PWM Output
MISC
AD
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
INV_PWM <19>
F AN_PWM <6>
EC_BEEP <28>
A COFF <38,39>
0.01U_0402_16V7K
C720
E CA G ND
1
2
BATT_TEMP <37>
BATT_OVP <37>
A DP_I <38>
A DP _ID <37>
TP_BTN# <33>
ANA_MIC_DET <29>
DA C_ BRIG <19>
V CTRL <38>
IRE F <38>
AC_SET <38>
R583
10K_0402_5%
R721
10K_0402_5%
L I D_SW#
01/03 Change to +3VS
11/07 Add SYSON and SUSP# PD
@ R585
10K_0402_5%
2
0_0402_5%
77
78
79
80
EC_PME#
<22>
<22>
<22>
<33>
EC_PME#
SLP_S3#
SLP_S5#
EC_SMI#
L ID_SW#
C723
15P_0402_50V8J
1
2
Y5
EC DEBUG port
NC
+5VL
GPO
OUT
NC
IN
32.768KHZ_12.5P_1TJS125DJ2A073
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
GPI
V18R
@
R595
20M_0402_5%
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
XCLK1
XCLK0
122
123
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
C RY 2
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
GND
GND
GND
GND
GND
11/07 Connect
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
P S2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
S PI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
S M Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
11
24
35
94
113
<34> DOCK_SLP_BTN#
R191
<31,33,37>
10K_0402_5%
<31,33,37>
OPP@
<6>
<6>
SLP_S3#
SLP_S5#
2
EC_SMI#
0_0402_5%
L I D_SW#
ESB_CLK_R
R592 1
ON/ OFFBTN
ESB_DAT_R
2
EC_PME#
0_0402_5%
1 @ R591 2 0_0603_5%
DOCK_SLP_BTN# to ON/OFFBTN
<9> TSATN#
CO NA#
<34> CONA#
W W A N_ POWER_OFF
<26> W W A N_ POWER_OFF
UTX
R5931
L A N _POWER_OFF_R
2
+3VL
ON/ OFFBTN
4.7K_0402_5%
<33> ON/OFFBTN
DI M_LED
<36> DIM_LED
NU M_LED#
<33> NUM_LED#
R190 1
OPP@
<33> WL_BLUE_BTN
11/15 Delete PCI_PME#

@ R589 1
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
+3VALW
+3VL
<20> PCI_PME#
TP_BTN#
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
@ C792 1
2 100P_0402_50V8J
KSO10
@ C793 1
2 100P_0402_50V8J
KSO11
@ C794 1
2 100P_0402_50V8J
KSO14
@ C795 1
2 100P_0402_50V8J
KSO13
@ C796 1
2 100P_0402_50V8J
KSO12
@ C797 1
2 100P_0402_50V8J
KSO3
@ C798 1
2 100P_0402_50V8J
KSO6
@ C799 1
2 100P_0402_50V8J
KSO8
@ C800 1
2 100P_0402_50V8J
KSO7
@ C801 1
2 100P_0402_50V8J
KSO4
@ C802 1
2 100P_0402_50V8J
KSO2
@ C803 1
2 100P_0402_50V8J
KSI0
@ C804 1
2 100P_0402_50V8J
KSO1
@ C805 1
2 100P_0402_50V8J
KSO5
@ C806 1
2 100P_0402_50V8J
KSI3
@ C807 1
2 100P_0402_50V8J
KSI2
@ C808 1
2 100P_0402_50V8J
KSO0
@ C809 1
2 100P_0402_50V8J
KSI5
@ C810 1
2 100P_0402_50V8J
KSI4
@ C811 1
2 100P_0402_50V8J
KSO9
@ C812 1
2 100P_0402_50V8J
KSI6
@ C813 1
2 100P_0402_50V8J
KSI7
@ C814 1
2 100P_0402_50V8J
KSI1
@ C815 1
2 100P_0402_50V8J
C RY 1
1
+ E C_AVCC
@ R582
D OCK_VOL_UP#
DOCK _VOL_DWN#
119
120
126
128
R227
R228
R229
73
74
89
90
91
92
93
95
121
127
L30
0_0603_5%
1
1
1
11/09 don't stuff when use C0
DOCK_VOL_UP# <34>
DOCK _VOL_DWN# <34>
F RD# <31>
F W R# <31>
SPI_CLK <22,31>
FSEL# <31>
33_0402_5%
33_0402_5%
33_0402_5%
2 10K_0402_5%
+5VL
C IR_ IN <29,34>
11/09 PU
V CC1 _ PWRGD <31>
F S TCHG <38>
STD_ADP <38>
CAPS_LED# <33>
BAT_LED# <33>
ON/OFFBTN_LED# <31,33>
S Y S ON <26,33,36,41>
V R_ ON <43>
SLP_S4#
ENBKL
E A P D_CODEC
T HERM_SCI#
SUSP#
PWRBTN_OUT#
NM I_DBG#
F RD#
F W R#
SPI_CLK
FSEL#
2
2
2
CIR_ IN
V CC1 _ PWRGD
F S TCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON /OFFBTN_LED#
S Y SON
V R _ON
A C_ IN
14" INT_KBD
CONN.( TYPE "D"
KB)
JP19
to South bridge
A D P_ID
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
+3VL
2
D16
1
R714
10K_0402_5%
D1 4
1
+3VL
2 P C I_SERR#
P CI_SERR# <20>
R715
10K_0402_5%
11/07 Correct direction pretect leakage
L A N _POWER_OFF_R
1
C726
0_0402_5%
2
0.1U_0402_16V4Z
L31
1
R443
A C_ IN
2
0_0603_5%
D13
1
A CIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ACES_85201-2405
C ONN@
A CIN <38>
1
+3VL
2
100P_0402_50V8J
Vendor
Recommend
R1099
4.7K_0402_5%
R1100
4.7K_0402_5%
<33> ESB_CLK
<33> ESB_DAT
C791
+3VL
<25> L A N_POWER_OFF
+3VS
R407
10K_0402_5%
2
1
DOCK _VOL_DWN# 2
1
R408
10K_0402_5%
NM I_DBG#
D OCK_VOL_UP#
1
10K_0402_5%
+3VL
C724
4.7U_0603_6.3V6K
+5VL move to M/B
EC_RSMRST# <22>
E C_LID_OUT# <22>
E C_ ON <39>
WL_BLUE_LED# <33>
P M_PWROK <9,22>
B KOFF# <19>
M _PWROK <9,22>
TP_LED# <33>
SLP_S4# <22> 11/07 Add SLP_S4#

ENBKL <11>
E A P D_CODEC <28>
T HERM_SCI# <22>
SUSP# <26,28,36,38,40,41>
PWRBTN_OUT# <22>
124
2 10K_0402_5%
2 10K_0402_5%
2 4.7K_0402_5%
R586
EC_RSMRST#
100
101 R588 1
2
E
C
_ON
0_0402_5%
102
WL_BLUE_LED#
103
PM_PWROK
104
BKOFF#
105
M _PWROK
106
TP_LED#
107
108
110
112
114
115
116
117
118
R579 1
R580 1
TP_CLK <33>
TP_DATA <33>
R720
For C
Revision
+3VL_EC
C725
15P_0402_50V8J
97
98
99
109
EC_MUTE# <29>
USB_EN# <30>
I2 C_INT <33>
MUTE_LED <34>
1
2 L A N _POWER_OFF_R
1 0_0402_5%
0_0805_5%
EC_MUTE#
USB_EN#
I2 C_INT
MUTE_LED
TP_CLK
TP_DATA
E CA G ND
83
84
85
86
87
88
KB926QFB0_LQFP128_14X14
JP20
R442 1
R233 2
+5V_TP
+3VS
R713
100K_0402_5%
R581
8.2K_0402_5%
1
1
U RX
2
2
UTX
3
3
4
4
ACES_85205-0400
C ONN@
21
23
26
27
+3VALW
PCI_RST#
SUSP#
S Y SON
GATEA20
KB_RST#
S I RQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
KSO15
11/17 Change to +3VALW
R213
8.2K_0402_5%
For EMI
VCC
VCC
VCC
VCC
VCC
VCC
R573
R577
R574
R575
11/09 EC recommend
2
0_0805_5%
U30
SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2
+ EC_AVCC
67
C717
2
2
1000P_0402_50V7K
AVCC
C716
100P_0402_50V8J
AGND
C715
2
2
0.1U_0402_16V4Z
1000P_0402_50V7K
69
0.1U_0402_16V4Z
1
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
R731
R732
1
1
Compal Secret Data
2 0_0402_5%
2 0_0402_5%
ESB_CLK_R
ESB_DAT_R
Issued Date
2007/08/28
Deciphered Date
2006/07/26
Title

EC KB926/KB Conn.
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
32
of
46
T/P Board (Inculde T/P_ON/OFF)
+5V_TP
R1095
TP ON/OFF
Cap lock
S W1
TJG-533-V-T/R_6P
3
1
R1097
D53
White
White
R1098
470_0402_5%
2
Battery
Charge LED
+5VS
R728
470_0402_5%
Amber
QSMF-C16E_AMBER-WHITE
AMBER
11/07 Change part number
HDD LED
+3VS
R609
200_0402_5%
AMBER
R718
10K_0402_5%
2
R610
820_0402_5%
+5VS_LED
GS@
<22> HDDHALT_LED#
White
White
+5VALW_LED
Amber
<21> SATA_LED#
2
470_0402_5%
HT-F196BP5_WHITE
TP_BTN# <32>
5
6
White
D52
1
<32> BAT_LED#
+5VS_LED
470_0402_5%
TouchPAD ON/OFF LED

R611 @
10K_0402_5%
+5VS_LED
D1 2
QSMF-C16E_AMBER-WHITE
HT-F196BP5_WHITE
White
D50
1
<32> CAPS_LED#
System LED
TP_LED#
TP_LED# <32>
<31,32,37> SMB_EC_CK1
<32> ESB_CLK
<32> ESB_DAT
<32> I2 C_INT
1
1
1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
<32> NUM_LED#
<31,32,37> SMB_EC_DA1
R730
3
1
2
3
4
5
6
7
8
9
10
11
12
2 0_0402_5%
R1101
10K_0402_5% 1
Cypress
1
33_0402_5%
C310
2
ESB_CLK
@ R234
2
15P_0402_50V8J
4.7U_0603_6.3V6K
1
2
3
4
5
6
7
8
9
10
GND
GND
@ R612
10K_0402_5%
Q23
1
2
3
4
G1
G2
1
2
3
4
TP_CLK
TP_DATA
TP_CLK <32>
TP_DATA <32>
ACES_85201-04051
C ONN@
D
@ Q24
2N7002_SOT23-3
ACES_85201-1005N
C ONN@
@ C729
0.1U_0402_16V4Z
JP23
S Y SON 2
G
EMI request
5
6
<26,32,36,41> S Y S ON
+5V_TP
JP59
SMB_EC_DA1
2 0_0603_5%
R729
R56
R149
+5V_TP
R691 1
SMB_EC_CK1
ESB_CLK Main@
ESB_DAT Main@
2 0_0402_5%
2 0_0402_5%
D28
PSOT24C_SOT23-3
@
1
1
+5VALW
R53
0_0805_5%
OPP@
R151
R169
TP_DATA
TP_CLK
T/P Board Conn
ENE
OPP@
OPP@
On (TP_LED#=L)-> White
Off (TP_LED#=H)-> Amber
+5VALW_LED
R51
0_0805_5%
Main@
WL_BLUE_LED#
+5VS_LED +3VL
Capacitor Sensor Conn
<32> WL_BLUE_BTN
System
Power LED
+5VALW_LED
R980
470_0402_5%
HT-F196BP5_WHITE
ON /OFFBTN_LED#
2
G
Q4
2N7002_SOT23-3
D17 White
@ C730
100P_0402_50V8J
@ C731
100P_0402_50V8J
C313
01/03 EMI request
ON/OFF Button Connector
Mini card LED
Keyboard backlight Conn
+3VS
1
+3VS
JP9
3
47K
<26> W W _LED#
<30> BT_LED
+3VS
01/03 Keyboard backlight reserve a 0805 size resistor
R716
100K_0402_5%
Q20
DTA114YKAT146_SOT23-3
2MiniC@
WL_BLUE_LED# <32>
10K
Q11B
Lid Switch Connector
W L_LED
1
R717
100K_0402_5%
+3VALW
2
Q11A
ACES_85201-04051
C ONN@
ACES_85201-04051
C ONN@
<26> WL_LED#
5
6
Q14
DTA114YKAT146_SOT23-3
10K
G1
G2
G1
G2
1
2
3
4
0_0805_5%
5
6
1
2
3
4
1
2
3
4
<32> ON/OFFBTN
<31,32> ON/OFFBTN_LED#
+5VS_LED
2N7002DW-7-F_SOT363-6
47K
R205
JP10
1
ON/ OFFBTN
2
ON /OFFBTN_LED# 3
4
2N7002DW-7-F_SOT363-6
R193
10K_0402_5%
+5VALW_LED
<32> L ID_SW#
1
2
3
4
JP11
1
2
3
4
G1
G2
11/20 Reserve WW_LED function
5
6
ACES_85201-04051
CONN@
2007/08/28
Issued Date
01/03 Change Lid switch connector type

A
Compal Secret Data
2006/07/26
Deciphered Date
C
Title

KBD, ON/OFF, SW, CIR
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
E
33
of
46
Atlas/ Saturn Dock

J DOCK1
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<22>
<22>
DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on
+3VALW
R975 1
DOCK@
2 1K_0402_5%
DOCK@
1K_0402_5%
2
1
2
G
Q58
2N7002_SOT23-3
DOCK@
38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12
6
8
2
4
12/18 Correct GND
D57
2
1
DOCK _ P WRON
+5VS
R974 1
R ED
GR EEN
BLUE
D_ DD CDATA
D_ DDC CLK
D_ HS Y NC
D_ V S YNC
USB20_N3
USB20_P3
R ED
GREEN
BLUE
D_ DDCDATA
D_ DDCCLK
D_ HS Y NC
D_ V S YNC
USB20_N3
USB20_P3
DAN202U_SC70
DOCK@
<25>
<25>
<25>
<25>
RJ 45_MIDI1RJ 45_MIDI1+
+V_BATTERY
R976
10K_0402_5%
DOCK@
CRT_Red
CRT_Green
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USBUSB+
Digital gnd
MDI3MDI3+
MD2IMDI2+
MDI1MDI1+
MDI0MDI0+
Battery out
Battery out
Digital gnd
TV Luma
TV chroma
TV composite
TV ground
CIR input
PWR_ON
Mute_LED
Sleep Botton
Jack Detect
VOL_up
VOL_down
SPDIF
Audio Output gnd
Right headphone
Left headphone
Mic_Right
Mic_Left
Mic gnd
Dock_present
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
12/18 Correct GND

11/07 Delete TVout function from Docking
V G A_GND
CIR_ IN
DOCK _ P WRON
MUTE_LED
DOCK_SLP_BTN#
JACK_DET#
R_VOL_UP#
R_ V OL_DWN#
S PDIFO_L
A UDIO_ OGND
DOC K_LOUT_R
D OCK_LOUT_L
DOCK _ MIC_R_C
DOC K_MIC_L_C
A UDIO_ I GND
D OCK_PRESENT
CIR_ IN <29,32>
MUTE_LED <32>
DOCK_SLP_BTN# <32>
JACK_DET# <28,29>
DOCK_VOL_UP# <32>
DOCK _VOL_DWN# <32>
R617 1
R618 1
2 200_0402_5%
2 200_0402_5%
DOCK@
GNDA DOCK@
DOCK_LOUT_R <29>
DOCK_LOUT_L <29>
GNDA
R620 1
2 2K_0402_5%
<36,42> S Y SON#
PJP3
B+
GND
GND
GND
GND
45
46
P AD-OPEN 2x2m
GND
GND
+ DOCKVIN
41
42
43
44
+ DOCKVIN
C ONN@ FOX_QL1122L-H212AR-7F
C305 1
@
2
1000P_0402_50V7K
C306 1
@
2
1000P_0402_50V7K
C734
1000P_0402_50V7K
2 DOCK@
11/12 Change to +3VL
Dock PRESENT
GNDA
+3VL
2
11/17 Reserve
DOC K_MIC_L_C
1
2
L37 DOCK@
FBM-11-160808-601-T_0603
C754
220P_0402_50V7K
DOCK@
C755
220P_0402_50V7K
2 DOCK@
1
2
B
C64
DOCK@
1
2
D
@ Q55
2N7002_SOT23-3
Q30
MMBT3904_NL_SOT23-3
DOCK@
2
G
S PDIFO_L
1
C819
220P_0402_25V8J
2
DOCK@
Compal Secret Data

2007/08/28
Deciphered Date
S PDIF_OUT <28>
R723
DOCK@
1
2
0_0603_5%
1U_0603_10V6K
DOCK@
R977
DOCK@
1
2
220_0402_5%
0.1U_0402_16V7K
2006/03/10
Title
GNDA
R722 @
33_0402_5%
Q29
2N7002_SOT23-3
DOCK@
Issued Date
C741
DOCK@
+1.5VS_HDA
2
G
C757
R633
47K_0402_5%
DOCK@
GNDA
2
2
1
DOC K_MIC_L_C
C740
DOCK@ 2
C745
DOCK@
11/17 Recommend
SENSE_B# <28>
R625
10K_0402_5%
DOCK@
R626
10K_0402_5%
DOCK@
Q32
MMBT3904_NL_SOT23-3
DOCK@
C
2
B
E
2
DOC K_LOUT_R
D OCK_LOUT_L
1
GNDA GNDA
+3VS
R632
1
2
10K_0402_5%
DOCK@
1 1
<28> DOCK_MIC_L
<28> DOCK _ MIC_R
C744
DOCK@ 2
0.01U_0402_16V7K
L36 DOCK@
FBM-11-160808-601-T_0603
DOCK _ MIC_R_C
1
2
R623
2K_0402_5%
DOCK@
Q27
2N7002_SOT23-3
DOCK@
22_0402_5%
DOCK@
2
G
1
R979
D OCK_PRESENT
1000P_0402_50V7K
R_VOL_UP#
R_ V OL_DWN#
Need 600 Ohm 500 mA
0.01U_0402_16V7K
MIC_Dock
<32> CONA#
1000P_0402_50V7K
R621
10K_0402_5%
R978
110_0402_5%
DOCK@

DOCK CONN.

Da te:
Rev
0.3
UMA LA 4101P
Sheet
34
of
46
+3VS_LS
R650
2.2K_0402_5%
+3VS_LS
3
4
R649
2.2K_0402_5%
5
R653
2
1 1K_0402_5%
TMDS_B_HPD
7
8
<9> HDMIDAT_NB
38
39
40
37
GND
IN_D1-
IN_D1+
42
43
44
45
46
41
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
GND
VCC3V
FUNCTION4
FUNCTION1
FUNCTION3
FUCNTION2
VCC3V
DDC_EN
ANALOG1(REXT)
GND
HPD_SOURCE
HPD_SINK
SDA_SOURCE
SDA_SINK
SCL_SOURCE
SCL_SINK
2 0_0603_5%
+3VS_LS
36
35
11/07 Enable DDC_EN pin
34
33
R651
1 0_0402_5%
@ R652
1 0_0402_5%
+3VS_LS
32
+3VS_LS
31
30
H DMI_DETECT
29
HD MIDAT
2
G
26
+3VS_LS
@ R654
1 0_0402_5%
R655
1 0_0402_5%
+3VS_LS
GND
25
24
OUT_D1-
23
OUT_D1+
22
21
VCC3V
OUT_D2-
20
OUT_D2+
19
GND
18
OUT_D3-
17
OUT_D3+
VCC3V
27
CH7318A-BF-TR_QFN48_7X7
TMDS_B_HPD# <11>
@C769
HDM ICLK+
R744
7.5K_0402_1%
S
2N7002_SOT23-3
HDM ICLK-
@ R656
2
68_0402_5%
0.5P_0402_50V8B
+3VS_LS
@ R657
2
68_0402_5%
+3VS_LS
@C770
HDMI_TX_0+
0.5P_0402_50V8B
HDMI_TX_1-
R743
20K_0402_5%
OE*
HDM ICLK
28
HDMI_TX_0-
Q28
TMDS_B_HPD#
16
13
R742
20K_0402_5%
VCC3V
15
GND
OUT_D4-
VCC3V
12
GND
OUT_D4+
11
+3VS_LS
+3VS_LS
ANALOG2
14
10
TMDS_B_HPD
VCC3V
GND
GND
R648 1
+3VS
9
<9> HDM ICLK_NB
IN_D4-
IN_D4+
Follow Intel
Feedback putting
2.2K ohm
47
TMDS_B_DATA0 <11>
TMDS_B_DATA0# <11>
48
TMDS_B_DATA1 <11>
TMDS_B_DATA1# <11>
<11> TMDS_B_CLK#
<11> TMDS_B_CLK
U43
+3VS_LS
<11> TMDS_B_DATA2#
<11> TMDS_B_DATA2
+3VS_LS
VCC3V
@C771
HDMI_TX_2+
HDMI_TX_2-
Follow Vendor Feedback
@ R658
1
@ R659
1
2
68_0402_5%
2
68_0402_5%
0.5P_0402_50V8B
@C772
HDMI_TX_1+
0.5P_0402_50V8B
11/07 correct TMDS_B_HPD# connection to North bridge
R206 1
R211 1
1
R214
L41
1
HDMI_TX_1+
HDMI_TX_2+
1
4
1
R222
HDMI_TX0-
WCM-2012-900T_0805
HDMI_TX0+
3
HDMI_TX1-
H DMI_DETECT
WCM-2012-900T_0805
HDMI_TX1+
3
D32
SKS10-04AT_TSMA
2 0_0402_5%
2
0_0402_5%
R665
1
2
1K_0402_1%
L40
1
HDM I_CLKHD MI_CLK+

HDMI_TX0HDMI_TX0+
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
12
10
9
7
6
4
3
1
C774
330P_0402_50V7K 2
0.1U_0402_16V4Z
C773
+5V
SDA
SCL
HP_DET
CKCK+
D0D0+
D1D1+
D2D2+
CEC
Reserved
GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND
13
14
2
5
8
11
20
21
22
23
17
HDMI_TX2SUYIN_100042MR019S153ZL
C ONN@
WCM-2012-900T_0805
HDMI_TX2+
3
2
0_0402_5%
01/03 Reserver 0 ohm co lay with common choke
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
5
18
16
15
19
FBML10160808121LMT_0603
R666
10K_0402_1%
HD MIDAT
HDM ICLK
@
2
J HDMI1
L42
1
2 0_0402_5%
2
0_0402_5%
R220 1
1
R221
HDMI_TX_2-
1
2
+5VS_HDMI
R217 1
1
R219
HDMI_TX_1-
11/07 Follow recommend change to 3.9K
R50
3.9K_0402_1%
RB411D T146 _SOT23-3

D31
Vendor suggests 4K PU
2 0_0402_5%
2
0_0402_5%
HDMI_TX_0+
WCM-2012-900T_0805
HD MI_CLK+
3
R49
3.9K_0402_1%
2
1
HDMI_TX_0-
L39
+5VS
HDM I_CLK-
HDM ICLK+
B
HDMI Connector
L38
HDM ICLK-
2 0_0402_5%
Title

HDMI LS & Conn.

Da te:
Rev
0.3
UMA LA 4101P
Sheet

1
35
of
46
+5VALW to +5VS Transfer
+3VALW to +3VS Transfer
DIM LED
+5VALW
+5VALW
+5VS
+3VALW
+5VALW_LED
Q33
+3VS
@ C65
0.01U_0402_16V7K
01/03 Sparate+5VS
and +3VS power
timing
Q34B
0.1U_0402_16V4Z
D IM_LED#
DI M_LED
<32> DIM_LED
Q35
2N7002_SOT23-3
2
G
C765
0.01U_0402_16V7K
+5VS
2N7002DW-7-F_SOT363-6
+5VS_LED
Q15
S
1
+1.8V to +1.8VS Transfer
D IM_LED#
+1.8VS
U34 @
+3VL
R640
Q13A
<26,32,33,41> S Y S ON
2
1
11/07 BOM Delete +1.8VS for Cardreader internal LDO
S Y SON
SUSP
SUSP <42>
Q13B
SUSP#
SUSP# <26,28,32,38,40,41>
1
+5VS
+ VCCP
+1.5VS
+3VS
+1.8V
+0.9V
H2
HOLEA
H3
HOLEA
H1
HOLEA
Discharge circuit
H4
HOLEA
H5
HOLEA
H6
HOLEA
H7
HOLEA
H8
HOLEA
H9
HOLEA
H1 0
HOLEA
R U NON
100K_0402_5%
S Y SON#
100K_0402_5%
<34,42> S Y SON#
R639
@ C768
+3VL
2N7002DW-7-F_SOT363-6
4
3
2
@ C767
AO4466_SO8
1
2
3
4
2N7002DW-7-F_SOT363-6
S
S
S
G
10U_0805_10V4Z
D
D
D
D
0.1U_0402_16V4Z
8
7
6
5
10U_0805_10V4Z
@ C766
C294
0.1U_0402_16V4Z
+1.8V
C758
0.1U_0402_16V4Z
2
4
2
1
2N7002DW-7-F_SOT363-6
R637
10K_0402_5%
C764
1
R638
SUSP
1
1
C763
470_0402_5%
2
Q34A
2
RUNO N_3VS
@ R224
470_0402_5%
SUSP
AO4466_SO8
R U NON
10U_0805_10V4Z
1
2
3
4
S
S
S
G
D
D
D
D
330K_0402_5%
2
8
7
6
5
10U_0805_10V4Z
C759
1
2
C762
10U_0805_10V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
330K_0402_5%
C761
AO4466_SO8
R636
R223
1
2
3
4
S
S
S
G
C760
U33
D
D
D
D
U32
8
7
6
5
B+
B+
+1.8VS
H1 9
H20
HOL EC HOLEC
H18
HOLEA
H17
HOLEA
470_0402_5%
H16
HOLEA
SUSP
@ R647
470_0402_5%
1
2
3
Q12B
SUSP
2
6
Q12A
S Y SON# 2
2N7002DW-7-F_SOT363-6
H15
HOLEA
R646
2N7002DW-7-F_SOT363-6
1
2
Q9B
SUSP
470_0402_5%
2
6
Q9A
SUSP
R643
470_0402_5%
2
3
Q6B
SUSP
R645
470_0402_5%
2N7002DW-7-F_SOT363-6
2
6
1
2N7002DW-7-F_SOT363-6
Q6A
SUSP
R644
470_0402_5%
2N7002DW-7-F_SOT363-6
R642
470_0402_5%
2N7002DW-7-F_SOT363-6
R641
FM1
@ Q44
FM2
1
FM3
1
FM4
1
2
G
2N7002_SOT23-3
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title

DC/DC Interface
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
36
of
46
+3VALW
3
PQ3
T P0610K-T1-E3_SOT23-3
BATT
AC_LED <38>
499K_0402_1% 340K_0402_1%
P R4 1
P R1 1
2
2
8
2
105K_0402_1%
P R6 1
2
AD P IN
PL2
SMB3025500YA_2P
P R5
10K_0402_5%
3
PL1
SMB3025500YA_2P
0
-
BATT_OVP <32>
P R3
10K_0402_5%
5
4
3
2
1
1
2
0.01U_0402_25V7K
P C6
1
2
P C5
1000P_0402_50V7K
1
2
P C4
100P_0402_50V8J
P C3
1000P_0402_50V7K
1
2
@PJSOT 24C_SOT23-3
P C2
100P_0402_50V8J
P D1
+DOCKVIN
2
1
PJP1
VIN
RLZ3.6B_LL34
AD P _SIGNAL
5
4
3
2
1
@1000P_0402_50V7K
PD4
P R2
10K_0402_5%
ACES_88334-057N
PR8
100_0402_5%
2 1
ADP_ID <32>
PC12
+5VALW
0.01U_0402_25V7K
P C1
P U1A
LM358ADT_SO8
VMB
PL3
HCB2012KF-121T50_0805
PJP2
PL4
HCB2012KF-121T50_0805
P D2
@SM05_SOT23
PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C
EC_SMD
EC_SMC
BATT
1
2
PC8
1000P_0402_50V7K
P C9
0.01U_0402_50V4Z
P R7
47K_0402_1%
+5VS
CPU
SUYIN_200275MR008GXOLZR
2
3
1
1
8
7
6
5
4
3
2
1
GND
GND
8
7
6
5
4
3
2
1
9
10
P R14
100_0402_5%
P R13
P H1
10K_T H11-3H103FT_0603_1%
P R15
150K_0402_1%
0
-
PR11
150K_0402_1%
PR12
2.55K_0402_1%
P C10
0.22U_0603_10V7K
+3VL
PQ1
SSM3K7002FU_SC70-3
2
G
PU1B
LM358ADT_SO8
BAT _ID <38>
+5VALW
SMB_EC_CK1 <31,32,33>
PC11
1000P_0402_50V7K
SMB_EC_CK1
PR10
15K_0402_1%
SMB_EC_DA1 <31,32,33>
SMB_EC_DA1
PR16
6.49K_0402_1%
ENTRIP1 <39>
100_0402_5%
PD3
@SM24.TC_SOT23-3
ENTRIP2 <39>
PR17
1K_0402_5%
PQ2
SSM3K7002FU_SC70-3
2
G
BATT_TEMP <32>
Issued Date
Compal Secret Data

2007/05/29
Deciphered Date
2008/05/29
A
Title

DC Connector/CPU_OTP
Size
D o cument Number
R ev
0.3

D ate:

D
Sheet
37
of
46
P4
B+
BATT
V IN
P2
1
2
1
PR1 39
1 0 0 K_0402_5%
P A C IN
+3VLP
<37> AC_LED
CHG _ B+
5
6
7
8
PC130
2 7 0 P_0402_50V7K
S PQ114
SSM3 K7 0 0 2FU_SC70-3
ACO F F <32,39>
2
G
PC129
4 7 0 P_0402_50V7K
V IN
PR1 05
1 0 K_0402_5%
PC134
PC110
1 U_ 0 8 05_25V6K
29
1 0 0 0P_0402_50V7K
PC1 05
4 .7 U_0805_25V6-K
PC1 04
4 .7 U_0805_25V6-K
1
2
ACN
CHGEN
3
ACP
5
ACDET
7
LPREF
PR1 08
10_1206_5%
1
TP
PR103
4 7 K_0402_5%
ACO F F#
C H G EN#
ACSET
PC1 03
4 .7 U_0805_25V6-K
1
PC1 09
@0 .1 U_ 0 603_25V7K
PR1 40
1 0 0 K_0402_5%
PR110
0_0402_5%
<2 6 ,2 8,32,36,40,41> S USP#
PU1 0 1
BQ 2 4 7 4 0 RHDR_ QFN28_5X5
26
D H_ CHG
25
L X_ CHG
24
R E GN 2
23
D L _ CHG
5
6
7
8
1
2
1
2
21
20
19
18
BQ 2 4 7 4 0VREF
4 7 K_0402_5%
PR119
BAT _ ID <37>
PQ111
SSM3 K7 0 0 2 FU_SC70-3
IREF <32>
PR121
200K_0402_1%
PC1 22
@0 .1 U_0603_25V7K
PR1 20
133K_0402_1%
PR122
6 8 1 K_0402_1%
BATT
17
PC118
0 .1 U_ 0 402_10V7K
PR117
100K_0402_5%
PR123
1M_0402_5%
AO 4 466_SO8
PC131
@1 0 0 0P_0402_50V7K
PC135
4 7 0 P_ 0603_50V8J
1 U_ 0 6 03_10V6K
PC123
0 .1 U_ 0 402_10V7K
DPMDET
CELLS
SRP
SRN
BAT
SRSET
IADAPT
1
2
PC1 20
0 .2 2 U_0603_10V7K
2
PC1 21
1 0 0 P_0402_50V8J
16
15
PR118
10K_0402_5%
<32> ADP_I
PQ110
PC119
IADAPT
PR1 16
39K_0402_5%
22
PGND
3
2
1
ISYNSET
LODRV
14
Charge Detector
PR1 41
4 .7 _1206_5%
2 2
EXTPWR
PR115
100K_0402_1%
PC117
1 U_ 0 6 03_10V6K
RL S4148_LL34-2
BATT
PC116
4 .7 U_ 0805_25V6-K
REGN
PR112
0 .0 15_1206_1%
PC115
4 .7 U_ 0805_25V6-K
VADJ
PL102
1 0 U_ L F 9 1 9 AS-100M-P3_4.5A_20%
PH
<32> VCT RL
12
13
1 SS3 5 5_SOD323-2
V A DJ
PQ106
DT C1 1 5 EUA_SC70-3
0 .1 U_ 0402_10V7K
HIDRV
VDAC
PR114
@0_0402_5%
PD1 02
PR113
1 4 3 K_0402_1%
VREF
3
2
1
10
27
PQ108
AO 4 466_SO8
+3VL
11
SSM3 K7 0 0 2 FU_SC70-3
BTST
PD1 01
BST _ CHG
AGND
BQ 2 4 7 40VREF
1 U_ 0 6 03_6.3V6M
PQ109
28
ACO F F#
PVCC
PC1 12
IADSLP
PC111
P A C IN
PC114
4 .7 U_ 0805_25V6-K
PC128
@1 8 0 P_ 0402_50V8J
PC113
4 .7 U_ 0805_25V6-K
PR1 09
1 5 0 K_0402_5%
PR1 11
3K_0402_1%
8
7
6
5
CHG _ B+
1
2
PC102
1 U_ 0 6 03_6.3V6M
ACSET
1
1
1
2
PC1 08
0 .1 U_0603_25V7K
PQ105
DT C1 1 5 EUA_SC70-3
1
2
3
PL101
HCB2 0 1 2KF-121T50_0805
PC124
0 .1 U_ 0603_25V7K
PC1 07
@0 .0 1 U_0402_16V7K
PC133
4 7 0 P_0402_50V7K
ACDET
PR104
0_0402_5%
PR1 06
2 0 0 K_0402_5%
PC1 06
0 .2 2 U_0603_16V7K
PQ104
DT A1 4 4 EUA_SC70-3
PQ107
SSM3 K7 0 0 2FU_SC70-3
<32> AC_ SET
PR102
0 .0 12_2512_1%
8
7
6
5
PR107
47K_0402_1%
1
2
3
PR101
4 7 K_0402_5%
PQ103
AM4 8 3 5EP-T1-PF_SO8
1
2
3
PC101
4 7 P_ 0402_50V8J
8
7
6
5
LPMD
PQ101
AM4 8 35EP-T1-PF_SO8
PC1 32
@1 0 0 0P_0402_50V7K
PQ102
AM4 8 3 5EP-T1-PF_SO8
P2
+3VL
PR1 24
1 K_ 0402_5%
V IN
V IN
P A C IN
L M3 93DG_SO8
O
4
PR133
1 0 K_0603_0.1%
PU1 0 2B
8
P
PR134
10K_0402_5%
PD103
RL Z4 .3 B_LL34
2
1
S
F ST CHG#
P2
PQ113
SSM3 K7 0 0 2 FU_SC70-3
STD_ADP <32>
PR1 36
4 9 .9K_0402_1%
<32> F ST CHG
1 .2 4 VREF
PQ112
SSM3 K7 0 0 2 FU_SC70-3
ACIN <32>
PR127
1 0 K_0402_1%
PR1 32
100K_0402_5%
1
O
PU1 0 2A
L M3 93DG_SO8
PC1 26
0 .0 4 7 U_0402_16V7K
1
1
C H G EN#
PR135
1 0 K_ 0603_0.1%
PR130
2 .1 5K_0402_1%
1
2
PR1 28
10K_0402_5%
1
2
+3VL
PC125
0 .1 U_ 0603_25V7K
PR1 26
100K_0402_1%
1
PR131
1 3 3 K_0402_1%
PR129
1 0 K_0402_1%
PR1 25
47_1206_5%
V IN
+3VL
S
PU1 0 4
ACDET
ANODE
NC
1 .2 4 VREF
2
4
L MV4 3 1ACM5X_SOT23-5
Compal Secret Data
Issued Date
2007/05/29
Deciphered Date
2008/05/29
A
CATHODE
NC
2 2 P_ 0 402_50V8J
1 0 0 K_0402_1%
PR138
PC127
PR137
20K_0402_1%
REF
4
1
Title

Charger
Size
Do cu me n t Number
Rev
0.3
Mo ntevina Blade UMA LA4101P

Da te:
Sa tu r d a y, Ja n u a ry 05, 2008
D
Sheet
38
of
46
B++
B+
PL301
HCB2012KF-121T50_0805
PC302
0.22U_0603_10V7K
2VREF_51125
PR301
13.7K_0402_1%
PR302
30.9K_0402_1%
PR303
20K_0402_1%
PR304
20K_0402_1%
B++
5
6
7
8
1
2
10U_1206_25V6M
PC305
PC317
@0.1U_0402_25V4K
1
2
19
LG_5V
5
6
7
8
+5VALWP
1
+
1
2
2
3
2
1
T PS51125RGER_QFN24_4X4
PC311
10U_0805_10V6K
3
2
1
UG1_5V
PL303
10U_LF919AS-100M-P3_4.5A_20%
PC310
150U_D_6.3VM
LX_5V
PC304
2200P_0402_50V7K
ENTRIP1
PQ306
SSM3K7002FU_SC70-3
ENTRIP1
1
2
1
2
1
2
2VREF_51125
U G_5V
20
VCLK
EN0
13
2
B++
21
VL
<37> ENT RIP2
PQ305
SSM3K7002FU_SC70-3
VFB1
VREF
DRVL1
PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
2 1
2
PR311
620K_0402_5%
VFB2
DRVL2
PC312
0.1U_0603_25V7K
<37> ENT RIP1
22
LL1
1
2
PC314
@680P_0603_50V7K
PR315
@4.7_1206_5%
12
PC309
220U_6.3VM_R15
DRVH1
LL2
18
LG_3V
DRVH2
23
11
VBST1
PQ302
AO4466_SO8
PC315
@680P_0603_50V7K
10
PGOOD
VBST2
VREG5
U G_3V
VREG3
VIN
17
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V
BST_3V
16
24
VO1
GND
+3VALWP
2 1
PR316
@4.7_1206_5%
PR307
VO2
SKIPSEL
SP8K10S-FD5_SO8
TONSEL
P PAD
PL302
4.7UH_SIQB74B-4R7PF_4A_20%
PU301
25
15
U G1_3V
8
7
6
5
1G
1S/2D
1S/2D
1S/2D
PR306
147K_0402_1%
14
D1
D1
G2
S2
PQ301
1
2
3
4
PC306
10U_0805_6.3V6M
PC303
4.7U_0805_25V6-K
1
2
PC301
2200P_0402_50V7K
PC316
@0.1U_0402_25V4K
PR305
174K_0402_1%
ENTRIP2
+3VLP
ENTRIP2
PQ304
FDS6690AS_NL_SO8
PR318
R_EC_RSMRST# <22>
0_0805_5%
+5VL
VL
PJP304
+ 5VALWP
PR313
100K_0402_5%
PQ307
P AD -OPEN 2x2m
+5VALW
(4.5A,180mils ,Via NO.= 9)
+3VALWP
G
SSM3K7002FU_SC70-3
EC_ON <32>
+3VL
+3VLP
P AD -OPEN 4x4m
PJP303
PR317
604K_0402_1%
VL
PJP301
2
+3VALW
(3A,120mils ,Via NO.= 6)
1
P AD -OPEN 2x2m
P AD -OPEN 4x4m
100K_0402_5%
PR314
PC318
0.022U_0402_25V7K
5
P
2
PQ308
SSM3K7002FU_SC70-3
32,38> ACOFF
PJP302
PU302
74LVC1G14GW_SOT353-5
NC
+3VL
Compal Secret Data

2007/05/29
Issued Date
Deciphered Date
2008/05/29
A
Title

3.3VALWP/5VALWP
Size
D o cument Number
R ev
0.3

D ate:
Sheet
E
39
of
46
PR401
0_0402_5%
PL401
HCB1608KF-121T30_0603
2200P_0402_50V7K
PC405
B+
VOUT
LL
13
12
1
2
1
2
1
2
1
2
D H_1.05V
PR411
3
2
1
VBST
DRVH
PQ401
AO4466_SO8
0_0402_5%
LX_1.05V
PL402
2.2UH_PCMC063T -2R2MN_8A_20%
VFB
V5DRV
DRVL
PR406
18.7K_0402_1%
+ 5VALW
10
5
6
7
8
11
PR407
4.7_1206_5%
4
T PS51117RGYR_QFN14_3.5x3.5
PC415
4.7U_0805_10V6K
PGOOD
+1.05V_VCCP
PR408
TRIP
2 2
PC409
1U_0603_10V6K
V5FILT
PGND
PC406
@680P_0402_50V7K
14
15
TP
0_0402_5%
TON
PC402
0.1U_0402_10V7K
+1.05V_VCCP
PC408
220U_6.3VM_R15
GND
EN_PSV
PR404
255K_0402_1%
PU401
+1.05V_VCCP
BST 1_1.05V
1
PR402
0_0402_5%
PR403
316_0402_1%
PR405
5
6
7
8
+ 5VALW
BST _1.05V
1
4.7U_0805_25V6-K
PC404
PC401
@1000P_0402_50V7K
@0.1U_0402_25V4K
PC414
1.05V_B+
PR410
@10K_0402_5%
4.7U_0805_25V6-K
PC403
6,38,41> SUSP#
PC412
220P_0603_50V8J
2
3
2
1
10.5K_0402_1%
PQ402
FDS6690AS_NL_SO8
DL_1.05V
PR409
25.5K_0402_1%
PJP401
+1.05V_VCCP
+ VCCP
(6A,240mils ,Via NO.=12)
P AD -OPEN 4x4m
Issued Date
Compal Secret Data

2007/05/29
Deciphered Date
2008/05/29
A
Title

1.05V_VCCP
Size
D o cument Number
R ev
0.3

D ate:

D
Sheet
40
of
46
+1.5VSP
PR505
0_0402_5%
PR504
14.3K_0603_0.1%
+1.8VP
B+++
B+
PL502
HCB2012KF-121T50_0805
BST _1.5V
U G_1.5V
10
PR508
11
12
DR VH1
LL2
LL1
DR VL2
DR VL1
24
1
2
1
2
2200P_0402_50V7K
PC505
1
2
1
2
PC504
4.7U_0805_25V6-K
22
BST _1.8V
21
U G_1.8V
20
LX_1.8V
19
LG_1.8V
PC507
0.1U_0402_10V7K
PR507
0_0402_5%
23
UG1_1.8V
+1.8VP
PL501
3.3UH_PCMC063T -3R3MN_6A_20%
PR509
0_0402_5%
1 2
PC519
@680P_0603_50V7K
3
2
1
PR511
16.5K_0402_1%
PR510
17.8K_0402_1%
PQ503
FDS6690AS_NL_SO8
2
1
PC508
PC510
4.7U_0805_6.3V6K
220U_D2_4VY_R25M
TRIP1
PGND1
T PS51124RGER_QFN24_4x4
18
17
V5IN
16
TRIP2
V5FILT
15
PGND2
13
PR516
@4.7_1206_5%
PC518
@680P_0603_50V7K
1
2
3
PC516
4.7U_0805_25V6-K
5
6
7
8
VO1
VFB1
GND
VBST1
DR VH2
1 2
AO4466_SO8
VBST2
PR515
@4.7_1206_5%
PC509
4.7U_0805_6.3V6K
VFB2
EN1
5
6
7
8
LX_1.5V
LG_1.5V
PGOOD1
EN2
PQ504
1
2
220U_B2_2.5VM
PC517
1
+
0_0402_5%
8
7
6
5
1 2
UG1_1.5V
PGOOD2
14
PL503
3.3UH_PCMC063T -3R3MN_6A_20%
1
2
3
+1.5VSP
PR506
0_0402_5%
PC521
@0.1U_0402_25V4K
PC506
0.1U_0402_10V7K
PQ501
AO4466_SO8
3
2
1
P PAD
TONSEL
25
VO2
8
7
6
5
PU501
PQ502
AO4466_SO8
PR503
10.2K_0603_0.1%
@0.1U_0402_25V4K
PC520
1
2
2200P_0402_50V7K
PC502
1
2
PC501
4.7U_0805_25V6-K
B+++
PR502
75K_0402_1%
PR501
73.2K_0402_1%
PR513
10K_0402_5%
<26,28,32,36,38,40> SUSP#
PR512
0_0402_5%
1
1
SYSON <26,32,33,36>
+ 5VALW
PR517
100K_0402_5%
PC512
@0.1U_0402_16V7K
PC515
4.7U_0805_10V6K
1
2
PC513
0.1U_0402_16V7K
PC514
1U_0603_10V6K
PR514
3.3_0402_5%
PJP501
+1.5VSP
+1.5VS
(4A,160mils ,Via NO.=8)
+1.8V
P AD -OPEN 4x4m
PJP502
+1.8VP
2
P AD -OPEN 4x4m
Compal Secret Data

2007/05/29
Issued Date
Deciphered Date
2008/05/29
5
Title

1.5VSP/1.8VP
Size
D o cument Number
R ev
0.3

D ate:
Sheet
1
41
of
46
+1.8V
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
+5VALW
3
P R 601
1K_0402_1%
7
8
1
2
P C 602
@ 1 0U_0805_10V4Z
1
P C 601
1 0U_0805_10V4Z
P U 601
TP
P C 603
1U_0603_16V6K
P R 602
@ 0_0402_5%
+0.9VP
2
G
P R 603
1K_0402_1%
1
P R 604
0_0402_5%
<36> SUSP
P Q601
S S M 3K7002FU_SC70-3
P C 605
10U_0805_6.3V6M
P C 606
@ 0.1U_0402_16V7K
P C604
0.1U_0402_16V7K
G 2 9 92F1U_SO8
<34,36> SYSON#
P JP601
+ 0.9VP
+ 0.9V
P A D - O P EN 3x3m
Compal Secret Data
S ecurity Classification
Issued Date
2006/11/23
Deciphered Date
2007/11/23
5
Title

0.9VP/1.1V_PCIE
Size
D o c u m ent Number
Rev
0 .3
Mo n te v in a Bla d e UMA LA4 1 0 1P

D a te:

1
Sheet
42
of
46
+5VS
1
2
1
2
P C240
2200P_0402_50V7K
P C208
1000P_0402_50V7K
P C239
6 8 U_25V_M_R0.44
P C207
2200P_0402_50V7K
1
2
P C206
4.7U_0805_25V6-K
P C205
4.7U_0805_25V6-K
P C234
4.7U_0805_25V6-K
P C233
4.7U_0805_25V6-K
1
2
4
3
2
1
G
S
S
S
P C237
@ 0.1U_0402_25V4K
D
D
D
D
5
6
7
8
PL202
0 .3 6 UH_ PCMC104T-R36MN1R17_30A_20%
0_0603_5%
P R217
+ VC C_CORE
P R220
10K_0402_1%
P R219
3.65K_0805_1%
P R218
4.7_1206_5%
5
6
7
8
2 1
5
6
7
8
37
38
39
P C204
6 8 U_25V_M_R0.44
P C242
470P_0402_50V7K
1
1
1
2
P R213
0_0402_5%
0_0402_5%
P R205
P R212
1
2
0_0402_5%
P R211
0_0402_5%
2
40
41
42
P C241
6 8 U_25V_M_R0.44
<7>
<7>
<7>
CP U_ V ID2
<7>
CP U_ V ID1
<7>
CP U_ V ID0
<7>
<7>
CP U_ V ID3
CP U_ V ID4
CP<32>
U_ V ID5
P R210
0_0402_5%
P R209
0_0402_5%
P R208
P R207
1
43
44
45
46
47
P Q201
AO4474_SO8
2
49
2.2_0603_5% 0.22U_0603_10V7KUGA T E_CPU1-2

P R214
P C209
P C202
0.022U_0402_16V7K
B OO T_CPU1
P R223
1_0402_5%
470P_0402_50V7K
P C222
2
220P_0402_50V7K
255_0402_1%
3
2
1
3
2
1
P C238
@0.1U_0402_25V4K
1
2
P C236
4.7U_0805_25V6-K
1
2
1
1
V S UM
P C223
0.22U_0603_10V7K
IS E N2
C PU_B+
P R240 1K_0402_1%
P C226 820P_0603_50V7K
2
V S UM
P C228
0.01U_0603_50V7K
P R243 1K_0402_1%
P R244 3.57K_0402_1%
P C230 0.1U_0402_16V7K
V CC_ P RM
2
2
10KB_0603_5%_ERTJ1VR103J
P H201
1
2
P R242
P C229 180P_0402_50V8J
11K_0402_1%
< 7> V SSSENSE
P C227
@0.022U_0603_50V7K
P R241
1
2
@0_0603_5%
P C225
0.1U_0603_25V7K
1_0402_5%
P R233
V CC_ P RM
< 7> V CCS E NSE
P Q206
F DS6676AS_SO8
P R239
10_0603_5%
P C224 1000P_0402_50V7K
P R2381
+5VS
P R232
1
PL203
2.61K_0402_1%
P C235
4.7U_0805_25V6-K
P Q205
F DS6676AS_SO8
P R234 1_0603_5%
P C221
1U_0402_6.3V6K
0 .3 6 UH_ PCMC104T-R36MN1R17_30A_20%
1
1
2 P R237 1
1K_0402_1%
1 P R236 2
@0_0402_5%
UGA T E_CPU2-2
P U201
IS E N1
IS E N2
P C214
2200P_0402_50V7K
P R225
UGA T E_CPU2-1 1
2
0_0603_5%
B OO T_CPU2
1
2
1
2
P R227
2.2_0603_5%
P C217
0.22U_0603_10V7K
25
C PU_B+
26
P HA S E_CPU2
P R231
10K_0402_1%
27
28
PQ204
AO4474_SO8
G
S
S
S
29
P C218 1000P_0402_50V7K
P R235 97.6K_0402_1% P C220
P C212
4.7U_0805_25V6-K
D
D
D
D
L G ATE_CPU2
ISEN1
NC
24
ISEN2
23
VDD
22
GND
21
VIN
20
VSUM
19
VO
18
13
DFB
2
1
17
FB2
16
12
RTN
1000P_0402_50V7K P C216
P R228 6.81K_0402_1%
15
BOOT2
DROOP
FB
VSEN
UGATE2
V CC_ P RM
11
COMP
IS E N1
0.22U_0603_10V7K
1 2
10
PHASE2
VDIFF
13K_0402_1%
PGND2
VW
30
P R229
4.7_1206_5%
14
P R226
LGATE2
IS L6262ACRZ-T_QFN48_7X7
OCSET
31
4
3
2
1
SOFT
0.022U_0603_25V7K P C215
PVCC
5
6
7
8
NTC
P C211
L G ATE_CPU1
32
5
6
7
8
1 2
2
PQ203
F DS6676AS_SO8
P C213
4.7U_0805_25V6-K
LGATE1
P HA S E_CPU1
33
5
6
7
8
VR_TT#
34
3
2
1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
DPRSTP#
PGND1
P R224
@0_0603_5%
V S UM
PHASE1
RBIAS
PQ202
F DS6676AS_SO8
UGA T E_CPU1-1
VR_TT#
PMON
35
P R230
3.65K_0805_1%
36
P C219
470P_0603_50V7K
BOOT1
UGATE1
P C210
470P_0603_50V7K
PSI#
3
2
1
1 P R221 2
@0_0402_5% P R222 147K_0402_1%
3V3
PGOOD
< 7> H_ P SI#
CLK_EN#
GND
1
< 17,22> VGATE
0_0402_5%
P C201
1U_0603_6.3V6M
P R216
1.91K_0402_1%
+3VS
0_0402_5%
48
P R206
+3VS
0_0402_5%
<17> CL K_ENABLE#
P R215
0_0402_5%
P R204
@499_0402_1%
0_0402_5%
< 7,9,21> H_ DPRSTP#
P C203
2 .2U_0603_6.3V6K
P R203
PL201
SMB3025500YA_2P
499_0402_1%
<9,22> DP RS L PVR
CP U_ V ID6
V R_ ON
P R201
B+
C PU_B+
P R202
1_0603_5%
P C232 0.22U_0402_6.3V6K
P C231
0.22U_0603_10V7K

Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
5
Size
Do c u m e n t Number
Cu s to m
Da te:
R ev
0 .3
S a tu r d a y , January 05, 2008
Sheet
1
43
of
46
Item
Fixed Issue
(Reason for change)
Transation Fail
Disable TV out function from Docking
PAGE
08
1134
Update Connetor Library
Modify List
Date
Phase
C41C42C43C44 Change ESR=7m ohm
11/21
SI-1
R61R62R63 change to 75 OhmTV_DCONSEL_0TV_DCONSEL_1 connect to GND
11/07
SI-1
CRT(JCRT1)HDMI(JHDMI1)ESATA(JP53)Finger print(JJP24)FAN(JP2)Speaker(JP60)Multi
bay(JP12)Dual LED(D53D12)
11/17
SI-1
Schematic Delete
11/17
SI-1
Change U42 to G916-390T1UF SOT23, it adjustable mode, R1091=215KR1093=100K
11/07
SI-1
GPIO6= CR_CPPE#GPIO22=CR_WAKE#
11/17
SI-1
Swap PCIE4 and PICE6
11/17
SI-1
Delete LVDS B channel
USB camera Footprint error
Reserve Card reader D3E function
Swap PCIE LAN and New card
Add HDCP ROM for ICH9M
2231
Add HDCP ROM for ICH9M
11/17
SI-1
Change G sensor control from SBLED drive by +5VS
2233
Change G sensor control from SB
11/17
SI-1
10
Avoid Battery mode can't boot issue
2239
Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue
11/17
SI-1
11
Add G sensor ST and Bosch
24
Add G sensor ST and Bosch
11/17
SI-1
12
Change LAN solution (Marvell to Realtek)
25
Change LAN solution (Marvell to Realtek)
11/17
SI-1
13
LAN can't work
25
U46 Change to correct transformer type
11/17
SI-1
14
Cardreader schematic review and update, add D3E function
27
R709-->10KR402-->8.2KR704-->StuffR705-->@U37-->@Cardreader LED-->+5VSadd D3E function
11/17
SI-1
15
Jack can't detect normal
28
R1059 change from 39.2 to 39.2K
11/17
SI-1
16
Speaker work un normal
28
Add and Stuff C1362R1065R596
11/17
SI-1
17
HP audio team recommend
C285~C292C1352C1354 change to 0.022UAmp output setup to 15.6 dBReserve C305C306 for GNDA and GND
11/17
SI-1
18
Audio jack can't detect normal
29
Add Pull up resistor R401 to +3VALW
11/17
SI-1
19
Docking HP audio test fail
29
Add C295 BC296 to avoid DC level, and add R409R410 to reduce HP out level
11/17
SI-1
20
Leakage problem
32
Correct direction pretect leakage
11/07
SI-1
21
EC pin define update
32
Delete EC_PME#SYSON PUSUSP# PULID_SW# change to +3VALWDelete CLKRUN#R582->@ for C0 chipCIR

PU+5VLadd 100P to BATT_OVP(EC recommend)
11/07
SI-1
22
Can't Hibernation(SLP_S4#)
32
Connect SLP_S4# to SB
11/17
SI-1
23
EC can't receive docking present
34
CONA# change +3VL
11/12
SI-1
24
HDMI can't detect
35
DDC _EN must enable TMDS_B_HPD# inverse
11/07
SI-1
25
LVDS power on timing
19
C238 change to 0.047u to meet TI timing
01/03
SI-2
26
Prevent WWAN nosie
21
Add 12p on HDA_SDOUT and HDA_SDOUT
01/03
SI-2
27
Power leakage
Change HDCP ROM to +3VS power plane
01/03
SI-2
1119
19
2227
22
C
2829
2131
28
Prevent WLAN leakage
26
Add Diode prevent WLAN leakage
01/03
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title
SI-2

PIR
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
44
of
46
Item
Fixed Issue
(Reason for change)
PAGE
Modify List
Date
Phase
29
New card PTH connector GND
26
New card PTH connector GND
01/03
SI-2
30
Change Cardreader LED control
27
Change Cardreader LED control
01/03
SI-2
31
Change SPDIF to SPDIF1
28
Change to SPDIF1
01/03
SI-2
32
Shut down pop noise
29
Change C293 to 1U
01/03
SI-2
33
Change BT power to +3VS
30
Change BT power to +3VS
01/03
SI-2
34
EMI Request
31
SPI_FSEL#SPI_CLK_RSPI_FWR# reserver RC
01/03
SI-2
35
Reserver 0 ohm co lay with common choke
35
Reserver 0 ohm co lay with common choke
01/03
SI-2
36
Sparate+5VS and +3VS power timing
36
Sparate+5VS and +3VS power timing
01/03
SI-2
37
Keyboard backlight reserve a 0805 size resistor
33
Keyboard backlight reserve a 0805 size resistor
01/03
SI-2
38
Change Lid switch connector type
33
Change Lid switch connector type
01/03
SI-2
39
C
C
40
41
42
43
44
45
46
47
B
48
49
50
51
52
53
54
55
A
56
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
5
Title

PIR 2
Size
Do c ument Number
Rev
0.3

Da te:
Sheet
1
45
of
46
Version Change List ( P. I. R. List ) for Power Circuit

A
Title
Item Page#
1
37
39
DC Connector
/CPU_OTP
3.3VALWP/5VALWP
Date Request
Owner
Compal
Add PD4 & PC12
11/06
Compal
for Layout
Solution Description
Issue Description
11/06
Rev.
1
Add PD4 & PC12
Change PQ301 cancel PQ303

3
38
43
39
38
Charger
11/06
Compal
EMI solution
Add pc128
+CPU_CORE
11/06
Compal
EMI solution
3.3VALWP/5VALWP
11/14
Compal
for Layout
Change PL303 and PC310
12/31
Compal
EMI solution
Add PC129, PC130, PC131, PC132, PC133
Add PC240
Charger
43
39
+CPU_CORE
12/31
Compal
EMI solution
Add PC242
3.3VALWP/5VALWP 12/31
Compal
PWR request
Add PU302, control signal changed to ACOFF
10
11
3
12
13
14
Compal Secret Data
2007/08/02
Issued Date
2008/08/02
Deciphered Date
A
Title

Power Changed-List History-1

Cu s tom
Montevina
Da te:
Rev
0.3
B lade UMA LA 4101P

Sheet

E
46
of
46

Compaq Presario Cq40 - Compal La-4101p

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Compaq Presario Cq40 - Compal La-4101p

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A

Compal Secret Data

Compal Electronics, Inc.

Size Do c ument Number

S aturday, January 05, 2008

Montevina Consumer 14" UMA

667/800/1066 MHz 1.05V

DDR2 667MHz 1.8V

Intel Cantiga MCH

P9,10, 11, 12, 13, 14

AMP & Audio Jack

SATA HDD Connector

SATA ODD Connector

USB Board Conn

Touch Pad CONN.

K/B backlight Conn

Capsense switch Conn

DC/DC Interface CKT.

Compal Electronics, Inc.

Size Do c ument Number

S aturday, January 05, 2008

: means Digital Ground

USB-0 Right side

: means Analog Ground

45@ : means need be mounted when 45 level assy or rework stage.

GS @ : means just reserve for G sensor

CONN@ : means ME part

BATT @ : means need be mounted when 45 level assy or rework stage.

USB-9 Express card

DEBUG@ : means just reserve for debug.

@ : means just reserve , no build

Multi @ : means just reserve for Multi Bay

NewC@ : means just reserve for New card

FP @ : means just reserve for Finger Print

DOCK@ : means just reserve for Docking

Main@ : means just reserve for Main stream

S5 S4/ Battery only

OPP@ : means just reserve for OPP

S5 S4/AC & Battery

2MiniC@ : means just reserve for 2nd Mini card slot

SMBUS Control Table

I2C / SMBUS ADDRESSING

CLOCK GENERATOR (EXT.)

Compal Secret Data

43154432L01 UMA GM PA FF (SI-1)

43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP @/ESATA@/GS@/Multi@/2MiniC@

Compal Electronics, Inc.

Size Do c ument Number

S a turday, January 05, 2008

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

Compal Secret Data

Compal Electronics, Inc.

Mo n tevina Blade UMA LA4101P

Compal Secret Data

Compal Electronics, Inc.

Size Do c ument Number

S a turday, January 05, 2008

Change value in 5/02

This shall place near CPU

Place R191 within 200ps (~1") to CPU

For Merom, R14 and R15 are 0ohm

H_THERMDA, H_THERMDC routing together,

PWM Fan Control circuit