Gii thiu v ADC 1. Chuyn i t tn hiu tng t (Analog) v tn hiu s (Digital) 1.

1 Khi nim chung

UD 111 110 101 100 011 010 001 000

1
ULSB

2 3 4 5

7 8
UAmax

UA

Hnh 1-1. c tuyn truyn t ca b bin i tng t - s Trong qu trnh bin i tng t s, tn hiu tng t a vo c chuyn thnh tn hiu c dng bc thang u (hnh 1-1). Vi mi khong gi tr ca tn hiu vo c mt gi tr ri rc i din cho n. Trong cc b ADC th gi tr ri rc ny thng c biu din theo h c s 2 (m nh phn). Ni mt cch khc th gi tr u vo c chuyn v h c s 2 theo biu thc: SD=bn-12n-1+ bn-22n-2++ b020 (1) Trong cc h s bk=0 hoc 1 (vi k=0..n-1) c gi l bit. Gi tr b n-1 c gi l bit c trng s ln nht (MSB Most Significant Bit) v b0 c gi l bit c trng s nh nht (LSB Least Significant Bit). Vi mt b bin i c N bit th mi nc trn hnh bc thang chim mt khong gi tr: Q = ULSB =
U A max 2 N 1

(2)

Trong , UAmax l gi tr cc i cho php ca tn hiu vo. Khong gi tr Q ny c gi l mc lng t. V d: Vi b bin i 8bit v in p ti a cp cho b bin i ADC l UAmax=5V th Q = ULSB = UAmax/(2N-1) = 5V/(256-1) 0.02V Sai s do qu trnh chuyn i t tng t sang s gi l sai s lng t ha c xc nh bng:

UQ=0.5Q
mu ca b ADC phi tun theo nh l ly mu. Tc l: fM 2fthmax 2B

(3)

m bo vic khi phc li tn hiu c chnh xc th i hi tn s ly

trong , fthmax l tn s cc i ca tn hiu tng t u vo; B l di tn ca tn hiu vo. Nu tun th c iu kin ny th s m bo khng c s trng lp ca ph c bn (ph tn hiu vo) v cc thnh phn ph khc sinh ra do qu trnh ly mu (cc thnh phn ph ny phn b v hai pha ca fM v bi s ca fM ng thi cch chng mt khong ng bng di tn B ca tn hiu). 1.2. Cc tham s c bn. Di bin i ca in p tng t u vo l khong in p m b chuyn i AD c th thc hin chuyn i c. N c nh lng bng gi tr UAmax. i vi mt b bin i c u vo mt cc tnh th di bin i ca n t 0 - UAmax cn vi b bin i c u vo hai cc tnh th di bin i ca n s t -UAmax n +UAmax. chnh xc ca b bin i AD. o phn gii ca mt b ADC c k hiu l Q v c tnh theo biu thc (2). Q chnh l gi tr ca mt mc lng t ha cn gi l 1 LSB.

o Sai s lch 0 l do ng c tuyn khng bt u vi gi tr ng vi LSB. o Sai s khuch i l sai s gia dc trung bnh ca ng c tuyn thc v ng c tuyn l tng. o Sai s n iu cng do tnh phi tuyn ca ng c tnh bin i gy ra nhng y l trng hp c bit lm cho dc ca ng trung bnh bin thin khng n iu thm ch cn lm mt mt vi m. o Ngoi ra, nu b ADC lm vic l tng th vn tn ti sai s lng t ha c tnh theo biu thc (3). y chnh l sai s h thng ca b ADC. Tm li, c trng cho tnh chnh xc ca b ADC bao gm: phn bit, mo phi tuyn, sai s khuch i, sai s lch khng v sai s n iu. y l cc sai s do b ADC lm vic khng chnh xc gy nn. Ngoi ra cn c sai s h thng l sai s lng t ha. Ngi ta quy c rng tng cc sai s khng c ln hn sai s l tng sao cho b ADC c thit k vi chnh xc N+1 bit th t c chnh xc N bit. Tc chuyn i l s kt qu chuyn i trong 1 giy hay cn gi l tn s chuyn i fc. Cng c th dng tham s thi gian chuyn i T c c trng cho tc chuyn i. Tc l thi gian cn thit cho mt kt qu chuyn i. 1.3 ADC trong Atmega64 Vi iu khin Atmega64 c mt b bin i ADC tch hp trong chip c cc c im: + phn gii 10 bits. + Sai s phi tuyn :0.5LSB. + chnh xc +/-2LSB. + Thi gian chuyn i:65-260s. + 8 Knh u vo c th c la chn. + C hai ch chuyn i (chuyn i n v t do).

+ Khong in thp ng vo l 0 - Vcc + C ngun bo ngt khi hon thnh chuyn i. + Loi b nhiu trong ch ng. B bin i ADC ca Atmega64 c phn gii 10 bits c ni vi 8 knh u vo cc chn ca Port F. Cc in th cc chn ng vo c tham chiu vi 0V (GND). B bin i ADC c tch hp mch ly v gi mu (Sample and Hold circuit) nhm m bo gi tr in th ng vo lun mc c nh trong qu trnh chuyn i. S khi ca b bin i ADC hnh sau:

S khi ca b bin i ADC

T s khi cc ta thy: Tm u vo ca ADC l tm chn ca PORTA v chng c chn thng qua mt MUX. iu khin hot ng vo ra d liu ca ADC v CPU chng ta c 3 thanh ghi:ADMUX - thanh ghi iu khin la chn knh u vo cho ADC; ADCSR - thanh ghi iu khin v thanh ghi trng thi ca ADC; ADCD - thanh ghi d liu. Sau y l tng thanh ghi: 1. ADMUX: Multiplexer select register

Bit 7:6 REFS1:0: Reference Selection Bits Hai bit ny dng chn ch in th tham chiu cho b bin i ADC. Cc bit ny thay i trong qu trnh chuyn i s khng nh hng n kt qu ca qu trnh cho ti khi qu trnh chuyn i kt thc. Ty chn dng in th tham chiu ni c th khng c hiu lc nu ta ni in th tham chim bn ngoi vi chn AREF. Bng ty chn cc ch in th tham chiu:

Bit 5 ADLAR: ADC Left Adjust Result y l bit cho kt qu chuyn i dch tri trong thanh ghi d liu ADC (ADCDR) khi c set ln 1, ngc li set mc 0 s dch sang phi. Khi bit ny thay i th thanh ghi ADCDR thay i tc thi bt k b chuyn i ang thc thi hay khng.

Bit 4 kt hp 3 bit cui chn knh ng vo v h s khuch i Vi 3 bit c nh ngha l MUX2,MUX1,v MUX0.ng vi cc t hp logic cc bn c th chn knh u vo.C th:

Ch : Nu nh ta thay i knh trong thi im m ADC anh chuyn i th khi qu trnh chuyn i hon thnh th knh vo mi c thay i. 2. ADCSRA :ADC control and status register A. y l thanh ghi iu khin v lu trng thi ca ADC:

Bit 7-ADEN: ADC enable y l bit iu khin hot ng ca ADC .Khi bit ny c set 1 th ADC c th hot ng v ngc li.Nu nh ta ngng hot ng ca ADC trong khi n ang chuyn i th n s kt thc qu trnh chuyn i mc d cha chuyn i xong.

Bit 6-ADSC: ADC start conversion Trong ch chuyn i n th bit ny phi c set ln 1 bt u chuyn i.Trong ch chuyn i t do th bit ny cn c set ln 1 bt u ln chuyn i u tin. Bit ny c gi st trong qu trnh chuyn i v c xa khi m chuyn i xong. Bit 5-ADRR: ADC Free Running select Khi bit ny c set th ADC hot ng theo ch chuyn i t do. y l ch m ADC t ng ly mu v chuyn i (khi n c php chuyn i)t mt knh nh sn. Khi xa bit ny th ch ny lp tc ngng hot ng. Bit 4-ADIF: ADC interrupt Flag Bit ny c set ln 1 bi phn cng khi m qu trnh chuyn i hoang thnh v thanh ghi d liu c update. Bit ny c xa bng phn cng nu nh ngt ny c php v c phc v hoc n c th c xa bng cch ghi gi tr logic 0vo c ny. C th khi ngt b cm ta c th s dng cc lnh sbi v cbi tc dng ln bit ny. Bit 3-ADIE: ACD interrupt Enable Nu bit ny set 1 v ngt ton cc c cho php th ngt ny c php phc v (Khi chuyn i xong d liu) v nu b xa th ngc li. Bit 2.1.0-ADPS2ADPS0:Bit la chn xung nhp(Tc ) S qua v ngun xung:Ngun xung c ly t ngun xung ca VK (XTAL)v c chia tn thng qua b chia tn:

3.Thanh ghi d liu ADCDR: y l thanh ghi 16 bit v ta c th truy nhp chng nh hai thanh ghi 8 bit vi a ch v cc bit tng ng: Khi ADLAR = 0:

Khi ADLAR = 1: