Ecad & Vlsi Lab

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
LABORATORY MANUAL FOR
ECAD & VLSI LAB

(IV B.Tech., I Sem)
BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE

Laknepally, Narsampet, Warangal
ECAD AND VLSI LAB

Department of Electronics &Communication Engineering ECAD & VLSI Lab
LIST OF EXPERIMENTS: ECAD Programs:
1. HDL code to realize all the logic gates. 2. Design of 2-to-4 decoder. 3. Design of 8-to-3 encoder.(with out and with parity) 4. Design of 8-to-1 multiplexer 5. Design of 4-bit binary to gray converter 6. Design of multiplexer/demultiplexer, comparator 7. Design of full adder using three modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counter (Synchronous/asynchronous reset) or any sequence counter 10. Finite state machine design
VLSI Programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement and route for complex design state timing analysis, IR drop analysis and cross talk analysis of the following i. ii. iii. iv. v. vi. Basic logic gates CMOS inverter CMOS NOR/NAND gates CMOS XOR and MUX gates CMOS 1-bit full adder Static/ Dynamic logic circuits (register cell)
ECAD & VLSI Lab
Department of Electronics &Communication Engineering
vii. viii.
Latch Pass transistor
3. Layout of any combinational circuit (complex CMOS logic gate)Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter/ Differential amplifier 6. Analog circuit simulation (AC analysis) CS & CD amplifier 7. System level design using PLL PROCEDURE TO CODE A DESIGN AND VERIFY THE RESULT USING
XILINX ISE SIMULATOR WITH SPARTAN3 FPGA/COLD Implementation Step1: File New Project Enter the Project Name Top level Source type : HDL Click Next Step2: New Project Wizard Project Properties window opens Select the Device and the Design flow for the Project: Product Category Family Device Package Speed Synthesis Tool : : : : : : All Spartan3 XC3S200 -4
FT256 XST (VHDL/Verilog)
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Simulator Click Next
ISE Simulator
(VHDL/Verilog)
New Project Wizard Create New Source Window opens Click on New Source Select VHDL Module and enter the file name. see that Add to Project is selected. Click Next New Source Wizard Design module window opens Enter the port name and select the direction appropriately Click Next Finish Next Next Finish. Step3: To enter the logic in the program, click the mouse at the place where the logic needs to be entered. Go to Edit Language Templates Synthesis Constructs Coding Examples Select the design you are coding. After selection click Edit Use in File Save the Program. Step4:To synthesize the Design Double click Check Syntax in Synthesize XST in Processes window After checking syntax double click Synthesize XST Double click View Technology Schematic to view the Schematic diagram of the design. Step5: To Implement the Design Double click Implement Design in Processes window. Step6: To view the wave forms. Click Project New Source New Source Wizard Select Source Type window opens.
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Select Test Bench Waveform and type the source file name with _tbw at the end. See that Add to project has been selected. Click Next Next Finish. Initial Timing and Clock Wizard Initialize Timing window opens Set the timings as required if any clock is needed in the design otherwise no need of any settings. Click Finish. Set the waveforms as required. Save and Close the waveforms window. Select Behavioral simulation as Sources for in sources window and click on the .tbw file in sources window. Now double click Simulate Behavioral Model in Xilinx ISE Simulator in processes window to view the output waveform of the design. Step7: To assign the package pins: Double click Assign Package Pins in User Constraints in processes window. Project Navigator window opens. Click Yes. Xilinx PACE window opens. Select Package View. Select appropriate pins and enter them in the Loc in design object lis I/O pins. Save the Window Bus Delimiter window opens. Select XST default, click OK and close it. Implement the design again by double clicking Implement Design in Processes window. Step8: Select Post-Route Simulation as Sources for in sources window. Select .tbw file in sources window. Double click Simulate Post-Place and Route Model in processes window. ISE simulator window opens. Click Yes. Waveforms with delay appear on the window. Step9: To dump the code onto the Spartan3 kit: Double click Generate Programming File in processes window. Double click Configure Device (iMPACT) iMPACT window opens.
Select Configure device using boundary-scan (JTAG) and click Finish. Assign new configuration file window opens. Select .bit file and click open. For the next assign new configuration window click bypass. Right click the XC3S200 FPGA and click program. Programming properties window opens. Click OK.
Program succeeded
Appears on the screen and the leds on the spartan3 kits glow indicating the success of the design. Step10: Verify the result by connecting the digital trainer kit to the pins selected.
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EXPERIMENT- 1 VHDL CODE FOR AND GATE AIM: To implement AND gate using VHDL. THEORY: The AND gate performs logical multiplication, more commonly known as AND function. And gate can have any number of inputs greater than one. The operation of AND gate is such that output is HIGH only when all of the inputs are HIGH. When any of the inputs are LOW the output is LOW. TRUTH TABLE:
A 0 0 1 1 BOOLEAN EXPRESSION: C=AB RTL SCHEMATIC:
B 0 1 0 1
C 0 0 0 1
CIRCUIT DIAGRAM:
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VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end andgate; architecture Behavioral of andgate is begin c<= a and b; end Behavioral; TIMING WAVEFOMRS:
ECAD & VLSI Lab
VHDL CODE FOR OR GATE AIM: To implement OR gate using Xilinx procedure. THEORY: The OR gate performs logical addition, more commonly known as OR function. OR gate can have any number of inputs greater than one. The operation of OR gate is such that output is HIGH only when any one of the inputs are HIGH. TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 C 0 1 1 1
BOOLEAN EXPRESSION: C=A+B RTL SCHEMATIC:
CIRCUIT DIAGRAM:
VHDL CODE: library IEEE;
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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end orgate; architecture Behavioral of orgate is begin c <= a or b; end Behavioral; TIMING WAVEFORM:
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VHDL CODE FOR NAND GATE AIM: To implement NAND gate using Xilinx procedure. THEORY: The term NAND is a contraction of NOT-AND and implies an AND function with a complemented output. It is a universal gate. the logical operation of NAND gate is such that a Low output occurs only when all inputs are HIGH. when any of the inputs are LOW, output will be HIGH. TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 C 1 1 1 0
BOOLEAN EXPRESSION: C=A+b= (AB) RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:
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VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nandgate is port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nandgate; architecture Behavioral of orgate is begin c <= a nand b; end Behavioral; TIMING WAVEFORM:
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VHDL CODE FOR NOR GATE AIM: To implement NOR gate using Xilinx procedure. THEORY: The term NOR is a contraction of NOT-OR and implies an OR function with a complemented output. It is a universal gate. the logical operation of NOR gate is such that a Low output occurs when any of the inputs are HIGH. when all of the inputs are LOW, output will be HIGH. TRUTH TABLE:
A 0 0 1 1 BOOLEAN EXPRESSION:
B 0 1 0 1
C 1 0 0 0
C= (A+B)=AB RTL SCHEMATIC:
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PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity norgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end norgate; architecture Behavioral of norgate is begin c <= a nor b; end Behavioral; TIMING WAVEFORM;
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VHDL CODE FOR XOR GATE AIM: To implement XOR gate using Xilinx procedure. THEORY: It recognizes only the words that have an odd number of ones. This means that for odd number of ones, output of XOR gate is HIGH. TRUTH TABLE:
B 0 1 0 1
C 0 1 1 0
C=AB+AB RTL SCHEMATIC:
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PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xorgate; architecture Behavioral of xorgate is begin c <= a xor b; end Behavioral; TIMING WAVEFORM:
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VHDL CODE FOR XNOR GATE AIM: To implement XNOR gate sing Xilinx procedure. THEORY: It recognizes only the words that have an even number of ones/zeros. This means that for odd number of ones, output of XNOR gate is LOW. TRUTH TABLE:
B 0 1 0 1
C 1 0 0 1
C=AB+AB CIRCUIT DIAGRAM:
TIMING WAVEFORM:
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PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnorgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xnorgate; architecture Behavioral of xnorgate is begin c <= a xnor b; end Behavioral;
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VHDL CODE FOR NOT GATE AIM: To implement NOT gate using Xilinx procedure. THEORY: The inverter (NOT circuit) performs a basic logic function called inversion or complementation. The inverter changes one logical level to its opposite level. In terms of bits, it changes logic1 to logic 0 and logic 0 to logic1. TRUTH TABLE: A 0 1 B 1 0
BOOLEAN EXPRESSION: B=A RTL SCHEMATIC:
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PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port ( a : in STD_LOGIC; b : out STD_LOGIC); end notgate; architecture Behavioral of notgate is begin b <= not a; end Behavioral; TIMING WAVEFORM:
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EXPERIMENT- 2 VHDL CODE FOR 2x4 DECODER AIM: To design a 2x4 decoder and to simulate in VHDL. THEORY: A decoder is a combinational circuit with multiple input, multiple output logic circuit that converts coded inputs to coded outputs, where the inputs are lesser in number than output codes. The input code is generally has fewer bits than the output code, there is one-to-one mapping from input code words into output code words. in a one-to-one mapping, each input code word produces a different output code word. The general structure of a decoder circuit can be shown as follows. The enable inputs, if present must be asserted for the decoder to perform its normal mapping function. Otherwise the decoder maps all the input code words into a single disabled output code word. The corresponding IC number is 74138. TRUTH TABLE:
e 0 1 1 1 1 PROGRAM CODE: library IEEE;
i0 x 0 0 1 1
i1 x 0 1 0 1
f0 0 1 0 0 0
f1 0 0 1 0 0
f2 0 0 0 1 0
f3 0 0 0 0 1
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2x4 is Port ( x : in STD_LOGIC_VECTOR (1 downto 0); d : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2x4;
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architecture Behavioral of decoder2x4 is begin process (x) is begin case x is when "00"=> d <="1000"; when "01"=> d <="0100"; when "10"=> d <="0010"; when others=> d <="0001"; end case; end process; end behavioral; TECHNOLOGY SCHEMATIC DIAGRAM FOR 2x4 DECODER:
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SIMULATION RESULTS FOR 2x4 DECODER:
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VHDL CODE FOR 3x8 DECODER AIM: To design a 3x8 decoder and to simulate in VHDL. TECHNOLOGY SCHEMATIC DIAGRAM FOR 3-8 DECODER:
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bejoy_3x8 is port(a,b,c:in std_logic; d0,d1,d2,d3,d4,d5,d6,d7:out std_logic); end bejoy_3x8; architecture arc of bejoy_3x8 is begin d0<= (not a) and (not b) and (not c); d1<= (not a) and (not b) and c; d2<= (not a) and b and (not c);
d3<= (not a) and b and c; d4<= a and (not b) and (not c); d5<= a and (not b) and c; d6<= a and b and (not c); d7<= a and b and c; end arc; SIMULATION RESULTS FOR 3X8 DECODER:
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VHDL CODE FOR DECODER 4X16 USING 2X4 AIM: To design a 4X16 decoder using 2x4 decoder and to simulate in VHDL. TECHNOLOGY SCHEMATIC DIAGRAM FOR 4X16 DECODER:
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PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder4x16 is Port ( a,b,c,d,e : in STD_LOGIC; y : out STD_LOGIC_vector(15 downto 0)); end decoder4x16; architecture Behavioral of decoder4x16 is signal c1,c2,c3,c4: std_logic; component decoder16 is port (p,q,e: in std_logic; d1,d2,d3,d4:out std_logic); end component; begin P1: decoder16 port map(a,b,e,c1,c2,c3,c4); P2: decoder16 port map(c,d,c1,y(0),y(1),y(2),y(3)); P3: decoder16 port map(c1,d,c2,y(4),y(5),y(6),y(7)); P4: decoder16 port map(c,d,c3,y(8),y(9),y(10),y(11)); P5: decoder16 port map(c,d,c4,y(12),y(13),y(14),y(15)); end Behavioral; Component declaration of decoder16 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder16 is Port ( p,q,e : in STD_LOGIC; d1,d2,d3,d4 : out STD_LOGIC); end decoder16; architecture Behavioral of decoder16 is begin
d1<= ((not p) and (not q) and e); d2<= ((not p) and (q) and e); d3<= (p and (not q) and e); d4<= (p and q and e); end Behavioral; SIMULATION RESULTS OF DECODER 4X16:
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EXPERIMENT- 3 VHDL CODE FOR 8 to 3 ENCODER AIM: To design a 8x3 encoder and to simulate in VHDL. RTL SCHEMATIC DIAGRAM FOR 8x3 ENCODER:
TRUTH TABLE: input

e n din( 7) din( 6) din( 5) din( 4) din( 3) din( 2) din( 1) din( 0) dout( 2)
output
dout( 1) dout( 0)
1 0 0 0 0 0 0 0 0
x 0 0 0 0 0 0 0 1
x 0 0 0 0 0 0 1 0
x 0 0 0 0 0 1 0 0
x 0 0 0 0 1 0 0 0
x 0 0 0 1 0 0 0 0
x 0 0 1 0 0 0 0 0
x 0 1 0 0 0 0 0 0
x 1 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1
0 0 0 1 1 0 0 1 1
0 0 1 0 1 0 1 0 1
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( en : in STD_LOGIC; din : in STD_LOGIC_VECTOR (7 downto 0); dout : out STD_LOGIC_VECTOR (2 downto 0)); end encoder8_3; architecture Behavioral of encoder8_3 is begin process (en,din) begin
if (en='1') then dout<="000"; else case din is when "00000001"=>dout<="000"; when "00000010"=>dout<="001"; when "00000100"=>dout<="010"; when "00001000"=>dout<="011"; when "00010000"=>dout<="100"; when "00100000"=>dout<="101"; when "01000000"=>dout<="110"; when "10000000"=>dout<="111"; when others => null; end case; end if; end process; end Behavioral; SIMULATION FOR 8x3 ENCODER:
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VHDL CODE FOR PRIORITY ENCODER AIM: To design a priority encoder and to simulate in VHDL. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity priorityencoder is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priorityencoder; architecture Behavioral of priorityencoder is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else "010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "---"; end Behavioral;
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TECHNOLOGY SCHEMATIC DIAGRAM FOR PRIORITY DECODER:
SIMULATOIN RESULTS OF PRIORITY ENCODER:
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EXPERIMENT- 4 VHDL CODE FOR 8:1 MULTIPLEXER AIM: To design a 8:1 multiplexer and to simulate in VHDL. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8 is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0); e : in STD_LOGIC; o : out STD_LOGIC); end mux8; architecture Behavioral of mux8 is begin process(s,i) begin case s is when "000" => o <=i(0); when "001" => o <=i(1); when "010" => o <=i(2); when "011" => o <=i(3); when "100" => o <=i(4); when "101" => o <=i(5); when "110" => o <=i(6); when "111" => o <=i(7); when others => o <= i(0); end case; end process; end Behavioral;
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SCHEMATIC DIAGRAM OF 8:1 MULTIPLEXER:
TIMING DIAGRAM OF 8:1 MULTIPLEXER:
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VHDL CODE FOR 16X1 MULTIPLEXER AIM: To design a 16x1 multiplexer and to simulate in VHDL. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux16 is Port ( i : in STD_LOGIC_VECTOR (15 downto 0); s : in STD_LOGIC_VECTOR (3 downto 0); e : in STD_LOGIC; o : out STD_LOGIC); end mux16; architecture Behavioral of mux16 is begin process(s,i) begin if e='1' then case s is when "0000" => o <=i(0); when "0001" => o <=i(1); when "0010" => o <=i(2); when "0011" => o <=i(3); when "0100" => o <=i(4); when "0101" => o <=i(5); when "0110" => o <=i(6); when "0111" => o <=i(7); when "1000" => o <=i(8); when "1001" => o <=i(9); when "1010" => o <=i(10); when "1011" => o <=i(11); when "1100" => o <=i(12); when "1101" => o <=i(13); when "1110" => o <=i(14);
when "1111" => o <=i(15); when others => o <= i(0); end case; end if; end process; end Behavioral; TECHNOLOGY SCHEMATIC FOR 16X1 MULTIPLEXER:
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SIMULATION FOR 16X1 MULTIPLEXER:
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EXPERIMENT- 5 VHDL CODE FOR 4 BIT BINARY TO GRAY CONVERTER AIM: To design a 4 bit binary to gray converter and to simulate in VHDL. TRUTH TABLE: Input (Binary) b3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Binary_Gray is port( B: in std_logic_vector(3 downto 0); G: out std_logic_vector(3 downto 0)); end binary_gray; architecture behavioral of Binary_gray is begin G(3)<= B(3); G(2)<= B(3) xor B(2); G(1)<= B(2) xor B(1); G(0)<= B(1) xor B(0); end behavioral; outputv g3 g2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 (Gray) g1 g0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 0 0
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SIMULATION RESULTS FOR 4 BIT BINARY TO GRAY CONVERTER
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VHDL CODE TO GRAY TO BINARY AIM: To design a 4 bit gray to binary converter and to simulate in VHDL. TRUTH TABLE: g3 0 0 0 0 0 0 0 0 1 Input (Gray) g2 g1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 g0 0 1 1 0 0 1 1 0 0 Output (Binary) b3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gray_binary is port( G: in std_logic_vector(3 downto 0); B: inout std_logic_vector(3 downto 0)); end gray_binary; architecture behavioral of Binary_gray is begin B(3)<= G(3); B(2)<= B(3) xor G(2); B(1)<= B(2) xor G(1); B(0)<= B(1) xor G(0); end behavioral;
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SIMULATION RESULTS FOR 4 BIT GRAY TO BINARY CONVERTER
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EXPERIMENT- 6 VHDL CODE FOR 1X4 DEMULTIPLEXER AIM: To design a 1x4 demultiplexer and to simulate in VHDL TRUTH TABLE: Input inp ut X X X X s1 0 0 1 1 s0 0 1 0 1 A x 0 0 0 Output B 0 x 0 0 C 0 0 x 0 D 0 0 0 x
RTL SCHEMATEIC DIAGRAM:
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dml is Port ( x : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); a,b,c,d : out STD_LOGIC); end dml; architecture Behavioral of dml is begin process(sel,x) begin case sel is when "00"=>a<=x;b<='0';c<='0';d<='0';
when "01"=>b<=x;a<='0';c<='0';d<='0'; when "10"=>c<=x;a<='0';b<='0';d<='0'; when others=> d<=x;a<='0';b<='0';c<='0'; end case; end process; end Behavioral; SIMULATION RESULTS OF 1X4 DEMULTIPLEXER:
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VHDL CODE FOR 4-BIT COMPARATOR AIM: To design a 4-bit comparator and to simulate in VHDL TRUTH TABLE: a3 1 0 1 a2 1 0 1 a1 1 0 1 a0 1 1 1 b3 0 1 1 b2 1 0 1 b1 0 1 1 b0 0 1 1 Equa l 0 0 1 Great Lessth er an 1 0 0 1 0 0
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator4bit is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); equal : out STD_LOGIC; greaterthan : out STD_LOGIC; lessthan : out STD_LOGIC); end comparator4bit; architecture Behavioral of comparator4bit is begin equal <='1' when a=b else '0'; greaterthan <='1' when a > b else '0'; lessthan <= '1' when a < b else '0'; end Behavioral;
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TECHNOLOGY SCHEMATIC FOR 4-BIT COMPARATOR:
SIMULATION FOR 4-BIT COMPARATOR:
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EXPERIMENT- 7 VHDL CODE FOR HALF ADDER AIM: To design and simulate half adder using VHDL. TRUTH TABLE: Sum 0 1 1 0
B 0 1 0 1
Carry 0 0 0 1
Sum= A(+)B CIRCUIT DIAGRAM:
PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is Port ( a,b : in STD_LOGIC; sum, carry : out STD_LOGIC); end halfadder; architecture Behavioral of halfadder is begin process (a,b)
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begin if a<='0' and b<='0' then sum<='0'; carry<='0'; elsif a<='1' and b<='0' then sum<='1'; carry<='0'; elsif a<='0' and b<='1' then sum<='1'; carry<='0'; else sum<='0'; carry<='1'; end if; end process; end Behavioral; ( or ) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is port (a,b : in bit ; s,c : out bit); end halfadder; architecture arc of halfadder is begin s<= a xor b; c <= a and b; end arc; TIMING WAVEFORM:
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VHDL CODE FOR FULL ADDER AIM: To design and simulate full adder using three modeling techniques using VHDL. TRUTH TABLE FOR FULL ADDER: A 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1
Cin 0 0 0 0 1 1 1 1 BOOLEAN EXPRESSION:
B 0 0 1 1 0 0 1 1
Carry 0 0 0 1 0 1 1 1
Sum = A XOR B XOR Cin ; Carry = (A AND B) OR (Cin AND A) OR (Cin AND B) ; CIRCUIT DIAGRAM FOR FULL ADDER:
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VHDL CODE FOR FULL ADDER USING DATA FLOW MODEL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladd is port ( cin, x, y : in std_logic ; s, cout : out std_logic ) ; end fulladd ; architecture beh of fulladd is begin s <= x xor y xor cin ; cout <= (x and y) or (cin and x) or (cin and y) ; end beh ; VHDL CODE FOR FULL ADDER USING STRUCTURAL MODEL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bejoy_fa is port(In1,In2,c_in : in std_logic; sum, c_out : out std_logic); end bejoy_fa; architecture arc of bejoy_fa is component half_adder port(a,b : in std_logic; sum, carry : out std_logic); end component; component or_2 port(a,b : in std_logic; c : out std_logic); end component;
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signal s1, s2, s3 : std_logic; begin H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3); H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2); O1: or_2 port map(a=> s2, b=>s3, c=>c_out); end arc; entity half_adder is port (a,b : in bit ; sum,carry : out bit); end half_adder; architecture arc of half_adder is begin sum<= a xor b; carry <= a and b; end arc; entity or_2 is port (a,b : in bit ; c : out bit); end or_2; architecture arc of or_2 is begin c<= a or b; end arc VHDL CODE FOR FULL ADDER USING BEHAVIORAL MODEL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladd is port (a,b,c : in std_logic ; s, cout : out std_logic ) ; end fulladd ;
architecture beh of fulladd is begin process(a,b,c) begin if c='0' and b='0' and a='0' then s<= '0' ; cout<= '0'; elsif c='0' and b='0' and a='1' then s<= '1' ; cout<= '0'; elsif c='0' and b='1' and a='0' then s<= '1' ; cout<= '0'; elsif c='0' and b='1' and a='1' then s<= '0' ; cout<= '1'; elsif c='1' and b='0' and a='0' then s<= '1' ; cout<= '0'; elsif c='1' and b='0' and a='1' then s<= '0' ; cout<= '1'; elsif c='1' and b='1' and a='0' then s<= '0' ; cout<= '1'; elsif c='1' and b='1' and a='1' then s<= '1' ; cout<= '1'; end if; end process; end beh; SIMULATION RESULT FOR FULL ADDER:
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EXPERIMENT- 8 VHDL CODE FOR D-FLIP FLOP AIM: To implement negative edge D filp flop using xilinx procedure. THEORY: One way to eliminate the undesirable condition of the indetermined state in the RS-ff is to ensure that inputs S&r are never equal to 1 at the same time.this is done in the D-ff.the D-ff has only two inputs:D and CLK.the input goes directly to the S input and its complement to the R input as long as the CLK input is at 0.the input is sampled when CLK=1.if D is 1,the Q output goes to 1,placing the circuit in the set state.If D is 0,the output Q goes to 0 and the circuit switches to the clear state. The D-ff receives the designation from its ability to hold data into its internal storage.this type of flipflop is sometimes called a gated d-latch.the CLK input is often given the designation gate to indicate that this input enables the gated latch to make possible data entry into circuit.the binary information present at the data input of the D-ff is transferred to the Q output when the CLK input is enabled.the output follows the data input as long as the pulse remains in its 1 state.when the pulse goes to 0 the binary information that was present in the data input at the time the pulse transition occurred its retained at the Q output until the pulse input is enabled again. The truth table shows that the Q(t+1) of the flip flop is independent of the presnt state since Q(t+1) is equals to input D whether Q is equal to 0 or 1. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity negativedff is Port ( clk : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end negativedff; architecture Behavioral of negativedff is
begin process (a) begin if clk'event and clk='0' then c <= b; end if; end process; end Behavioral; CIRCUIT DIAGRAM:
TIMING WAVEFORM:
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AIM: To implement positive edge D filp flop using xilinx procedure. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity negativedff is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end negativedff; architecture Behavioral of negativedff is begin process (a) begin if a'event and a='1' then c <= b; end if; end process; end Behavioral; CIRCUIT DIAGRAM:
TIMING WAVEFORM:
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VHDL CODE FOR JK FLIP FLOP AIM: To design and implement JK filp flop using VHDL. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( clk,reset,j,k : in STD_LOGIC; q : buffer std_logic); end jkff; architecture Behavioral of jkff is begin process (clk, reset) begin if (reset = '1') then q<='0'; elsif (clk'event and clk='1') then if ( j='0' and k='0') then q<=q; elsif (j='0' and k='1') then q<='0'; elsif (j='1' and k='0') then q<='1'; elsif (j='1' and k<='1') then q<= not q; end if; end if; end process; end Behavioral;
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TECHNOLOGY SCHEMATIC DIAGRAM FOR J-K FLIP FLOP:
TIMING WAVEFORM:
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VHDL CODE FOR T-FLIP FLOP AIM: To design and implement T- filp flop using VHDL. PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is port (t: in bit; clk: in std_logic; q: buffer bit); end tff; architecture behavioural of tff is begin process (clk) begin if (clk'event and clk='1') then if ( t='0') then q<=q; elsif (t='1') then q<=(not q); end if; end if; end process; end behavioural; TECHNOLOGY SCHEMATIC DIAGRAM FOR T-FLIP FLOP:
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EXPERIMENT- 9 VHDL CODE FOR DECADE COUNTER AIM: To design a decade counter and to simulate in VHDL. THEORY: A (modulo-10) decade counter is one that counts numbers from 0 to 9.this can be constructed from a modulo-16 counter by resetting the counter at the 10th pulse. It is shown in below table. We see that each binary number is unique and its uniqueness can be used for resetting the counter at the desired level. this is illustrated below consider the Q column of table resetting of the counter at any desired level is done by taking outputs from the flipflop terminals noted in the table, and use them to drive a suitable NAND gate for clearing. Thus for the modulo-10 decade counter we connect output terminals D and B to a NAND gate and connect the output of the NAND gate to the CLR terminals of all the T-FFs TRUTH TABLE: CLK RST(1) 1 2 3 4 5 6 7 8 9 10 PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Q 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
entity decadecounter is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; qout : out STD_LOGIC_VECTOR (3 downto 0)); end decadecounter; architecture Behavioral of decadecounter is signal q:std_logic_vector(3 downto 0); begin process(clk, rst) begin if(rst='1' or cnt="1010")then q<="0000"; else if(clk='1' and clk'event)then if(q=1001)then q<=0000; else q<=q+1; end if; end if; end if; end process; qout<=q; end Behavioral; CIRCUIT DIAGRAM:
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SIMULATION RESULTS FOR DECADE COUNTER:
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EXPERIMENT- 10
STATE MACHINE WITH MEALY OUTPUT

AIM: To implement the state machine with melay output using VHDL. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; entity fsm is port(x,clk:in std_logic; y:out std_logic); end fsm; architecture mealy_case of fsm is type state_type is(reset,got1,got10); signal state:state_type:=reset; begin process(clk) begin if clk='0' then case state is when reset => if x='0' then y<='0';state<=reset; else y<='0';state<=got1; end if; when got1 => if x='0' then y<='0';state<=got10; else y<='0';state<=got1; end if; when got10 => if x='0' then y<='0';state<=reset; else y<='1';state<=got1; end if; end case; end if; end process; end mealy_case;
SIMULATION RESULTS:
RTL Schematic
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STATE MACHINE WITH MOORE OUTPUT:

AIM: To implement the state machine with melay output using VHDL. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; entity fsm is port(x,clk : in std_logic; y : out std_logic); end fsm; architecture moore_case of fsm is type state_type is(reset, got1, got10, got101); signal state:state_type:=reset; begin process(clk) begin if (clk='0') then case state is when reset => if x='0' then state<=reset; else state<=got1; end if; when got1 => if x='0' then state<=got10; else state<=got1; end if; when got10 => if x='0' then state<=reset; else state<=got101; end if; when got101 => if x='0' then state<=got10; else
state<=got1; end if; end case; end if; if state=got101 then y<='1'; else y<='0'; end if; end process; end moore_case;
SIMULATION RESULTS:
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EXPERIMENT-11 VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM: To design a serial in serial out shift register simulate in VHDL. THEORY: Shift registers are used in digital systems for temporary information storage and for data manipulation or transfer there are two ways to shift data into register i.e., serial or parallel, and similarly two ways of shift data out of register. In this type of shift register, data is stored into the register one bit at a time(serial) and taken out serially .they delay data by one clock time for each stage they will store a bit of data for each register. A serial in serial out shift register may be 1 to 64 bits in length, longer if registers or packages are cascaded. TRUTH TABLE: si X 0 1 0 1 VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shiftregister is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; si : in STD_LOGIC; p : out STD_LOGIC_VECTOR (3 downto 0); sout : out STD_LOGIC); end shiftregister; architecture siso of shiftregister is signal q:std_logic_vector(3 downto 0); clk rst 1 2 3 4 q 0000 0000 1000 0100 1010 sout X 0 0 0 0
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begin process(rst,clk) begin if(rst='1')then q<="0000"; else if(clk'event and clk='1') then q(3)<=si; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); sout<=q(0); end if; end if; end process; p<=q; end siso; TECHNOLOGY SCHEMATIC:
SIMULATION RESULTS:
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VHDL CODE FOR SERIAL IN PARALLEL OUT SHIFT REGISTER AIM: To design a serial in parallel out shift register and to simulate in VHDL and verify experimentally in digital IC Lab. THEORY: shift registers are used in digital systems for temporary information storage and for data manipulation or transfer there are two ways to shift data into register i.e., serial or parallel, and similarly two ways of shift data out of register. In this type of shift register, data is stored into the register one bit at a time(serial) and taken out in parallel it makes all the internal stages available as outputs. If four bits are shifted in by four clock pulses via a single wire ,the data becomes available simultaneously on four outputs. TRUTH TABLE: si X 0 1 0 1 VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shiftregister is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; si : in STD_LOGIC; pout : out STD_LOGIC_VECTOR (3 downto 0); end shiftregister; architecture siso of shiftregister is signal q:std_logic_vector(3 downto 0); begin process(rst,clk) begin
clk rst 1 2 3 4
pout 0000 0000 1000 0100 1010
if(rst='1')then q<="0000"; else if(clk'event and clk='1') then q(3)<=si; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); end if; end if; end process; pout<=q; end siso;
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SIMULATION RESULTS:
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VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM: To design a serial in serial out shift register and to simulate in VHDL. VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity piso is generic(x : integer := 8); port( din: in std_logic_vector(x-1 downto 0); clk,ld,r,dir_r,se: in std_logic; so: out std_logic ); end piso; architecture rtl of piso is signal pre_q : std_logic_vector((x-1) downto 0) := (others => 'x'); begin shift_register_process: process(clk,r) begin if (r = '1') then pre_q <= (others => '0'); elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then if (ld = '1') then pre_q <= din; elsif (se = '1') and (dir_r = '1') then pre_q(x-1) <= '0'; pre_q((x-2) downto 0) <= pre_q((x-1) downto 1); elsif (se = '1') and (dir_r = '0') then pre_q((x-1) downto 1) <= pre_q((x-2) downto 0); pre_q(0) <= '0'; end if; end if; end process shift_register_process; so <= pre_q(0) when dir_r = '1' else pre_q(x-1) when dir_r = '0' else 'x';
end rtl;
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SIMULATION RESULTS:
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VHDL CODE FOR SERIAL/PARALLEL IN SERIAL/PARALLEL OUT SHIFT REGISTER
AIM: To design a serial/parallel simulate in VHDL. VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity spispo is generic(x : integer := 8);
in serial/parallel out shift register and to
port( din: in std_logic_vector((x-1) downto 0); dout: out std_logic_vector((x-1) downto 0); clk,ld,r,dir_r,se,si: in std_logic; so: out std_logic ); end spispo; architecture rtl of spispo is signal pre_q : std_ulogic_vector((x-1) downto 0) := (others => 'x'); begin shift_register_process: process(clk,r) begin if (r = '1') then pre_q <= (others => '0'); elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then if (ld = '1') then pre_q <= din; elsif (se = '1') and (dir_r = '1') then pre_q((x-1)) <= si; pre_q((x-2) downto 0) <= pre_q((x-1) downto 1); elsif (se = '1') and (dir_r = '0') then pre_q((x-1) downto 1) <= pre_q((x-2) downto 0); pre_q(0) <= si; end if; end if; end process shift_register_process; dout <= pre_q;
so <= pre_q(0) when dir_r = '1' else pre_q((x-1)) when dir_r = '0' else 'x'; end rtl;
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SIMULATION RESULTS:
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EXPERIMENT-12 ALU AIM: To design a ALU performing operations. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity ALU is port ( A: B: Sel: end ALU; architecture behv of ALU is begin process(A,B,Sel) begin case Sel is when "00" => Res <= A + B; when "01" => Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end process; end behv; TECHNOLOGY SCHEMATIC:
in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0);
Res: out std_logic_vector(1 downto 0) );
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SIMULATION RESULTS:
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CMOS Layers

n-well process p-well process Twin-tub process
n-well process
MOSFET Layers in an n-well process
Layer Types

p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide

Insulated glass Provide electrical isolation
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Top view of the FET pattern
Metal Interconnect Layers

Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias
Metal Interconnect Layers
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Interconnect Layout Example
Designing MOS Arrays
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Parallel Connected MOS Patterning
Basic Gate Design
Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well Contacts are needed from Metal to n+ or p+
The CMOS NOT Gate
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Alternate Layout of NOT Gate
NAND2 Layout
NOR2 Layout
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NAND2-NOR2 Comparison
General Layout Geometry
Graph Theory: Euler Path
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Stick Diagrams

Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout
compaction, power/ground routing, etc. Stick Diagrams
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Stick Diagram - Example I
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Stick Diagram - Example II
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Design Rules
Description of digital IC
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Process design rules
Lambda rules
Feature Size: minimum distance between source and transistor Feature size = 2 (@ 90nm feature size =45)
drain of
According to Moores Law, how much does the feature scale by every ~2 years?
size
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Design rules and gate layout
CMOS Process Layers
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Intra-Layer Design Rules
Transistor Layout
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Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4
2 2
Select Layer
2 3 2 1 3 3 Select
Substrate
Well
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CMOS Inverter Layout

GND In VDD
Out (a) Layout
A p-substrate n
+
A n p
+
Field Oxide
(b) Cross-Section along A-A
A CMOS Inverter
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A CMOS NAND Gate
A CMOS NOR Gate
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DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LABORATORY MANUAL FOR

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BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE

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LIST OF EXPERIMENTS: ECAD Programs:

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Latch Pass transistor

FT256 XST (VHDL/Verilog)

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Simulator Click Next

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A 0 0 1 1 BOOLEAN EXPRESSION: C=AB RTL SCHEMATIC:

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BOOLEAN EXPRESSION: C=A+B RTL SCHEMATIC:

VHDL CODE: library IEEE;

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BOOLEAN EXPRESSION: C=A+b= (AB) RTL SCHEMATIC:

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C= (A+B)=AB RTL SCHEMATIC:

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C=AB+AB RTL SCHEMATIC:

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C=AB+AB CIRCUIT DIAGRAM:

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BOOLEAN EXPRESSION: B=A RTL SCHEMATIC:

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e 0 1 1 1 1 PROGRAM CODE: library IEEE;

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SIMULATION RESULTS FOR 2x4 DECODER:

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