AG1(Alviso) Block Diagram 2005/11/01

CLK GEN.

Mobile CPU

IDT CV125

Dothan

Project Code:91.4G301.001
PCB:05223-01

G792
19

RGB

400MHz

CRT
CONN

400MHz

400 MHz

CPU DC/DC
ISL6218CV-T
14

34
INPUTS

LCD

Intel 910GML

11,12

LVDS

OUTPUTS
VCC_CORE

XGA
DCBATOUT

13

DDR II

4, 5

HOST BUS

DDR II

0.844~1.3V
27A

400MHz

400 MHz

6,7,8,9,10
11,12

SYSTEM DC/DC
DMI I/F

TPS51120 35

100MHz

Line In27

Codec

ACLINK

PCI BUS

ALC655

Int.
MIC In

INPUTS

ENE
CB1410

DCBATOUT

PWR SW
25

24,25

Line Out
27

LAN

G1421B 27

1D5V_S0

3D3V_S0

2D5V_S0

SYSTEM DC/DC
ISL6227

28

INPUTS

10/100
RTL8110CL

TXFM

RJ4523

23

22, 23

INT.SPKR

5V_S5

Mini-PCI
802.11A/B/G

37

OUTPUTS
5V_S5

DCBATOUT
3D3V_S3
2

MODEM
MDC Card

27

3D3V_S5
5V_S5

APL5912-LAC
APL5308-25AC
36
INPUTS
OUTPUTS

ONE SLOT
25

ICH6-M

OP AMP

PCMCIA

CP2211

26
27

OUTPUTS

TPS51100DGQ

37

DDR_VREF
5V_S5

21

DDR_VREF_S3

LPC BUS

CHARGER
ISL6255

PATA

15,16,17,18

PCB Layer Stackup

L1: Signal 1
L2:VCC
L3: Signal 2
L4: Signal 3
L5: GND
L6: Signal 4

KBC

CD ROM

20

BIOS ROM

INPUTS

4M BITS

29

OUTPUTS

31

DCBATOUT

4 PORT

BT+
16.8V

3A

21

20

<Core Design>
1

21

Touch
Pad 30

MINI USB
Blue-tooth

INT_KB

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

30
Title

BLOCK DIAGRAM
Size
Document Number
Custom

Rev

01

AG1(Alviso)

Date: Tuesday, November 01, 2005

A

38

PM39LV040-70JCE

ENE KB3910

USB
HDD

Xbus

Sheet
E

of

40

Alviso Strapping Signals

and Configuration
Pin Name

ICH6-M Integrated Pull-up

and Pull-down Resistors ICH6-M

page 7

EDS 14308

0.8V1

Configuration

Strap Description

ACZ_BIT_CLK, DPRSLP#, EE_DIN,

CFG[2:0]

FSB Frequency Select

CFG[3:4]

Reversed

CFG5

DMI x2 Select

CFG6

DDR I / DDR II

CFG7

CPU Strap

CFG[8:11]

Reversed

CFG[12:13]

XOR/ALL Z test
straps

CFG[14:15]

Reversed

CFG16

FSB Dynamic ODT

000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed

=
=
=
=

DMI
DMI
DDR
DDR

x2
x4 (Default)
II
I

00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)

ICH6 internal 10K pull-ups

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,

ICH6 internal 20K pull-downs

SPKR, EE_CS,

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled
(Default)

CPU core VCC

Select

0 = 1.05V (Default)
1 = 1.5V

CFG19

CPU VTT Select

0 = 1.05V (Default)
1 = 1.2V

SDVO Present

LAN_RXD[2:0]

ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,

Reversed

Reversed

PME#, PWRBTN#, TP[3]

0 = Prescott
1 = Dothan (Default)

CFG18

CFG20

ICH6 internal 20K pull-ups

LAD[3:0]#/FB[3:0]#, LDRQ[0],

0
1
0
1

CFG17

SDVOCRTL
_DATA

EE_DOUT, GNT[5]#/GPO[17],
GNT[6]#/GPO[16], LDRQ[1]/GPI[41],

USB[7:0][P,N]

ICH6 internal 15K pull-downs

DD[7], SDDREQ

ICH6 internal 11.5K pull-downs

LAN_CLK

ICH6 internal 100K pull-downs

ICH6-M IDE Integrated Series

Termination Resistors

PCI Routing

DD[15:0], DIOW#, DIOR#, DREQ,

0 = No SDVO device present
(Default)
1= SDVO device present

NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.

IDSEL

IRQ

REQ/GNT

1410

25

B.F.G

MiniPCI

21

LAN

23

approximately 33 ohm
DDACK#,

IORDY, DA[2:0], DCS1#,

DCS3#, IDEIRQ

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Memo
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Tuesday, November 01, 2005

Sheet

of

40

IN
(3D3V_S0)
H
X

SCD1U16V2ZY-2GP

C105

1
2

SCD1U16V2ZY-2GP

C122
SCD1U16V2ZY-2GP

C109

C108

C104

3D3V_CLKGEN_S0

1 R110
2
0R0603-PAD
C103
SCD1U16V2ZY-2GP

3D3V_48MPWR_S0

SC4D7U6D3V3KX-GP

1
2

EN
(6218_PGOOD)
L

C295
SCD1U16V2ZY-2GP

1
2

SC4D7U10V5ZY-3GP

C124

3D3V_S0

1 R105
2
2R3J-2-GP

SC10U10V5ZY-1GP

3D3V_S0

1 R122
2 3D3V_APWR_S0
0R0603-PAD

3D3V_S0

OUT
(VTT_PWRGD#)
H

Hi - Z
AG1-910-01

3D3V_CLKGEN_S0

R251 1

28 PCLK_MINI

U28

2 33R2J-2-GP
PCLK_MINI_1
PCLK_LAN_1
PCLK_PCM_1
PCLK_KBC_1

22
24
29
16

AG1-A-SA
AG1-910-01
2

R369
1KR2J-1-GP

R98
1KR2J-1-GP

8
7
6
5

PCLK_LAN
PCLK_PCM
PCLK_KBC
CLK_ICHPCI

1
2
3
4

H/L: 100/96MHz

SS_SEL

RN7
SRN33J-4-GP

FS_A

56
3
4
5
9
8

ITP_EN

H/L : CPU_ITP/SRC7

16 PM_STPPCI#

CPU_SEL1 7
CPU_SEL0 4,7

11,18 SMBC_ICH
11,18 SMBD_ICH

R102
1KR2J-1-GP

AG1-910-SB

AG1-910-01

3
4

7 DREFCLK
7 DREFCLK#

SC22P50V2JN-4GP

RN63 SRN33J-5-GP-U
DREFCLK_1
2
DREFCLK#_1
1

C116
1
2

XTAL_IN
XTAL_OUT

26
16

CLK_Audio
CLK_ICH14

X1
X-14D31818M-31GP

R252

1
1

FS_C

FS_B

FS_A

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CPU

3
4
RN13

2
1
SRN33J-5-GP-U
2
475R2F-L1-GP

VTT_PWRGD#

C120
SC27P50V2JN-2-GP

266M
133M
200M
166M
333M
100M
400M
Reserved

SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#

19
20
22
23
24
25
26
27
31
30
33
32

CPU2_ITP/SRC7
CPU2_ITP#/SRC7#

36
35

CPU0
CPU0#
CPU1
CPU1#

44
43
41
40

CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA

54
53
16
12

PCIF1/SEL100/96#
PCIF0/ITP_EN
PCI_STOP#

46
47

SCL
SDA

14
15

DOT96
DOT96#

50
49

XTAL_IN
XTAL_OUT

52
39

REF
IREF

10

VTT_PWRGD#/PD

CLK_ICH14 & CLK14_SIO

need equal length

LVDS
LVDS#

PCI0
PCI1
PCI2
PCI3

55

2nd

17
18

DREFSSCLK1
DREFSSCLK#1

2
1

3
4

DREFSSCLK 7
DREFSSCLK# 7

RN62
SRN33J-5-GP-U

RN10
CLK_PCIE_ICH1
CLK_PCIE_ICH#1
CLK_MCH_3GPLL1
CLK_MCH_3GPLL#1

4 SRN33J-5-GP-U
3

1
2

RN18 1
2

CLK_CPU_BCLK1
CLK_CPU_BCLK#1
CLK_MCH_BCLK1
CLK_MCH_BCLK#1
CPU_SEL0
CPU_SEL1
FS_A
R103

4
3

CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

SRN47J-7-GP

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

RN12

1
2

4 SRN33J-5-GP-U
3

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

RN11

1
2

4 SRN33J-5-GP-U
3

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16,34

1
22R2J-2-GP

CLK48_ICH 16

AG1-910-01
2
6

VSS_PCI
VSS_PCI

VDD_SRC
VDD_SRC

34
21

51
45
38
13
29

VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC

VDD_PCI
VDD_PCI

7
1

VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC

48
42
37
11
28

AG1-910-01

3D3V_S0

3D3V_CLKGEN_S0

3D3V_APWR_S0
3D3V_48MPWR_S0

8
7
6
5

IDTCV125PAG-GP

AG1-A-SA

1
2
3
4

RN64
SRN10KJ-4-GP

RN20 1
2

4 SRN49D9F-GP
3

CLK_MCH_BCLK
CLK_MCH_BCLK#

RN19 1
2

4 SRN49D9F-GP
3

RN14 1
2

4 SRN49D9F-GP
3

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

AG1-A-SA

ITP_EN
SS_SEL

2
S

2N7002PT-U

R106
10KR2J-2-GP

DY

CLK_PCIE_ICH
CLK_PCIE_ICH#

RN9

R104
10KR2J-2-GP

1
2

EMI capacitor

4 SRN49D9F-GP
3

CLK_ICH14

EC45 1

PCLK_PCM

EC41 1

PCLK_MINI

EC70 1

PCLK_KBC

EC42 1

CLK_ICHPCI

EC43 1

CLK48_ICH

EC39 1

2 SC10P50V2JN-4GP
DY
2 SC10P50V2JN-4GP
DY
2 SC10P50V2JN-4GP
DY
2 SC10P50V2JN-4GP
DY
2 SC10P50V2JN-4GP
DY
2 SC10P50V2JN-4GP
DY

DY
Q23

VTT_PWRGD#

32,34 6218_PGOOD

CLK_CPU_BCLK
CLK_CPU_BCLK#

<Core Design>

AG1-910-01
DREFSSCLK#
DREFSSCLK

RN60

DREFCLK#
DREFCLK
RN61

2
1

3
4

2
1

3
4

Wistron Corporation

SRN49D9F-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Clock Generator - IDT125

SRN49D9F-GP
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Friday, October 28, 2005

Sheet

of

40

ADDR GROUP 0

AG1-A-SA

C2
D3
A3

A20M#
FERR#
IGNNE#

15
15
15
15

C6
D1
D4
B4

STPCLK#
LINT0
LINT1
SMI#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

BR0#

N4

H_BREQ#0 6

IERR#
INIT#

A4
B5

LOCK#

J2

AG1-910-01

R261
56R2J-4-GP

62.10053.061
CONNECTOR

H_INIT# 15

B11
H1
K1
L2
M3

H_LOCK# 6
H_CPURST# 6
H_RS#[2..0] 6

H_RS#0
H_RS#1
H_RS#2

U41B
TUALA-SKT-1
H_TRDY# 6

K3
K4

HIT#
HITM#

Place testpoint on
H_IERR# with a GND
0.1" away

H_IERR#

H_HIT# 6
H_HITM# 6

BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28

TP78
TP87
TP86
TP77
TP85
TP76
TP81
TP82
TP83
TP84
TP91
TP88

PROCHOT#
THERMDA
THERMDC

B17
B18
A18

CPU_PROCHOT#

THERMTRIP#

C17

PM_THRMTRIP-I# 7,15,19

ITP_CLK1
ITP_CLK0
BCLK1
BCLK0

A15
A16
B14
B15

CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3

TPAD28 TP89
H_THERMDA 19
H_THERMDC 19

AG1-A-SA

PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)

AG1_A-SA : 62.10079.001

1D05V_S0

TP90

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#

Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#16
H23
H_D#17
G25
H_D#18
L23
H_D#19
M26
H_D#20
H24
H_D#21
F25
H_D#22
G24
H_D#23
J23
H_D#24
M23
H_D#25
J25
H_D#26
L26
H_D#27
N24
H_D#28
M25
H_D#29
H26
H_D#30
N25
H_D#31
K25
H_DSTBN#1 K24
H_DSTBP#1 L24
H_DINV#1 J26

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#

AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

To V-CORE SWITCH TP92

R264
TPAD28
1
2 0R3-0-U-GP

DY

3,7 CPU_SEL0
TPAD28

E1
C16
C14

AG1-910-01
XDP_TDI

2 150R2F-1-GP

R256 1
R259 1

2 39D2R3F-GP

XDP_TDO

R257 1

2 54D9R2F-L1-GP

H_CPURST#

R258 1

2 54D9R2F-L1-GP

R282
2KR3F-L-GP

TP80
TP94
TP93
TP49

C3
AF7
AC1
E26

TPAD28
TPAD28
TPAD28
TPAD28
GTLREF0

3D3V_S0

XDP_DBRESET# R263 1

2 150R2F-1-GP

XDP_TCK

R255 1

2 27D4R2F-L1-GP

XDP_TRST#

R260 1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#

G1
B7
C19
E4
A6

TEST1
TEST2

C5
F23

PSI#
BSEL0
BSEL1

AD26

RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0

Layout Note:
0.5" max length.

COMP0
COMP1
COMP2
COMP3

R281
R279
R287
R284

H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

AG1-910-01
2

1D05V_S0

1
1
1
1

2
2
2
2

27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP

H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6

R154
200R2F-L-GP

AG1-910-01
H_PW RGD 15,19

H_CPUSLP# 6,15
TEST1
TEST2

TPAD28 TP79
TPAD28 TP51

AG1-A-SA
62.10053.061
CONNECTOR
Y

XDP_TMS

R283
1KR2F-3-GP

1 2

2 56R2F-1-GP

COMP0
COMP1
COMP2
COMP3

P25
P26
AB2
AB1

MISC

1D05V_S0

CPU_PROCHOT# R262 1

H_D#[63..0] 6

H_D#0
A19
H_D#1
A25
H_D#2
A22
H_D#3
B21
H_D#4
A24
H_D#5
B26
H_D#6
A21
H_D#7
B20
H_D#8
C20
H_D#9
B24
H_D#10
D24
H_D#11
E24
H_D#12
C26
H_D#13
B23
H_D#14
E23
H_D#15
C25
H_DSTBN#0 C23
H_DSTBP#0 C22
H_DINV#0 D25

6 H_ADSTB#1
15 H_A20M#
15 H_FERR#
15 H_IGNNE#

L4
H2
M2

RESET#
RS0#
RS1#
RS2#
TRDY#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1

DEFER#
DRDY#
DBSY#

H_ADS# 6
H_BNR# 6
H_BPRI# 6

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5

1D05V_S0

N2
L1
J3

DATA GRP 0
DATA GRP 2

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R2
P3
T2
P1
T1

TPAD28

ADS#
BNR#
BPRI#

DATA GRP 1
DATA GRP 3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0

CONTROL

6 H_ADSTB#0
6 H_REQ#[4..0]

P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3

ADDR GROUP 1
XTP/ITP SIGNALS

6 H_A#[31..3]

HCLK THERM

TP53

U41A
TUALA-SKT-1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

BSEL[1:0] Freq.(MHz)
(A Stepping)
LL
100
LH
133
BSEL[1:0] Freq.(MHz)
(B Stepping)
LH
100
LL
133

680R3F-GP

<Core Design>

Wistron Corporation

All place within 2" to CPU

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

AG1-910-01
Title

CPU (1 of 2)
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Monday, October 31, 2005

A

Sheet
E

01
4

of

40

VCC_CORE_S0

U41D
A2
A5
A8
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11

VCC_CORE_S0
U41C
TUALA-SKT-1

F26
B1
N1
AC26

VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21

VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5

C311
SCD01U16V2KX-3GP

C161
SC10U10V5ZY-1GP

1D05V_S0

P23
W4
E2
F2
F3
G3
G4
H4

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

34
34
34
34
34
34

TC8

DY

ST100U6D3VBM-9GP

1
2

C164
SCD1U16V2ZY-2GP

1
2

C180
SCD1U16V2ZY-2GP

C177
SCD1U16V2ZY-2GP

62.10053.061
CONNECTOR
Y

TPAD28 TP59

TP_VSSSENSE

C163
SCD1U16V2ZY-2GP

AF6

VSSSENSE

TPAD28 TP58

TP_VCCSENSE

AE7

C187
SCD1U16V2ZY-2GP

1D05V_S0

VCCSENSE

AG1-A-SA
2

VCCA0
VCCA1
VCCA2
VCCA3

1D5V_S0

G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6

VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

C178
SCD1U16V2ZY-2GP

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58

AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21

Layout Note:

C194
SC10U6D3V5KX-1GP

1
2

C196
SC10U6D3V5KX-1GP

C169
SC10U6D3V5KX-1GP

C168
SC10U6D3V5KX-1GP

AG1-A-SA

C203
SC10U6D3V5KX-1GP

1
2

1
2

1
2

C201
SC10U6D3V5KX-1GP

DY

C200
SC10U6D3V5KX-1GP

C211
SCD1U16V2ZY-2GP

DY

1
2

1
2

DY

C213
SCD1U16V2ZY-2GP

DY

C209
SCD1U16V2ZY-2GP

1
2

DY

C166
SCD1U16V2ZY-2GP

VCC_CORE_S0

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

VCC_CORE_S0

C167
SCD1U16V2ZY-2GP

VCCSENSE and VSSSENSE lines

should be of equal length.

AG1-910-SB
1

C202
SC10U6D3V5KX-1GP

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

CONNECTOR
62.10053.061

Y
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (2 of 2)
Document Number

Rev

AG1(Alviso)

Date: Monday, October 17, 2005

B

Wistron Corporation

Size
A3
A

D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24

VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

<Core Design>

VCC_CORE_S0

TUALA-SKT-1

Sheet
E

01
5

of

40

H_XRCOMP

R290
24D9R2F-L-GP

U38A
4 H_D#[63..0]

H_XSWING

R289
100R2F-L1-GP-U

C331
SCD1U16V2ZY-2GP

AG1-910-01

H_YRCOMP

R292
24D9R2F-L-GP

AG1-910-01

1D05V_S0

AG1-910-01

54D9R2F-L1-GP
R295

H_YSCOMP
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

1D05V_S0

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

HCLKINN
HCLKINP

AB1
AB2

HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5

R172
100R2F-L1-GP-U
3

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4

H_VREF

H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4

CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#

R175
200R2F-L-GP

AG1-910-01

H_DBSY# 4
H_DEFER# 4

H_DINV#[3..0] 4

H_DPWR# 4
H_DRDY# 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

TPAD28 TP57
H_HIT# 4
H_HITM# 4
H_LOCK# 4

TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2

H_REQ#[4..0] 4

TPAD28 TP55

H_RS#[2..0] 4

H_CPUSLP# 4,15
H_TRDY# 4

H_YSWING

R294
221R2F-2-GP

C1
C2
D1
T1
L1
P1

HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCPURST#

F8
B9
E13
J11
A5
D5
E7
H10

1D05V_S0

R288
221R2F-2-GP

1D05V_S0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_XSCOMP

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

AG1-910-01

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

54D9R2F-L1-GP
R291

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

1D05V_S0

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

C186
SCD1U16V2ZY-2GP

H_A#[31..3] 4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

HOST

AG1-910-01

71.0GMCH.08U
C335
SCD1U16V2ZY-2GP

AG1-910-01

R293
100R2F-L1-GP-U

<Core Design>

Place them near to the chip

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (1 of 5)
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Tuesday, October 25, 2005

A

Sheet
E

01
6

of

40

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

Y33
AA37
AB33
AC37

DMITXP0
DMITXP1
DMITXP2
DMITXP3

AM33
AL1
AE11
AJ34
AF6
AC10

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

AN33
AK1
AE10
AJ33
AF5
AD10

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

11 M_CLK_DDR0
11 M_CLK_DDR1
11 M_CLK_DDR3
11 M_CLK_DDR4
11 M_CLK_DDR#0
11 M_CLK_DDR#1
11 M_CLK_DDR#3
11 M_CLK_DDR#4
3

R168
40D2R2F-GP

40D2R2F-GP

R155

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

11,12
11,12
11,12
11,12

M_CS#0
M_CS#1
M_CS#2
M_CS#3

AN16
AM14
AH15
AG16

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

AF22
AF16

SM_OCDCOMP0
SM_OCDCOMP1

AP14
AL15
AM11
AN10

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

11,12
11,12
11,12
11,12

M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP

DDR_VREF_S3

1
C304

1
BC4

1
C219

1
BC2

SMXSLEW
SMYSLEW

DDR

PM

MUXING

AP21
AM21
AH21
AK21

M_OCDCOMP0
M_OCDCOMP1

CFG6

BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#

DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

R366
TP50
TP48

SCD1U16V2ZY-2GP

SC2D2U6D3V3MX-1-GP

SCD1U16V2ZY-2GP

SC2D2U6D3V3MX-1-GP

2D5V_S0

SDVOC_CTRLDATAH24
SDVOC_CTRLCLK H25
AB29
AC29

AG1-910-01

AG1-910-01

J23
J21 PM_EXTTS#0
H22 PM_EXTTS#1
F5
AD30
AE29
1
2
R152 100R2J-2-GP
A24
A23
C37
D37

150R2F-1-GP

14 GMCH_DDCCLK
14 GMCH_DDCDATA
14 GMCH_BLUE
R158
1
2

150R2F-1-GP

14 GMCH_GREEN
1 R157
2

150R2F-1-GP

14 GMCH_RED
1 R162
2
1
R159 1
R156 1

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

A15
C16
A17
J18
B15
B16
B17

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

R161
261R2F-GP

AG1-910-01
R254

PM_BMBUSY# 16

HSYNC
CRTIREF
VSYNC

2
2 39R2J-L-GP
2 39R2J-L-GP

14 GMCH_VSYNC
14 GMCH_HSYNC

LBKLT_CRTL

AG1-910-SB

E25
F25
LCTLA_CLK
C23
LCTLB_DATA
C22
CLK_DDC_EDID F23
DAT_DDC_EDID F22
F26
LIBG
C33
L_LVBG C31
L_VREFH F28
L_VREFL F27

29 BL_ON
PM_THRMTRIP-I# 4,15,19
VGATE_PWRGD 16,32
PLT_RST1# 16,18,29

13 CLK_DDC_EDID
13 DAT_DDC_EDID
13 GMCH_LCDVDD_ON

DREFCLK# 3 AG1-910-01
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3

TP42
TP44
TP46

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

AG1-A-SA
2
1

TPAD28
TPAD28

3 CLK_MCH_3GPLL#
3 CLK_MCH_3GPLL

71.0GMCH.08U

U38G

2K2R2J-2-GP

DY

M_CKE0
M_CKE1
M_CKE2
M_CKE3

3
3,4

R165

10KR2J-2-GP
VGATE_PWRGD 2
1

11,12
11,12
11,12
11,12

Layout Note:
Route as short
as possible

CPU_SEL1
CPU_SEL0

1D5V_PCIE_S0
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die

MISC

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AA33
AB37
AC33
AD37

CFG0

TV

16
16
16
16

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

VGA

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

Y31
AA35
AB31
AC35

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

PCI-EXPRESS GRAPHICS

16
16
16
16

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

CFG/RSVD

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMI

16
16
16
16

AA31
AB35
AC31
AD35

CLK

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

NC

16
16
16
16

CFG[2:0] Freq.(MHz)
101
400
001
533

R166
10KR2J-3-GP

U38B

SRN10KJ-5-GP
PM_EXTTS#0
3
PM_EXTTS#1
4

TPAD28
TPAD28
TPAD28

LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

13 GMCH_TXACLK13 GMCH_TXACLK+
13 GMCH_TXBCLK13 GMCH_TXBCLK+

B30
B29
C25
C24

LACLKN
LACLKP
LBCLKN
LBCLKP

13 GMCH_TXAOUT013 GMCH_TXAOUT113 GMCH_TXAOUT2-

B34
B33
B32

LADATAN0
LADATAN1
LADATAN2

13 GMCH_TXAOUT0+
13 GMCH_TXAOUT1+
13 GMCH_TXAOUT2+

A34
A33
B31

LADATAP0
LADATAP1
LADATAP2

13 GMCH_TXBOUT013 GMCH_TXBOUT113 GMCH_TXBOUT2-

C29
D28
C27

LBDATAN0
LBDATAN1
LBDATAN2

13 GMCH_TXBOUT0+
13 GMCH_TXBOUT1+
13 GMCH_TXBOUT2+

C28
D27
C26

LBDATAP0
LBDATAP1
LBDATAP2

LVDS

1D05V_S0

AG1-910-01

EXP_COMPI
EXP_ICOMPO

D36
D34

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

24D9R2F-L-GP

AG1-910-01

RN24
71.0GMCH.08U

1D8V_S3

AG1-A-SA

R171
80D6R2F-L-GP

DY

2D5V_S0

RN21
LCTLA_CLK
LCTLB_DATA

M_RCOMPN

1
2

4
3

SRN2K2J-1-GP
RN23

M_RCOMPP

CLK_DDC_EDID 1
DAT_DDC_EDID 2

R173
80D6R2F-L-GP

4
3

SRN2K2J-1-GP
BL_ON
LBKLT_CRTL

4 RN22
3

1
2
SRN100KJ-6-GP

LIBG

1 R271

<Core Design>

1K5R2F-2-GP

AG1-910-01

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (2 of 5)
Size
Document Number
Custom

R ev

AG1(Alviso)

Date: Tuesday, October 25, 2005

A

Sheet
E

01
7

of

40

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

U38D

SA_BS0#
SA_BS1#
SA_BS2#

AK15
AK16
AL21

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

AN15
AP16
AF29
AF28
AP15

SA_RCVENIN#
SA_RCVENOUT#

DDR SYSTEM MEMORY A

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

11 M_B_DQ[63..0]
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_A[13..0] 11,12

TP43
TP47

M_A_CAS# 11,12
M_A_RAS# 11,12
TPAD28
TPAD28
M_A_WE# 11,12

Place Test PAD Near to Chip

as could as possible

71.0GMCH.08U

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

SB_BS0#
SB_BS1#
SB_BS2#

AJ15
AG17
AG21

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

AH14
AK14
AF15
AF14
AH16

SB_RCVENIN#
SB_RCVENOUT#

DDR SYSTEM MEMORY B

U38C
11 M_A_DQ[63..0]

M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11
3

M_B_A[13..0] 11,12

TP52
TP54

M_B_CAS# 11,12
M_B_RAS# 11,12
TPAD28
TPAD28
M_B_WE# 11,12

Place Test PAD Near to Chip

ascould as possible

71.0GMCH.08U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GMCH (3 of 5)
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Monday, October 17, 2005

A

Sheet
E

01
8

of

40

0R0805-PAD

0R0805-PAD

C136
SC10U10V5ZY-1GP

C226
SC10U10V5ZY-1GP

C225
SC10U10V5ZY-1GP

2
1D5V_DPLLA_S0

L3
1D5V_DPLLB_S0

1D5V_HPLL_S0

C334
SCD1U16V2ZY-2GP

C318
SC4D7U6D3V3KX-GP

C150
SCD1U16V2ZY-2GP

1
R163 2

0R0402-PAD

R276

DY

DY

0R3-0-U-GP

C319
SCD1U16V2ZY-2GP

C135
SCD1U16V2ZY-2GP

L13

Layout Notes: VSSA_CRTDAC

Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.

2
2D5V_S0

1D05V_S0

2D5V_CRTDAC_S0

1 R277
2
0R0603-PAD
C324
SCD47U10V3ZY-GP

C314
SCD1U16V2ZY-2GP

1
R278

1KR2J-1-GP

DY

2
D27

1
1D05V_S0

SSM5818SLPT-GP

Size
A3

AG1-910-SB

C185
SC4D7U10V5ZY-3GP
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
<Core Design>
connect to the gnd plane.

C333
SCD1U16V2ZY-2GP
C325

1D05V_S0

DY

L12
1D5V_MPLL_S0

Date: Monday, October 17, 2005

SC2D2U6D3V3MX-1-GP

VCCP_GMCH_CAP4

C328

F37
G37

2D5V_TXLVDS_S0

VCCA_3GBG
VSSA_3GBG

C330
SCD1U16V2ZY-2GP

VCCP_GMCH_CAP2
VCCP_GMCH_CAP3

Y29
Y28
Y27
1

SCD22U16V3ZY-GP
2
1

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

C216
SCD1U16V2ZY-2GP

1
VCCP_GMCH_CAP1

0R0603-PAD

AG1-910-SB

1D05V_S0

C151
SCD1U16V2ZY-2GP

AE37
W37
U37
R37
N37
L37
J37

C323
2
1

AF20
AP19
AF19
AF18

B28
A28
A27

Note: All VCCSM

pins shorted
internally

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

Note: All VCCSM

pins shorted
internally
SCD1U16V2ZY-2GP
C131

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

SCD1U16V2ZY-2GP
C133

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

2D5V_S0
2D5V_TXLVDS_S0

1D8V_S3

SCD1U16V2ZY-2GP

Sheet
E

SCD1U16V2ZY-2GP

L5

R273

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

0R0603-PAD

1D5V_HMPLL_S0

VCC_SYNC

K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

2
C310
SC10U10V5ZY-1GP

C184

0R0805-PAD

2D5V_S0

H20

2D5V_ALVDS_S0

R178

GMCH_VCC_SYNC

0R0603-PAD

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

R275

F19
E19
G19

2D5V_S0

C210

1
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

2D5V_ALVDS_S0

C313
SCD1U16V2ZY-2GP

V1.8_DDR_CAP1 1
AM37
2
V1.8_DDR_CAP2 1
AH37
2
AP29 V1.8_DDR_CAP5
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
2
1
AH26
AG26
AF26
AE26
SC10U10V5ZY-1GP
AP25
AN25
AM25
2
1
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
2
1
AE21
C316
AE20
SC10U10V5ZY-1GP
AE19
AE18
AE17
AE16
2
1
AE15
C317
AE14
SC10U10V5ZY-1GP
AP13
AN13
AM13
AL13
2
1
AK13
C321
AJ13
SC10U10V5ZY-1GP
AH13
AG13
AF13
AE13
AP12
AN12
2
1
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8 V1.8_DDR_CAP6
V1.8_DDR_CAP4
AM1
2
1
V1.8_DDR_CAP3 2
AE1
1

B22
B21
A21

A35

B26
B25
A25

AC2
AC1
B23
C35
AA1
AA2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

VCCHV0
VCCHV1
VCCHV2

VCCA_LVDS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

D19
H17

H18
G18

F17
E17
D18
C18
F18
E18

0R0603-PAD

VCCD_TVDAC
VCCDQ_TVDAC

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

2
C162
SCD1U16V2ZY-2GP

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

2D5V_TVDAC_S0

C144
SCD1U16V2ZY-2GP

T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17

1D5V_S0

C195
SCD1U16V2ZY-2GP

C312

0R0805-PAD
C141
SC10U10V5ZY-1GP

1D5V_S0

0R0805-PAD

2
C154
SCD1U16V2ZY-2GP

2
C172
SC4D7U6D3V3KX-GP

VCC 1D05_S0 for low speed

graphic clock.1D5V_S0 for
high speed clock.default
use 1D05V_S0

C145
SC4D7U6D3V3KX-GP

1D5V_DLVDS_S0

2
C176
SC4D7U6D3V3KX-GP

SCD47U10V3ZY-GP

C157
SC4D7U6D3V3KX-GP
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane

POWER

1D5V_DLVDS_S0
E

R274 2
1D5V_DDRDLL_S0

1
R160

1D5V_S0

C315
ST100U6D3VBM-9GP
0R0603-PAD

R272 2
C309
SCD01U16V2KX-3GP
4

1D5V_PCIE_S0
R142

2
1D5V_S0

C126
SC10U10V5ZY-1GP
0R0603-PAD

C143
SC4D7U10V5ZY-3GP

1D5V_3GPLL_S0
R153

2
1D5V_S0

C142
0R0603-PAD
SC10U10V5ZY-1GP

2D5V_3GBG_S0

1
R253

2
2D5V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
Document Number

GMCH (4 of 5)
AG1(Alviso)
of
40

Rev

01

C305
SCD1U16V2ZY-2GP

0R0603-PAD

U38E

71.0GMCH.08U

Route ASSA3GBG gnd from GMCH to

decoupling cap groung lead and
then connect to the gnd plane

C329
SCD22U16V3ZY-GP

71.0GMCH.08U

1D05V_S0

A
B

Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

U38H

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NTTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26

1
C160
SCD1U16V2ZY-2GP

C188
SCD1U16V2ZY-2GP

C152
SCD1U16V2ZY-2GP

C175
SCD1U16V2ZY-2GP

C181
SCD1U16V2ZY-2GP

C322
SC10U10V5ZY-1GP

L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

71.0GMCH.08U

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

VSSALVDS

U38F

Y1
D2
G2
J2
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

B36

AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

A
B
C

VSS

Size
A3
Date: Monday, October 17, 2005
Sheet
E

10

1D8V_S3

Place these Hi-Freq decoupling caps near GMCH

1D05V_S0
3

NCTF

<Core Design>
1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
Document Number

GMCH (5 of 5)

AG1(Alviso)
of
40

Rev

01

AG1-A-SA
AG1-A-SA

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

11
29
49
68
129
146
167
186

/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

ODT0
ODT1

1
2

VREF
VSS

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

8 M_B_DQ[63..0]

8 M_B_DQS#[7..0]

8 M_B_DQS[7..0]

7,12
7,12

M_ODT2
M_ODT3

202
2

C140
SC4D7U6D3V3KX-GP

DDR_VREF_S3

BC1

GND

DM1

/CS0
/CS1

110
115

M_CS#2 7,12
M_CS#3 7,12

CKE0
CKE1

79
80

CK0
/CK0

30
32

M_CLK_DDR3 7
M_CLK_DDR#3 7

CK1
/CK1

164
166

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_CLK_DDR4 7
M_CLK_DDR#4 7
M_B_DM[7..0] 8

SDA
SCL

195
197

SMBD_ICH_1
SMBC_ICH_1

VDDSPD

199

SA0
SA1

198
200

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

GND

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

8,12

M_A_BS#2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

8,12
8,12

M_A_BS#0
M_A_BS#1

107
106

BA0
BA1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

11
29
49
68
129
146
167
186

/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

ODT0
ODT1

1
2

M_CKE2 7,12
M_CKE3 7,12

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

8 M_A_DQ[63..0]
SRN33J-5-GP-U
RN51
1
2

4
3

AG1-A-SA
SMBD_ICH 3,18
SMBC_ICH 3,18

3D3V_S0
1

R183

3D3V_S0

AG1-910-01

1D8V_S3

8 M_A_DQS[7..0]

8 M_A_DQS#[7..0]

7,12
7,12

M_ODT0
M_ODT1

DDR_VREF_S3
C307
SC4D7U6D3V3KX-GP

201

202

DDR2-200P-5-GP 62.10017.771
CONNECTOR

BC3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2nd
/RAS
/WE
/CAS

108
109
113

M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12

/CS0
/CS1

110
115

M_CS#0 7,12
M_CS#1 7,12

CKE0
CKE1

79
80

CK0
/CK0

30
32

CK1
/CK1

164
166

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

SDA
SCL

195
197

VDDSPD

199

SA0
SA1

198
200

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VREF
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

GND

GND

201

NORMAL TYPE

BA0
BA1

M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12

107
106

108
109
113

M_B_BS#0
M_B_BS#1

/RAS
/WE
/CAS

M_B_BS#2

8,12
8,12

2nd

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

10KR2J-3-GP

8,12

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

NORMAL TYPE

DM2

8,12 M_B_A[13..0]

8,12 M_A_A[13..0]

DDR2-200P-4-GP 62.10017.761
CONNECTOR

M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SMBD_ICH_1
SMBC_ICH_1
3D3V_S0

1D8V_S3

High 5.2mm
2nd source:62.10017.661

High 9.2mm
2nd source:62.10017.A61
B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR Socket

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR0 7
M_CLK_DDR#0 7

Size
Document Number
Custom
Date: Tuesday, October 25, 2005

R ev

01

AG1(Alviso)
Sheet
E

11

of

40

PARALLEL TERMINATION

Put decap near power(0.9V) and pull-up resistor

DDR_VREF

Decoupling Capacitor

AG1-910-01

C248
SCD1U16V2ZY-2GP

1
2

C199
SCD1U16V2ZY-2GP

C205
SCD1U16V2ZY-2GP

C204
SCD1U16V2ZY-2GP

C251
C238
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

C247
C207
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

1
2
1
2

1
2
1

C222
C212
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

SRN56J-2-GP

C198
C214
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

M_B_A12
M_B_A5
M_B_A3
M_B_A10

1
2
3
4

RN34

8
7
6
5

SRN56J-2-GP

M_CKE2 7,11
M_B_BS#2 8,11

M_B_A[13..0] 8,11

M_A_A[13..0] 8,11

C234
C227
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

8
7
6
5

M_CS#3 7,11
M_ODT3 7,11

SRN56J-4-GP
RN30
1
2 M_B_A8
3
4 M_B_A9

Put decap near power(0.9V)

and pull-up resistor

DDR_VREF

1
2

M_ODT1 7,11

4
3

C249
C193
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

M_CKE0 7,11

2 56R2J-4-GP

2 56R2J-4-GP

1 R179
RN43

C237
C245
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

1 R177

RN42

8
7
6
5

1
2
3
4

M_B_A13
M_ODT2 7,11
M_CS#2 7,11
M_B_RAS# 8,11

1D8V_S3

Place these Caps near DM1

SRN56J-2-GP

C228
SC2D2U6D3V3MX-1-GP

C224
SC2D2U6D3V3MX-1-GP

C235
SC2D2U6D3V3MX-1-GP

C192
SC2D2U6D3V3MX-1-GP

C197
SC2D2U6D3V3MX-1-GP

M_B_BS#1 8,11

M_B_A2
M_B_A0
M_B_A4

1
2
3
4

8
7
6
5

RN37

SRN56J-2-GP
RN33

8
7
6
5

1
2
3
4

M_B_A6
M_B_A7
M_B_A11
M_CKE3 7,11

SRN56J-2-GP
RN38

8
7
6
5

1
2
3
4

M_B_A1
M_B_BS#0 8,11
M_B_WE# 8,11
M_B_CAS# 8,11
1D8V_S3

SRN56J-2-GP

Place these Caps near DM2

1

C231
SC2D2U6D3V3MX-1-GP

C208
SC2D2U6D3V3MX-1-GP

C218
SC2D2U6D3V3MX-1-GP

C229
SC2D2U6D3V3MX-1-GP

SRN56J-2-GP
2

C190
SC2D2U6D3V3MX-1-GP

M_A_A13

M_A_RAS# 8,11
M_CS#0 7,11
M_ODT0 7,11

1
2
3
4

8
7
6
5

RN39

RN36

8
7
6
5

1
2
3
4

M_A_A4
M_A_A2
M_A_A0
M_A_BS#1 8,11

SRN56J-2-GP
RN40

8
7
6
5

1
2
3
4

M_A_BS#0
M_A_WE#
M_A_CAS#
M_CS#1

8,11
8,11
8,11
7,11

SRN56J-2-GP
RN31

8
7
6
5

1
2
3
4

M_A_A12
M_A_A9
M_A_A8

M_A_BS#2 8,11

M_A_A11
M_A_A7
M_A_A6

M_CKE1 7,11

SRN56J-2-GP
RN32

8
7
6
5

1
2
3
4

<Core Design>
1

SRN56J-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

RN35

8
7
6
5

1
2
3
4

M_A_A5
M_A_A3
M_A_A1
M_A_A10

Title

DDR2 Termination Resistor

Size
A3

SRN56J-2-GP

Document Number

Rev

Date: Tuesday, October 25, 2005

A

01

AG1(Alviso)
Sheet
E

12

of

40

LED

AG1-A-SA

LCDVDD

6
5
4

WLAN_LED#
3

D26

IN
GND
IN

OUT
GND
ON/OFF#

BAV99PT-GP-U
2

AAT4280IGU-1-T1GP

C220
SC1U10V3ZY-6GP

1
2
1KR2J-1-GP

GMCH_LCDVDD_ON

7 GMCH_LCDVDD_ON

AG1-910-01

3D3V_S0
LED-Y-26-U-GP 83.01608.D70
LED4
1
LED-G-98-GP 83.01608.J70
LED6
A

U21

1
2
LCDVDD_ON_1 3

R189

5V_S0

3D3V_S0

Layout 40 mil

AG1-910-01

C223
SCD1U16V2ZY-2GP

28

WLAN_LED#

WLAN_LED#

1
R205

29,30 FRONT_PWRLED#
29 STDBY_LED#
29 CHARGE_LED#
29 DC_BATFULL#

AG1-910-01
3

D24

3D3V_S5

SRN100J-4-GP

BAV99PT-GP-U
BLT_LED#

2
K

DY
1

C236
SC1U10V3ZY-6GP

2
100R2J-2-GP

FRONT_PWRLED#
4
STDBY_LED#
3
CHARGE_LED# 2
DC_BATFULL# 1

DY

5
6
7
8

LED-Y-26-U-GP 83.01608.D70
1 LED3
LED-Y-26-U-GP 83.01608.D70
1 LED2
LED-G-98-GP
83.01608.J70
A LED1

2
2
K

RN57

5V_S0

LCD/INVERTER/CCD CONN

29

BLT_LED#

BLT_LED#

1
R200

2
470R2J-2-GP

LED-B-27-U-GP
1

83.00190.P70

3D3V_S0

5V_S0

LED5

LED BD CONN

EC62
SCD1U16V2ZY-2GP

DY
CCD Pin

AG1-910-01

Pin

Symbol
5V_S0

PWRBTN#

PROGRAM#

EBUTTON#

INTERNET#

MAIL#

KCOL19

MAIL_LED#

STDBY_LED#

10

PWRLED#

11

GND

12

GND

46
MH2
44

42

1
2

2D5V_S0

ODD CHANNEL

GMCH_TXBOUT2- 7
GMCH_TXBOUT2+ 7

SRN2K2J-1-GP
RN3

GMCH_TXBCLK- 7
GMCH_TXBCLK+ 7
BRIGHTNESS
FPBACK

BRIGHTNESS 29
FPBACK 29
7 CLK_DDC_EDID

DCBATOUT
EC65
SCD1U16V2ZY-2GP

Layout 60 mil

IPEX-CON40-2-GP
20.F0763.040
CONNECTOR

C233
SC10U35V0ZY-GP

C32

DY

DY

TOP VIEW

AG1-A-SA

LCD

C33
SCD1U50V3ZY-GP

EC64
SCD1U16V2ZY-2GP

7 DAT_DDC_EDID

EDID_CLK

Q26
FDN337N-1-GP

SC1000P50V3JN-GP

GMCH_TXBOUT1- 7
GMCH_TXBOUT1+ 7

EDID_DAT

Q22
FDN337N-1-GP

DY
EC67
SCD1U16V2ZY-2GP

Launch BD

3D3V_S0

GMCH_TXBOUT0- 7
GMCH_TXBOUT0+ 7

GND

1
2

GND

EVEN CHANNEL

GMCH_TXAOUT0- 7
GMCH_TXAOUT0+ 7

4
3

EC50
SCD1U16V2ZY-2GP

BLON

3D3V_S0

GMCH_TXAOUT1- 7
GMCH_TXAOUT1+ 7

CAP_LED# 29
NUM_LED# 29
IDE_LED# 20

PWM

CAP_LED#
NUM_LED#
IDE_LED#

Vin

MLX-CON8-7-GP-U
CONNECTOR
20.K0185.008

GMCH_TXAOUT2- 7
GMCH_TXAOUT2+ 7

DY

Vin

GMCH_TXACLK- 7
GMCH_TXACLK+ 7

EC63
SCD1U16V2ZY-2GP

DY

Pin Symbol

C155
SCD1U16V2ZY-2GP

Inverter Pin

EDID_CLK
EDID_DAT

GND

2
3
4
5
6
7
8
9

LCDVDD

GND

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

45

SC10U10V5ZY-1GP
C173

USB+

41

43
MH1

USB-

5V

10
1

LEDB1

LCD1

Pin Symbol

DY

EC66
SCD1U16V2ZY-2GP

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD CONN & LED

1
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Friday, October 28, 2005

Sheet

13

of

40

CRT CONNECTOR
Ferrite bead impedance: 75ohm@100MHz
7 GMCH_RED

L6

50 Ohm Impedance

GMCH_RED

75 Ohm Impedance

CRT_R

BLM18BA100SN1DGP
L7
7 GMCH_GREEN

GMCH_GREEN

CRT_G

2
BLM18BA100SN1DGP
L8

1
EC26

1
2

DY

EC23

SC6D8P50V2DN-GP

EC22

SC6D8P50V2DN-GP

CRT_B

2
BLM18BA100SN1DGP

SC6D8P50V2DN-GP

DY

EC29
SC3P50V2CN-1-GP

AG1-910-01

SC3P50V2CN-1-GP

DY

EC27

EC28
SC3P50V2CN-1-GP

150R2F-1-GP

R79

R46
150R2F-1-GP

150R2F-1-GP

1
R53

GMCH_BLUE

7 GMCH_BLUE

Hsync & Vsync level shift

5V_S0

DAT_DDC1_5
CR T_HSYNC1
CRT_VSYNC1

TSAHCT125PW-GP

CLK_DDC1_5
C11
SC33P50V2JN-3GP

EC3
SC10P50V2JN-4GP

DDC_CLK & DATA level shift

SC10P50V2JN-4GP

AG1-910-SB

EC2

EC4
SC100P50V2JN-3GP

EC1

ESD Protection Diode

DY

SC100P50V2JN-3GP

DY

1
2

C15
SC33P50V2JN-3GP

CRT_VSYNC1

3
U3A

CR T_HSYNC1

TSAHCT125PW-GP
U3D

7 GMCH_VSYNC

11

GMCH_VSYNC

14

12

GMC H_HSYNC

7 GMCH_HSYNC

13

14

C14
SCD1U16V2ZY-2GP

5V_S0
BAV99PT-GP-U
2
CRT_R 3

AG1-910-01

5V_CRT_S0

BAV99PT-GP-U
2

5V_S0
2D5V_S0

D1

DY

D4

8
7
6
5

5V_CRT_S0

CH521S-30-GP-U
EC5
SCD01U16V2KX-3GP

CRT_G 3

BAV99PT-GP-U
2

DY

RN2
SRN2K2J-2-GP

D2

DY
CRT_B 3

D3

1
2
3
4

DY

AG1-A-SA
CRT1

2D5V_S0

AG1-910-SB
17

6
1

11

CRT_R
CRT_G

FDN337N-1-GP
Q6

7 GMCH_DDCCLK

DAT_DDC1_5
CRT_B
5V_CRT_S0

7 GMCH_DDCDATA

S
FDN337N-1-GP
Q7

DCLK_DDC1_5

7
2
8
3
9
4
10
5

12

DAT_DDC1_5

13

CR T_HSYNC1

14

CRT_VSYNC1

15

CLK_DDC1_5

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

16
VIDEO-15-42-GP-U
CONNECTOR
20.20378.015

Title

CRT Connector
Size
Document Number
Custom

R ev

01

AG1(Alviso)

Date: Friday, October 28, 2005

Sheet

14

of

40

1
R219
56R2J-4-GP

R227

RCT_RST#

AA2

RTCRST#

2 1MR2J-1-GP

INTRUDER#
INTVRMEN

AA3
AA5

INTRUDER#
INTVRMEN

AG1-910-01
26 ACZ_BITCLK
21,26 ACZ_SYNC

2nd source: 20.F0736.003

21,26 ACZ_RST#

AG1-910-01

R90 1
1
39R2J-L-GP
1
39R2J-L-GP

2 0R0603-PAD
ACZ_SYNC_R
2
R99
ACZ_RST#_R
2
R100

26 ACZ_SDATAIN0
21 ACZ_SDATAIN1
TP36

21,26 ACZ_SDATAOUT

R94

2
39R2J-L-GP

LAN_CLK

LAN_RSTSYNC

E12
E11
C13

LANRXD[0]
LANRXD[1]
LANRXD[2]

C12
C11
E13

LANTXD[0]
LANTXD[1]
LANTXD[2]

C10
B9

ACZ_BIT_CLK
ACZ_SYNC

A10

ACZ_RST#

TPAD28
ACZ_SDATAOUT_RC9

AE3
AD3
AG2
AF2

2 SCD01U16V2KX-3GP

DY
AG1-910-SB

ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO

R56
100KR2J-1-GP

AG1-910-01

P.H. for internal VCCSUS1_5

INTVRMEN

20
20
20
20
20

R60
0R2J-GP

IDE_PDIORDY
INT_IRQ14
IDE_PDDACK#
IDE_PDIOW#
IDE_PDIOR#

LFRAME#/FWH[4]

P3

TP27 TPAD28
TP25 TPAD28
LPC_LFRAME# 29

AF22
AF23

KA20GATE_1 29
H_A20M# 4

CPUSLP#

AE27

H_CPUSLP# 4,6

DPRSLP#
DPSLP#

AE24
AD27

H_DPRSLP# 4
H_DPSLP# 4

FERR#

AF24

CPUPWRGD/GPO[49]

AG25

IGNNE#
INIT3_3V#
INIT#
INTR

AG26
AE22
AF27
AG24

AD7
AC7
AF6
AG6

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

AC2
AC1

SATA_CLKN
SATA_CLKP

AG11
AF11

SATARBIAS#
SATARBIAS

AF16
AB16
AB15
AC14
AE16

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

R214
56R2J-4-GP

AG1-910-01

R216 1

2 56R2J-4-GP

H_FERR# 4

H_PW RGD 4,19

FWH_INIT#

H_IGNNE# 4

TP2
3

H_INIT# 4
H_INTR 4

RCIN#

AD23

KBRCIN#_1 29

NMI
SMI#

AF25
AG27

H_NMI 4
H_SMI# 4

STPCLK#

AE26

H_STPCLK# 4

THRMTRIP#

AE23

H_THERMTRIP_R

1D05V_S0
C260
SC4700P50V2KX-1GP

DY

R211
75R2F-2-GP

1 R210
2
56R2J-4-GP

AC16
AB17
AC17

IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20

DCS1#
DCS3#

AD16
AE17

IDE_PDCS1# 20
IDE_PDCS3# 20

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

DDREQ

AB14

DA[0]
DA[1]
DA[2]

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

H_FERR_R

A20GATE
A20M#

SATALED#

RTC_AUX_S5

LPC_LDRQ#0
LPC_LDRQ1

F12

F11
F10
B10

N6
P4

1D05V_S0

B11

AC19

EC69

10KR2J-3-GP

ACES-CON3-1-GP
20.F0735.003
RTC1 CONNECTOR

4
3

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LDRQ[0]#
LDRQ[1]#/GPI[41]

BAT

R101

D12
B12
D11
F13

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

19 INTRUDER#

P2
N3
N5
N4

LAN

C53
SCD1U16V2ZY-2GP

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

2 20KR2F-L-GP

R222 1

AG1-910-01

BAT

RTC

R215 1

AG1-910-01

1
2
3

BAT54C-1-GP

2nd
3

RTCX1
RTCX2

AG1-A-SA

R202
1KR2J-1-GP

1
2

LPC_LAD[0..3] 29
RCT_X1 Y1
RCT_X2 Y2

C272
SC22P50V2JN-4GP

KBRCIN#_1
KA20GATE_1

U26A

AG1-910-01

BAT_D2

10KR2J-3-GP
R77
2

RN16
SRN10KJ-5-GP

CPU

C259
SC1U10V3ZY-6GP

H_DPSLP#

AC-97/AZALIA

10MR3J-L1-GP

X-32D768KHZ-38GPU
D22

SATA
IDE

X2

LPC_LDRQ1

DY

3
RTC_AUX_S5

AG1-910-01
3D3V_S0

AG1-910-01
3D3V_AUX_S5

AG1-A-SA

1D05V_S0

SC22P50V2JN-4GP
C277
1
2

AG1-910-SB

PM_THRMTRIP-I# 4,7,19
Layout Note: R632 needs to placed
within 2" of ICH6, R634 must be placed
within 2" of R632 w/o stub.

AG1-910-01

IDE_PDD0 20
IDE_PDD1 20
IDE_PDD2 20
IDE_PDD3 20
IDE_PDD4 20
IDE_PDD5 20
IDE_PDD6 20
IDE_PDD7 20
IDE_PDD8 20
IDE_PDD9 20
IDE_PDD10 20
IDE_PDD11 20
IDE_PDD12 20
IDE_PDD13 20
IDE_PDD14 20
IDE_PDD15 20

IDE_PDDREQ 20

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH6-M (1 of 4)
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Thursday, October 27, 2005

Sheet
E

15

of

40

Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.

U26C
3D3V_S0

29 PM_SUS_STAT#
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

R76

22,24,28
22,24,28
22,24,28
22,24,28

DBRESET#
7 PM_BMBUSY#

210R2J-2-GP
PCI_DEVSEL# 22,24,28
PCI_PERR# 22,24,28

PCI_LOCK#

PCI_SERR# 22,24,28
PCI_STOP# 22,24,28
PCI_TRDY# 22,24,28

C67
SC22P50V2JN-4GP

TP60

INT_PIRQB#

TP17
TP3
TP10
TP11
TP18

TPAD28
TPAD28
TPAD28
TPAD28
TPAD28

AC5
AD5
AF4
AG4
AC9

PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#/GPI[4]
PIRQ[H]#/GPI[5]

RESERVED
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
TP[3]

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

D9
C7
C6
M3

TPAD28
TPAD28
TPAD28
TPAD28

AD9
AF8
AG8
U3

TP16
TP15
TP14
TP22

22,24,28,29 PM_CLKRUN#

10
9
8
7
6

3D3V_S0

10
9
8
7
6

3D3V_S0

1
2
3
4
5

R69
ECSWI#

2
8K2R2J-3-GP

1
1

DY
DY

1KR2J-1-GP

2
100KR2J-1-GP
2
100KR2J-1-GP

10
9
8
7
6

ECSCI#_1

1
2
3
4
1
R203

8
7
6
5

AG1-910-01

34 PM_DPRSLPVR

ICH_GPIO33
ICH_GPIO34

THRM#

U5

GPIO[25]
GPIO[27]
GPIO[28]
CLKRUN#
GPIO[33]
GPIO[34]
WAKE#

AB20

SERIRQ

AC20

THRM#

AF21

VRMPWRGD
CLK14

3 CLK48_ICH

A27

CLK48

18 PM_SUS_CLK

V6

SUSCLK

T4
T5
T6

SLP_S3#
SLP_S4#
SLP_S5#

29,37 PM_SLP_S4#

PM_SLP_S5#

TPAD28

AA1

19 PWROK

2
R204
100R2J-2-GP

PM_DPRSLPVR_RAE20
PM_BATLOW#_R
PM_PWRBTN#

LAN_RST#

PM_SLP_S3# 18,29,32,35,37
R80
100KR2J-1-GP

2
R207
100KR2J-1-GP

3D3V_S5
CHK_PW#
PM_RI#
DBRESET#

P5
R3
T3
AF19
AF20
AC18

3 CLK_ICH14

29 PM_PWRBTN#
PM_SLP_S3#_ICH 1
R78 2
0R0402-PAD
PM_DPRSLPVR_R

RN5

10
9
8
7
6

CHK_PW#

3D3V_S0
INT_SERIRQ
THRM#
MCH_SYNC#
INT_PIRQB#

R83

E10

TP23
Need to check what power we will use

STP_CPU#

GPIO[24]

7,32 VGATE_PWRGD

SRN10KJ-4-GP
2
100KR2J-1-GP

AD22

V3

PM_SLP_S3#_ICH

3D3V_S0
PCI_REQ#3
INT_PIRQE#
PM_CLKRUN#
PCI_REQ#2

SRN10KJ-L3-GP
SMB_LINK_ALERT# 1
SMLINK0
2
SMB_ALERT#
3
SMLINK1
4
5
3D3V_S5

PCI_REQ#6
PCI_REQ#1
BOOT_BLOCK#

AG1-910-01

SRN10KJ-L3-GP
RN45
PCI_REQ#0
INT_PIRQA#
INT_PIRQC#
INT_PIRQH#

ECSMI#

GPO[19]

GPO[21]
GPO[23]

TPAD28
TPAD28

STP_PCI#

AB21

ICH_GPO21
AD20
KBC_SLP_WAKE AD21

10KR2J-3-GP 1

TP4
TP20

AC21

PWROK
DPRSLPVR

V2

BATLOW#

U1

PWRBTN#

V5

LAN_RST#

Y3

RSMRST#

1
2
3
4
5

R238

R84

SRN10KJ-L3-GP
RN59
PCI_LOCK#
INT_PIRQG#
PCI_DEVSEL#
P CI_IRDY#

PCI_FRAME#
PCI_STOP#
PCI_TRDY#
PCI_PERR#

PM_BATLOW#_R

3D3V_S0

1
2
3
4
5

TPAD28

24,28,29 INT_SERIRQ
3D3V_S0
19 THRM#

3D3V_S5

R70

ICH_GPO19

31 PCB_VER0
31 CHK_PW#

AG1-910-01

INT_PIRQD#
PCI_REQ#5
PCI_SERR#
INT_PIRQF#

3D3V_S0

TPAD28

31 PCB_VER1

RN6
RN47

GPI[12]
GPI[13]

ICH6_WAKE#

ICH6 Pullups
ICH6_WAKE#

SMBALERT#/GPI[11]

29 KBC_SLP_WAKE

AG1-910-01

GPI[7]
GPI[8]

M2
R6

3,34 PM_STPCPU#

INT_PIRQE# 22
INT_PIRQF# 28
INT_PIRQG# 24

BMBUSY#

AE19
R1

ICH_GPI12

PLT_RST1# 7,18,29
TP6

AD19

TPAD28

29,32 RSMRST#_KBC

24

N2
L2
M1
L3

SYS_RESET#

W6

3 PM_STPPCI#

1 R67
247R2J-2-GP
CLK_ICHPCI 3
ICH_PME# 22,29Int. PH

Interrupt I/F
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

SUS_STAT#/LPCPD#

U2

SMB_ALERT#

29 ECSWI#

TP21
PLT_RST1#_1

W3

AG1-910-01
PCI_IRDY# 22,24,28
29 ECSCI#_1
PCI_PAR 22,24,28
29 ECSMI#
PCIRST1# 22,24,28

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

DY

R336
100KR2J-1-GP

AG1-910-01

DY

PERn[1]
PERp[1]
PETn[1]
PETp[1]

H25
H24
G27
G26

PERn[2]
PERp[2]
PETn[2]
PETp[2]

K25
K24
J27
J26

PERn[3]
PERp[3]
PETn[3]
PETp[3]

M25
M24
L27
L26

PERn[4]
PERp[4]
PETn[4]
PETp[4]

P24
P23
N27
N26

DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

T25
T24
R27
R26

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

7
7
7
7

DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

V25
V24
U27
U26

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

7
7
7
7

DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

Y25
Y24
W27
W26

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

7
7
7
7

DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

AB24
AB23
AA27
AA26

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

7
7
7
7

DMI_CLKN
DMI_CLKP

AD25
AC25

CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3

DMI_ZCOMP

F24

DMI_IRCOMP

F23

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

C23
D23
C25
C24

OC[0]#
OC[1]#
OC[2]#
OC[3]#

C27
B27
B26
C26

USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

USBRBIAS#
USBRBIAS

A22
B22

Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.

1D5V_S0

26 ACZ_SPKR

SATA[0]GP/GPI[26]
SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

PCI-EXPRESS

TPAD28

TPAD28

RI#

Place within 500 mils of ICH

3

R86
24D9R2F-L-GP

AG1-910-SB
2

FRAME#

TP37

Y4
W5
SMB_LINK_ALERT# Y5
SMLINK0
W4
SMLINK1
U6
MCH_SYNC# AG21
F8

18 SMB_CLK
18 SMB_DATA

TPAD28

AF17
AE18
AF18
AG18

Direct Media Interface

PLTRST#
PCICLK
PME#

R5
G6
P6

TP35
BOOT_BLOCK#
TP34
PCI_REQ#5
PCI_GNT#5
PCI_REQ#6
PCI_GNT#6

T2

SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3

GPIO

A3
E1
R2
C3
E3
C5
G5
J1
J2

PCI_REQ#3

PM_RI#

CLOCKS

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#

PCI_REQ#2

RN15
SRN10KJ-4-GP
1
8SATA0_R0
2
7SATA0_R1
3
6SATA0_R3
4
5SATA0_R2

24
24
28
28
22
22

AG1-910-01

DMI_IRCOMP_R
3D3V_S5
RN72
USB_OC#6

USB_OC#6 21

USB_OC#0
USB_OC#1

USB_OC#0 21

1
USB_OC#1 2
USB_OC#6 3
USB_OC#0 4

8
7
6
5
SRN10KJ-4-GP

AG1-910-SB
USBPN0 21
USBPP0 21

USBPN1
USBPP1
USBPN2
USBPP2
USBPN3
USBPP3

3D3V_S0

R7F9

TPAD28 TP71
TPAD28 TP72
TPAD28 TP75
TPAD28 TP70
TPAD28 TP69
TPAD28 TP74
USBPN4 21
USBPP4 21

USBPN5
USBPP5
USBPN6
USBPP6
USBPN7
USBPP7

R85

USB_RBIAS_PN

1 R250

2
DY 1KR2J-1-GP

ACZ_SPKR

R7F8

TPAD28 TP73
TPAD28 TP68
USBPN6 21
USBPP6 21
USBPN7 21
USBPP7 21

R97

1KR2J-1-GP
1
2

PCI_GNT#6

R87

1KR2J-1-GP
1
2

PCI_GNT#5

DY

R7F7

DY

100KR2J-1-GP
R223 1
2

PWROK

DY

22D6R2F-L1-GP

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

J6
H6
G4
G2

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2

Place within 500 mils of ICH

R337
10KR2J-3-GP

AG1-910-01

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]

PCI

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1

J3

2,24,28 PCI_FRAME#

AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

POWER MGT
USB

U26B

2,24,28 PCI_AD[31..0]

ICH6-M Strapping Options

FUNCTION

DEFAULT

OPTIONAL OVERRIDE

R7F9

No Reboot

NO_STUFF

STUFF

R7F8

A16 Swap
Override

NO_STUFF

STUFF

R7F7

Boot BIOS

NO_STUFF

STUFF

REF

SRN10KJ-L3-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH6-M (2 of 4)
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Monday, October 31, 2005

Sheet
E

16

of

40

C96

EC33
SCD1U16V2ZY-2GP

C91
SCD1U16V2ZY-2GP

1
1
2
2
1
1

3D3V_S5

3D3V_S5

DY

Place within 100

mils of ICH
C95
SCD01U16V2KX-3GP

G11
G10

C79

AG23
AD26
AB22

RTC_AUX_S5

Place within 100

mils of ICH
pin G10

C49
SCD1U16V2ZY-2GP

1D05V_S0
C50
SCD1U16V2ZY-2GP

C281

1D5V_INT_S5

VOUT
VIN
GND

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

C88
SCD1U16V2ZY-2GP

DY
C

DY

APL5308-15AC-GP

<Core Design>

1
C84
SCD1U16V2ZY-2GP

C287

C51
SCD1U16V2ZY-2GP

Layout Note:
Place near AG23

Place within 100

mils of ICH
pin V7

2
1

Layout Note:
Place near AB3

AB3

DY

SC1U10V3ZY-6GP

3
Place within 100
mils of ICH
C94
SCD1U16V2ZY-2GP

1D5V_INT_S5

U35

1D5V_ICH_S0

Layout Note:
Place near AB18

A25
A24

AG1-910-SB

Place within 100

mils of ICH
pin A17

ICH6-M (3 of 4)
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Monday, October 31, 2005

B

C78
SC1U10V3ZY-6GP

2D5V_S0

DY

V5REF_SUS

R81

1
2
0R3J-3-GP

3D3V_S5

C56
SCD1U16V2ZY-2GP

AG1-910-01

2
1
2
2
2

C89
SCD1U16V2ZY-2GP

AG1-910-SB
V2D5S_PCI_IDE

1
2

DY

10R2J-2-GP
R248

RB751V-40-1-GP
D25

V5REF_S5

C107
SC1U10V3ZY-6GP

5V_S5

1
Layout Note:
Place near ICH6

C81
SCD1U16V2ZY-2GP

Place both
within 100 mils
of ICH near D27

AB18
P7

G16
G15
F16
F15
E16
D16
C16

1
2
1

1
C75
SCD1U16V2ZY-2GP

VCCUSBPLL
VCCSUS3_3

VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCRTC
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCSUS3_3
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
V_CPU_IO
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

1
2
1

1
2

1D5V_S0

C74
SCD1U16V2ZY-2GP
AA18
A8
V5REF_S0
V5REF_S5
F21

V5REF
V5REF

EC32
SCD1U16V2ZY-2GP

EC24
SCD1U16V2ZY-2GP

2
1
2
1
2

CORE
IDE

VCCSATAPLL
VCC3_3

VCC2_5
VCC2_5

3D3V_S5

3D3V_S5

1
2

C69
SC10U10V5ZY-1GP

Place within 100

mils of ICH
pin A13

EC36
SCD1U16V2ZY-2GP

1D5V_S0

AE1
AG10

A17
B17
C17
F18
G17
G18

G8

10R2J-2-GP
R109

C55
SCD1U16V2ZY-2GP

C68
SCD1U16V2ZY-2GP

1D5V_INT_S5

SCD1U16V2ZY-2GP

3D3V_S5

VCC1_5_A

C62
SCD1U16V2ZY-2GP

C45
SCD1U16V2ZY-2GP

G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

V5REF_S0

1
2

Place within 100

mils of ICH
pin AG10

VCCDMIPLL
VCC3_3

A11
U4
V1
V7
W2
Y7

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

1D5V_INT_S5

C246
SCD1U16V2ZY-2GP

VCCSUS1_5

G19

5V_S0

RB751V-40-1-GP
D16

Place within 100

mils of ICH
pin AE1

3D3V_S0

AC27
E26

A13
F14
G13
G14

1 R212
2
0R0603-PAD

U7
R7

3D3V_S0

C97
SCD1U16V2ZY-2GP

1D5V_ICH_S0

C90
SCD1U16V2ZY-2GP

1D5V_S0

Place within 100

mils of ICH
near E26, E27

VCCSUS1_5
VCCSUS1_5

3D3V_S0

SC2D2U6D3V3MX-1-GP

3D3V_S0

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

*Within a given well, 5VREF needs to be up before the

corresponding 3.3V rail

Layout Note:
Distribute in PCI section
near pin A2-A6 near D1-H1

C262
SCD01U16V2KX-3GP

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

C256
SCD1U16V2ZY-2GP

2
1

1
C266
SC10U10V5ZY-1GP

Place within 100

mils of ICH

1 R224
2
0R0603-PAD

AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

Layout Note:
Place near pin AA19

ALL NO_STUFF Caps do

not have layout
requirements but if
layout allows then place
next to ICH6

3D3V_S0

C44
1D5V_GPLL_ICH_S0

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

Place within 100

mils of ICH pin
AG13, AG16

1D5V_S0
2

AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

1D5V_S0
Place within 100
mils of ICH
near pin AG9

SCD1U16V2ZY-2GP

C43

SCD1U16V2ZY-2GP

Place within 100

mils of ICH
near pin AG5

1D5V_S0

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

SCD1U16V2ZY-2GP

PCI

Layout Note:
PCI decoupling

USB

DY

USB CORE

EC37
SCD1U16V2ZY-2GP

PCI/IDE
REF

1D5V_S0

1
2

SCD1U16V2ZY-2GP

C257

VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B

PCIE

Layout Note:
IDE decoupling
3D3V_S0

AA22
AA23
AA24
AA25
AB25
AB26
AB27
F25
F26
F27
G22
G23
G24
G25
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22

SATA

DY

SCD1U16V2ZY-2GP

C80

TC5
ST220U2D5VBM-2GP

U26E
1D5V_S0

EC31
SCD1U16V2ZY-2GP

Layout Note:
Place above caps within
100 mils of ICH near F27, P27, AB27

C82
SCD1U16V2ZY-2GP

1D5V_S0

Sheet
E

01
17

of

40

AG1-910-01

U30

1
2
3

16,29,32,35,37 PM_SLP_S3#
16 PM_SUS_CLK

OE
A
GND

E27
Y6
Y27
Y26
Y23
W7
W25
W24
W23
W1
V4
V27
V26
V23
U25
U24
U23
U15
U13
T7
T27
T26
T23
T16
T15
T14
T13
T12
T1
R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N7
N17
N16
N15
N14
N13
N12
N11
N1
M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13
K7
K27
K26
K23
K1
J4
J25
J24
J23
H27
H26
H23
G9
G7
G21
G12
G1

3D3V_S5

32K suspend clock output

VCC

R237
32KHZ

G791_32K 19

10R2J-2-GP

NC7SZ126P5X-GP

R239
100KR2J-1-GP

AG1-910-01

AG1-910-01

AG1-910-SB
5V_S0
U3C

10

14

33R2J-2-GP
R367

7,16,29 PLT_RST1#

RSTDRV#_5 20

0R0402-PAD

TSAHCT125PW-GP

R190
10KR2J-3-GP

AG1-910-01

C447
SC100P50V2JN-3GP

R201 2

1
1

PCIRST# 3V to 5V level shift for HDD & CDROM

AG1-A-SA

3D3V_S0

8
7
6
5

3D3V_S5

1
2
3
4

RN17
SRN10KJ-4-GP

5V_S0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

SMBUS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

U26D

SMBC_ICH 3,11

2
S

16 SMB_DATA

<Core Design>

Q94 & Q95 connect SMLINK and

SMBUS in S) for SMBus 2.0
compliance

Q27
2N7002PT-U

16 SMB_CLK

Wistron Corporation

SMBD_ICH 3,11

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Q14
2N7002PT-U

Title

ICH6-M (4 of 4)
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Tuesday, October 25, 2005

A

Sheet
E

01
18

of

40

FAN1_VCC

1
D13
BAT54-4-GP

5V_S0

DY
AG1-910-01

DY

C73
SC2200P50V2KX-2GP

R82
10KR2J-3-GP

AG1-910-SB

2nd
FAN1

AG1-910-SB

3
2
1

FAN1_VCC

*Layout* 15 mil

C76
SC100P50V2JN-3GP

4
ACES-CON3-1-GP
20.F0735.003
CONNECTOR

AG1-910-01

R241
49K9R2F-L-GP

G792_DXN3
G30

AG1-910-SB

AG1-910-01

Place near chip as close

as possible
DCBATOUT

1
3

H_THERMDA 4
H_THERMDC 4

5V_S5_G913

PMBS3904-1-GP

System ,V GA

AG1-910-01

PMBS3904-1-GP

Q24
C139 1

System Sensor

R88
1MR2J-1-GP

DY
5

LOW3_OFF

VCC

HTH
GND
RESET#/RESET LTH

1
2
3

HTH

G680LT1F-GP

Output type:
Open-Drain RESET#

3D3V_AUX_S5

R92

INTRUDER# 15

DY

0R2J-GP

RSMRST# 29

R93
110KR2F-GP

DY
2

D14
BAT54-4-GP

(dummy, KBC already delay)

C85
SCD1U16V2ZY-2GP

DY
<Core Design>

Wistron Corporation

AG1-910-01
1

1KR2J-1-GP
C412
SCD1U16V2ZY-2GP

AG1-910-SB

Q15
PMBT2222A-1GP

Title

Thermal/Fan Controllor

H_PWRGD

4,15

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

R95

Size
Document Number
Custom

AG1-910-01

R249

DY

BAW56-2-GP
D15

R247
10KR2J-3-GP

DY

15KR2F-GP

T8_HW_SHUT#

U27

DY

C92
SCD1U16V2ZY-2GP

DY

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree

Q25
1

C171

G29

G792_RESET#

2
4K7R2J-2-GP
R235

THRM# 16

R236
10KR2J-3-GP

C65
SC2200P50V2KX-2GP

R244
10KR2J-3-GP

PWROK

16

SC470P50V2KX-3GP
SC470P50V2KX-3GP

G792_DXN2

G792SFUF-GP

3D3V_S0

H_THERMDC

V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC

SGND1
SGND2
SGND3

8
10
12

H_THERMDA
G792_DXP3
G792_DXP2

ALERT#
THERM#
THERM_SET
RESET#

5
17

C290
SC2200P50V2KX-2GP

15
13
3
2

DGND
DGND

G791_32K 18
SMBD_G792 29
SMBC_G792 29

C308
SC2200P50V2KX-2GP

DXP1
DXP2
DXP3

7
9
11

FAN1
FG1
CLK
SDA
SCL
NC#19

VCC
DVCC

1
4
14
16
18
19

C83
SC2200P50V2KX-2GP
2
1

THRM#
T8_HW_SHUT#
V_DEGREE

6
20

GAP-CLOSE
1
2

1
C71

C72
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2
1

SC4D7U10V5ZY-3GP
2
1

C66

Setting T8 as
100 Degree

R242
4K99R2F-L-GP

1
2

C286
SCD1U16V2ZY-2GP

200R2F-L-GP

2nd source: 20.F0736.003

U19
5V_G791_S0

AG1-910-01 *Layout* 30 mil

GAP-CLOSE
1
2

R246

5V_S0
5V_S0

C77
SC10U10V5ZY-1GP

1
2

C70

SCD1U16V2ZY-2GP

*Layout* 15 mil

PM_THRMTRIP-I# 4,7,15

Rev

01

AG1(Alviso)

Date: Thursday, October 27, 2005

Sheet

19

of

40

HDD Connector

CD-ROM Connector

5V_S0

15
15

IDE_PDCS3#
IDE_PDCS1#

15
15
15

IDE_PDA2
IDE_PDA1
IDE_PDA0

51
1

AG1-910-01

RESERVED#44
RESERVED#32

44
32

IDE_PDCS3#
IDE_PDCS1#

38
37

CS1#
CS0#

IDE_PDA2
IDE_PDA1
IDE_PDA0

36
33
35

DA2
DA1
DA0

NP2
NP1

NP2
NP1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

40
30
26
24
22
43
19
45
46
2

INT_IRQ14
IDE_PDIORDY
IDE_PDIOR#
IDE_PDIOW#
IDE_PDDREQ
IDE_PDDACK#

RSTDRV#_5 18
IDE_LED#
13
INT_IRQ14 15
IDE_PDIORDY15
IDE_PDIOR# 15
IDE_PDIOW#15
IDE_PDDREQ15
IDE_PDDACK#15

5V_S0

PDIAG
IDE_PDA2
IDE_PDCS3#

10KR2J-3-GP

5V_S0

C263
SC10U10V5ZY-1GP

C268

C270

DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0

IDE_PDDACK#
R217

2
1
470R2J-2-GP

RSTDRV#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDIOW#
IDE_PDIORDY
INT_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
IDE_LED#
5V_S0
R225
CSEL

10KR2J-2-GP

18
16
14
12
10
8
6
4
3
5
7
9
11
13
15
17

HDDCSEL
PDIAG
RSTDRV#_5

SCD1U16V2ZY-2GP

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

AG1-910-01

R305

20
28
34
1
39
31
27
25
23
21
29

KEY
CSEL
PDIAG#
RESET#
DASP#
INTRQ
IORDY
DIOR#
DIOW#
DMARQ
DMACK#

+5V_MOTOR
+5V_LOGIC

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
52
STC-CONN50-4R

20.80251.050
CONNECTOR

AG1-910-SB

IDE_PDIORDY
IDE_PDDACK#
INT_IRQ14

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

R226
0R2J-GP

PIN 49,50 DON'T USE

DY

1
2
3
4

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ
IDE_PDIOR#

IDE_LED#

42
41

SYN-CON44-1-GP
CONNECTOR

ODD1

SCD1U16V2ZY-2GP

Check

AG1-910-01
R218
10KR2J-3-GP

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

8
7
6
5
TC16

AG1-910-01

1
2

RN68
SRN4K7J-6-GP

HDD1

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

5V_S0

AG1-910-SB

ST100U6D3VDM-5

DY D23
A

C347

SSM22LLPT-GP

1
2

1
2

SCD1U16V2ZY-2GP

C345

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

C346

AG1-910-SB

3D3V_S0

20.F0793.044

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HDD and CDROM

Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Monday, October 31, 2005

Sheet

20

of

40

5V_USB0_S0

10 0 mil

5V_S5

USB PORT

5V_USB1_S0

U45

SRN0J-6-GP

5V_USB0_S0
CONNECTOR
22.10218.J11
SKT-USB-105-GP

AG1-910-SB

29 USB_PWR_EN#

2
1

8
7
6
5

GND
OC1#
IN
OUT1
EN1/EN1# OUT2
EN2/EN2# OC2#

3
4

USB_OC#0 16
USB_OC#6 16

RN66

8
6

AG1-910-01
16
16

4
3
2

USBPN6
USBPP6

1
5
7

EC74

DY DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

EC73

G546A2P1UF-GP

EC53
SC1000P50V3JN-GP

DY

1
2
3
4

EC52
SCD1U16V2ZY-2GP

SE100U10VM-4GP

TC13

5V_USB1_S0

USB2

5V_USB0_S0
CONNECTOR
22.10218.J11
SKT-USB-105-GP

AG1-910-SB

8
6
16
16

10 0 mil

4
3
2

USBPN7
USBPP7

5V_USB0_S0

USB3

EC54
SC1000P50V3JN-GP

DY
SCD1U16V2ZY-2GP

SE100U10VM-4GP

TC20

SE100U10VM-4GP

TC17

5
7
EC55

5V_USB1_S0
CONNECTOR
22.10218.J11
SKT-USB-105-GP

8
6

BLUETOOTH MODULE

16
16

3D3V_BT_S0

1
2
3

EC56

DY

SCD1U16V2ZY-2GP

USBPN0
USBPP0

3D3V_S0

U42
3D3V_BT_S0

4
3
2

OUT
IN
GND
NC#3 ON/OFF#

1
5
7

5
4

USB4

BLUETOOTH_EN 29

AAT4250IGV-T1-GP

AG1-A-SA
AG1-A-SA

74.04250.A3F

2nd
BLUE1

6
4
3
2

USBPN4 16
USBPP4 16
3D3V_BT_S0

1
5
ETY-CON4-16-GP
20.F0760.004
CONNECTOR

1st source: 20.D0197.104

MDC 1.5 CONNECTOR

SCD47U10V3ZY-GP

1
10R2J-2-GP

TPAD28
3D3V_S5
<Core Design>
ACZ_BTCLK_MDC 26

Wistron Corporation

C243

R213

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

C258
DUMMY-C2
Title

USB / MDC / BLUETOOTH

2nd source: 20.F0604.012

R47

1 C40

TPAD28

TP7

DY

DY
2

TP5

100KR2J-1-GP

15,26 ACZ_SYNC
15 ACZ_SDATAIN1
15,26 ACZ_RST#

3
4
5
6
A CZ_SYNC
7
8
R49 2
ACSDATAIN1_A 9
1
10
0R0402-PAD
ACZ_RST#
11
12
MH2
17
16
18
C41
SC22P50V2JN-4GP
AMP-CONN12A-GP
CONNECTOR
20.F0582.012

15,26 ACZ_SDATAOUT

15
14
2

0R0402-PAD
R44
ACZ_SDATAOUT
2
1

2nd

SC4D7U10V5ZY-3GP

MDC1

13
MH1
1

Size
A3

AG1-910-01

Document Number

Rev

AG1(Alviso)

Date: Friday, October 28, 2005

Sheet

01
21

of

40

TGP0

TGP1

16,24,28 PCI_C/BE#[3..0]

2
1

TGN1

2
1

TGN0

CLOSE TO
LAN CHIP

RN67
SRN49D9F-GP

16,24,28 PCI_AD[31..0]

RN69
SRN49D9F-GP

C355
SCD01U50V3KX-4GP

C254
SC15P50V3JN-GP

X3
XTAL-25MHZ-70GP

3
4
1
C352
SCD01U50V3KX-4GP

MID1X

MID0X

3
4

AG1-910-SB
LAN_X2

AG1-A-SA

LAN_X1

C255
SC15P50V3JN-GP
3D3V_LAN_S5
U48

ACT_LED#
LDVDD
RTL_LED1#
LAN_EESK
LDVDD
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
LAN_EECS_3

R304

1
3

RTL_LED1# 23

2
5K6R3F-GP

VCC
DC
ORG
GND

8
7
6
5

CS
SK
DI
DO

C350

AT93C46-10SU-1GP

EEPROM LED OPTION USE '01'

(DEFINED IN SPEC)
=> LED0 : ACT
=> LED1 : LINK
(BOTH 10/100 AND GIGA CHIP)

ACT_LED# 23

1
2
3
4

SCD1U16V2ZY-2GP

LAN_X2

LAN_EECS_3
LAN_EESK
LAN_EEDI
LAN_EEDO

1 R302
2 10KR2J-2-GP
1
2
R303
3K6R3-GP

3D3V_LAN_S5
3D3V_LAN_S5

DY
LAN_X1

3D3V_LAN_S5
3D3V_LAN_S5

PCI_AD0
PCI_AD1

LDVDD
PCI_AD31
PCI_AD30

1
2

1
2

XTAL1

XTAL2

VSS

VSS

CTRL18

AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LANWAKE
PCIAD0
PCIAD1

C364

PCI_PAR 16,24,28
PCI_SERR# 16,24,28

3D3V_LAN_S5

PCI_PERR#
PCI_STOP#
PCI_DEVSEL#
PCI_TRDY#
PM_CLKRUN#

R306
0R0603-PAD

PCI_PERR# 16,24,28
PCI_STOP# 16,24,28
PCI_DEVSEL# 16,24,28
PCI_TRDY# 16,24,28

1
2

PCI_AD27
PCI_AD26
3D3V_LAN_S5

AG1-910-01
R311
PCI_AD23

100R2F-L1-GP-U

LAN_IDSEL

PCI_AD19
LDVDD
PCI_AD20

PCI_IRDY# 16,24,28
PCI_FRAME# 16,24,28

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

G42

3D3V_LAN_S5
3D3V_S5

RTL8100CL

3D3V_LAN_S5
Size
A3

GAP-CLOSE-PWR

Document Number

Rev

AG1(Alviso)

Date: Tuesday, October 25, 2005

A

SCD1U16V2ZY-2GP

<Core Design>

LDVDD
P CI_IRDY#
PCI_FRAME#
PCI_C/BE#2
PCI_AD16
PCI_AD17
PCI_AD18

PCI_AD25
PCI_AD24
PCI_C/BE#3
LDVDD
LAN_IDSEL
PCI_AD23
PCI_AD22
PCI_AD21

C357

C356
SC1U10V3ZY-6GP

GIGALAN: RTL8110SBL
10/100 LAN:RTL8100C

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

RTL8100CL-U
Y

LAVDDL

PM_CLKRUN# 16,24,28,29

PCIAD27
PCIAD26
VDD33
PCIAD25
PCIAD24
CBEB3
VDD18
IDSEL
PCIAD23
GND
PCIAD22
PCIAD21
VSSPST
GND
PCIAD20
VDD18
PCIAD19
VDD33
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAME#
GND
IRDY#
VDD18

PCI_AD29
PCI_AD28

C353

PCI_GNT#2
PCI_REQ#2

PCI_AD15
LDVDD
PCI_C/BE#1
PCI_PAR
PCI_SERR#

C369

INT_PIRQE#
3D3V_LAN_S5
16,24,28 PCIRST1#
3
PCLK_LAN
16
PCI_GNT#2
16
PCI_REQ#2
16,29 ICH_PME#

PCI_AD13
PCI_AD14

C354

16

C351

PCI_AD10
PCI_AD11
PCI_AD12

ISOLATE#
LDVDD

1
2
R307 15KR2F-GP

LDVDD

PCI_AD8
PCI_AD9

SCD1U16V2ZY-2GP

LAVDDL

PCI_AD7
PCI_C/BE#0

SCD1U16V2ZY-2GP

BCP69T1-1-GP
Q33

SCD1U16V2ZY-2GP

LAVDDL

3 1 R308
2
1KR2J-1-GP

CTRL25

AG1-910-01
1

LDVDD
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6

SCD1U16V2ZY-2GP

LDVDD

3D3V_LAN_S5

PCI_AD2

D30
BAT54-4-GP

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

TGP1
TGN1
LAVDDL
CTRL25

PCIAD2
VSSPST
GND
VDD18
PCIAD3
PCIAD4
PCIAD5
PCIAD6
VDD33
PCIAD7
CBEB0
VSSPST
PCIAD8
PCIAD9
M66EN
PCIAD10
PCIAD11
PCIAD12
VDD33
PCIAD13
PCIAD14
VSSPST
GND
PCIAD15
VDD18
CBEB1
PAR
SERR#
NC
GND
NC
VDD33
PERR#
STOP#
DEVSEL#
TRDY#
VSSPST
CLKRUN#

TGP1
TGN1

MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATE#
VDD18
INTA#
VDD33
PCIRST#
PCICLK
GNT#
REQ#
PME#
VDD18
PCIAD31
PCIAD30
GND
PCIAD29
PCIAD28
VSSPST

23
23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

TGP0
TGN0
LAVDDL

TGP0
TGN0

SC10U10V5ZY-1GP

3D3V_S0

23
23

AVDD18

VSS
RSET

SCD1U16V2ZY-2GP

C365

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

121

122

123

124

125

126

U39

128
127

RSET

01

Sheet
E

22

of

40

10/100M Lan Transformer

2nd

U14
22
22

XRF_TDC
C215
SCD1U16V2ZY-2GP

TD+
TD-

6
14
11
3

CT
CT
CT
CT

TX+
TX-

10
9

RD+
RD-

1
2

RX+
RX-

16
15

TDP_RJ45-1
TDN_RJ45-2
TGP1
TGN1

22
22

RDP_RJ45-3
RDN_RJ45-6

RJ45_45
RJ45_78

4
3
2
1

1
2

C174
SCD1U16V2ZY-2GP
2
1

XRF_RDC

DY

7
8

TGP0
TGN0

RN1
SRN75J-1-GP

5
6
7
8

C31
LAN_TERMINAL 1

SC1KP2KV8KX-LGP
C445

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

SCD01U50V3KX-4GP

DY
AG1-910-SB

LAN Connector
AG1-910-01
LAN1

R20

3D3V_S5
22 ACT_LED#

9
CONN_PWR_B2 B1
2
1
470R2J-2-GP
NP1
ACT_LED#
B2
TDP_RJ45-1
RJ45_1
TDN_RJ45-2
RDP_RJ45-3

MDCW1

3
1
2

RJ45_2
RJ45_3
RJ45_4
RJ45_45
RJ45_5
RDN_RJ45-6
RJ45_6
RJ45_7
RJ45_78
RJ45_8
A1
R33
CONN_PWR
2
1
A2
3D3V_S5
470R2J-2-GP
RTL_LED1#
A3
22 RTL_LED1#
RING
RJ11_1
TIP
RJ11_2
B2:YELLOW
NP2
10
A1:ORANGE

2nd
TIP_MDC
RING_MDC

1
1

L2
L1

2 0R0603-PAD
2 0R0603-PAD

TIP
RING

4
ACES-CON2-GP-U
20.F0714.002
CONNECTOR

AG1-910-01

2nd source: 20.D0196.102

RJ45-107-GP
connector
22.10245.J01

A3:GREEN

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN CONN
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Saturday, October 29, 2005

A

01

Sheet
E

23

of

40

AG1-910-01
R182
4K7R2J-2-GP

C276
SCD1U16V2ZY-2GP

3D3V_S0
RN50
CB_MFUNC5
CB_MFUNC4
INT_SERIRQ
CB_MFUNC2

C280
SCD1U16V2ZY-2GP

1
2

1
2

C289
SC1000P50V3JN-GP

CBB_D[0..15] 25
CBB_A[0..25] 25

3D3V_S0

3D3V_S0

CB1410_GBRST#

3D3V_S0

3D3V_S0

1
2
3
4

C261
SCD1U16V2ZY-2GP

8
7
6
5

SRN10KJ-4-GP
3D3V_S0

16,22,28 PCI_FRAME#
16,22,28 PCI_IRDY#
16,22,28 PCI_TRDY#
16,22,28 PCI_STOP#
PCI_AD25
R188
1
2
100R2F-L1-GP-U
16,22,28 PCI_DEVSEL#
16,22,28 PCI_PERR#
16,22,28 PCI_SERR#
16,22,28 PCI_PAR

AG1-910-01
2

PCLK_PCM
16,22,28

1
2

TP95
16
16

PCI_GNT#0
PCI_REQ#0

DY

C271
SC22P50V2JN-4GP

DY

CLK33_PCM12

R187
10R2J-2-GP

PCIRST1#

C_BE3#
C_BE2#
C_BE1#
C_BE0#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
PAR
PCI_CLK
RST#
RI_OUT#/PME#
GNT#
REQ#

C267
SC10P50V2JN-4GP

25
25
25
25

VCCD1#
VCCD0#
VPPD1
VPPD0
3D3V_S0

1
R184

CBB_D3 25
CBB_D2 25
CBB_D1 25
CBB_D0 25
CBB_OE# 25
CBB_WE# 25
CBB_IORD# 25
CBB_IOWR# 25

CBB_D1
CBB_D0
CBB_OE#
CBB_IORD#
CBB_IOWR#

4
3
2
1
5
6
7
8

90
126

63
AUX_VCC

SOCKET_VCC
SOCKET_VCC

14
66
86
102
122
138
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC

GRST# CORE_VCC

GND
GND
GND
GND
GND
GND
GND
GND

2
10KR2J-3-GP

R191

CBB_REG# 25
CBB_A25 25
CBB_RESET
CBB_A24 25
CBB_OE#
CBB_A23 25
CBB_CE2#
CBB_A22 25
CBB_CE1#
CBB_A21 25
CBB_A20 25
CBB_A19 25
CBB_A18 25
CBB_A17 25
1
2 33R2J-2-GP
CBB_A15 25
CBB_A14 25
CBB_A13 25
CBB_A12 25
CBB_A11 25
CBB_A10 25
CBB_A9 25
CBB_A8 25
CBB_A7 25
CBB_A6 25
CBB_A5 25
CBB_A4 25
CBB_A3 25
CBB_A2 25
CBB_A1 25
CBB_A0 25
CBB_D15 25
CBB_D14 25
CBB_D13 25
CBB_D12 25
CBB_D11 25
CBB_D10 25
CBB_D9 25
CBB_D8 25
CBB_D7 25
CBB_D6 25
CBB_D5 25
CBB_D4 25 VCC_ASKT_S0

12
27
37
48
28
29
31
33
CARD_IDESL 13
32
34
35
36
21
20
59
2
1

REG#/CCBE3#
A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RFU
A17/CAD16
A16/CCLK#
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12
A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RFU
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RFU
D1/CAD29
D0/CAD27
OE#/CAD11
WE#/CGNT#
IORD#/CAD13
IOW#/CAD15
WP/IOIS16/CCLKRUN#
INPACK#/CREQ#
RDY_IREQ#/CINT#
WAIT#/CSERR#
CD2/CCD2#
CD1/CCD1#
CE2/CAD10
CE1#/CCBE0#
RESET/CRST#
BVD2/SPKR/LED/AUDIO
BVD1/STSCHG/RI/CSTSCHG
VS2/CVS2
VS1/CVS1

CBB_REG#
CBB_A25
CBB_A24
CBB_A23
CBB_A22
CBB_A21
CBB_A20
CBB_A19
CBB_A18
CBB_A17
A_CCLKXX
CBB_A15
CBB_A14
CBB_A13
CBB_A12
CBB_A11
CBB_A10
CBB_A9
CBB_A8
CBB_A7
CBB_A6
CBB_A5
CBB_A4
CBB_A3
CBB_A2
CBB_A1
CBB_A0
CBB_D15
CBB_D14
CBB_D13
CBB_D12
CBB_D11
CBB_D10
CBB_D9
CBB_D8
CBB_D7
CBB_D6
CBB_D5
CBB_D4
CBB_D3

AG1-910-01
CBB_A16 25
3

AG1-910-01
R192
10KR2J-3-GP

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

SRN47KJ-L1-GP
RN52

U40

125
116
113
111
109
107
105
103
100
98
108
110
104
101
112
95
89
97
99
115
118
120
121
124
127
128
129
87
84
82
80
77
144
142
140
85
83
81
79
76
143
141
139
92
106
93
96
136
123
132
133
137
75
91
88
119
134
135
117
131

CBB_WP 25
CBB_INPACK# 25
CBB_RDY 25
CBB_WAIT# 25
CBB_CD2# 25
CBB_CD1# 25
CBB_CE2# 25
CBB_CE1# 25
CBB_RESET 25
CBB_BVD2# 25
CBB_BVD1# 25
CBB_VS2# 25
CBB_VS1# 25

CBB_CE2#
CBB_CE1#

CB-1410-U

AG1-910-01
Reduce start up noise
RC1
CB_MFUNC2

DY

CB_SPKR 26

2 43KR3-GP
INT_PIRQG# 16
INT_PIRQB# 16

16,22,28 PCI_C/BE#[3..0]

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C288
SCD1U16V2ZY-2GP

AG1-910-01
R185
47KR2J-2-GP

INT_SERIRQ 16,28,29

CB_MFUNC4
CB_MFUNC5

<Core Design>

Wistron Corporation

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

VCCD1#/SMBCLK/SCLK
VCCD0#/SMBDATA/SDATA
VPPD1
VPPD0/SLATCH
SUSPEND
O2MF6
O2MF5
O2MF4
O2MF3
O2MF2
O2MF1
O2MF0
SPKR_OUT#

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

74
73
72
71
CBUS_SUSPEND
70
69
68
67
65
64
61
60
62

16,22,28 PCI_AD[31..0]

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

18
30
44
50

6
22
42
58
78
94
114
130

C269
SC1000P50V3JN-GP

C265
SCD1U16V2ZY-2GP

1
C274
SCD1U16V2ZY-2GP

1
2

C264
SC1000P50V3JN-GP

VCC_ASKT_S0

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

PM_CLKRUN# 16,22,28,29

AG1-910-01

Title

CardBus_ENE CB1410
Size
A3

Document Number

Rev

AG1(Alviso)

Date: Tuesday, November 01, 2005

A

01

Sheet
E

24

of

40

Cardbus I/F
CBB_IORD# 24
CBB_IOWR# 24
CBB_OE# 24
CBB_WE# 24
CBB_REG# 24
CBB_RDY 24
CBB_WP 24
CBB_RESET 24
CBB_WAIT# 24
CBB_INPACK# 24

CBB_CE1#
CBB_D15
CBB_A10
CBB_CE2#
CBB_OE#
CBB_VS1#

VCC_ASKT_S0
CBB_A11
SCD1U16V2ZY-2GP

C375

DY

C379

SC10U10V5ZY-1GP
2
1

CBB_IORD#
CBB_A9
CBB_IOWR#
CBB_A8
CBB_A17
CBB_A13
CBB_A18
CBB_A14
CBB_A19

C374
SC1000P50V3JN-GP

CBB_WE#
CBB_A20
C BB_RDY
CBB_A21

VPP_ASKT_S0

CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6

C372
SCD1U16V2ZY-2GP

CBB_VS2#
CBB_A16

CBB_A5
CBB_RESET
CBB_A4
CBB_WAIT#
CBB_A3
CBB_INPACK#
CBB_A2

CBB_REG#
CBB_A1

Place close to pin 19.

CBB_BVD2#

C371
DUMMY-C2

CBB_BVD1#
CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10

CBB_A0

24

CBB_WP
CBB_CD2#

CBB_CD2#

VCC_ASKT_S0

CBB_CE1# 24
CBB_CE2# 24
CBB_BVD1# 24
CBB_BVD2# 24

1
C362
SCD1U16V2ZY-2GP

4K7R2J-2-GP
R318

C361
SC1U10V3ZY-6GP

U50
C363
SCD1U16V2ZY-2GP

C358
SC1U10V3ZY-6GP

CBB_VS1# 24
CBB_VS2# 24

TP96
24
24

TPAD28

VCCD0#
VCCD1#

3
4
5
6
9

3.3V
3.3V
5V
5V
12V

1
2

VCCD0#
VCCD1#

15
14

24 VPPD0
24 VPPD1

VPPD0
VPPD1

AG1-910-01

2211_SHDN#

SHDN#

16

AVCC
AVCC
AVCC

13
12
11

VCC_ASKT_S0

10

VPP_ASKT_S0

AVPP
OC#

GND

TPS2211AIDBR-1GP

PC1

CARDBUS-SKT43-GP
21.H0057.011
CONNECTOR

70

R309
DUMMY-R2

CARDBUS68P-15-GP
62.10024.671
CONNECTOR

4 7K

NP2

Clock AC termination
33MHz clock for 32-bit
Cardbus card I/F

5V_S0

CBB_CD1#

24
CBB_CD1#
CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14

3D3V_S0
3D3V_S0

CBB_D3
4

35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

69

Power switch

CBB_D[0..15] 24
CBB_A[0..25] 24

PCH1

NP1

PCMCIA Socket

C359
SCD01U16V2KX-3GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCMCA
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Tuesday, October 25, 2005

Sheet
E

25

of

40

CB_SPKR

ALC655 AC97 AUDIO CODEC

C368
24

SCD47U10V3ZY-GP
RN70

ACZ_SPKR

CB_SPKR1
ACZ_SPKR1
KBC_BEEP1

1
2
3
4

C367

29

AUDIP_PC_BEEP

SCD1U16V2ZY-2GP

SRN47KJ-L1-GP

KBC_BEEP

C377
1
2

AUDIO_BEEP

SCD47U10V3ZY-GP

8
7
6
5

16

R317
22KR2J-GP

C373
SC3900P50V3KX-GP

AG1-910-SB

3
2

24
23

LINEIN_R
LINEIN_L

SDOUT
SDIN

SURR-OUT-R
SURR-OUT-L

41
39

JD1/GPIO1
JD2

17
16

AUX-R
AUX-L

15
14

SPDIFI/EAPD
SPDIFO
XTL-OUT
XTL-IN
NC#40
NC#33
40
33

AVDD
AVDD
25
38

1
9

VDD
VDD

AG1-910-01

LINE_IN_R 27
LINE_IN_L 27

C383
SC1U10V3ZY-6GP

CD-GND
CD-R
CD-L
LINE-R
LINE-L

SOUNDR 27
SOUNDL 27

SC1U10V3ZY-6GP
C387
2
1 LINE_IN_R
2
1 LINE_IN_L

C397

C396

37

44
43

13
12

42
26

19
20
18

36
35

MIC_IN 27

XTLSEL
JD0/GPIO0

47
48

R319
1
2
0R0402-PAD

CLK_Audio

46
45
5
8

AC97_SDIN
2
47R2J-2-GP

1
R316

15 ACZ_SDATAIN0

SYNC
BITCLK

1 MIC_IN
SC1U10V3ZY-6GP

SC1000P50V3JN-GP

15,21 ACZ_SDATAOUT

10
6

C381

SC1000P50V3JN-GP

EPSON
FA-365 20PF
50PPM

0R0402-PAD
R315 1
2

FRONT-OUT-R
FRONT-OUT-L

SOUNDR
SOUNDL

CODEC_XTLSEL

AG1-910-01

MIC

DY

3D3V_S0_AU
AFLT1
AFLT2
VRDA

VREFOUT

2 SC3300P50V2KX-1GP
2 SC1000P50V3JN-GP
2 SC1U10V3ZY-6GP

1
1
1

AC97_BTCLK
ACZ_RST#

1
2
3

ALC655_VREF

A
B
GND

VCC

3D3V_S0_AU
R312 1

2 33R2J-2-GP

ACZ_BITCLK 15

NC7SZ08M5X-NL-GP R310 1

2 33R2J-2-GP

ACZ_BTCLK_MDC 21

AG1-910-01
C392
SCD1U16V2ZY-2GP

C400
SC1U10V3ZY-6GP
C391
SCD1U16V2ZY-2GP

1
2

C404
SC1U10V3ZY-6GP

AG1-910-01

U51

VREFOUT 27

C393
SCD1U16V2ZY-2GP

C390
C399
C398

ALC655_VREF

SCD1U16V2ZY-2GP
C376
2
1

SCD1U16V2ZY-2GP
C279
2
1

5VA_S0

C382
SCD1U16V2ZY-2GP

AFILT2
AFILT1

AC97_BTCLK
0R0402-PAD
R321 1
2

22
21

30
29

15,21 ACZ_SYNC

U52
ALC655-U-GP
Y

MIC2
MIC1

RESET#

VRAD
VRDA

11

15,21 ACZ_RST#

MONO-OUT-R

10R2J-2-GP

32
31

DY

LFE-OUT
CEN-OUT

SCD47U10V3ZY-GP

FRONT-MIC
VREFOUT
VREF

34
28
27

DY 1

PHONE
PC-BEEP

R314

AGND
AGND

C370

GND
GND

7
4

SCD47U10V3ZY-GP

C366

R313

1
2
0R0402-PAD

AC97_BTCLK1

AG1-910-01

1
C449

GND

IN

5
3D3V_S0_AU

OUT

4
1
C416

C451

C450

SC2D2U16V5ZY-2GP

G923-330T1UF-1GP

C389
SC2D2U16V5ZY-2GP

SC22P50V2JN-4GP

1
2

C384
SC1U10V3ZY-6GP

G923-330T1UF-1GP

SHDN# SET

SC1U10V3ZY-6GP

R333
10KR3F-L-GP

AG1-910-01
1

OUT

5VA_SETPIN

DY

0R3-0-U-GP

U63

IN

GND

R370

3D3V_S0
R332
28K7R3F-GP

SC1U10V3ZY-6GP

SHDN# SET

5V_S0

SC1U10V3ZY-6GP

C409

U53

*Layout*
20 mil

5V_S0

5VA_S0

C407
SC22P50V2JN-4GP

POWER GENERATE

<Core Design>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AG1-910-01

AC'97 CODEC - ALC655

Size
A3

Document Number

Rev

Date: Tuesday, November 01, 2005

A

01

AG1(Alviso)
Sheet
E

26

of

40

AUDIO OP AMPLIFIER
AG1-910-SB

I/P signal level

need +5V level
OP+5V
R335
1
2
0R0603-PAD
1

1
R320
10KR2J-3-GP

NC#9
NC#11
GND
SGND
PGND

SPKR_L+1
SPKR_R+1

AG1-910-SB

HP_R

2
1
R323
10KR2J-3-GP
2
1
2

C443
SC2D2U16V5ZY-2GP

AG1-910-01

1
3

C388
SC470P50V2KX-3GP

GND

HP_L

2
1
R194
10KR2J-3-GP

C294
SC470P50V2KX-3GP

3
Q34
CHDTC124EU-1GP

C442
SC2D2U16V5ZY-2GP

17
2
13

G1410Q4U-GP

5
7

3
15

OUTL
OUTR
SVSS
PVSS

SHDNR#
SHDNL#

SYS_LOUT_IN

C395

9
11

SVDD
PVDD
1
16

12
14

HP_R

C401
SC1U10V3ZY-6GP

R365
100KR2J-1-GP

29 KBC_MUTE

BAT54C-1-GP

R322
10KR2J-3-GP

IN

SYS_LOUT_IN 2

SOUND_R1

DY

C386

G1432Q5U-GP

MUTE_5

MUTE
11
29 KBC_MUTE

C385
SC1U10V3ZY-6GP

C1N
C1P

R2

SOUNDR

INL
INR

R1

D31

1
R326
10KR2J-3-GP

4
8

U62

OUT

AG1-910-01

SOUND_R_OP1

16
1

RBYPBASS

26

10KR2J-3-GP
R193
1
2 HP_L

NC#6
NC#8
NC#23

SPKR_R+
SPKR_R-

SOUNDR

SC1U10V3ZY-6GP
C293
SOUNDL
1
2 SOUND_L1

6
10

13
IN1#/IN2

LBYPASS

18
17
19
12

SC1U10V3ZY-6GP
10KR2J-3-GP
R327
C394
SOUND_R_OP1 2
SOUND_R2 2
1
1

SC2D2U16V5ZY-2GP

6
8
23

DY

RIN1
RIN2
ROUT+
ROUT-

GND
GND

C298
SC1U10V3ZY-6GP

LIN1
LIN2
LOUT+
LOUT-

AG1-910-01

14
25

2
R195
10KR2J-3-GP
1

20
4
15
VOL
LVDD
RVDD

SPKR_L+
SPKR_L-

1
2
24
7

SHUTDOWN

SOUND_L_OP1

SOUND_L_OP1

SC2D2U16V5ZY-2GP

C446

GND/HS
GND/HS
GND/HS
GND/HS

SOUNDL

AG1-910-SB

AG1-910-01

9
10
21
22

26

AG1-910-01
3D3V_S0_AU

TP28
TPAD28

DY

U61
SC1U10V3ZY-6GP
10KR2J-3-GP
C299
R196
1
2 SOUND_L2 1
2

29

C441
SC10U10V5ZY-1GP

C406
SCD1U16V2ZY-2GP

1
2

C410
SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

AMP_SHUTDOWN
C405

SC2D2U16V5ZY-2GP

5V_S0

AG1-910-01

LINE OUT
Y
MIC2

AG1-910-01

EC59

LINE IN
SRN1KJ-7-GP

26
26

2
1

LINE_IN_R
LINE_IN_L

AUD_LINE_R
AUD_LINE_L

3
4

1
2
C

C408
SC100P50V2JN-3GP

SC100P50V2JN-3GP

C411

4
3

RN54

RN55
SRN10KJ-5-GP

4
3
2

SPKR_R+

SPKR1
CONNECTOR
2nd

SRC100P50V-2-GP
ERC8

1st source: 20.D0197.104

AG1-A-SA

SPKR_LSPKR_L+
SPKR_R-

8
7
6
5

DY

ETY-CON4-16-GP
6

LOUT1 CONNECTOR
22.10138.091
Y

C402
SC680P50V2KX-2GP

C403

RN56
SRN1KJ-7-GP

2
SC330P50V2KX-1GP

C302
SCD1U16V2ZY-2GP

PHONE-JK221-GP
22.10138.101

1
R206

SPKR_L+1

INT_MIC

SYS_LOUT_IN
SPKR_R+1

C301
SC3300P50V2KX-1GP

MIC_IN

100KR2J-1-GP
1 R368
2

2
1

30
26

INT_MIC
2 EXT_MIC_IN_1
300R3-GP

Internal Speaker

NP2
NP1
8
7
5
4
3
6
2
1

AG1-910-01

NP2
NP1
8
7
5
4
3
6
2
1

20.F0760.004

PHONE-JK222-GP-U

3
4

C300
SC4D7U10V5ZY-3GP

R199
2K2R2J-2-GP
2

AG1-910-01

VREFOUT
1

26

SYS_LOUT_IN=High after PLUG-IN

R364
1
2
2K2R2J-2-GP

SC680P50V2KX-2GP
2

AG1-A-SB
3D3V_S0_AU

EXT\Internal MIC IN

1
2
3
4

AG1-A-SA

AG1-A-SA
AG1-910-01

PHONE-JK222-GP-U
NP2
NP1
8
7
5
4
3
6
2
1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LIN1
Y

CONNECTOR
22.10138.091

Audio AMP and Jack

Size

Document Number

Rev

01

AG1(Alviso)
Date: Monday, October 31, 2005
D

Sheet
E

27

of

40

1
2

1
2

C93
SCD1U16V2ZY-2GP

16,22,24 PCI_AD[31..0]

C125
SCD1U16V2ZY-2GP

2
4

C110
SCD1U16V2ZY-2GP

3D3V_S0

MINI1

BT_COEX2
PCI_C/BE#3
PCI_AD23

16,22,24 PCI_C/BE#3

PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2

16,22,24 PCI_C/BE#2
16,22,24 PCI_IRDY#
16,22,24,29 PM_CLKRUN#
16,22,24 PCI_SERR#
16,22,24 PCI_PERR#
16,22,24 PCI_C/BE#1

PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10

PCI_AD1

3
80211_ACTIVE

2N7002PT-U
Q17

1
G

AG1-910-01

2 PCI_AD21
R123
100R2J-2-GP

PCI_PAR 16,22,24

PCI_AD18
PCI_AD16

WIRELESS_EN

2N7002PT-U
Q20

1
G

PCI_FRAME# 16,22,24
PCI_TRDY# 16,22,24
PCI_STOP# 16,22,24

PCI_DEVSEL# 16,22,24
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C/BE#0

AG1-A-SA
PCI_C/BE#0 16,22,24

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

Q16
CHDTC124EU-1GP

INT_SERIRQ 16,24,29

GND

124
126

PCI_AD22
PCI_AD20

TPAD28 TP38

C106
SC22P50V2JN-4GP

IN

123

PCI_AD28
PCI_AD26
PCI_AD24
MOD_IDSEL

TP39

R2

PCI_AD3
5V_S0

TPAD28

PME#_MINI
BT_COEX1
PCI_AD30

R1

PCI_AD5

OUT

PCI_AD8
PCI_AD7

PCI_GNT#1 16

TP40

PCI_AD27
PCI_AD25

TPAD28

PCIRST1# 16,22,24
3D3V_S0

PCI_AD31
PCI_AD29

WLAN_LED# 13

PCI_REQ#1

INT_PIRQF# 16

16

R129
100KR2J-1-GP

5V_S0

3 PCLK_MINI
3

AG1-910-01
PIN 3-16 : LAN RESERVE

TPAD28

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122

TP41

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121

3D3V_S0

INT_PIRQF#
3D3V_S0

125
2

80211_ACTIVE
29 WIRELESS_EN

29 WLAN_TEST_LED

PCISLT124-4-GP
CONNECTOR
62.10032.061

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI-PCI
Size
A3

Document Number

Rev

01

AG1(Alviso)

Date: Tuesday, October 25, 2005

Sheet
E

28

of

40

3D3V_AUX_S5

AG1-910-SB
1
KCOL[1..16] 30
KROW [1..8] 30

3D3V_S0

1
2
3
4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
81
82
83
84
87
88
89
90

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7

GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7

S
S

100KR2J-1-GP

100KR2J-1-GP
R170
2
1

AG1-910-01

AG1-A-SA

PM_PWRBTN#

KBC_MUTE 27
KEY5# 30

3D3V_AUX_S5

RN29

W IRELESS_BTN# 30

KBRCIN#
KA20GATE

39
39

KEY4# 30

2
1

BAT_SCL
BAT_SDA

3
4

BAT_IN# 39
SRN8K2J-3-GP
ECSMI#

ECSMI# 16
W IRELESS_EN 28
PM_CLKRUN# 16,22,24,28
FPBACK 13
NUM_LED# 13
BLUETOOTH_EN 21
DC_BATFULL# 13
BLT_LED# 13
WLAN_TEST_LED 28
MAIL_LED# 30
CHARGE_LED# 13

KBC_SLP_WAKE 2
1
R285
10KR2J-2-GP
PRE_CHG
2
1
R286
10KR2J-2-GP

PLT_RST1# 7,16,18
3D3V_S5

DY
DY

R296
100KR2J-1-GP

VCC3VSB

AG1-910-01

KBC_PCIRST#
1 R297
BL_ON 0R0402-PAD

AMP_SHUTDOWN 27

BL_ON 7

C332
SC1U10V3ZY-6GP

C336
SC150P50V2JN-3GP

CHANGE TO 71.03910.B0G

AG1-910-SB
3D3V_AUX_S5

SRN10KJ-5-GP

PM_PWRBTN#
RSMRST#_KBC
S5_ENABLE
BRIGHTNESS

C413

GAP-OPEN
G11

PM_SLP_S3#
KBC_PWRBTN#
AC_IN#
KBC_LID#
KBC_SLP_WAKE

AG1-910-01
R240
10KR2J-3-GP

CAP_LED# 13
FRONT_PW RLED# 13,30

2
16,18,32,35,37
30
38
30
16

1
D

160
158

BAT_SCL
BAT_SDA
KBC_SCL2
KBC_SDA2

XCLKO
XCLKI

INTERNET# 30
MAIL# 30
PM_SLP_S4# 16,37
3S1P_I 38
PM_SUS_STAT# 16

KBC_SLP_WAKE

2
1

CH3906PT-GP
Q28

3
4

RSMRST# 19
35

RN49

S5_ENABLE

AG1-910-01
R34
100KR2F-L1-GP

16
16,32
35
13

3D3V_S5

BAT_IN#
KBC_BB_ENABLE#

STDBY_LED# 13

ECSW I#

A1

R186
10KR2J-3-GP

TP56

E51CS#

EC_RST#
E CSCI#

KBC_BEEP

KBC_BB_ENABLE#

26
16

99
100
101
102
1
42
47
174

SRN10KJ-5-GP

RSMRST#_KBC

43
40
39
38
37
36
33
32

TDATA_5
TCLK_5

AG1-910-01

168
175
171
165
162
156

E51TXD

AG1-910-01

RN26

4
3

SCL1
SDA1
SCL2
SDA2

PS/2

SRN10KJ-4-GP

1
2

163
164
169
170

71
72
73
74
77
78
79
80

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

161

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1

GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A

5V_S0

1
2
3
4

98
97
94
93
92
91

MATRIXID2# 31
MATRIXID1# 31
PRE_CHG 38
BLT_BTN# 30
CHG_ON# 38
AD_OFF 39

SMBC_G792 19
SMBD_G792 19

117
116
115
114
111
110

GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A

SMBC_G792
SMBD_G792
3D3V_AUX_S5

TDATA_5
TCLK_5

41
28
27
25
24
23

RN25

8
7
6
5

30
30

GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A

SCD1U16V2ZY-2GP

5V_S0

GND
GND
GND
GND
GND
GND

ECSCI#

17
35
46
122
137
167

AGND
BATGND

96
159

KBRCIN#

KB3910

ECRST#
ECSCI#

X-bus
ROM

Q30
2N7002PT-U

155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3

2
Q31
2N7002PT-U

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

KBC_SCL2
KBC_SDA2

GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00

124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

2
26
29
30
44
76
172
176

ECSCI#_1

31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31

D0
D1
D2
D3
D4
D5
D6
D7

C327
SC22P50V2JN-4GP
U44

LPC

BRIGHTNESS

KBRCIN#_1

KA20GATE

CH731UPT-GP

RN41
SRN10KJ-4-GP

138
139
140
141
144
145
146
147

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

KBC_XI

KB Matrix

PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0

15

16

LFRAME#
LCLK
SERIRQ
RD#
WR#
MEMCS#
IOCS#

KBC_D[0..7]

D20

9
18
7
150
151
173
152

LAD0
LAD1
LAD2
LAD3

19
31

31

KBCBIOS_RD#
KBCBIOS_WE#
KBCBIOS_CS#

15
14
13
10

VCCBAT

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA

2
16
34
45
123
136
157
166
95

C182
SCD1U16V2ZY-2GP

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

31 KBCBIOS_RD#
31 KBCBIOS_WE#
31 KBCBIOS_CS#

C179

SCD1U16V2ZY-2GP

0R0603-PAD

15 LPC_LFRAME#
3
PCLK_KBC
16,24,28 INT_SERIRQ

KA20GATE_1

3D3V_KBC_AUX_S5

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1 L10

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

C217

15 LPC_LAD[0..3]

15

C326
SC22P50V2JN-4GP
X4

AG1-910-SB

1
C191

SCD1U16V2ZY-2GP

C206

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_AUX_S5

3D3V_AUX_S5

5V_S0

2
8
7
6
5

KBC_XO

100KR2J-1-GP
R176
2
1

R174

Place near K/B Connector (TOP side)

A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable
A4 for DMRP==>High=Disable,Low=Enable
1

A5 for EMWB==>High=Enable,Low=Disable
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)
GPIO06 for DPLL test mode==> High=Test Mode,Low=Normal operation(Recommended)

21 USB_PW R_EN#
<Core Design>
38

3S2P_I

AG1-A-SA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

KBC ENE
Size
Document Number
Custom

R ev

Date: Thursday, October 27, 2005

A

01

AG1(Alviso)
Sheet
E

29

of

40

LAUNCH BD CONN

Cover Up Switch

3D3V_S5

SRN10KJ-4-GP

MAIL_LED#

2 SC100P50V2JN-3GP

COVER_SW# 1

KBC_LID#

100R2F-L1-GP-U

PUSH-SW81-GP
62.40014.141
CONNECTOR

KBC_LID# 29
4

C183
SCD22U16V3ZY-GP

TOUCH PAD

R58
10KR2J-3-GP

MAIL#
29
INTERNET# 29
KEY4#
29
KEY5#
29

AG1-910-01

R169

5V_S0

R61
470R2J-2-GP

EC21

KBC_PWRBTN# 29

EC51
SCD1U16V2ZY-2GP

C58
SCD1U16V2ZY-2GP

1
C189
SC1U10V3ZY-6GP

1
2

SRN470J-3-GP
RN28

8
7
6
5

1
2
3
4

AG1-910-01

1
MAIL_LED# 29

MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1
PWRBTN#

2nd source: 20.K0185.012

EC30 1

3D3V_AUX_S5

29
29

1
2

TDATA_5
TCLK_5

TP_DATA
TP_CLK

4
3

5
6
7
8

SRN100J-3-GP
TP_SCROLL_UP
1 SCRL1
2

TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_DOWN
TP_LEFT
TP_RIGHT

3D3V_S0

TP_SCROLL_LEFT
1 SCRL2
2

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR

TP_SCROLL_LEFT
TP_SCROLL_RIGHT
1 SCRL3
2

2nd

1
2

DY

WLBTN1
EC58
SCD1U16V2ZY-2GP

DY

2
3

2
3

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR

2nd

BLT_BTN# 29

TP_SCROLL_DOWN
1 SCRL4
2

Level Trigger

2nd

2nd source: 20.K0185.012

1 LEFT1

TP_LEFT
2

SW-SLIDE34
62.40018.191
CONNECTOR

TP_RIGHT
1 RIGHT1 2

2nd source: 62.40009.341

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR
2nd

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR
2nd

3
4
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR
2nd

EMI Bypass cap.

Internal KeyBoard CONN

KROW[1..8] 29
KCOL[1..16] 29

KB1

25

NC#26
C01
C02
C03
R01
R02
R03
C04
R04
R05
R06
R07
R08
R09
C05
R10
C06
C07
R11
R12
C08
R13
R14
R15
R16
NC#25
NC#27

........

26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27

KROW1
KROW2
KROW3
KCOL1
KCOL2
KCOL3
KROW4
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KROW5
KCOL10
KROW6
KROW7
KCOL11
KCOL12
KROW8

ACES-CON25-GP

KCOL13
KCOL14
KCOL15
KCOL16

ERC10
ERC6

Pin1 ==>*R01
Pin2 ==>*R02
Pin3 ==>*R03
Pin4 ==> C01
Pin5 ==> C02
Pin6 ==> C03
Pin7 ==>*R04
Pin8 ==> C04
Pin9 ==> C05
Pin10 ==> C06
Pin11 ==> C07
Pin12 ==> C08
Pin13 ==> C09
Pin14 ==>*R05
Pin15 ==> C10
Pin16 ==>*R06
Pin17 ==>*R07
Pin18 ==> C11
Pin19 ==> C12
Pin20 ==>*R08
Pin21 ==> C13
Pin22 ==> C14
Pin23 ==> C15
Pin24 ==> C16
Pin25 ==> NC

KROW7
KCOL11
KCOL12
KROW8

8
7
6
5

TP_DATA
TP_CLK
TP_RIGHT
TP_SCROLL_RIGHT

DY

1
2
3
4

8
7
6
5

1
2
3
4

KCOL2
KCOL3
KROW4
KCOL4

1
2
3
4

SRC100P50V-2-GP
ERC3
8
7
6
5

KCOL9
KROW5
KCOL10
KROW6

1
2
3
4

SRC100P50V-2-GP
ERC5
8
7
6
5

KROW1
KROW2
KROW3
KCOL1

1
2
3
4

SRC100P50V-2-GP
ERC2
8
7
6
5

1
2
3
4

SRC100P50V-2-GP
ERC7
8
7
6
5

DY

ERC9
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN
TP_LEFT

1
2
3
4

8
7
6
5

DY

DY

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY

Title

BUTTONs / KB / TOUCHPAD
Size
A3

Document Number

Rev

01

AG1-910

Date: Tuesday, November 01, 2005

C

SRC100P50V-2-GP

DY

SRC100P50V-2-GP
B

DY

SRC100P50V-2-GP
SRC100P50V-2-GP
ERC4
8
7
6
5

KCOL13
KCOL14
KCOL15
KCOL16

2nd source: 20.K0198.025

1
2
3
4

KCOL5
KCOL6
KCOL7
KCOL8

2nd
20.K0197.025
CONNECTOR

2nd

ACES-CON12-GP
CONNECTOR
20.K0174.012

5
SW-SLIDE34
62.40018.191
CONNECTOR

BTBTN1

1
2

1
2

RN58
SRN10KJ-5-GP

29 WIRELESS_BTN#

1
13

4
3

AG1-A-SB

EC57
SCD1U16V2ZY-2GP

14
12
11
10
9
8
7
6
5
4
3
2

RN27
SRC100P50V-2-GP
ERC1

WIRELESS_BTN#
BLT_BTN#

TPAD1

DY

4
3
2
1

SCD1U16V2ZY-2GP

ACES-CON12-GP
20.K0174.012
CONNECTOR
2nd

AG1-910-01

INT_MIC 27

1
13

LID1

1
2
3
4

EC20
SCD1U16V2ZY-2GP

MAIL_LED#

AG1-910-SB

14
12
11
10
9
8
7
6
5
4
3
2

R167
10KR2J-3-GP

AG1-A-SA

8
7
6
5

MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1

3D3V_S0

LAUNCH1

3D3V_AUX_S5

AG1-A-SA
RN44

Sheet
E

30

of

40

KBC_D[0..7] 29

29 KBCBIOS_WE#
29 KBCBIOS_RD#
29 KBCBIOS_CS#
D

A18
A17
A16

29
29
29

3D3V_AUX_S5

22
24
31

1
30
2
A18
A17
A16

VDD

A15
A14
A13
A12
A11
A10
A9
A8

16

3
29
28
4
25
23
26
27

A15
A14
A13
A12
A11
A10
A9
A8

29
29
29
29
29
29
29
29

A0
A1
A2
A3
A4
A5
A6
A7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

12
11
10
9
8
7
6
5

13
14
15
17
18
19
20
21

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

VSS

29
29
29
29
29
29
29
29

CE#
OE#
WE#

32

U49

C360
SCD1U16V2ZY-2GP

(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT

C

29
29
29
29
29
29
29
29

A0
A1
A2
A3
A4
A5
A6
A7

ROM SIZE MAX. 512KBYTE

3D3V_S0

2
1

PLCC32 Socket P/N:

SSKT3262.10002.032
SSKT32 62.10005.032

SRN10KJ-5-GP
RN8

AG1-910-01
3
4

Plz put G12 close SW1

2
GAP-OPEN
G12

PH at ICH6M

SW1

1
2
3
4

16 CHK_PW#
29 MATRIXID1#
29 MATRIXID2#

SW-DIP-4-2-U2-GP
CONNECTOR

DY

Board ID

3D3V_S0

Keyboard matrix ( from vendor )

16
16

Eur

R221
10KR2J-3-GP

DY

DY

PCB_VER0
PCB_VER1

Other

MATRIXID1#

High Bit

MATRIXID2#

Low Bit

Jap

R243
10KR2J-3-GP

US

PCB_VER0
PCB_VER1

DY

EC44
SC1000P50V3JN-GP

R245
10KR2J-3-GP

R220
10KR2J-3-GP

DY

DY

1
2

5
6
7
8

Planar ID(2,1,0)
SA:
SB:
-1 :

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BIOS ROM
Size
A3

Document Number

Rev

Date: Tuesday, November 01, 2005

5

01

AG1-910
Sheet
1

31

of

40

Run Power
5V_S0
C42
1

Q11
TP0610K-T1-GP

R48

1
2
3
4

SCD1U16V2ZY-2GP
RUN_POWER_ON

2RUN_POWER2

330KR2J-L1-GP

D
D
D
D

3D3V_S0

8
7
6
5

AG1-910-01
1

K
A

AG1-910-01

R51
1KR2J-1-GP

AG1-910-01

S
S
S
G

AO4422-1-GP

D8

3D3V_S0

MMGZ5242BPT-GP

R50

R52
330KR2J-L1-GP

C46

10KR2J-3-GP

RUN_POWER1

PWRGD for NB and SB

5V_S5
U13

U11

1
2
3
4

S
S
S
G

D
D
D
D

R209
1KR2J-1-GP

3D3V_S5

8
7
6
5

AG1-910-01

SCD1U50V3ZY-GP

DCBATOUT

R208

3,34 6218_PGOOD

VGATE_PWRGD 7,16

0R0402-PAD

AO4422-1-GP

PM_SLP_S3 2

AG1-910-01

PWRGD to Turn on CPU_Core_Power

OUT

AG1-A-SA
R1

R2

Q13
CHDTC124EU-1GP

GND

IN

16,18,29,35,37 PM_SLP_S3#

5V_S5

AG1-910-01
R300
10KR2J-3-GP

Aux Power

AG1-910-01

16,29 RSMRST#_KBC

3D3V_AUX_S5

CH3906PT-GP
Q32

R301
10KR2J-3-GP

5V_S5

3D3V_AUX_S5

3D3V_AUX_S5

LP2951CDR2G-GP

C283
SC1U50V5ZY-1-GP

G913CF-GP
C338
SC10U10V5ZY-1GP

OUT

3D3V_G913_SET

1
2

DUMMY-C3

2
1

C282

8
7
6

C341

1
2

Output = 3.3V
output=1.25(1+(Rx/Ry))

R299
10KR2F-2-GP

C343

AG1-910-01

Ry

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OUTPUT
INPUT
SENSE
FEEDBACK
SHUTDOWN
VO TAP
100mA
GND
ERROR# OUTPUT

DUMMY-C5

1
2

1
2

SC1U10V3ZY-6GP

1
2
3
4

C342
SC1U10V3ZY-6GP

C344

SC10U10V5ZY-1GP

U47 SCD1U16V2ZY-2GP
C349
SCD1U16V2ZY-2GP

C337

DCBATOUT

C348
1
2

1
C340

SET

SC1U10V3ZY-6GP

DY

SHDN#
GND
IN

SC1U10V3ZY-6GP

CH521S-30-GP-U

1
2
3

R298
16K5R2F-1-GP

U46
D28

Rx

C339

5V_AUX_2951

SC22P50V2JN-4GP
2
1

5V_S5_G913

2
CH521S-30-GP-U

D29

Title

RUN POWER and 3D3V_AUX_S5

Size
A3

Document Number

Rev

01

AG1-910

Date: Tuesday, October 25, 2005

Sheet

32

of

40

CPU_CORE

PGOOD(OD / 3.3V)

VID1(I / 1.05V)

H_VID2

Input Signal
6218_PGOOD

SHUTDOWN_S5

H_VID3

PM_SLP_S3#

VID3(I / 1.05V)

PM_SLP_S3#

VID5(I / 1.05V)

VCC_CORE(O)

CPUCORE_ON

EN(I / 3.3V)

PM_DPRSLPVR

DRSEN(I / 3.3V)

PM_STPCPU#

DSEN# (I / 3.3V)

STBY_LDO(I / 5V) FOR

1.8V

VCC_CORE (27A)
DCBATOUT_5130

Input Signal

PGOUT(OD / 5V)

DCBATOUT_5130

DCBATOUT

STBY_VREF5(I / 28V)

3D3V (6A)

3D3(O)

STBY_VREF3.3(I / 28V)

5V (6A)

5V(O)

1D05V(O)

1D05V (5.2A)

VIN (I / 28V)

5V_S5

2D5V (O)

REG5V_IN(I / 5V)

Voltage Sense
5V_AUX_S5

VSEN(I / 1.55V / 1.35V)

Output Power

Input Power

VCC_CORE_S0

TPS5130_PWRGD

SS_STBY3(I / 5V) FOR

1.05V

Output Power

VID4(I / 1.05V)

H_VID5

Output Signal

FOR
SS_STBY1(I / 5V) 5V
FOR
SS_STBY2(I / 5V) 3.3V

SHUTDOWN_S5

VID2(I / 1.05V)

H_VID4

TPS5130
3D3V/5V/1D05V/2D5V

Output Signal

VID0(I / 1.05V)

H_VID1

ISL6218CV

VID Setting

H_VID0

2D5V (3.5A)

5V_AUX_S5

5V_S0

For PGOUT

Input Power
DCBATOUT

VCC(I)

5V_S0

VCC(I)

ISL6227
1D8V/1D5V
Input Signal

Output Signal

PM_SLP_S4#

Charger_ISL6255

CHG_ON#/OFF
BAT_IN#

Input Signal
EN (I / 3.3V)
THM (I / 3.3V)

PM_SLP_S3#_ICH

Output Signal

KBC_SDA0
CHG_I_PRE_SEL

CPUCORE_ON

PG2/REF

EN2 (I)

AC_IN

ACPRN (O / 3.3V)

Input Power

Output Power

CHARGE_LED#

XTAL2/PB4 (O/5V)

1D8V_S3 (6A)

1D8V (O)

5V_S5
KBC_SCL0

CPUCORE_ON

PG1

EN1 (I)

VCC (I)

SCL (IO / 5V)

SDA (IO / 5V)
CHLIM (IO / 5V)

1D5V_S0 (6A)

1D5V (O)
Output Power

DCBATOUT

VCC (O)

Adapter

BT+

VCC (O)
PB0/MOSI/AIN0

Input Signal

AD_OFF

(I)

Output Signal
(O)

DC_IN+
<Core Design>

Input Power

Wistron Corporation

DCIN (I)

Input Power
AD_JK

VCC(I)

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Output Power
VCC(O)

AD+

Title

Power Diagram

5V_AUX_S5

Size
A3

VCC(I)

Document Number

Rev

AG1(Alviso)

Date: Monday, October 17, 2005

A

Sheet
E

01
33

of

40

AO4422-1-GP

4
3
2
1

4
3
2
1

L22

R137

L-D56UH-2-GP

DY

K
A

DY

VCC_CORE_S0

TC12

CORE_AGND

R133

C119
SC2200P50V2KX-2GP

2
2

3K57R3F-L-GP

1
2

VCC_CORE_S0

C128
SC1U10V3ZY-6GP

TC6
SE330U2VDM-4-GP
2nd

75KR3F-GP

12.4uA/0.87/0.5 = 28.54uA

1
2

2
1
2

SC1000P50V3JN-GP

1
2

R124

DY

C130

TC14
SE470U2D5VDM-LGP
2nd

R140

C132

Rds(on) *Io = Isen * Rsen

SC680P50V2KX-2GP

R125
4K7R3F-GP

54K9R3F-GP 46K4R3F-1-GP
R130
174KR3F-GP

C118

SC1800P50V3KX-GP

IMVP IV
Load Line Slope :3mR
25A*3mV/A=> 75mV
Idroop = 75mV / 6.04K = 12.4uA

1 2

R131

CORE_AGND
R127
15KR3F-GP

DY

TC15
SE330U2VDM-4-GP
2nd

GAP-CLOSE

C115
DUMMY-C3

TC7
SE470U2D5VDM-LGP
2nd

C320
SC1000P50V3JN-GP

AG1-910-01

DY

2
1

D19
SSM34APT-GP

DY

6217_DRSV
6217_STV
6217_OCSET

2nd

4
3
2
1

2nd

U34

4
3
2
1

AG1-910-SB

AO4430-1-GP

U33

AO4430-1-GP

5
6
7
8

6217_LG1

5
6
7
8

R280
0R2J-GP

G41

C113
SCD022U16V2KX-3GP

2
1

ISL6218CVZ-TGP

2nd

6217_ISEN1
6217_PHASE1
6217_UG1
6217_BOOT1

1
2

SC10U25V0KX-3GP

1
2

5
6
7
8
AO4422-1-GP

1
2

5
6
7
8

1
3

R121
6K04R3F-GP

SC470P50V2KX-3GP

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

C112

1 2

DY

VBAT
ISEN1
PHASE1
UG1
BOOT1
VSSP1
LG1
VDDP
NC#31
NC#29
NC#28
NC#27
NC#26
NC#25
VSEN
DRSV
STV
OCSET
VSS

ST330U3VDM-1-GP

1K8R3F

VDD
DACOUT
DSV
FSET
NC#5
EN
DRSEN
DSEN#
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT

1
R111

VCC_CORE_S0

S
S
S
G

6217_EA+
6217_COMP
6217_FB
6217_SOFT

EC48

4K7R3F-GP

U29

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S
S
S
G

3,32 6218_PGOOD

6217_DAC
6217_DSV
6217_FSET
6217_PWRCH
6217_EN#
6217_DRSEN
6217_DSEN#
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

C134
SCD33U16V3ZY-GP

2nd

D
D
D
D

37 CPUCORE_ON
16 PM_DPRSLPVR
3,16 PM_STPCPU#
5 H_VID0
5 H_VID1
5 H_VID2
5 H_VID3
5 H_VID4
5 H_VID5 PH 10K P.45

2
1
CORE_AGND

CORE_AGND

U32

D
D
D
D

1
2
1
2
100KR2F-L1-GP
243KR3F-GP 1
2 R113
0R0402-PAD
1
2 R115
1KR2J-1-GP
1
2 R114
0R0603-PAD
1 R117
2
0R0603-PAD
1 R116
2

2nd

CORE_AGND

R112

C170

S
S
S
G

C127
SCD1U50V3ZY-GP

1K21R2F-2-GPCORE_AGND

R108

U31

AG1-910-01

S
S
S
G

C114
SC1U10V3ZY-6GP

C111

D
D
D
D

AG1-910-01

SCD027U50V3KX-GP
1

0R0402-PAD
R132

6217_VBAT

6217_VDD

C159

D
D
D
D

BAT54-4-GP
D17

AG1-910-01

R126
10R3J-3-GP

R138
4D7R3J-L1-GP

SC10U25V0KX-3GP

1
2

BLM41PG600-GP

5V_S0

C129
SC4D7U10V5ZY-3GP

C138

SCD1U50V3ZY-GP

L4

C148

5V_S0

SC10U25V0KX-3GP

DCBATOUT_6218

DCBATOUT

SC10U25V0KX-3GP

DCBATOUT_6218

(5m/2)*25A=28.54uA*Rsen

R33 = 2.18K ~ 2.15K

CORE_AGND

1D05V_S0

AG1-910-01
CORE_AGND

1
2

R151
DUMMY-R2

1
2

R149
DUMMY-R2

1
2

R150
DUMMY-R2

1
2

R147
DUMMY-R2

R148

1
2

R270
DUMMY-R2

1
2

R268
DUMMY-R2

1
2

R269
DUMMY-R2

1
2

R266
DUMMY-R2

1
2

R267
DUMMY-R2

<Core Design>
R265
DUMMY-R2

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

1. U12,U14:AO4422 84.04422.037
U13,U15:AO4430 84.04430.B37
R100:3K83R2F
2. U12,U14:IRF7413 84.07413.037
U13,U15:IRF7832-U 84.07832.037
R100:2K43R2F

DUMMY-R2

R146

DUMMY-R2

AG1-910-SB

VCC_CORE_S0

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VCC_CORE
Size
A3

Document Number

Date: Thursday, October 27, 2005

A

Rev

01

AG1(Alviso)
Sheet
E

34

of

40

AG1-SB-910
DCBATOUT_51120

G44

G43

2nd

S
S
S
G

51120_GND

4
3
2
1
30
11

DRVL1
DRVL2

25
16

51120_PGD1
1
51120_PGD2 R3501
R351
51120_DRVL1
51120_DRVL2

DRVH1
DRVH2

27
14

51120_DRVH1
51120_DRVH2

DY

2
R363
0R0603-PAD

51120_VREF2

2nd

11KR3F-GP

4
3
2
1

DY

VFB1

N/A

not use

ADJ.

VFB2

N/A

not use

ADJ.

EN1,EN2 Switcher OFF

not use

EN3,EN5

not use

LDO OFF

Swithchr ON Switcher ON
LDO ON

VREG3 on

1
2
R356

G64

SANYO 220uF ESR=25mohm

Iripple=2.4A

51120_GND

DY

C431

51120_GND

For TPS51120,
Vout=5V
1. If you use
2. If you use
3. If you use
Vout=3.3V
1. If you use
2. If you use
3. If you use

<Core Design>

a 6.8uH inductor, the minimum ESR is 70m ohm.

a 4.7uH inductor, the minimum ESR is 48m ohm.
a 3.3uH inductor, the minimum ESR is 34m ohm.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

a 4.7uH inductor, the minimum ESR is 51m ohm.

a 3.3uH inductor, the minimum ESR is 36m ohm.
a 2.5uH inductor, the minimum ESR is 27m ohm.

TPS51120_3D3V_5V
Size
A3

Document Number

Date: Friday, October 28, 2005

5

GAP-CLOSE-PWR

R357
13KR3F-GP

1
1

51120_GND

5V
Fixed Output
3.3V
Fixed Output

180k/CH1
280k/CH2

290k/CH1
440k/CH2

380k/CH1
590k/CH2

TC2
ST220U6D3VDM-13GP
2nd

Vout=1V*(R1+R2)/R2

220k/CH1
330k/CH2

TONSEL

DY
C430

D-Cap
MODE

CURRENT
MODE

C429

N/A

N/A

DY

51120_GND

SC680P50V3JN-GP

COMP

PWM

GAP-CLOSE-PWR

AG1-SB-910

22KR3F-GP

51120_COMP2_PL

PWM

SC1000P50V3JN-GP

AUTOSKIP
/FAULTS
OFF

51120_COMP1_PL

AUTOSKIP

SC390P50V3JN-GP

SKIPSEL

DY
R359

DY
SC390P50V3JN-GP

DY

C428

R358
30KR3F-2-GP

DY
V5FILT

FLOAT

GAP-CLOSE-PWR
G63
1
2

DY

51120_COMP2

51120_COMP1

VREF2

3D3V_PWR

GAP-CLOSE-PWR
G62
1
2

3D3V Iomax=5A
OCP>10A

L14
1
2
IND-2D5UH-7-GP

51120_VFB2

GND

SC10U35V0ZY-1GP

AG1-910-SB

C427

51120_DRVL2

3D3V_S5

GAP-CLOSE-PWR
G61
1
2

C30

30K9R3F-GP

51120_GND

GAP-CLOSE-PWR
G58
1
2

U8
AO4702-1-GP

R355
0R0603-PAD

GAP-CLOSE-PWR
G60
1
2

51120_CS2

G
S
S
S

51120_DRVH2
51120_LL2

C34

SC33P50V3JN-GP

R354

GAP-CLOSE-PWR
G59
1
2

DCBATOUT_51120

AG1-910-01
1

3D3V_PWR

AG1-910-01

GAP-CLOSE-PWR
G55
1
2
GAP-CLOSE-PWR

DY

2
0R2J-GP
2
0R2J-GP

23
18

51120_GND
51120_CS1

4
3
2
1

DY

U7
AO4422-1-GP
2nd

151120_SKIPSEL 32
31

CS1
CS2

PGND1
PGND2
GND
GND
24
17
5
33

TPS51120RHBR-GPU1

G
S
S
S

2
20
22

VBST1
VBST2

V5FILT
VIN

7
2
PGOOD1
PGOOD2

100KR2J-1-GP

SC10U35V0ZY-1GP

51120_LL2
51120_LL1

S
S
S
G

R353

U12

11KR3F-GP
1
2

15
26

D
D
D
D

51120_V5FILT

SC1000P50V3JN-GP

C424

51120_GND

R348

LL2
LL1

VREF2

SANYO 220uF ESR=25mohm

Iripple=2.4A

GAP-CLOSE-PWR
G54
1
2

TC3
ST220U6D3VDM-13GP
2nd

51120_VREF2

GAP-CLOSE-PWR
G53
1
2

GAP-CLOSE-PWR
G57
1
2

VO1
VO2

5V_S5

G56

1
8

GAP-CLOSE-PWR
G50
1
2
GAP-CLOSE-PWR
G52
1
2

51120_GND

COMP2
COMP1

19
21

28
13

VFB2
VFB1

5V_PWR
3D3V_PWR

3D3V_S0

AG1-910-01

EN1
EN2
EN3
EN5

AG1-910-01

6
3

5V_PWR

R345
7K5R3F-L1-GP

DY

51120_VFB2
51120_VFB1

1
2
R3491 0R0603-PAD
2
R352 0R0603-PAD

51120_V5FILT

29
12
10
9

51120_VFB1

5
6
7
8

TPAD28
TPAD28

0R0603-PAD
R347
51120_EN1
1
2
51120_EN2
1
2
R346 0R0603-PAD TPS51120_EN3
TPS51120_EN5

R342

51120_DRVL1

4
3
2
1

TP24
TP26

51120_GND

5V Iomax=5A
OCP>10A

5
6
7
8

AG1-SB-910

C423

2
0R0603-PAD
2
0R0603-PAD

SKIPSEL
TONSEL

32 S5_ENABLE

51120_COMP2 1
R343
51120_COMP1
1
R344

DY

C421

2nd
51120_V5FILT

51120_VREG3

VREG3
VREG5

51120_GND

C420
SCD1U50V3ZY-GP

1
2

C422

SC10U10V5KX-2GP

SC10U10V5KX-2GP

AG1-910-01

251120_LL1_1 1
251120_VBST1
0R0603-PAD
SCD1U50V3ZY-GP
51120_VREG5

DY

30KR3F-2-GP

C419
51120_LL1 1
R341

5V_PWR

D
D
D
D

U9
AO4702-1-GP

SC33P50V3JN-GP

GAP-CLOSE-PWR

SC10U35V0ZY-1GP

5
6
7
8

DCBATOUT_51120

251120_LL2_1 1
251120_VBST2
0R0603-PAD
SCD1U50V3ZY-GP

D
D
D
D

C418
51120_LL2 1
R340

GAP-CLOSE-PWR
G48
1
2

GAP-CLOSE-PWR
G51
1
2

EC7
SCD1U50V3ZY-GP

AG1-910-01

C87

L17
2nd
1
2
IND-4D7UH-85-GP

51120_DRVH1
51120_LL1

C417
SC1U10V3ZY-6GP

AG1-910-SB

C117

51120_VREG5 1
2
5D1R3F-GP

1
R339

GAP-CLOSE-PWR
G49
1
2

D
D
D
D

U10
AO4422-1-GP

GAP-CLOSE-PWR
G46
1
2

DCBATOUT

5
6
7
8

51120_V5FILT

SC10U35V0ZY-1GP

GAP-CLOSE-PWR
G45
1
2

GAP-CLOSE-PWR
G47
1
2

DCBATOUT_51120

Rev

01

AG1(Alviso)
Sheet
1

35

of

40

AG1-910-SB
5V_S5

10KR2J-3-GP
R96

SC10U10V5ZY-1GP

GAP-CLOSE-PWR
G68
1
2

1
C433

C434

GAP-CLOSE-PWR
G67
1
2

2
5912_FB_2

1D5V_S0

GAP-CLOSE-PWR

1
C435

R362

2KR3F-L-GP

R361

SCD01U16V3KX-LGP

APL5912-KAC-GP

FB

1K78R3F-GP

AG1-910-01

VOUT
VOUT

GAP-CLOSE-PWR
G69
1
2

1D5V_LDO

EN

3
4

16,18,29,32,35 PM_SLP_S3#

5
9

VIN
VIN

5912_EN_8
1
2
R360 0R0603-PAD

POK

TC23
ST220U2D5VBM-2GP

Trace Length=3cm
Trace Width=5mils
KEMET
Trace Resistance>80mohm
100uF, 4V, B2 Size
Iripple=1.1A, ESR=70mohm

GND

1D05V_EN

16,18,29,32,35 1D05V_EN

VCNTL

U59

GAP-CLOSE-PWR
G66
1
2

1
C432

AG1-910-01

G65

1
SC10U10V5ZY-1GP

SC1U10V3ZY-6GP

3D3V_S0

1D8V_S3

AG1-910-01

Vo=0.8*(1+(R1/R2))

3D3V_S0

1
1

C297

GND

VIN

C306

SC10U10V5ZY-1GP

VOUT

C303

APL5308-25AC-1GPU

DY

DY

C296
SC1U10V3ZY-6GP

3
B

2D5V_S0

U37

SC10U10V5ZY-1GP

SC2D2U16V5ZY-2GP

AG1-910-SA

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

1D5V/2D5V(LDO)

Document Number

Rev

AG1(Alviso)

Date: Monday, October 31, 2005

Sheet
1

01
36

of

40

DCBATOUT_6227

G70

5
6
7
8

D9
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

AG1-910-SB

2R3J-2-GP
R59

1D8V_S3

AG1-A-SA
L21

AG1-SB-910

2nd

1
2
IND-4D7UH-85-GP

2
3
7
9
10

6227_LDRV1

BOOT2

23

6227_BOOT2

16
1

PG2/REF
GND

UGATE2
PHASE2

24
25

6227_HDRV2
6227_SW2

LGATE2
PGND2
ISEN2
VSEN2
OCSET2

27
26
22
19
18

6227_LDRV2

2 2KR3F-L-GP

U23
2nd

R68
78K7R3F-GP

1
2

L20

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS

1
2
1
2

AG1-910-01

2
2

<Core Design>

C232
SC10U10V5ZY-1GP

Wistron Corporation

1
2

C252
SCD1U16V2ZY-2GP

TPS51100DGQ-1-GP

DDR_VREF_S3

79.2271V.20L
ESR=15mohm
Iripple=2.7A

DDR_VREF

1
2
3
4
5

GND

10
9
8
7
6

11

16,18,29,32,35 PM_SLP_S3#

1
2
R181 0R0402-PAD
1
2
R180 0R0402-PAD

TC10
SE220U2D5VDM-4GP
2nd
AG1-910-SB

DY

U36

16,29 PM_SLP_S4#

C292
SCD1U16V2ZY-2GP

1
1

G
S
S
S

R232
0R0402-PAD

R228
10KR3F-L-GP

C250
SC10U10V5ZY-1GP
C244
SC10U10V5ZY-1GP

DY

5
6
7
8
D
D
D
D

AG1-910-01

4
3
2
1

1D8V_S3

R229
1K74R3F-GP

R233
0R2J-GP

2nd

SCD01U16V2KX-3GP

C275

AO4702-1-GP
U25

AG1-910-SB

1D05V/6A
OCP>7.8A

1
2
IND-4D7UH-85-GP
2nd

5V_S5

EC35
SCD1U50V3ZY-GP

1D05V_S0

C64
SCD01U16V2KX-3GP

OCP
7.8A=>R169=151K
9.0A=>R169=133K

0D9V

2
1
1
2

R63

C284

6227_ISNS2
6227_VSEN2
6227_ILIM2

U16
ISL6227CAZ-1-GP

C278

R66

C61
SCD01U16V2KX-3GP

VOUT2

S
S
S
G

AG1-910-01

78K7R3F-GP
2
1

10KR2J-3-GP

20

DY

R74

D
D
D
D

C57
3D3V_S0

SCD1U50V3ZY-GP

2
0R0402-PAD

AO4422-1-GP

6227_SS2
6227_PG2

DCBATOUT_6227

AG1-910-01

5
6
7
8

AG1-910-SB

1
1

1
R231

ISL6227
6227_EN2

DDR
EN2
SOFT2

1 R57
2
2KR3F-L-GP

6227_VSEN1

13
21
17

6227_ISNS1

SC10U25V6KX-1GP

PG1

SC10U25V6KX-1GP

15

AG1-910-SB
TC11
SE220U2D5VDM-4GP
2nd

AG1-910-01

6227_PG1

C291
SCD1U16V2ZY-2GP

LGATE1
PGND1
ISEN1
VOUT1
VSEN1

5
6
7
8
6227_HDRV1
6227_SW1

R64

2
0R0402-PAD

5
4

1
R65

1
R73

UGATE1
PHASE1

TC9

2
0R0402-PAD

34 CPUCORE_ON

6227_BOOT1

OCSET1
EN1
SOFT1

1
11
8
12

BOOT1

0R0402-PAD

VIN

4
3
2
1

21D8V_S3_PG 1
R72
10KR2J-2-GP

16,18,29,32,35 1D05V_EN

G
S
S
S

14
6227_ILIM1
6227_EN1
6227_SS1

2
0R0402-PAD

DY
1 R71

D
D
D
D

VCC

DY

4
3
2
1

5V_S5

R230
0R2J-GP

28

1
R62

16,29 PM_SLP_S4#

C48

DY

2nd
AO4702-1-GP
U20

R234

C273

10KR3F-L-GP

AG1-910-01

AG1-910-01

10R3J-3-GP

6227_VCC

SC4D7U10V5ZY-3GP

R54

C63
SCD1U50V3ZY-GP

10KR3F-L-GP

R75
10R3J-3-GP

5V_S5

SCD01U16V2KX-3GP

2R3J-2-GP

1 R55

1D8V / 6A ,OCP>7.8A

ST330U3VDM-1-GP

DCBATOUT_6227

GAP-CLOSE-PWR

EC34
SCD1U50V3ZY-GP

4
3
2
1

BAW56PT-U

U22
2nd

S
S
S
G

C54
16227_BOOT_1
1

GAP-CLOSE-PWR
G73
1
2

AO4422-1-GP

5V_S5

GAP-CLOSE-PWR
G72
1
2

D
D
D
D

6227_BOOT_2

C285
SC10U25V6KX-1GP

C52

GAP-CLOSE-PWR
G71
1
2

DCBATOUT_6227

DCBATOUT

C230
SC10U10V5ZY-1GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

1D8V/1D05V/0D9V
Size
A3

Document Number

Date: Thursday, October 27, 2005

A

Rev

01

AG1(Alviso)
Sheet
E

37

of

40

DY

D11

1
DCBATOUT

AD+_TO_SYS

1
2
3
4

2
1
G2

U24
S
S
S
G

D
D
D
D

8
7
6
5

BT+

AO4407-1-GP

For EMI

EC68

ID = 10A @
VGS = 10V

GAP-CLOSE

1
2
3
4

EC9
SCD1U50V3ZY-GP

2
G3
GAP-CLOSE

AG1-A-01

AG1-A-SA

AG1-910-SB

C23

C448

SC1U50V5ZY-1-GP

D02R3720F-2-GP

AO4411-1-GP

DY

1
SCD015U50V3KX-GP

S
S
S
G

SCD1U50V3ZY-GP

EC61

D
D
D
D

8
7
6
5

SCD1U50V3ZY-GP

R30

U6

SSM34PT

AD+

DY

ISL6255_CSIN_1

18R3-GP
R14

ACLIM

29

GND

DY

DY

2S

2
1

C25
SC10U35V0ZY-GP

C24
SC10U35V0ZY-GP

2
1

Cell voltage

VREF

4.41V/cell

Float

4.20V/cell

GND

3.99V/cell

24K3R3F-GP
1
R35

DY

1
2

2
D

R27

3S2P_I 38

AG1-A-SA
<Core Design>

3
1

Q1

1K74R3F-GP

DY

DY

AG1-910-01

Wistron Corporation

Q9

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

R7
G
S

AG1-910-SB

100KR3F-GP

PRE_CHG 29
G

Title

CHARGER ISL6225

2N7002PT-U

3S1P_I

ISOURCE_MAX = (((ACLIM/VREF)*0.05+0.05)/Rsense)
Adaptor is 65W/19V : I_LIMIT = 2.9A ( 85% )

Q4
2N7002PT-U

R19

2
1
21K5R3F-GP

C2

1
2

1
2
1

1 2
2

1
2

0R0603-PAD

R2
2N7002PT-U

24K3R3F-GP

DY

AG1-A-SA
AG1-910-01

Float

DY

3S

R36

2N7002PT-U

GND

29

R3
AG1-A-SA
100R2F-L1-GP-U

SCD1U16V2ZY-2GP

4S

3
2

VDD

R22 1
2
0R0603-PAD

Operate Mode

10KR2J-3-GP SCD01U16V2KX-3GP
R4
C3

CELLS

ISL6255_CELLS

C5
SC100P50V2JN-3GP

C1

SC6800P25V2KX-1GP

CHG_ON#

DY

R24

29

0R3-0-U-GP

Q3

ISL6255_VCOMP

AG1-A-SA

ISL6255_VREF

ISL6255_ICM
ISL6255_VDD

VADJ

ISL6255_CHLIM

R5

ICHG : 3S2P = 3.0A/

3S1P = 1.4A
IPRE_CHG = 400mA

AG1-A-SA

ISL6255_EN

R1
10KR2J-3-GP

5
6
7
8
C4
SC2700P50V3KX-1GP

AG1-910-01
100KR2J-1-GP
1
2

DY

SC680P50V2KX-2GP
C7
1
2

ISL6255_VDD

C242

AG1-A-SA

R40
20KR3F-GP

CHLIM

VREF

ICM

EN

R9
15K8R3F-GP

DY DY

C241

SC10U25V0KX-3GP

DCSET

R39
R6
20KR3F-GP
80K6R3F-1-GP

C240

SC10U25V0KX-3GP
2

28

U1
2nd

C101

Near ISL6255
Pin 26

4
3
2
1

3
1

1
VADJ

GND

ACSET

VCOMP

C16

VDD

27

ICOMP

ACSET Threshold 1.27V typ.

ACSET > 1.29V Max. --> AC
DETECT

R10
15K4R3-GP

R8
200KR3F-GP

ISL6255_ACSET

10

CELLS

26

S
S
S
G

ISL6255_VDD

SC1U10V3ZY-6GP

AG1-910-01

AD+

ISL6255_VREF

C102

11

DY

SC10U25V0KX-3GP
2

PGND

DCIN

C239

Near ISL6255 Pin 13

D
D
D
D

25

ISL6255_LGATE SC1U10V3ZY-6GP

12

SC10U25V0KX-3GP
2

LGATE

4
3
2
1

24

Imax= 6A

DCPRN

0R0402-PAD

12*12*4

AG1-A-SA

13

SC10U25V0KX-3GP
2

VDDP

ACPRN

23

ISL6255_ACPRN#

R11

1
2ISL6255_VDD
2R3J-2-GP
C17
ISL6255_VDDP 1
2

BT+

L9
1
2 CHG_PWR-3
1 R118
2
IND-15UH-41-GP
2nd
D03R3720F-1-GP

SCD1U50V3ZY-GP

14

G6
GAP-CLOSE

AO4422-1-GP

BOOT

CHG_PWR-2

AC_IN# 1

G1
GAP-CLOSE

D5
BAT54-4-GP

UGATE

0R0402-PAD
R12

CSON

DY

AC_IN#

AO4422-1-GP

2
1

15

16
PHASE

17
BGATE

18
SGATE

2nd

C18
SCD1U50V3ZY-GP

5
6
7
8
1

ISL6255_CSIP

U2
ISL6255HRZ

R89
29

U5

SCD1U50V3ZY-GP
C19
1
2
22

19

21

R91
100KR2J-1-GP

CSOP

AG1-910-01

C20
SCD1U50V3ZY-GP
S
S
S
G

C21
SC1U50V5ZY-1-GP

ISL6255_UGATE

CSIP

Q2

ISL6255_CSIN

20

AG1-A-SA

CSIN

ISL6255_VDD

D
D
D
D

5V_S5_G913

DCBATOUT

AG1-910-01

R13
2R3J-2-GP

AG1-910-SB

ISL6255_BGATE

D
BSS84LT1G-GP

ISL6255_SGATE
SCD1U50V3ZY-GP
C22
1
2

Size
A3

(Power Team)

Document Number

Rev

01

AG1(Alviso)

Date: Tuesday, November 01, 2005

Sheet

38

of

40

DY

Adaptor in to generate DCBATOUT

D10
PZM24NB1

AG1-A-01

3
1

AD+

DC1
AD_JK

4
4

C6
SCD1U50V3ZY-GP

E
C

PDTA124EU-1-GP
Q10

D
D
D
D

8
7
6
5

C10
SCD1U50V3ZY-GP

AO4411-1-GP

ID = -10A/70deg
Rds(ON) = 24mohm
SO-8
AG1-910-SB
1

OUT

AG1-A-SA

R1

R2

DC-JACK115-GP
22.10037.C51
connector

100KR2J-1-GP
2

5
6
MH1

R37

C13
SC1U50V5ZY-1-GP

AD+_2

U4
S
S
S
G

1
2
3
4

R38
56KR3F-GP

R1

1
1

AD_OFF

GND

IN

29

R2

Q5
CHDTC124EU-1GP

AG1-910-01
3

AG1-910-01

R42
1KR2J-1-GP

3D3V_AUX_S5

BATTERY CONNECTOR
D6
BAV99PT-GP-U

29
29
29

BAT_SCL
BAT_SDA
BAT_IN#

DY

D7
BAV99PT-GP-U

2
3
4
5
6
7
9

BATA_SCL_1
2
27R3F-GP BATA_SDA_1

1
R43
2
27R3F-GP

1
R41

BAT1

8
1

DY

1
2

1
2

1
2

1
2

EC17

EC13
SC10P50V2JN-4GP

DY

SC10P50V2JN-4GP

EC16

SC1000P50V3JN-GP

EC15
SCD1U50V3ZY-GP

SC1000P50V3JN-GP

EC14
SCD1U50V3ZY-GP

EC12

DY

BT+
2

SYN-CON7-11-UGP
20.80577.007
CONNECTOR

<Core Design>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AD/BATT CONN
Size
A3

Document Number

Rev

Date: Tuesday, November 01, 2005

A

01

AG1(Alviso)
Sheet
E

39

of

40

H32
HOLE

H33
HOLE

H34
HOLE

34.4A908.001

SPRING-23-GP

H27
HOLE

H26
HOLE

1
2

1
2

1
2

1
2

EC84

DY

30

AG1-910-SB

K3

1
SPRING-23-GP

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

H25
HOLE

SCD1U16V2ZY-2GP

K2

EC83

SCD1U16V2ZY-2GP

K1

EC82

SCD1U16V2ZY-2GP

AG1-910-SB

EC81

SCD1U16V2ZY-2GP

EC80

SCD1U16V2ZY-2GP

EC19

SCD1U50V3ZY-GP

EC11

SCD1U50V3ZY-GP

EC6

SCD1U50V3ZY-GP

EC10

SCD1U50V3ZY-GP

EC78

SCD1U50V3ZY-GP

EC77

SCD1U50V3ZY-GP

EC76

SCD1U50V3ZY-GP

EC75

SCD1U50V3ZY-GP

EC18

SCD1U50V3ZY-GP

EC38

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

H24
HOLE

BT+
INT_MIC

EC71

H23
HOLE

H22
HOLE

H21
HOLE

5V_S0

3D3V_S0
DCBATOUT

1
H20
HOLE

H19
HOLE

H18
HOLE

H17
HOLE

H16
HOLE

H15
HOLE

H14
HOLE

34.4A904.001

H31
HOLE

H13
HOLE

34.4A905.001

H30
HOLE

H12
HOLE

34.4A906.001

H29
HOLE

H11
HOLE

34.4A905.001

34.4A902.001

D
H28
HOLE

H10
HOLE

3
H9
HOLE

H8
HOLE

34.4A908.001

34.4A902.001

H5
HOLE

H4
HOLE

H3
HOLE

H2
HOLE

34.4A903.001

5
H1
HOLE

K4

1
SPRING-23-GP

K5

1
SPRING-29-GP

K6

1
SPRING-29-GP

K7

1
SPRING-14

K8

1
SPRING-14

K9

1
SPRING-14

AG1-910-SB

K10

K11

1
SPRING-28

1
SPRING-28

SPRING-28

AG1-910-01

AG1-910-SB

<Core Design>

14

5V_S0

A
6

Wistron Corporation

U3B
TSAHCT125PW-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

EMI
Document Number

Rev

AG1(Alviso)

Date: Wednesday, November 02, 2005

Sheet

40

01
of

40