1

Colour television

Chassis

A8.0A

Training Manual
Contents
Introduction Mechanical Control Power supply Video processing Synchronization Audio processing Horizontal deflection Vertical deflection Teletext + On-Screen Display Widescreen view modes
Published by TG9866 Television Service Department Printed in The Netherlands Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips

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5 4822 727 21613

Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips Published by TG9866 Television Service DepartmentPrinted in The Netherlands 5 4822 727 21613

INTRODUCTION Block diagram

A8.0A

INTRODUCTION Block diagram

1125 TUNER

7150-A IF

YC PIP PANEL Y Y/CVBS IO PANEL C C Y COMB FILTER PANEL C Y C 7150-0 VIDEO PROCESSING Y U V

DW PANEL

YU V

YU V

YUV PANEL

7150-C RGB PROCESSING

RGB AMP SCAVEM

R G B

RGB SWITCH

SIF QSS PANEL AM

SOUND PROCESSING

AUDIO AMPLIFIER

TOP CONTROL PANEL

OSD/TXT CONTROLS

I2C

7150-D SYNC

LINE DRIVE

LOT

220V

SUPPLY SMPS

EW+ PANORAMA PANEL

+140 +33 +14 +8 +15 +5 +5 - STBY

FRAME AMPLIFIER

CL 86532033_009.AI 160698

The power is supplied by an SMPS (Switch Mode Power Supply) creating the deflection power supply voltage ( +140V), the sound power supply voltage (+15V) and a number of low voltages (+14V, +8v, +5v and +5vSTANDBY). The controls located on the mono carrier are activated by the keyboard and RC5 signals from the remote control receiver. The internal control is via I2C. The TUNER transmits an IF video signal on 38.9 MHz to the TDA884x (IC7150). In this IC the video processing (PAL,NTSC and SECAM) and synchronization along with the geometrical alignments are implemented. Sound decoding is performed in the sound processing part which can be BTSC dedicated (TDA9855) or multi standard (MSP3410) (mono, stereo, nicam). In some stereo sets (mainly NICAM and FM DK) the QSS panel (Quasi Split Sound) will be applied to improve the SIF signal The CRT-panel contains integrated RGB amplifiers and SCAVEM circuitry. The RGB signals are then transmitted to the picture tube via the RGB amplifiers. The horizontal and vertical deflection signals (line and frame) are amplified in the driver stages, which drive the deflection coils. In all sets except 21" E/W correction is needed which is accommodated on a separate panel. For 16:9 sets the panorama circuitry is also accommodated on this panel

Personal notes

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Mechanical Chassis Set-up

Mechanical Chassis Set-up

POWER SUPPLY HOR. DEFLECTION + LINE OUTPUT VERTICAL DEFLECTION

A1 A2 A3 A4 A5 A6 A7 A8 A10 A11 A12 A13 A14 A15 H

N B C S M Q R G J I E T

TOP CONTROL PANEL CRT PANEL EAST WEST PANEL OSD SIDE AV PANEL

TUNER + VIF VIDEO PROCESSING SYNC RGB PROCESSING CONTROLS AUDIO PROCESSING BTSC AUDIO PROCESSING NICAM/2CS/FM/AM AUDIO OUTPUT IO SWITCHING FRONT AV FRONT CONTROL

INCREDIBLE SOUND PANEL YUV PANEL COMB. FILTER PANEL QSS-DK PANEL QSS (BGLI NICAM) I/O CINCH PANEL PIP PANEL

MAINS FILTER PANEL

CL 86532033_055.AI 180698

(The A8 has a mono carrier and panels for East West, I/O SCART/Cinch, Side AV, QSS, Teletext, Mains filter and Top Control. The mono carrier is a double sided panel with SMDs at the solder side. It accommodates: the control part video signal processing source select(front/rear) IF sound processing audio amplifier horizontal and vertical deflection power supply front control(IR, LED) teletext in the micro-processor. Different panels can be placed on the mono carrier: QSS panel YUV panel COMB. Filter panel E/W Panel OSD panel incredible sound panel Loose panels are Top Control panel Side AV panel Mains filter panel

I/O panel. PIP panel/ DW panel The CRT panel (contains the RGB amplifier circuit and SCAVEM)

Mechanical Removing the separate mains filter

A8.0A

Removing the separate mains filter

2
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In order to remove the rear cover from the A8, all screws at the side, the bottom and the top of the rear cover have to be removed. The screws near the I/O cinch connectors should NOT be removed.

lift the panel from its bracket

CAUTION!
Remember to disconnect the subwoofer connector !! Unplug the mains cord before working on the separate mains filter; the separate mains filter carries permanent mains voltage (even when the mains knob is switched OFF).

Disconnect the separate mains filter panel

To disconnect the separate mains filter bracket from the chassis tray: firmly depress the click (with a screwdriver) in the chassis tray (1) push the mains filter bracket in the direction of the CRT

Remove the separate mains filter panel

To remove the separate mains filter panel from its bracket: push the 2 clips at the right hand side of the mains filter bracket outside (2)

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Mechanical Removing the chassis

Removing the chassis

1 1
M1 6

2
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Service position without the need for a large table or workbench To remove the chassis tray from the cabinet: disconnect the degaussing coil (connector M16 on the mono carrier) pull the clips (1) backwards and pull the chassis tray as indicated (2)

Personal notes

The chassis tray should be turned 90 degrees counter clock wise and flipped over to access the copper side of the mono carrier.

Mechanical Environment independent position

A8.0A

Environment independent position

NEL IO PA KET C BRA

B
CL 86532033_052.AI 180698

For home repair the chassis tray with mono carrier can be fixed in the cabinet. turn the chassis tray 90 degrees counter clock wise (1) flip the tray with the I/O panel towards the CRT (2) press (the hook of) the chassis tray firmly into the designated hole in the cabinet bottom (3) and pull the chassis tray forward (the speaker cables may have to be disconnected)

Personal notes

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Mechanical Accessing the I/O panel

Accessing the I/O panel

4 4 3 2
(4X)

CL 86532033_053.AI 180698

To access the copper side of the IO panel: push the clips (1) in the direction of the CRT (If the clips are broken, the I/O panel can also be screwed to chassis tray) slide the I/O panel bracket (2) to its horizontal position

Personal notes

To remove the I/O panel from its bracket: remove the 2 screws on the connector side of the panel (3) and (4).

Mechanical Repairing the mono carrier

A8.0A

Repairing the mono carrier

CL 86532033_054.AI 180698

For full access to the component and copper side of the mono carrier, it can be removed from the chassis tray. push the clicks of the chassis tray outwards (1) lift the mono carrier from the tray (2).

Personal notes

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CONTROLS User Menu

CONTROLS User Menu

1 2 3 4 5
AV INC. SURR. INCREDIBLE GAME A/CH

1 4 7
SMART

2 5 8 0

3 6 9
SMART

6 7 8 9 10
MENU

SURF

CH

11

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The complete control of TV sets with a A8 chassis is performed via menus. Selections within the menus are made by the arrow keys on the remote control (cursor control).

Personal notes

On the remote control the "smart controls" for picture and sound are present. Pressing one of these buttons will give a pre-programmed change of various audio or picture settings at the same time.

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CONTROLS Installation

A8.0A

Installation

Installation
Automatic Manually DST (RC7150)

Installation of the A8 can be done via the installation menu or via the Dealer Service Tool (DST); 1. With the Installation-menu the installation of the TV can be performed in two ways: Automatic: The complete TV band is searched and all transmitters are installed. Manually: The frequencies have to be given for all program numbers. 2. With the RC7150 Dealer Service Tool (DST) The RC7150 can install a complete TV program table in a single operation.

Personal notes

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CONTROLS Dealer Service Tool (DST)

11

Dealer Service Tool (DST)

RC7150
Service Features
Entering the Service Alignment Mode

Entering the Service Default Mode Defined settings for tuning and control

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The dealer service tool (DST, RC7150) is a remote control, especially developed for the dealer and service engineer. Dealer functions With the DST complete program tables can be transmitted to the TV. 10 different tables can be stored in the DST, e.g. for 10 different areas.

Personal notes

Programming tables into the DST can be performed in two ways: From the TV (GFL only). If a GFL TV is installed with a complete table of program information the complete table can be transmitted to the DST. As use is being made of the dealer link, the DST must be held at a short distance(within 10 cm) from the IR transmitter LED (next to the stand-by led). With a DST interface (22AV1376). This is a computer interface that can be used with the accompanying computer program to input tables in the computer and transmit these tables to the DST. Service features of the DST for the A8 Activating the Service Alignment Mode. By pressing the "ALIGN" key on the DST the Service Alignment Mode SAM) is activated. Activating Service Default Mode. By pressing the "DEFAULT" key on the DST the Service Default Mode (SDM) is activated. Downloading program tables from DST into the TV.

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CONTROLS Service Default Mode (SDM)

A8.0A

Service Default Mode (SDM)

SERVICE DEFAULT MODE

Shortcircuit 9040 & 9041 on the SSP Press the "default" key on the RC7150

Tuner tuned to 475.25 MHz All linear settings in "mid" position Volume set to "low"
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Entering the Service Default Mode (SDM):

By transmitting the "DEFAULT" command with the RC7150 Dealer Service Tool. By shorting the jumpers 9040 & 9041 while switching on the set with mains switch.

Personal notes

Exiting the Service Default Mode (SDM): Switch the set to stand-by (the error buffer is also cleared)

Specification of the Service Default Mode (SDM)

Default values of the following must be set according; Tune to 475.25MHz. PAL/Secam sets Tune to channel 3 (61.25 MHz) for NTSC sets All linear setting at 50%, except volume at 25% Disable service unfriendly modes; Timer Off Sleeptimer Off Hospitality disabled No-ident timer disabled Parental lock disabled The default system (for multi system sets) will be set according to the signal source input at the antenna.

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CONTROLS Service Default Mode (SDM)

13

Service Default Mode (SDM)

SDM Menu

S D M

E R R

n n

n n

n n

n n

n n

n n

MENU

P S F I

I O E N

C U A S

T N T T

U R E D U R E S A L L

B C C S C

R O O H O

I L N A L

G O T R O

H U R P U

S A M T N E S S R A S T N E S S R T E M P

S D M

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Others features of SDM

Error codes OSD can be switched on and off with OSD button Switch to user menu by pressing MENU button LED blinks with info of the error in error buffer Start channel search by pressing "P+" button on the remote control

Personal notes

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CONTROLS Service Alignment Mode (SAM)

A8.0A

Service Alignment Mode (SAM)

SERVICE ALIGNMENT MODE

From SDM via "Vol +" & "Vol -"

Service Menu
1 n n n n E R R O P R E O A E R P L L A T I 2 A 8 0 E U 1 - 1 . 0 n n n n n n n n n n n n n n n n n O S I G A D D E F A U L T E B U F F E R O N S N M E N T S 3 5 2 6 3 - 2 - 2 3 n n n n n n n n n n 4 5 S A M

n n n

n n n

6
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Entering the Service Alignment Mode (SAM

During normal operation and SDM by transmitting the "ALIGN" command with the RC7150 Dealer Service Tool. By pressing and holding VOL+ & VOL- keys on the local keyboard for 2 sec. while in SDM

Specification of the Service Alignment Mode (SAM)

1. Operating hour counter ( in Hexadecimal) 2. Software version 3. Software of separate teletext controller; NOT implemented for A/P. 4. Error code buffer (maximum the last 6 error codes 5. Option bytes (7 bytes possible 6. Sub menus Erase buffer Option codes Alignments and geometry information Reload default values Error code Description of possible defective components 0 No error detected - 1 EW and/or Vert protection active EW/Vertical circuit is defective 2 High beam protection active CRT amplifier circuit or picture tube 3 Reserved 4 5V protection active +5V supply line is low or short cuicuit 5 BiMOS s/w protection active or BiMOS register is corrupted IC7150 6 BiMOS

IIC error IC7150 7 General IIC bus error IIC bus s/c or o/c 8 Main uP Internal RAM error IC7000 9 OSD generator IIC error IC7101 on OSD panel 10 NVM addressing error IC7088 11 NVM IIC error IC7088 12 Histogram IIC error IC7770 on YUV interface panel 13 Reserved 14 Sound processor IIC error IC7430 (ITT) or IC7437 (BTSC) 15 Reserved 16 Main tuner IIC error U1125 17 PIP processor IIC error IC7350 on PIP panel 18 2nd tuner PIP IIC error U1126 or U1127 on PIP panel 19 EPG uProcessor/Guide Plus uProcessor IIC error IC7007 on EPG panel IC6 on guide plus panel 20 NV-clock IIC error IC7110 21 Reserve 22 EPG processor IIC internal RAM error IC7007 on EPG error

Exiting the Service Alignment Mode (SAM)

The SAM will be left by the stand-by command. In case the set is switched "off" and "on" again with the mains switch, the set will start up in the SDM again.

Specification of the Service Alignment Mode (SAM)

1. 2. 3. 4. Operating hour counter (in hexadecimal) Software version Software of separate teletext controller Error code buffer (maximum the last 6 error codes)

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CONTROLS Service Alignment Mode (SAM)

15

5. Option bytes (7 bytes possible) 6. Sub menus Erase buffer Option codes Alignments and geometry information Reload default values

The error code buffer is written from left to right and contains all errors detected since the last time the buffer is erased. An example can be: ERROR:0 0 0 0 0 0:No error code detected

Error code buffer

Error code Error description Possible defective components E/W Vertical circuit defective,line o/p stage.

ERROR:6 0 0 0 0 0:Error code 6 is last and only detected ERROR:5 6 0 0 0 0:Error code 6 is first detected, error code 5 last detected The last error detected (actual) is the error at the left side By leaving the SAM with the "standby" function or ERASE BUFFER function the error buffer is reset.

0 1

No error detected E/W and/or Vert. protection active/X-ray protection. High beam protection active Reserved 5V protection active

CRT amplifier circuit or picture tube +5V supply line is low or short circuit IC7150, + 8V supply.

3 4

Personal notes

BiMOS s/w protection active or BiMOS register is corrupted BiMOS IIC error General IIC error Main uP internal RAM error OSD generator IIC error NVM addressing error NVM IIC error Histogram IICerror

6 7 8

IC7150 IIC bus s/c or o/c IC7000

9 10 11 12

IC7101 on OSD panel IC7088 IC7088 IC7770 or YUV interface panel IC7430 or IC7437 (BTSC) U1125 IC7350 on PIP panel U1126 or U1127 on PIP panel IC7007 on EPG panel/ IC6 on Guide Plus panel IC7110

13 14

Reserved Sound processor IIC error Reserved Main tuner IIC error PIP processor IIC error 2nd tuner PIP IIC error

15 16 17 18

19

EPG uP/Guide Plus uP IIC error NV-clock IIC error Reserved EPG processor IIC internal RAM error

20 21 22

IC7007 on EPG panel

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CONTROLS Service Alignment Mode (SAM)

A8.0A

Service Alignment Mode (SAM)

Service Alignment Mode

HORSHIFT: HORWIDTH: SERV.BLANK: VERSHIFT: VERHEIGHT: VERSLOPE: EW PARABO: EW TRAPEZ: EW CORNER: VER S-COR: VERZOOM:

Horizontal shift Horizontal width Service blanking Vertical shift Vertical amplitude Vertical linearity E-W parabola E-W trapezium E-W corner Vertical S-correction Vertical zoom

Alignments
Selection of the desired alignment by the up/down cursor Change of the selected alignment by the left/right cursor The following alignments are possible (alignments for geometry are for the 4:3 picture format) A value between 0 and 63 can be given for all software alignments Important! Any changed values will only be stored if the geometry menu is exit by pressing the MENU button.

Personal notes

Easy way to adjust vertical geometry (4 X 3) 1. 2. 3. 4. Set vert. S-correction value to 13 Set vert. zoom value to 25 Set vert. blanking to ON Adjust vert. slope till test pattern centre line touches the centre edge 5. Adjust vert. shift and vert. height till best fix the screen.

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CONTROLS Service Alignment Mode (SAM)

17

Service Alignment Mode (SAM)

SAM Menu

P S F I

I O E N

C U A S

T N T T

U R E D U R E S A L L

B C C S C

R O O H O

I L N A L

G O T R O

H U R P U

S A M T N E S S R A S T N E S S R T E M P 3 5 2 6 3 - 2 - 2 3 n n n n n n n n n n 4 5 S A M

MENU

1 n n n n E R R O P R E O A 6 E R P L L A T I

MENU

L O A D N O W D O N ' T L O A D

A 8 0 E U 1 - 1 . 0 n n n n n n n n n n n n n n n n n O S I G A D D E F A U L T E B U F F E R O N S N M E N T S

n n n

n n n O O S A A B 6 B 7 T O R E L K n n n n n n O N O F F

MENU

MENU MENU

G G W T B

E E H U T

O O I N S

M M T E C

E T R Y E T R Y S W E T O N E R S O U N D

H H S V V

O O E E E

R R R R R

S W V S W

H I . H I

I D B I D

F T L F T

n n T n n H A N K I N G n n T n n H

n n n n

MENU

C O L D

R n n n

G n n n

B n n n

Only when HW option is present

T D A 9 8 5 5 L S W A A A A A n n n n n n n n n I I A A A F P L L F P L L G C F A F B n n n n n n n n n n n
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MENU

MENU

Options
Setting of individual options. Selection of the desired "option to be changed" by the up/down cursor. Change of the selected option (ON/OFF) by the left/right cursor or By keying the decimal values in the option bytes 1~7 item The options are activated immediately after they are stored and powered up.

Personal notes

Reload Default
By selecting LOAD NOW, the current values stored in the non volatile memory will be over written. Caution: It is used only when the non volatile memory data is corrupted and no other way to recover. Default values are activated when the set is restarted

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CONTROLS Microprocessor

A8.0A

Introduction
Microprocessor

Hardware and software diversity.

Europe sets:
Master micro processor 83C770 (64k ROM). Slave micro processor on TEXT/EPG panel, dedicated for EPG (Electronic Programming Guide) and Teletext decoding.

PN3:Pal/Multi; NO teletext; English and Arabic PT1:Pal/Multi WITH teletext; English, Malay and Chinese NG1:NTSC; 2CS sound; English and Korean NB1:NTSC; BTSC sound; English and Taiwanese

X = (main version number) Y = (subversion number)

Software identification of a separate Teletext micro controller (DDDD E FF) (not applicable for A8.0A)

Latam and USA standard sets:

Single micro processor 83C770 (64k ROM). Complete controls including Closed Caption decoding.

NVM
The NVM used for storing the default settings is ST24W16 is 16 KB and is interfaced with the main micro using the S/W I2C bus. This is to avoid any data corruption in the NVM data by controlling the Write CLock of the NVM by the main micro.

Low end USA sets:

Single micro processor 83C570 (48k ROM).

Asia/Pacific TXT sets:

Personal notes
Single micro processor SAA5297(masked) or SAA5499 (OTP).Complete controls TXT decoding.

Asia/Pacific NON-TXT sets:

Single micro processor 83C770 (64K ROM)

Software diversity:
Version Region EUROPE A8EU1.1: Western Europe without EPG A8EU1.2 : Eastern Europe A8EU1.3 : Western Europe with EPG USA A8US1.1 : USA (all) LATAM A8LA1.1 : LATAM (all) Software identification of the main micro controller (A80BBCX.Y) A80 is the chassis name for A8.0A BBC is 2 letter and 1 digit combination to indicate the software type and the supported languages: PN1:Pal/Multi; NO teletext; English, Malay and Chinese PN2:Pal/Multi; NO teletext; English and Hindi

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CONTROLS Microprocessor

19

Software control lines

Microprocessor

SOFTWARE CONTROL LINES DESCRIPTION for the main micro processor Logic 0 is : 0 V Logic 1 is : +5V

Pin 4: SEL _PIP_FRNT_RR 0 0 1 1

Pin 9: SEL_PIP_R1R2 0 1 0 1

PIP Source Selection REAR1 REAR2 FRONT INTERNAL

Pin 1: PAN_SWITCH/+5V_CNTRL
OUTPUT Activates 16:9 feature (EUROPE only) Activates+5V supply for the PIP board (USA only)

Pin 5: SEL_IF_TRAP_MAIN or L/L'

OUTPUT Select the MAIN IF TRAP and Sound Traps also.

Pin 1: PAN_SWITCH 0 1

Status Default Super Wide Selected in 16:9 sets

Pin 5: SEL_IF_TRAP_MA IN 0 1

A/P

Europe

ON - for NTSC M OFF - for others

ON - for othrs OFF - SECAM L'

Pin 1: +5V CNTRL 1 0

Status +5V OFF +5V ON

Pin 6: POSNEG_QSS or SEL_INCRED

OUTPUT Selects the positive and negative demodulation mode for the QSS IC during SECAM L reception (Europe only). Selects the Incredible Stereo feature (USA only)

Pin 2 & 3: SYS2 and SYS1

OUTPUT Selects the XTALS and Combfilters.

Pin 6: 0 Pin 2: SYS2 0 1 0 1 Pin 3: SYS1 0 0 1 1 System PAL M PAL B,G,H,I,D,K NTSC M PAL N 1

Status - POSNEG_QSS POSITIVE (SECAM L/ L') NEGATIVE (Others)

Status - INCRED Incredible stereo is on

Incredible stereo is off

Pin 7: SDM
INPUT Service Default Mode is activated by shorting this pin to GND.

Pin 4 & 9: SEL_PIP_FRNT_RR & SEL_PIP_R1R2

(valid for PIP sets) OUTPUTS Selects the PIP video source from rear I/O, main or front.

Pin 8 & 14: SEL_MAIN_R1R2 & SEL_MAIN_FRNT_RR

OUTPUTS Selects the MAIN video source from INTERNAL, FRONT or REAR.

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CONTROLS Microprocessor

A8.0A

Pin 14: SEL_MAIN_FRNT_ RR 0

Pin 8: SEL_MAIN_R1R2

MAIN Source Selection

Pin 10: Function AFC_TUNE R2 Output of Analog tp Digital Converter 0

ADC

Input DC voltage

REAR1 (AV2/ SVHS) REAR2 (AV1)

0 - 0.5 1 1.5 2 2.5 3 3.5 4 4.5

0 1

1 0

1-2 FRONT (AV3/ SVHS) INTERNAL 3-4 5-6 7-8 9 - 10 11 - 12 13 - 14

Note: For Multimedia and Institutional TV Interface pin 8 will be configured as TV CLK.

Pin 9: STAT2 or SEL_PIP_R1R2

(valid for non PIP sets) ADC input. Detects the presence of SCART2 Video source (CVBS) and also whether it is 4:3 or 16:9 video source.

15

Input Controls the Eco Double Window.

Pin 9: STAT2 ADC VALUES 0-4 5 - 10 11 - 15

Status - SCART2 Video Internal Video External 16:9 External 4:3

Pin 10: SYS_ECO_DW 0 1

System Status 50 Hz 60 Hz

Note: For Multimedia and Institutional TV Interface this pin will be configured as DATA IN.

Pin 10: STAT_EXT 1/ AFC_TUNER2/ SYS_ECO_DW

ADC input Comparator to sense different DC levels from I/O to indicate the presence of an EXTERNAL SCART video sources (CVBS), 4:3 or 16:9 SCART video.

Pin 11: FRNT_CNTRL

INPUT ADC Connected to the keyboard and protection line PROT_E_W. The keys are read by applying a unique voltage.

Input DC Voltage Pin 10: STAT1 ADC VALUES 0-4 5 - 10 11 - 15 Status - SCART1 Video Internal Video External 16:9 External 4:3 0 1V5 2V1 2V7 3V4 4V 5V

Function ketboard read Protection Program Up Program Down Menu (not forLatam) Volume Up Volume Down No Key Pressed

ADC input (Valid for NTSC-M) Indicates for the 2nd tuner PIP application for Y/C PIP and named AFC_TUNER2.

Pin 12: POR2

OUTPUT

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CONTROLS Microprocessor
Pin 18 : STAT_HP
INPUT. To sense the presence of a Head Phone jack.

21

Provides Power On Reset pulse during start-up for 2nd microp (both EPG and non-EPG boards used in Europe sets) and GEMSTAR decoder boards used for USA sets. For 2nd micro-p board the POR2 is high for at least 2 machine cycles when the oscillator is running and then go back to LOW. For Gemstar the POR2 must go from LOW to HIGH and remain HIGH during start-up Note: For Multimedia and Institutional TV Interface this pin will be configured as DATA IN.

Pin 18: STAT_HP 0 1

Status Headphone NOT connected Headphone connected

Pin 14: SEL_MAIN_FRNT_RR

See pin 8

Pin 19: STBY

OUTPUT To switch between standby and normal operation.

Pin 15: SVHS_MODE

OUTPUT Select/deselect the external SVHS or the CVBS inputs

Pin 19: STBY Pin 15: SVHS_MODE 0 1 Select SVHS CVBS 1 0

TVStatus In Stand-by Mode in Normal Operation

Pin 20: LED

OUTPUT

Pin 16: DEGAUS

OUTPUT Controls the DEGAUS circuit in the Power Supply block. During power ON this pin gives low going pulse for 2 seconds.

Pin 20 0

Europe LED brighter = Standby LED dimmer = normal operation

AP/Latam LED lighted = Standby LED OFF = normal operation

USA LED lighted = normal LED OFF = Standby

1 Pin 16: DEGAUS '0' for 2 seconds and then goes to '1'

Pin 17: AMP_MUTE1

OUTPUT Mutes the Audio Output Amplifier

Pin 21 SAA5297/P83C770: SEL_GAIN_SPLIT/ SEL_TUNER1_2

OUTPUT Selects the gain of the antenna splitter of the 2nd tuner for PIP (A/P and LATAM sets only).

Pin 17: AMP_MUTE1 0 1

Status MUTE OFF MUTE ON Pin 21: SEL_GAIN_SPLIT 0 1 Attenuation OFF ON

OUTPUT

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CONTROLS Microprocessor

A8.0A

Selects between the MAIN tuner 1 and MAIN tuner 2. (USA and 2 Tuner PIP sets only).

Pin 52 of P83C770 : FFBL_EXT/4_NORMA_SEL

Pin 52: FFBL-EXT Pin 21: SEL_TUNER1-2 0 1 Tuner 1 Tuner 2 0 Not selected Selected Selected Not selected 1

Status RGB present on the SCART No RGB on the SCART

Pin 30 P83C770: RMT_LOC_DATA

OUTPUT Signal: DATA to the REMOTE LOCATOR circuit (USA only), others this pin is pulled to high via 3063.

For LATAM sets this pin is used to select the respective crystals 4 or 2/3 Norma sets. This is configured by hardware as LOW or HIGH depending on the crystals connected to the BiMOS.

Pin 52: 4 NORMA_SEL 0 1

Status Selects 4 Norma Selects 2 or 3 Norma

Pin 46 for SAA5297 and P83C770 : WRITE_CTRL

OUTPUT

OTHER PIN DETAILS

Pin 13: Ground

Selects the global write protection control of the EEPROM (IC7088).

Ground line for digital circuits for SAA5297 and P83C770 Pin 22: VSSA (For SAA5297 and P83C770 ) Ground line for analog circuits Pin 23: Ground Input CVBS from which closed caption for USA/LATAM or TEXT data for EUROPE/AP is to be extracted. A positive going 1V (peak-to-peak) input is required. Pin 24: STN For P83C770 and CVBS1 for SAA5297

Pin 47 SAA5297/P83C770 : SCL_EEPROM

Clock output EEPROM I2C bus.

Pin 48 SAA5297/P83C770 : SDA_EEPROM

Data in - output EEPROM I2C bus.

Pin 49 SAA5297/P83C770 : SCL

Clock output of master I2C bus. For a survey of all connected ICs to this bus see the diagram "I2C overview" in the service manual.

For SAA5297 this data slicer decoupling capacitor input, connect to VSSA via a 100 nF capacitor (C2054). Pin 25: BLACK & BLK (For SAA5297 and P83C770 )

Pin 50 SAA5297/P83C770 : SDA

Data in - output of master I2C bus. CVBS signal black level reference, connected to VSSA via 100 nF capacitor (C2055). Pin 26: IREF (For SAA5297 and P83C770 ) CVBS signal reference current input, connect to VSSA via a 27K resistor (R3058) Pin 27: TEST (For SAA5297 and P83C770 )
Pin 51: RGB_KILL 0 1 Status Default Kill External RGB

Pin 51: RGB_KILL

(Valid for SCART sets !) Output

This pin is connected to +5V via 10 K Ohms resistor (R3060) Pin 28: TEST (For SAA5297 and P83C770 )

A8.0A

CONTROLS Microprocessor

23

This pin is connected to Digital gnd for SAA5297. For P83C770 this pin is pulled to high via 3061. Pin 29: TEST (For SAA5297 and P83C770 )

This is XTAL oscillator OUTPUT pin. All internal timing of the micro-controller is derived from this oscillator The oscillator frequency has to be 12MHz. Pin 43 for SAA5297 and P83C769 : POR

This pin is connected to +5V via 10 K Ohms resistor (R3062). Pin 31: RGBREF & REFH (For SAA5297 and P83C770 ) For SAA5297 this is the DC input voltage to define the output HIGH level on the RGB pins, For P83C770 this is the data slicer reference high capacitor input connected to VSSA via 100 nF capacitor (C2070). Pin 32 to 35 (For SAA5297 and P83C770 ): FBL, R, G and B Outputs 'RED', 'GREEN' and 'BLUE' deliver the colour components for the OSD, while output 'Blanking' is used as a fast blanking signal to insert R, G and B signals in the television picture. The output polarity of all four pins is active high. Pin 36: HSYNC for OSD /TXT (For SAA5297 and P83C770 ) Pin 52 for SAA5297 and P83C770: N.C This signals is derived from the deflection part to get a stable OSD picture on the television screen. The 'HSYNC' pins is supplied with active low horizontal sync pulses (polarity is software programmable). Pin 37: VSYNC for OSD/TXT (For SAA5297 and P83C770) This signal is derived from the deflection part to get a stable OSD picture on the television screen. The 'VSYNC' pin is supplied with active low vertical sync pulses (polarity is software programmable). Pin 38 for P83C770 & SAA5297 : VDDA No LED blinking to RC5 - Check NVROM This pin is connected to +5VA No OSD/TXT - Check H sync on pin 36 Pin 39: VDDT for SAA5297 & VDD_P P83C770 No TXT- Check CVBS_TXT on pin 23 and +5V at pin 39. For SAA5297 this pin is connected to +5V Teletext power supply. For P83C770 this pin is the Digital periphery power supply. Pin 40: OSCGND for SAA5297 & VSS_D for P83C770 For SAA5297 this pin is connected to crystal oscillator gnd. For P83C770 this pin is the Digital Ground. Pin 41 for SAA5297 and P83C770 : XTALIN This is XTAL oscillator INPUT pin Pin 42 for SAA5297 and P83C769 : XTALOUT No LED or IIC activity - Check for the +5V_STBY and the POR pulse Set always on standby - Check +8V of BiMOS LED Blinking - The set may be on protection. Check pin 11 For SAA5297 and P83C770 this pin can be used as an I/O port and is not connected. Pulled to high. 'POR' is used to reset the micro-controller after a power-on reset. This reset signal has to be HIGH until a stable 5V supply voltage is available and then it goes LOW. Also when the supply voltage drops below the minimum required voltage the micro-controller has immediately to be reset via pin 'POR'. Pin 44 for SAA5297 and P83C770: VDDM For SAA5297 and P83C770 this pin is +5V micro-controller power supply. Pin 45 for SAA5297 and P83C770 : RC-5 This input pin is connected to an RC5 remote control receiver(TFMS5360). The input should be high when no remote control signal is received.

Some hints on problem solving

24

POWER SUPPLY Degaussing

A8.0A

POWER SUPPLY Degaussing

*3908
+t ZPB 2

PTC

3
2

}
M16

TO DEGAUSSING COIL

*3906
PTC

*9950
0132
TO F15 OF MAINS FILTER

{
M15

1 3

2 4 +13V

10K 3910 BZX79-C3V3 6920 1N4148 6935 13V4

3911 4K7 13V4

6992 BZX79-C9V1

DEGAUS

A8-05

9999 3

BC557B 7900 0V RELAY SWITCHER

3950

2M2

G5P-1

1901 1N4148

6904 22n

2908

CL 86532033_011.AI 160698

The degaussing circuit is activated whenever the TV set is turned on. So from normal off to on and from stand-by to on the degaussing circuit is activated. During start-up the signal degaus (A8-05) is high which blocks TS7900. After start-up of the uP the signal degaus (A8-05) becomes low for 3 seconds which forces TS7900 in conduction. Now the +13V is put on the coil of the relay and switch G5P-1 is closed. The degaussing current passes through the degaussing coil. After three seconds, DEGAUS goes high, 7900 turns off , 1901 is de-energised and no current passes through the degaussing coil at normal operation due to the fact that switch G5P-1 is opened. PTC 3906 is present in 220V sets and PTC 3908 is present in 110V sets.

Personal notes

A8.0A

POWER SUPPLY General information

25

General information

CL 86532033_049.AI 160698

26

POWER SUPPLY General information

A8.0A

The A8 power supply is a Switch Mode Power Supply(SMPS) with minimum voltage switch. The topology is a flyback converter with primary current sensing, secondary voltage sensing and mains input Voltage measuring. The power supply is built with IC 7902 which has a built-in MOSFET and control circuit. The frequency ranges for normal operation are 25kHz to 130kHz (full range) and 40kHz to 130kHz (single range and 120V). The SMPS works in discontinuous mode, so with a T-on, T-off and a Tdead. The FET is switched on during T-dead when the voltage at the drain of the built-in FET (IC7902 pin 3) is minimal due to oscillation of C2913 and the primary inductance of T5912. This is reducing the switching losses.

Personal notes

Output voltages
+14V (For Line Circuit and input voltage for stabilizer 7908) : +13.5V. If +14V and +8V are not present check 1905. +33V (For Tuner) : +33V. Created via R3994 and zenerdiode 6955 Vbat (Battery Voltage for Line Output Stage) : +140V (9917 present) or +130V (9918 present). +8V (Bimos Supply ) : +8.3V. Output voltage from stabilizer 7908. This voltage is decreased in standby to 2V3. In standby TS7909 is conducting and switching R3933 parallel to R3932. This will decrease the output voltage of 7908. +5Vstby (P Supply) : +5.1V. This voltage is also present during standby. If this voltage and +5V are missing check 1906. If the voltage at pin 1 and 2 of IC7907 are present replace 7907. +5V (For Tuner, QSS, BTSC or ITT etc) : +5.1V. This voltage is disabled when the +13V is not present at pin 3 of IC7907. +13V is generated by the line-output circuit. So when the line-output circuit is working correctly the +5V is enabled and the POR signal is generated to start the set. +15V ( Audio Supply) : +18V or +14V

A8.0A

POWER SUPPLY Control circuitry

27

Control circuitry

DEMAGNITIZING DETECTION CIRCUIT

2904 2n2

1N5062

3902

9954

9952 1R5

2905

2n2

* *

6933

*9956 *
3905 -t NTC

6903 GBU4J 3

1N5062

6931

1N5062 2

* 6930

P1 290V (301V)

2906

470u

2911

100K

3995

22n

6932

1N5062

* 5912
1 2 3

TRANSFORMER

18 17 16 15 14 13 12 11 10

*
BYD33M 6906

*
100P 2971

4 5 6 7

5911

*
P3

100K

3941

3917

2M2

* * * 3959
3R3

8 9

*
6908 BYD33J P2

2920

10n 2912

* 17V6 (15V6) *7902 STR-F6626

4 1
VIN OCFB GND D S

47u

3920

2966

3n3

(301V) 290V 3

2913

3962

P5 6911 BYD33J

*
1K5 2914 1n5

P4

100mHz

3991

3922

2915

470p

680R

3924

0R1

5906

2K7

1V6 (0V7)

0V (0V)

1n5

3K3

BYD33J

6910

CL 86532033_005.AI 030898

Mains input circuit

The mains voltage is rectified by bridge rectifier D6903 or D6930 ,D6931 ,D6932, D6933 and filtered by C2906 . The DC voltage across C2906 is the DC input voltage for the SMPS at pin 6 of transformer T5912.

Start-up circuit
IC7902 is started when the voltage present at pin 4 is high enough. When the set is switched on, C2912 is charged through start-up resistor R3917. When the voltage across C2912 reaches 16V (Typical), the control circuit of IC 7902 starts to operate.

increases due to the increase of the drain current. When the voltage of pin 1 of IC7902 reaches the threshold voltage Vth(1) =0.73V, the MOSFET turns off. The voltage of pin 8 of T5912 becomes now positive . Power supply flybacks at this moment (so energy is released at the secondary side). Voltage applied at pin1 of 7902 is determined by the turn ratio of the transformer T5912 and R3962, R3991 ( Typical voltage is 3.5V) . This voltage is higher than threshold voltage Vth(2) (1.37V). Until the transformer is demagnetized, this voltage remains high. Once the energy stored in the transformer is fully transferred to the secondary side, the voltage at pin1 of IC7902 drops below the threshold voltage Vth1 after a certain delay time and a new cycle starts.

After the control circuit starts its operation, power is supplied by smoothing and rectifying the voltage of the supply winding ( 89 ) of T5912. The supply winding reaches the operation voltage before the voltage of C2912 drops below the shutdown voltage. Consequently, the control circuit can continue its operation.

Control circuit and oscillation phase

IC 7902 has two internal comparators . The thresholds of these two comparators are 0.73V and 1.37V. During T-on , the MOSFET inside IC7902 is conducting . The voltage across R3924

28

POWER SUPPLY Control circuitry

A8.0A

Control circuitry

SECONDARY VOLTAGE MEASUREMENT 2

(7V7) 2V9 11V5 (10V) 4 TCDT1101G 7950 (15V6) 5 17V6 1 2 REGULATOR OPTO-COUPLE 12V5 (11V) PIN 2 OF IC 7904 (MEASURING OUTPUT VOLTAGE) 13V

* 5912
1 2 3 4 5 6 7

TRANSFORMER

18 17 16 15 14 13 12 11 10

*
6908 2920 10n 2912 47u BYD33J P2

3959 8 3R3 9

D S

3920

2 2913 1n5

2966

3n3

(301V) 290V 3

3962

P5 6911 BYD33J 3991

*
1K5 2914 1n5

P4

100mHz

3922 2915 470p 680R

3924

*
CL 86532033_003.AI 030898

0R1

5906

2K7

0V (0V)

3K3

6910

P3

17V6 (15V6) 7902 STR-F6626 4 VIN 1 OCFB GND 1V6 5 (0V7)

BYD33J

A8.0A

POWER SUPPLY Control circuitry

29

Regulation
Control circuitry

Secondary voltage sensing

IC7902 (SMPS IC) and 7950 (Opto-Coupler ) form the secondary voltage regulation circuit. The error amplifier feedback is fed to the control circuit (7902, pin 1) by the opto-coupler. The feedback is realized as follows:

Personal notes

When the output voltage Vbat increases (decrease of the load ), the voltage at the base of the internal transistor of IC7904 increases. As a result, the collector current of the internal transistor of IC7904 and the current through the diode in the optocoupler 7950 increases. At the same time, Vce of the transistor part of 7950 decreases. Therefore, the voltage across C2915 increases. This will shorten the T-on time of the MOSFET of IC7902 The opposite story is valid for an increasing load (decrease of the output voltage Vbat). In case of a short-circuit between pin 3 and 2 of IC7902 check snubber circuit 2911, 6906,2971 and R3995.

30

POWER SUPPLY Control circuitry

A8.0A

Control circuitry

PRIMARY - CURRENT MEASUREMENT

2904 2n2

1N5062

3902

9954

9952 1R5

2905

2n2

* *

6933

*9956 *
3905 -t NTC

6903 GBU4J 3

1N5062

6931

1N5062 2

* 6930

P1 290V (301V)

2906

470u

2911

100K

3995

22n

6932

1N5062

* 5912
1 2 3

TRANSFORMER

18 17 16 15 14 13 12 11 10

*
BYD33M 6906

*
100P 2971

4 5 6 7

5911

*
P3

100K

3941

3917

2M2

* * * 3959
3R3

8 9

6908

2920

10n 2912

47u

BYD33J P2

* 17V6 (15V6) *7902 STR-F6626

4 1
VIN OCFB GND D S

3920

2966

3n3

(301V) 290V 3

2913

3962

P5 6911 BYD33J

*
1K5 2914 1n5

P4

100mHz

3991

3922

2915

470p

680R

3924

0R1

5906

2K7

1V6 (0V7)

0V (0V)

1n5

3K3

BYD33J

6910

CL 86532033_006.AI 160698

Control due to the mains voltage

A part of the rectified mainsvoltage is coupled to pin1 of IC7902 by dividing the voltage by R3924, R3922 and R3941. The higher the input voltage, the more the transformer current is limited. In this way the maximum power of the power-supply is limited.

Personal notes

A8.0A

POWER SUPPLY Control circuitry

31

Control circuitry

MEASURING MAINS - VOLTAGE

2904 2n2

1N5062

3902

9954

9952 1R5

2905

2n2

* *

6933

*9956 *
3905 -t NTC

6903 GBU4J 3

1N5062

6931

1N5062 2

* 6930

P1 290V (301V)

2906

470u

2911

100K

3995

22n

6932

1N5062

* 5912
1 2 3

TRANSFORMER

18 17 16 15 14 13 12 11 10

*
BYD33M 6906

*
100P 2971

4 5 6 7

5911

*
P3

100K

3941

3917

2M2

* * * 3959
3R3

8 9

*
6908 BYD33J P2

2920

10n 2912

* 17V6 (15V6) *7902 STR-F6626

4 1
VIN OCFB GND D S

47u

3920

2966

3n3

(301V) 290V 3

2913

3962

P5 6911 BYD33J

*
1K5 2914 1n5

P4

100mHz

3991

3922

2915

470p

680R

3924

0R1

5906

2K7

1V6 (0V7)

0V (0V)

1n5

3K3

BYD33J

6910

CL 86532033_004.AI 030898

Primary current measurement

The current through the MOSFET of IC7902 is also going through R3924 which increases the voltage on C2915 and so the voltage on pin1 of IC7902. This will shorten the on-time of the MOSFET.

Personal notes

32

POWER SUPPLY Control circuitry

A8.0A

Control circuitry

2904

2n2

1N5062

3902

9954

9952 1R5

2905

2n2

* *

6933

*9956 *3905-t
NTC

6903 GBU4J 3

1N5062

6931

1N5062 2

* 6930

P1 290V (301V)

2906

470u

2911

100K

3995

22n

*6932
1N5062

* 5912
1 2 3

TRANSFORMER

18 17 16 15 14 13 12 11 10

*
BYD33M 6906

*
100P 2971

4 5 6 7

5911

*
P3

100K

3941

3917

2M2

* * *
3959 3R3

8 9

6908

2920

10n 2912

47u

BYD33J P2

P6

* 17V6 (15V6) *7902 STR-F6626

4 1
VIN OCFB GND D S

3920

2966

3n3

(301V) 290V 3

2913

3962

P5 6911 BYD33J

*
1K5 2914 1n5

P4

100mHz

3991

P6 POWER
3922

2915

470p

680R

3924

0R1

5906

2K7

1V6 (0V7)

0V (0V)

1n5

3K3

BYD33J

6910

5V / div AC 0.2ms / div

CL 86532033_007.AI 180698

Protection
IC7902 has a latch circuit which latches when the thermal shutdown circuit or the over voltage shutdown protection circuit becomes active. The Latch circuit continues to stop the operation of the power supply when overvoltage protection or thermal shutdown circuit are or were in operation. As long as the sustaining current of the latch circuit is supplied via R3917 (startup resistor) the power supply circuit sustains OFF. A restart can be arranged by switching off the mains voltage and subsequently switching on again. If IC7902 is in protection the oscilloscope wave form P3 can be measured at pin 4 of IC7902.

secondary output which is caused when the control circuit is open . Check in this case IC7904, IC7950 and the +142V.

Under-voltage behavior of the power supply

In case a secondary voltage is short-circuited or loaded to much, the voltage on winding 8-9 of T5912 is decreasing and so is the voltage of pin 4 of IC7902. When this voltage drops below the shutdown voltage, IC7902 stops operating. This will enable an increase of the voltage on pin4 via R3917. Undervoltage can be recognized by an intermittently starting of the supply.

Thermal protection
The thermal shutdown circuit triggers the latch circuit when the frame temperature of IC7902 exceeds 140C (typ).

Over-voltage protection
The over-voltage protection circuit, triggers the internal latch circuit of IC7902 when the voltage across C2912 exceeds 22.0V (typ). Since the voltage across C2912 is supplied from the drive winding (8-9) of the transformer and this voltage is proportional to the output voltage, it prevents overvoltage at the

A8.0A

POWER SUPPLY Low power stand-by

33

Low power stand-by

(7V7) 2V9 11V5 (10V)

P6

TCDT1101G 7950 (15V6) 5 17V6 1

12V5 (11V)

3976

1K8

REGULATOR OPTO-COUPLE

3944

820R

3926

4K7

=H =L

10K BZX79-C10 3947

6940

STBY

A8-01

3948

3946

5K6

3945

3943

2919

1m

(-1V5) 0V6 7961 BC847B

7962 BC847B

7963 BC847B

0V OSCILLATOR (0V6) +5V_STBY

CL 86532033_010.AI 080698

LOW POWER STANDBY CONTROL

ON-OFF SWITCH OSCILLATOR

CL 86532033_010.AI 160698

To create a very low power consumption during standby, the SMPS is forced in burst mode. An oscillator formed by TS7961, TS7962, C2945, C2946, R3945 and D6940. During normal operation this oscillator is blocked by TS7910 via TS7963. During standby the oscillator is activated. The output of the oscillator is present at the collector of TS7960. When TS7960 is conducting, current is flowing through the diode of opto-coupler 7950 and the transistor part of IC7950 becomes saturated, which causes the voltage across C2915 to raise above 3V. This will prevent the oscillator of IC7902 from oscillation. Without any switching of the FET of IC7902 no switching losses will occur which will decrease the power consumption in standby. When TS7960 turns off, the SMPS will start working again. So in standby the power consumption will be low but the ripple on the output voltage will be higher. This is no problem due to the fact that the set is not operating.

Personal notes

22K

0V6 (0V)

3965

11V5 (0V6)

10K 0V (0V7) 7960 0V BC847B (7V2)

0V (0V6)

7910 *BC847B

22K

* 2947 1n

* * *3949 *2945 33n

* * *2946
100n

82K

13V5 (0V3)

5K6

34

VIDEO PROCESSING Tuner

A8.0A

VIDEO PROCESSING Tuner

Tuners The TELE9-087A for PAL MULTI. The TELE9-108A for PAL MULTI China. The TELH9-205A for NTSC-M only sets

The A8 chassis uses a PLL controlled tuner. The tuners are full band, but dependent on the system (PAL/SECAM/NTSC) the tuning range is as follows

Positive modulation system SECAM L' frequency range 44.75-110.25 MHz 110.25-890.00 MHz

Pal frequency range SECAM L Band low mid high frequency range 44.75-150.25 MHz (E2-S7) 150.25-426.50 MHz (S8-S36) 426.50-890.00 MHz (S37-E69) System B,G,H L I NTSC frequency range L' (band I) Band low mid high off-air/cable channels D,K China 55.25-127.25 MHz M 133.25-361.25 MHz 367.25-801.25 MHz 45.75 42.17 41.25 38. 0 33.57 31.5 32.15 33.9 38.33 40.4 picture 38.9 38.9 38.9 colour 34.47 34.47 34.47 sound1 33.4 32.4 32.9 32.35 sound2 33.16

Systems B,G,H,I,L,L',D, K,M and N can be received with the A8 chassis. Be aware that for most pattern generators the maximum tuning frequency is 860.00 MHz. At pin 9 of the tuner 33V (+VT =Voltage Tuning) has to be present for tuning a channel. This 33V is derived (via R3994 68k and D6955 33V zener diode) from Vbat (+140V) from main power supply (diagram A1).

A8.0A

VIDEO PROCESSING Block diagram video path without PIP

35

Block diagram video path without PIP

OSD/TXT/SCART etc TUNER IF CVBS+SIF IF SOUND BPF SOUND TRAP FBL R G B

TDA884X
RGB PROCESSING +SWITCH

R G B TO CRT

SIF (to sound proc..) SWITCH

CVBS_INT CVBS_EXT

CHROMA PROCESSING

MATRIX

CVBS_MON YC/CVBS_EXT YC/CVBS_EXT YC/CVBS_EXT COMB (opt.)

Y U V TDA9178 (opt.)

CVBS_MON

CL 86532063_002.eps 040898

The processing is largely handle by a single-chip video-processor IC7150 TDA8844 with built in IF-detector, CVBS and SVHS source select, luminance and chrominance separator, PAL/ NTSC/SECAM chrominance decoder, video controller and horizontal & vertical sync/geometry-processor. The difference with previous TV-processors is that the SECAMdecoder is integrated and also the delay-line. Three video-signal flow diagrams are possible in the A8 chassis: video path without PIP video path with YUV PIP (for Latam/AP) video path with YC PIP (for Taiwan/Korea)

Personal notes

The IF signal is fed to pin 54 of IC7150 (TDA8844). The demodulated CVBS is available on pin 6 and fed back to pin 13 for I/ O-switching. The selected video-signal on pin 38 is fed to I/O SCART/Cinch and optional a comb-filter. Without comb-filter is the video-signal internally processed, but the front-end signal can always be measured on pin 38 IC7150 to check correct tuning. YUV (pins 28,29,30) is fed via TDA9178 to the RGB matrix (pins 27,31,32). After the matrix it is possible to switch to an external RGB-source (or OSD/TXT).

36

VIDEO PROCESSING Block diagram video path with YUV PIP (for Latam/AP)

A8.0A

Block diagram video path with YUV PIP (for Latam/AP)

In this block diagram is a splitter added for the PIP-tuner and of course the PIP/DW circuitry (PAL/NTSC).

Personal notes

A8.0A

VIDEO PROCESSING Block diagram video path with YC PIP (for Taiwan/Korea)

37

Block diagram video path with YC PIP (for Taiwan/Korea)

In this diagram use is made of MC44462B for PIP processing. This IC is NTSC-only. For Pal Multi Asia Pacific sets an additional M-trap (L5145) will be required for filtering the sound carrier of an NTSC-M transmission to avoid interference in the picture. (see diagram A4 in the service manual)

Personal notes

38

VIDEO PROCESSING IF Demodulation (IC7150-A)

A8.0A

IF Demodulation (IC7150-A)

The video-signal is demodulated by means of a PLL carrier regenerator (no external LC-circuit anymore only a RC-network on pin 5 which determines the IF-loop filter). Internal there is a frequency detector and a phase detector. During acquisition the frequency detector will tune the VCO to the right frequency. The initial adjustment of the oscillator is realized via the IIC-bus. In the service menu IF-PLL is indicated, but this alignment has no effect anymore.

el). As R3131 is shortened, the AGC time-constant is shortly reduced giving a faster response.

Automatic Frequency Control (AFC)

The TDA8844 IC implement the alignment free IF-PLL concept which enables automatic frequency control via IIC. There is no AFC voltage anymore only control via software. For search tuning two input signals (internally in the TDA8844) are used: video IDENT and AFC. If a transmitter is tuned the IDENT is valid and a digital AFC level is followed (as long as the IDENT is valid). Automatic Channel Installation (ACI) is possible with the A8 chassis. All channels will be stored according to the ACI-data. This data is a hidden (not selectable for the customer) txtpage(s). If ACI is not used by the cable network then the auto-store procedure is used. For Europe the channels found will be stored beginning from max. program number downwards. For Asian Pacific the channels found will be stored beginning from program 1 upwards. For Germany, Austria, UK and Switzerland, the stored channels will be stored according to a table in the software (ATS).

Automatic Gain Control (AGC)

AGC control is used to maintain a constant signal at the tuneramplifiers when the incoming signal on pin 49 and 48 of TDA8844 becomes too high (above the take-over level). The take-over level (limiting point) of the AGC-control can be adjusted via I2C in the service menu. For negative modulation (BGIDKM systems have all negative modulation) the AGC circuit detects the top-sync level. The AGC DC signal from pin 54 TDA8844 is fed to pin 1 of the tuner. In normal situations (not at program switching) the AGC DC signal is smoothed by C2126 and R3126. To enable a fast AGC control at program switching, D6130 or D6131 shorten R3131 at high AGC peaks (a program switch gives a fast change from low to high or from high to low HF lev-

A8.0A

VIDEO PROCESSING IF Demodulation (IC7150-A)

39

Sound trap
The baseband CVBS signal (pin 6 of TDA8844), with a nominal value of 2Vpp, also contains the sound signals (FM demodulated mono sound for intercarrier sound processing; see Audio Processing) at a subcarrier of 4.5 / 5.5 / 6.0 / 6.5 MHz. These sound signal are filtered out by the sound trap crystals 1167,1168 and (selectable) 1165. Crystal 1167 is a 5.5 /5.75 MHz or triple trap 5.5/5.75/6.5 MHz ceramic filter, and crystal 1165 is a 4.5 MHz (for NTSC-M) ceramic filter (crystal 1168 is reserved and can be used as a 6.0 MHz sound trap for PAL/ NICAM I, or NTSC-M sound trap of 4.5MHz). For audio various concepts are possible: BASICFM mono/ AM mono NICAMFM stereo / NICAM BG/I/L'/M 2CS onlyFM mono/stereo BTSCmono/stereo and SAP (Second Audio Program)

Personal notes

BASIC
For the BASIC set, the FM-sound is demodulated by IC7150 (TDA8844). The baseband video-signal is fed via bandpass filter 1158 to pin 1 of IC7150. The mono output is pin 15. For AMsound comes from Quasi Split Sound pin 10 IC7401 (TDA9810 on QSS-panel). The demodulated AM-signal is directly fed to the amplifier.

NICAM, AM Sound
The IF-output from the tuner is also fed to the QSS-panel (Diagram I). On the QSS-panel are two SAW filters used depending on system L/L'. Also the IC is internally switched via pin 7 because of different IF-sound frequencies. The demodulated AMsound is available at pin 6 and fed to IC7430 (MSP3410D) for further sound selection. The IF-sound output pin10 IC7401 is fed to the MSP3410D. This IC can demodulate NICAM, 2CS and MONO signals.

2CS
The baseband output from IC7150 pin 6 is fed to the MSP3400C (without NICAM) for further demodulation.

BTSC/AV stereo
The baseband signal from IC7150 pin6 is fed to IC7437 (TDA9855) for decoding and sound processing. One of the rear cinch inputs, and the signal from the front cinch connectors is selected by IC7436 (HEF4052). The selected signal is fed to the TDA9855 (pin 12 and 41).

40

VIDEO PROCESSING I/O switching with SCART REAR I/O panel

A8.0A

I/O switching with SCART REAR I/O panel

In chassis A8 are two versions I/O-panels: I/O with SCART and the other with CINCH connectors. The block diagram below shows the I/O switching from the external inputs for sets with a SCART REAR I/O panel ( see Diagram E). The input of SCART1 is CVBS + RGB + LR and the output is always the video (+ sound) signal from the tuner (CVBS_INT). The input of SCART2 is YC + CVBS + LR. The output signal on SCART2 is CVBS_MON (+ sound), except when SCART2 is selected as the source for the main picture. Then the output on SCART2 is CVBS_INT (+ sound). SEL-MAIN-R1R2 is the selection between SCART1 (R1) and SCART2 (R2) via IC7100-A. With SEL-FRNT-RR selection is made between front and rear (IC7250 chassis).

Personal notes

A8.0A

VIDEO PROCESSING I/O switching with CINCH REAR I/O panel

41

I/O switching with CINCH REAR I/O panel

CINCH in/out (see Diagram F or L) Y/C and CVBS signal of REAR2 are connected together, The CINCH I/O panel has maximum 2 inputs and one output. The output is always the same source as the main picture (CVBS_MON). The selection for CVBS_MON is done in the BIMOS. Since the PIP panels can only handle external CVBS signals, the Y and C signals are added in order to create a CVBS_PIP signal in case of a YC input signal.

Personal notes

42

VIDEO PROCESSING Luminance processing

A8.0A

Luminance processing

The switching between external video (CVBS_EXT) and internal video (CVBS_INT) and the switching between YC and CVBS signals is done in the TDA8844. Two different comb filters are used: SAA4961 (PAL/NTSC) or SAA4963 (NTSC only). Since only the SAA4963 has a separate Y input and the SAA4961 has a combined Y/CVBS input, the switching between YC and CVBS is a little different for both comb filters. Switching on and off the comb filter is done via pen 33 IC7150 (TDA8844). The switching is done with the 4.43 MHz (or 3.58 MHz) oscillator signal imposed on a DC-level:

There is an Y/C adder realized with TS7243/TS7242(diagram A13) , this is necessary for PIP. IC7250-C selects between the video signal from front and rear and then via TS7270 fed to the PIP-panel. Y/C via rear or front: chrominance is fed via the combfilter to pin 10 TDA8844 (diagram A5) and luminance is fed to pin 11. In the TDA8844 source select takes place and then CVBS_MON is available on pin 38 . A second Y/C adder is realized around TS7261 (diagram A13). The transistor is driven by the SVHS-mode signal. In SVHS the base is low; chrominance is added via R3262/R3263 to the luminance via R3264. The video-signal is via the buffer-stage fed to I/O panel for Video out. The figure above shows the block diagram of the video switching of the TDA8844 in combination with SAA4963. In this case the CVBS_MON is the same as Y/CVBS_MON.

pin 33 low high

comb filter off on

If the video switching of the TDA8844 in combination with SAA4961. For CVBS_EXT and CVBS_INT sources the output signal of the TDA8844 (Y/CVBS_MON) is used for CVBS_MON out. For external YC signals the CVBS_MON is created by adding Y/CVBS_MON and C_EXT. This is controlled by the SVHS_MODE control signal from the uP. If the combfilter is not present then the jumpers (9200 and 4201 diagram A5) are present and the external Y/C signals are directly fed to the pins 10/11 IC7150.

A8.0A

VIDEO PROCESSING RGB - switching

43

RGB - switching

In A8 there 4 possible RGB sources: TXT and/or OSD from uP OSD from PCF8515 OSD generator EPG External RGB from SCART or Guide Plus (GEMSTAR)

The RGB_KILL signal is used to overrule an external RGB source from SCART.

Status signals
There are 3 status signals which come from SCART REAR I/O panel. With the information which comes from these status signals the set is set to the correct mode.

In previous chassis there was also RGB from PIP possible. In the A8 chassis the PIP/DW panel is in the YUV or Y/C signal path (see also the block diagram of the video path). The TDA8844 has only one RGB input, so switching between the different RGB sources is needed. The figure below shows the RGB switching. All sets have RGB_TXT and/or RGB_OSD from uP. Only AP sets have the PCF8515 (separate OSD-IC) If the set has TXT from uP and OSD from PCF8515, these RGB sources are connected together via diodes and then connected to the input of TDA8844 directly. The software should make sure that there is no OSD during TXT. Jumpers A are in. For EPG sets a separate TXT/EPG processor (IC7007 diagram S) is used. The RGB of the EPG and OSD from (P are connected together via diodes and then connected to the input of TDA8844 directly. Jumpers A are in. For sets with external RGB (SCART), the selection between RGB_TXT/OSD and RGB_EXT is done with a IC7275 (TDA8601) RGB-switch.

STATUS SIGNAL STAT1

DESCRIPTION

Remark

CVBS status from pin 8 of SCART1. . This is fed to uP pin 10

0 - 2V: internal CVBS 4.5 - 7.0V: 16:9 aspect ratio 9.0 - 12V: 4:3 aspect ratio 0 - 2V: internal CVBS 4.5 - 7.0V: 16:9 aspect ration 9.0 - 12V: 4:3 aspect ratio >0.9V is RGB mode

STAT2

CVBS status from pin 8 of SCART2.

This is fed to uP pin 9. FBL RGB status from pin 16 of SCART1

44

VIDEO PROCESSING Chrominance Processing

A8.0A

Chrominance Processing

TO/FROM COMB-FILTER
C_COMB Y_COMB

C_EXT 4201 Y_CVBS_EXT +8V 8V3 V5 Y_CVBS_MON 7176 BC847B 2V3 3175 100R V4 FOR WITHOUT COMB FILTER 9200 V7

V6

560R

3176

1V7 EXT. CVBS BUFFER

2181

2180

100n

100n

7150-B TDA8844 2176 17 470n 3V4 V2

CVBS_INT

2V3 38

1V2 10

3V4 11

COMB_ON 0V4 33 28 2V6 Y_OUT

V8a

Y 2177 470n 13 3V7 9 6V6

SANDCASTLE

PAL/INTSC

29 2V3 B_Y_OUT 30 2V3 R_Y_OUT

V8b

SY 16 2V5 35 * 4192 2V3

* 4195
1192

34

2V5

4V7

36

3197

V8c

2197

1190

2196

1189

2186

2187

2188

220n

22n

2u2

1191

*
2189 15p

*
2191 15p

*
2192 15p

*
2190 15p

33K

*7191

* 3191
33K

4190

* 3194

*
+8V

* 7190 BFS20 * 3190

33K

* * 3192
33K

BFS20

*7192
BFS20

BC847B

* 7189

* 3189
33K

SYS1 PAL M PAL BG NTSC M PAL N 0 0 1 1

SYS2 0 1 0 1
SYS2 SYS1

* 7193 BC847B

* 3193
33K

4198

100n

1n

100K

CL 86532063_006.eps 040898

Chrominance
The chrominance signal is internally applied to the PAL/NTSC/ SECAM chrominance decoder inside IC7150-B. Also the 64 S delay line is integrated in the TDA8844. Chrominance can also be fed in on pin 10 from COMB-filter or SCART and luminance on pin 11. The chrominance demodulator determines whether a PAL, NTSC or SECAM signal is present and subsequently decodes its R-Y and B-Y signals. For LATAM there are three BI-NORMA versions, one TRINORMA and one FOUR-NORMA. Depending on the version a 3.6MHz x-tal or a 4.4MHz x-tal is connected to pin 35 of the BI-MOS. During INITIALIZATION of the BIMOS the XA,XB control bits have to be set in order to get a correct calibration of the BIMOS. If the XA,XB setting does not tally with the x-tal connected to pin 35, the line output transistor can be killed. So, this can not be done via a software option!! A option jumper between pin 52 of the uP and ground is used to distinguish between the x-tals connected to the BIMOS.

Personal notes

A8.0A

VIDEO PROCESSING Chrominance Processing

45

Chrominance Processing

BI- TRI and FOUR NORMA configuration

SET VERSION BI-NORMA-M BI-NORMA-B BI-NORMA-N TRI-NORMA FOUR-NORMA possible systems PAL-M/NTSC-M PAL-BG/NTSC-M PAL-N/NTSC-M PAL-M/PAL-N/NTSC-M PAL-M/PAL-N/PALBG/NTSC-M x-tal on pin 34 1x 3.6MHz 1x 3.6MHz 1x 3.6MHz 1x 3.6MHz 3x 3.6MHz x-tal pin 35 1x 3.6MHz 1x 4.4MHz 1x 3.6MHz 2x 3.6MHz 1x 4.4MHz pin 52 high low high high low

The crystals are also used as a reference for the line frequency (sync diagram A6). This means in case of colour problems (only black/white) the crystal could cause the symptom. Replace the crystal only by an original one! In case of only blackwhite the problem can also be the loop filter on pin 36 IC7150. So not always the IC causes the problem but mostly components around the IC. A defective crystal: no synchronisation! The DC-level of the CVBS-signal (pin13 front-end signal and pin17 from SCART) is also very important. In case this level is not correct than the symptom could be no picture.

Personal notes

46

VIDEO PROCESSING Chrominance Processing

A8.0A

SCL 3335 7150-C TDA8844

SDA 3336 RGB_SW_OFF

BAS216 6300

V12a RO 21 1V9 3306 47R V12b 3309 47R 3310 V12c 47R 3311 47R 3312 10K

BAS216 6301

BAS216

SCL

SDA

6302

7100R 8100R 3V4 3V

1V9 M30 1 1V8 1V9 2 3 4 5V9

BCI

V9a Y_IN B_Y_IN R_Y_IN V9c V9b 2V6 2V3 2V3 27 31 32 LUMIN BYI RYI
G-Y MATRIX RGB

GO 20

1V8

3307 47R

BO 19

1V9

3308 47R

BLKIN 18 RI 23 GI 24 BI 25 RGBIN BCLIN 26 22

5V2

3303

2K2 3304

2K2 3305

2302

47p 2301

47p 2300

2K2

G_IN

R_IN

B_IN

3V7 3V5 0V2

M12A

****

+8VB TO M12B & M13B OF TRANSPARENT OSD A9 OR TO M12C & M13C OF

3V5 3V5

9222

2293

2294

2292

3325

**** M13A

CONTROLS A8 WHEN OSD PANEL IS PRESENT

180k

47n

47n

47n

AVE. BEAM - CURRENT LIMITER

V10a 12 R_OUT 11 FROM SEPARATE TXT-IC WHEN PRESENT G_OUT V10c 2V2 V10b 6328 BAS216 3331 47K EHT_INFO

2322

2323

4u7

2V2

2321

100n

B_OUT

FBL_OUT

3V6 100R

3293

1K

7325 BC857B

1V7

6325

22K

13

0V2

3323

3292

22R

2K2

10

3327

+8V

3330

2V2

150K

3326

1u

47p

3324 180k

BAS216 LOT SATURATION LIMITER

CL 86532063_004.eps 040898

YUV
The demodulated video-signal can be checked on pins 28,29,30 IC7150 and is fed to pins 27,31,32. In this path the YUV panel can be inserted. Without this panel, the jumpers 4225/4226/4227 are in. On the YUV-panel TDA9178 is used, which can control various picture improvements: histogram processing, colour transient improvement and luminance transient improvement. The TDA8844 can also do some picture improvements: Sets without TDA9178; for sets without TDA9178 the Dynamic Skin Control and the Blue Stretch is controlled in theTDA8844. There is no Green Enhancement. Sets with TDA9178: for sets with TDA9178 the Dynamic Skin Control and Green Enhancement are controlled in the TDA9178. The Blue Stretch is controlled in the TDA8844 and the Blue Stretch of the TDA9178 is switched off. Green Enhancement. Is intended to shift low saturated green colours towards more saturated green colours. This shift is effective for only that part of the picture that matches with low saturated green. Blue stretch. For parts of the picture that are white, the colour temperature is changed a little bluish coloured white to give a brighter impression.

Dynamic Skin Control. Skin tones are very sensitive for hue errors, because the human eye has an absolute feeling for skin tones. To make a picture look free of hue error, the goal is to make sure that skin tones are put at a correct colour.

When the TDA9178 is used then the noise reduction is also available. The action of the noise reduction has also influence on the sharpness control. IF a noisy signal is received then the noise reduction should be high and sharpness low and also vice versa: Good picture: DNR=low; sharpness= high; Bad(noisy) picture: DNR=high; sharpness=low

TO C30 OF CRT PANEL B

***

A8.0A

VIDEO PROCESSING Chrominance Processing

47

7101 PCA8515P 21 VDD 12 VSS 13 RESET_

FROM UC 7000 EXT/INT DATA SWITCHING BUFFER CHAR SIZE REGISTER/ CONTROL WRITE ADDRESS COUNTER ADDRESS BUFFER SELECTOR DISPLAY CHAR RAM DISPLAY ROM VERTICAL POSITION REGISTER/ COUNTER 5 CONTROL SIGNALS

CONTROL REGISTER P00 17 I/O PORT BUFFERS P01 19 P04|ACM 2

SLC

9 SCL|SCLK 8 SDA|SIN
I 2 C SLAVE RECEIVER OR HIGH-SPEED I/O BUFFER HORIZONTAL POSITION REGISTER/ COUNTER

SDA

14 E 15 HIO_|I2C

AVDD 24

5 C

PLL OSC

INSTRUCTION DECODER INTERNAL

AVSS 23

7 HSYNC 6 VSYNC
CSYNC SEPAR

SYNCHRONOUS

CIRCUIT

CRYSTAL OSCILLATOR

TESTING CIRCUITRY

DISPLAY CONTROL AND OUTPUT STAGE

ACM-VOB2

GVOW1

RVOW0

BVOW2

11

10

16 18 20 1

FBVOB

XTA2O

IVOW3

XTA1I

TST1

TST2

22

R G B FB TO RGB SWITCH 7275

9.4

CL 86532033_017.AI 160698

OSD-IC7101
See also chapter "Teletext and On-Screen Display. 253 fonts are possible with 4 different sizes, foreground/background colours, shadow. This IC is put on a separate panel. On the connector O06 Hand V-sync are fed in for stable OSD and for OSD-positioning. What has to displayed is transmitted via I2C. The RGB-outputs and fast-blanking are fed to IC7275 via connector O05. TXT/EPG (diagram P) uses a separate microprocessor for Europe, because in these countries features like ACI/FLOF/TOP are used. These features need also some memory and that was not enough available in the main microprocessor IC7000. In the circuit diagram P two versions are indicated: the SAA5262 and SAA5263: Both support also ACI and the SAA5263 can do the 'simple' Electronic Program Guide (EPG) feature. The commercial name for EPG is NextView: (this part is also described in the MG98/MD2.2 TM)

NexTView is a feature with which it is possible to retrieve a program listing with one press of the button. NexTView (Simple Program Guide): For each program, during installation the user should indicate on which teletext page the program guide can be found. This teletext page is then displayed when the nexTView command is given. This feature only requires a software modification and no hardware modification in the set. For each program the page number in which this information is contained has to be given.

48

VIDEO PROCESSING Chrominance Processing

A8.0A

+8V

3336 4R7

2226

100n 2225

7770 TDA9178

13 12 2
NC

10 23 24 18 20
GND VCC SOUT 21

10u

7150-C
Y - IN B - Y - IN R - Y - IN

Y - IN

6 YIN 8 UIN 9 VIN 22 CF

SDA

LUMA PROCESSING CHROMA PROCESSING CONTROL SPECTRAL PROC ADC

V12c

V12b

V12a

YOUT 19 UOUT 17 VOUT 16

WINDOW

27 31 32 G-Y MATRIX RGB

21 20 19 18

1M30 2M30 3M30 5M30

R G B BCI

1C30 2C30 3C30 5C30 TO CRT PANEL

U - IN V - IN

ADR

DEC

SCL

AD1

AD2

AD3

SC

FBL_TXT_OSD

14 11 7

15 3

1 RES
+8V

R_TXT_OSD G_TXT_OSD B_TXT_OSD

26 25 24 23
RGB_SW_OFF

SDA

3338

3339

SANDCASTLE

SCL

3337

100n

2227

0R

SDA

SCL

CL 86532063_005.eps 040898

RGB-dematrixing
RGB dematrixing dematrixes the -(R-Y), -(B-Y) and the Y signals into RGB signals. Contrast, saturation and brightness control are realized via I2C (for an external RGB-source brightness and contrast is also controlled).

If the beam current becomes too high, the picture tube could be damaged. If the voltage on pin 22 is reduced then also the contrast is decreased. The EHT-info is fed to R3331/3324. Via TS7325 a fast PWL is realized and via D6328 the average PWL because of RC-time C2322/3331. The voltage on pin 22 is also dependent of the contrast setting in the picture menu.

FBL-IN
Via the FBL-IN fast blanking signals on pin 26 of IC7150-C, both the fast blanking and the RGB source select is realized: When FBL-IN at pin 26 is higher than 4V DC, IC7119-4C is in the OSD mode (only the FBL-IN coming from the OSD generator of the P gives 8V DC). If pin 26 is higher than 4V DC, the RGB output pins 19-20-21 of the video controller are made high-ohmic, so RGB OSD info from the P can be inserted. This mode is not used in A8. When FBL-IN at pin 26 is between 0V9 and 4V DC, IC7150C is in the external RGB mode. RGB from TXT or SCART can be inserted at pins 23,24,25. When FBL-IN at pin 26 is lower than 0V9 DC, IC7119-4C is in the internal RGB mode.

Transparent OSD only Europe

See diagram A7/A9 Can be realized by controlling the peak white limit. To realize this the circuitry of diagram A9 is added. The fast blanking (FBL1) is fed to the collector of TS7361 to make a box with reduced contrast. To the base of the TS7361 is FBL2 fed. This makes the OSDblanking and the OSD is inserted via the RGB-lines from the P to the RGB-inputs (23-26). In the circuit diagram A7 there is an option for soft clipper with TS7316/TS7318/TS7320. This has also effect on the PWL pin 22. If one of the voltages of the RGB-drive is too high then TS7320 conducts to reduce contrast. In this case the peak white limit via the EHT-info has less function, because the peaks are now limited by the soft clipper.

Peak white limit (PWL)

See diagram A7

A8.0A

VIDEO PROCESSING Chrominance Processing

49

Via diodes D6300/6301/6302 the RGB-outputs are very fast switched off. At switch-off these diodes will conduct so the RGB-drive is made high. To prevent a very bright picture the vertical deflection is put on top of screen so the switch-off spot is not visible.

Personal notes

Cut-off control/white drive

The picture tube is continuously adjusted to prevent visible ageing of the picture tube. In this way the customer has always a perfect picture. This is so-called 'Continuous Cathode Calibration'. The function is realized by means of two-point black level stabilization. By inserting two levels for each gun and comparing the result with 2 different reference circuits the drive is controlled. With two different reference currents the influence of picture tube parameters like the spread in cut-off voltage can be eliminated. The measurement of the "high" and the "low" current of the 2point stabilization circuit is carried out in 2 consecutive fields. The leakage current is measured in each field, The maximum allowable leakage current is 100uA. The current is measured via Beam Current Information (BCI) that is fed back to pin 18 of IC7150-C. When the TV is switched-on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels and then there is RGB-drive.

50

VIDEO PROCESSING CRT panel

A8.0A

CRT panel

VDD 6 MIRROR 1 TDA6107Q MIRROR 4 CURRENT SOURCE 1x THERMAL PROTECTION CIRCUIT Vl(1), Vl(2), Vl(3) 1, 2, 3 Rl Ra 3x CASCODE 2 Rl VIP REFERENCE MIRROR 3 DIFFERENTIAL STAGE 6 Io(m) 3x 1x 9, 8, 7 Voc(3), Voc(2), Voc(1) MIRROR 5 CASCODE 1

MIRROR 2 4
CL 86532033_028.AI 160698

RGB amplifier
The RGB amplifier on position 7830 is located at the CRT-panel. This integrated RGB video amplifier has three amplifier channels inside and is intended to drive the three cathodes of the colour CRT. The main features of IC TDA6107 are : This amplifier is connected to 200V only because 13V reference is generated internally. Black current stabilization output is also generated internally and this signal goes directly to the BiMOS feedback input (see diagram A7). Thermal protection.

Cathode Calibration', provided by the BiMoS. In this concept the cathode drive is adjusted at two points and hence provides better accuracy of black level.

Picture tube flash over protection

TDA needs external protection consisting of D6831, D6833, and D6835 combined with 100 Ohm resistors R3831, R3833 and R3835 to protect the video amplifier against picture tube flash-over discharge. These diodes clamps the cathode output voltage to VDD + diode. To limit the diode current , external resistors of 1K R3832, R3833 and R 3835 are connected in series with the cathode output of each gun, in conjunction with the 2KV sparksgaps in the CRT socket.

The amplifiers are basically negative feedback op-amps located inside the IC TDA6107. Pins 1, 2 and 3 are inverting inputs for green, red and blue ; pins 7, 8 and 9 are cathode outputs for blue, red and green. Pin 5 is the black current stabilization output.

Cut-off stabilization
Cut-off stabilization is an auto tuning loop (active during a four line period prior to the end of a field blanking pulse) which stabilizes the black current of each RGB-channel sequentially and independently. This is a new concept known as 'Continuous

A8.0A

VIDEO PROCESSING CRT panel

51

CRT panel

SCAVEM # 5863 +200V 5u6 ## 5862 5u6 ## 3860 3874 8k2

3870

2871

100u 10u FOR 34" 3875

3865

4K7

18K

10R

SCAVEM DRIVER 2873 2874 56p 3868 2869 22n

7862 BD830 72V

5861

22u

1K

2860

72V6 3

C80 TO SCAVEM COIL

3861

3K3 2863 15p 3862

3877

5V6

2865

4p7

3869

3872

1N4148 3876 33R 2867 270p

15R

3881 1V410R 7860 BF199 RGB ADDER

4V7 6861 BAS216 6862 BAS216

150R

100n 7863 BD829 0V6

56K

3880
0V

2K7 2862 18p 3863

0V7 2864 470n

820R FOR 34"

2870 22n

2868

100p

3873

470R

220R

2861 22p

2K2

2K2

220R

470n 3866

3864

2866

3867

3882

## = 28"/29"/37" # = 34"

5860

1K

10R

47p

37V

2872

5V6

100R

6867 13V5 SCAVEM PRE-DRIVER 7861 1N4148 BF370 6868

9876 2876

3871

56K

10u

2 36V 1

# ##

##

CL 86532033_025.AI 160698

SCAVEM
Scavem means SCAn VElocity Modulation; the Scavem-circuitry is implemented in the layout of the picture tube panel so it is not an extra module. This means that the horizontal deflection is influenced by the picture content. In an ideal square wave, the sides are limited in slope by a limited bandwidth. (5 MHz). Scavem will improve the slope as follows: At a positive slope, a scavem-current is generated which supports the deflection current. The first half of the slope the spot is accelerated and the picture is darker, while at the second half of the slope, the spot is delayed and the slope becomes steeper. At the end of the slope, the scavem-current decays to zero and the spot is at the original position. An overshoot occurs which improves the impression of sharpness. At the negative slope, the scavem-current counteracts the deflection and during the first half of the slope, the spot is delayed, the slope becomes steeper. During the second half the spot accelerates and the scavem-current is zero at the end of the slope.

Operation
Via the three resistors R3861, R3862, R3863, red, green and blue are added together and offered to the emitter of 7860. On the collector of this transistor, configured in a common base, the sum of these three signals is obtained. Via the emitter follower 7861 this signal is conveyed to the differentiator C2867, R3868 and R3869. Only the high frequencies are differentiated (small RC). The positive and negative pulses of this signal drive 7863 and 7862 respectively into conductivity. The DC setting of the output stage is set by R3870, R3871, R3872 and R3783. The working voltage of the transistors is at half the supply voltage. At the positive section of the pulse, the current flows through R3869, C2869, the scavemcoil and TS7863. At the negative section of the pulse, the current flows through R3869, C2869, the scavem-coil and TS7862. Both currents flow through R3869 and the voltage across this resistor is a measure for the scavem-current. This voltage is fed back via R3868,.D6867 and D6868. In this way the feedback operates with an approx. 0.6V threshold. Because of this, the scavem-current is limited to 50mA.

52

Synchronization Horizontal and Vertical Synchronization

A8.0A

Synchronization Horizontal and Vertical Synchronization

+8V +8VB A2-17 PHASE_CORRECTION

2816

2815

3805

2819

4K7
L1 A2-08 H_DRIVE A2-10

2n2

3804

1u 15K

7150-D TDA8844 PH1LF

2V9 42 37

7V8

2n2

PH2LF

V_P2

43

4n7

A5-59 C14

BUFFER 3V9 +8V 8V3 7800 BC847B

HOUT

40

0V4

3814

2812

2817

39 220n SYNC PROCESSING SECTION DECDIG 4V9 2814 FBISO EWD VDRA 46 1V2 GND2 VDRB EHTO 47 50 1V3 2V2 45 44

1n

100R

A7-64 SANDCASTLE 0V6

41 0V8

L8 3V2 3802 1K

3812

4K7

3V8 51 VSC 3V8 I_REF 52 39K

2811

3801

22n

E_W_DRIVE

4K7
FOR E/W SET

2820

2821

1n

100n 2822

1n

3809

+8VB

3811

27K

C12 SOURCE A2-20 PROT_IBEAM_EHT_INFO

3800

33K

15p

L5

2813

RES 3813

A2-21 HFB

2818 100p

3806

4M7

3810

2810

100n

10K

+8VB 3808 1K 3807 1K F1

F2 SOURCE A3-24 VDRIVE_NEG A3-25 VDRIVE_POS

CL 86532033_029.AI 160698

SOURCE

Horizontal synchronization
Start up
Before the Video processor IC7150 can generate horizontal drive pulses the supply voltages on both pin 12 and 37 must be present. Pin 12 supplies the IC circuits and pin 37 supplies the horizontal drive circuits in the IC. After the start up command of the uP via the IIC the BIMOS starts giving horizontal pulses. First with a double line-frequency in order to obtain a smooth switching-on behavior of the horizontal output stage.

Sand-castle output (pin 41)

On pin 41 the sand-castle (SAND) is present. The burst-key and vertical blanking pulse are always available (made by IC7150-D). Pin 41 also act as input pin for the horizontal flyback pulse (HFB). This pulse is used for the horizontal phase correction. The sand-castle pulse is a 2 state pulse with the following values: 5V3 level for the burst-key timing ; 2V for line and frame blanking timing

Horizontal sync. Separator

The horizontal sync. Separator separates horizontal pulses out of the CVBS signal and so synchronizes the free-running horizontal sawtooth generator. Both the horizontal and vertical oscillator frequencies are internally locked to the 4.43 / 3.58 MHz chrominance oscillator on pin 34 / 35 IC7150-B and so "knows" whether the frame frequency is 50 or 60 Hz and the line frequency is 15625 or15750 Hz (also for black and white pictures this 4.43 / 3.58 MHz oscillator can be used for locking of the horizontal and vertical oscillator).

Horizontal Phase correction (pin 42)

The phase-correction signal at pin 42 give horizontal shift correction during beam currents changes. If the beam current increases (more white), the EHT voltage decreases so the picture will become off centre. The Phase correction signal takes care that the picture remains in the middle of the screen by adapting the timing of the horizontal drive pulse (H_DRIVE).

Vertical synchronization
Vertical sync. Separator
The vertical sync. separator separates frame sync. pulses from the CVBS signal and synchronizes the frame oscillator.

Horizontal sawtooth oscillator

The horizontal sawtooth oscillator signal is converted into a square wave voltage. This square wave HDRIVE signal at pin 40 is fed to the line output stage. The time constant of the sync. circuit (different for VCR and weak terrestrial signals) is automatically internally determined by IC7150-B.

VDRIVE_POS (pin 46) and VDRIVE_NEG (pin 47)

The VDRIVE_POS and VDRIVE_NEG signals are the balanced output currents (sawtooth shaped) of the frame oscillator

A8.0A

Synchronization Horizontal and Vertical Synchronization

53

(pin 46-47 of IC7150-D). The output signals are balanced, so they are less sensitive for disturbances and are applied to the horizontal deflection stage.

Personal notes
Vertical Ramp generator (pin 51)
At pin 51 an inside current source is present. This current source pumps energy in the capacitor 2822, connected on that pin, resulting in a sawtooth voltage across this capacitor. From this signal the vertical drive signals and the E/W correction signal are derived. The external resistor 3806 connected to the 8V is added to improve the linearity.

EW-Compensation (pin 45)

The E_W_Drive signal at pin 45 takes care for the correct pincushion correction for 110 tubes. It also corrects breathing of the picture due too beam-current variations. This correction is derived from the signal on pin 50 (PROT_IBEAM_EHT_INFO) which "measures" the beam-current. When no E/W signal is needed, pin 45 is connected to the 8V with a resistor of 4K7.

PROT_IBEAM_EHT_INFO (pin 50)

Above mentioned signal has two functions: To correct the pincushion due to beam current variations. As protection signal. As the beam current is to high (voltage on pin 50 >3,5V) the set is going in protection mode (error code 2).

54

AUDIO PROCESSING QSS sound demodulator

A8.0A

AUDIO PROCESSING QSS sound demodulator

3401

2K2

TO SAW FILTER 7405 BC847B

TO SAW FILTER

3402

3403

10K

2K2

FROM PIN 10 OF TDA9810 TO PIN 22 OF TDA9810

TO PIN 7 OF TDA9810

IF 3419 2K2 7407 BC847B

100R
TO PIN 8 OF TDA9810

3421

220p

3412 2412

10K

3407 2K2

BC857B 7408 3413 2K2

7410 BC847B

SOUND_IF OUT

CL 86532033_002.AI 160698

Two QSS panels are used in A8: 1. QSS-DK panel which is built around TDA3845 is used for China and Eastern Europe; it is a quasi split-sound circuit and AM demodulator. 2. QSS (NICAM L) panel which is built around TDA9810 and this is used for the multi France region. This IC is a multistandard Video Intermediate Frequency amplifier PLL (VIF -PLL) with quasi split sound (QSS) and AM demodulator circuitry. The main function of the QSS demodulator is to extract the sound carriers from the video IF which is supplied by the tuner part. The output of the IF sound is the sound that is modulated on the different sound carriers.

pin 1 via C2405 and leaves at the symmetrical output (pin 4 and 5), from where it enters the TDA3845 at pin 1 and at pin 16. Capacitor 2406 at pin 3 is the AGC control capacitor and capacitor 2407 peak/mean detector capacitor. Coil 5402 is used for demodulation and is adjusted to 38.9 MHz. The signal posneg_qss coming from the tuner part A4 will switch between AM and FM. Pin 6 (baseband_audio) is the AM output for AM. IC7401 converts the incoming signal between pint 1 and 16 from the IF-carrier at 38.9 MHz to a baseband audio signal. So, by now the sound carriers are put at the default position (so e.g. 6.5/5.85 MHz for China-DK). This IF sound signal is available at output pin 12 (sound_if).

1) QSS-DK; see circuit diagram J.

This circuitry is built around IC7401 (=TDA3845) and it is used for DK stereo sets with the ITT audio decoding IC MSP3400 or 3410. The signal from the tuner (IF-carrier at 38.9 MHz ) is filtered by a double bandpass SAW filter 1402 which only bypasses the sound and video IF carriers. The IF1 signal enters this filter at

3414

5K6

A8.0A

AUDIO PROCESSING QSS sound demodulator

55

QSS sound demodulator

5402 6

TYPE 3 2

220n

2406

4
s1

1 7 8

100n

2407

470R

2408

2u2

2405 4n7 15 3 16

7401 TDA9810

14

21

3415
18

19

17
AFC DETECTOR

TUNER AND VIF-AGC

VCO TWD

9 IF.INPUT 2 1 23 24
INTERNAL VOLTAGE STABILIZER SIF AMPLIFIER
SINGLE REFERENCE

VIF AMPLIFIER

FPLL

VIDEO DEMODULATOR AND AMPLIFIER VIDEO BUFFER AF AMPLIFIER SWITCH

12 13 6 120R 3404 BASEBAND_AUDIO 3 OUT

MIXER AND AM DEMODULATOR SIF-AGC

22

20 8

10

11

3405

RES 470n

2403

100n

2402

2410

100R

220p

3412

2412

SWITCH POS NEG.QSS

SOUND_IF OUT

SWITCH SEL.IF TRAP

3414

5K6

2411
CL 86532033_001.AI 160698

2u2

2) QSS (NICAM L/L'); see circuit diagram I.

This circuitry is built around IC7401 (=TDA9810) and this is used for NICAML/L' stereo sets with IC MSP3400 or 3410 of ITT. The signal coming from the tuner (IF-carrier at 38.9 MHz or 33.9MHz ) is filtered by a multi-system TV IF SAW filter 1402. The selection of which system filter is selected will be determined by the SEL_IF_TRAP_MAIN signal which switches the transistors 7407 and 7410. If SEL_IF_TRAP_MAIN is low, the filter with passband for sound carriers between 32.35Mhz and 33.4MHz is selected for NICAM L,I,BG,DK system. If SEL_IF_TRAP_MAIN is high the bandpass for the sound carrier at 40.4MHz and 39.75MH (L'NICAM) is selected. To get a positive modulated video signal pin 8 of TDA9810 is pulled low and to get a negative modulated video signal pin 8 is pulled high by the signal posneg_qss coming from the tuner part A4. Because the SECAML system is a positive video modulation system the posneg_qss signal is low and pin 8 of TDA9810 will be high.

22n

IC7401(=TDA9810) converts the incoming signal between point 23 and 24 from the IF-carrier at 38.9 MHz to a baseband audio signal. So the sound carriers are put at the default position ( e.g. 6.5/5.85 MHz for NICAML). This IF sound signal (=sound_if) is available at output pin 10 of the IC and also AM baseband sound is available at pin6. Coil 5402 is used for demodulation and is adjusted to 38.9 MHz.

56

AUDIO PROCESSING Global Audio

A8.0A

Global Audio

The function of the IC7430 (MSP3410D or MSP3400C) is to demodulate various combinations of the 4.5,5.5,6.0,6.5 MHz mono sound systems, the German (5.5/5.74 MHz) and Korean (4.5/4.72MHz) two carrier stereo and the 5.5/5.85, 6.0/6.552 and the 6.5/5.85 MHz NICAM stereo systems (NICAM only in MSP3410D). The mono input is used for the analog AM signal available from IC7401 (TDA9810). The analog input and output sections of MSP3410D/MSP3400C offer a wide range of switching facilities so that it is possible to distribute all possible source signals (internal and external) to the desired output channels (main, headphone or SCART outputs). The MSP3410D/MSP3400C has digital audio processing for volume, balance, bass, treble, pseudo stereo, etc. Features such as AVL and incredible sound will also be incorporated. Based on this the signal flow diagram is drawn. For the MONO only set, the audio output of the TDA8844 along with the stereo AV input is switched by HEF4052. The sound processing will be done on a separate module with NEC1853 and Incredible sound circuit.

Personal notes

A8.0A

AUDIO PROCESSING BTSC Audio

57

BTSC Audio

For BTSC sets, IC7437 (TDA9855 BTSC decoder) will be used. Since TDA9855 does not include source switching and incredible sound, an external switch HEF4052 is used on the main board for the AV source selection and an incredible sound panel is included to provide the widening effect of the stereo sound. Now the TDA8844 supplies the IF-audio signal to IC7437 (TDA9855 BTSC decoder). The monitor output there is the audio signal present of the displayed picture. This is available at pins 14/39. Other outputs are L/R (pin 6/47) fed to the amplifiers and from pin 4 the audiosignal for the subwoofer is available and needs only amplification.

Personal notes

58

AUDIO PROCESSING Audio source selection

A8.0A

Audio source selection

ANTI PLOP CIRCUIT

+15V

2567

100n

3559

3551
SOUND MUTE

10K

BAS216

16V2 BC857B 7552

15V6 3552 AMP_MUTE1 10K INVERTER

3560

2553

0V

18K

3570

2552

A4a

2565 22n 2550 100n 2V1 1

16V2 7550 TDA 8563Q 11

10

100n

6K8

7551 BC847B

100R

6550

3550

12K

17V8 +15V

S_GND A5a 4 8V9

L_AUDIO_IN VO 0

*3563
3564 8K2

60K

2555

1n

A5b 6 V12 2-CHAN AF AMP t A4b Distortion detector waveform R_AUDIO_IN 2566 22n 2551 100n 2V1 13 9 8V9 2
REF. VOLT.

8V9 +15V M56

1 2 3

17V7 3569 12 10K

A6a

*3565
3566 8K2

2556

current in output stage

1n

A6b
60K

8V9

Short-circuit over the load V12 VP

t 5 8

20ms

S_GND t Short-circuit waveform

CL 86532063_001.eps 030898

The table below shows the switching for AV stereo / BTSC using IC HEF4052:

MSP3410 source switching is done through the IC internal SCART switches. The IF-sound signal is fed-in on pin 58 of IC7430 (diagram A11) LF-AM sound is fed to pin 55 for NICAM L. In the circuit diagram can be seen that all external audiosignals are fed to the MSP3410.

SEL_MAIN_F RNT_RR

SEL_MAIN_R 1R2

I/0 CINCH

IN CINCH 0 0 1 0 1 0 REAR1 REAR2 FRONT

OUT CINCH

There are also four outputs:

MON MON MON

pins 25/26 for headphone pins 28/29 for the amplifier (IC7550) of main sound pin 31 for subwoofer pins 36/37 for EXT1 pins 33/34 for monitor output is fed to CINCH-outputs and also to EXT2

For the Europe set the MSP3410D is used. No external switching is required. The following table shows the external source connection for a SCART2 Europe set:

SELECTED SOURCE MAIN REAR (EXT 1) REAR (EXT 2) FRONT (EXT3) TUNER

SCART2 OUT REAR1 TUNER FRONT TUNER

A8.0A

AUDIO PROCESSING Audio source selection

59

ANTI PLOP CIRCUIT

+15V

2567

100n

3559

3551
SOUND MUTE

10K

BAS216

16V2 BC857B 7552

15V6 3552 AMP_MUTE1 10K INVERTER

3560

2553

0V

18K

3570

2552

A4a

2565 22n 2550 100n 2V1 1

16V2 7550 TDA 8563Q 11

10

100n

6K8

7551 BC847B

100R

6550

3550

12K

17V8 +15V

S_GND A5a 4 8V9

L_AUDIO_IN VO 0

*3563
3564 8K2

60K

2555

1n

A5b 6 V12 2-CHAN AF AMP t A4b Distortion detector waveform R_AUDIO_IN 2566 22n 2551 100n 2V1 13 9 8V9 2
REF. VOLT.

8V9 +15V M56

1 2 3

17V7 3569 12 10K

A6a

*3565
3566 8K2

2556

current in output stage

1n

A6b
60K

8V9

Short-circuit over the load V12 VP

t 5 8

20ms

S_GND t Short-circuit waveform

CL 86532063_001.eps 030898

Output Stage
The audio output stage is built around IC7550 which is a balanced amplifier. The gain of the amplifier is constant. This means that volume control with the IC is not possible. Pin 11 of IC7550 has three functions: Stand-by Mute: Input signal suppressed Normal operation

In case one of the protections is active, Pin12 becomes low as a result. Every 20mS IC7550 tries to start-up again for 50(S (as a result pin12 becomes every 20mS high for 50 (S). If the amplifier is clipping (to high output level) pin12 of IC7550 becomes also low. In this way diagnostics can be done by measuring this pin. The mute signal is also routed to the subwoofer panel. The subwoofer contains an active amplifier which has to be muted when the normal sound is muted. Subwoofer and subwoofer amplifier are always replaced together and thus treated as a single spare part. The headphone amplifiers are single transistor amplifiers separately for left and right.

The audio output stage is built around IC7550 which is a balanced amplifier. The gain of the amplifier is constant. This means that volume control with the IC is not possible. Pin 11 of IC7550 has three functions: During start-up pin11 of IC7550 is kept low till the capacitors at pin1 and pin13 are charged. In this way it is prevented that during switch-on a plop occurs. This is controlled by the circuit around transistors TS7551 and TS7552. When the signal AMP_MUTE1 becomes high, pin11 of IC7550 becomes low and the amplifier is muted. Two protections are present in IC7550: Thermal protection Short circuit protection

60

HORIZONTAL DEFLECTION Line output stage

A8.0A

HORIZONTAL DEFLECTION Line output stage

+VB

LPRIM

LOT

C1

D1

LDEFL C4 C3

IDEFL

C2

D2

IDEFL T1 T2

CL 86532033_019.AI 030898

A8.0A

HORIZONTAL DEFLECTION Line output stage

61

The principle of the horizontal deflection is based on a fly-back circuit and East/West correction (amplitude modulation) is based on a diode-modulator circuit.

Personal notes
Basically horizontal deflection is done by applying a constant voltage (during the scan) over the deflection coil, which creates a saw tooth current through the deflection coil. East/West correction is done by modulating the voltage over the deflection coil by means of a correcting current, resulting in a corrected line deflection current.

Principle of operation
In series with the line deflection circuitry - line deflection coil (LDEFL), S-correction capacitor (C4) and fly-back capacitor (C1) - an additional resonance circuit - bridge coil (L), bridge capacitor (C3) and fly-back capacitor (C2) - is placed. Modulator diodes (D1 and D2) and line output transistor (T) are the switches in this circuit. The primary winding of the LOT (LPRIM), is used to supply the circuit. Averaged in time there is no voltage across coils. Modulating the voltage over bridge capacitor (C3) modulates the total voltage across the line deflection coil (LDEFL) and consequently the horizontal deflection current (IDEFL) modulated (see East/West modulation). The resonance frequency of line deflection coil and fly-back capacitor (C1) - the influence S-correction capacitor (C4) is negligible - and the resonance frequency of bridge coil and its flyback capacitor C2 should be equal to prevent distortions.

Initial state
During the start-up all the voltage and magnetic fields in the coils has to be charged. For this analysis start-up behavior is neglected and voltages and fields are assumed to be in steady state. East/West modulation is dealt separately and omitted in this part of the description. The analysis starts at the end of the fly-back (= start of horizontal scan). At this moment the following situation exists: Diodes (D1 and D2) conduct. The voltage across the S-correction capacitor (C4) equals the supply voltage (VB). The voltage across the bridge capacitor (C3) equals a designed fraction (ranging from 15% to 25%) of the supply voltage (VB). At the end of the fly-back, the maximum negative current flows in all coils (LDEFL, LPRIM and L). At this very moment the spot is in the leftmost position on the screen.

The line output stage is analysed in four different time steps and at the end of the analysis these initial conditions are verified.

62

HORIZONTAL DEFLECTION Line output stage

A8.0A

+VB

LPRIM

LOT

C1

D1

LDEFL C4 C3

IDEFL

C2

D2

IDEFL T1 T2

CL 86532033_019.AI 030898

A8.0A

HORIZONTAL DEFLECTION Line output stage

63

t1-t2
During the first part of the scan diodes (D1 and D2) conducts and voltage across the line deflection coil (LDEFL) and the bridge coil L cause a linear current (IDEFL and IBRIDGE). The line deflection current (IDEFL) is caused by the resulting voltage across the S-correction capacitor (C4) and the bridge capacitor (C3), in total, VC4-VC3, approx. 75%-85% of the supply voltage (VB). The bridge current (IBRIDGE) is caused by the voltage across bridge capacitor (C3). These positive voltages reduce the negative currents in the coils (LDEFL and LBRIDGE). The S-correction capacitor (C4) is chosen such that during this time a low frequent resonance with line deflection coil (LDEFL) results. This causes a small distortion on the line deflection current (IDEFL), finally resulting in a more steep current towards t2 and a slight increase of the voltage across the S-correction capacitor (C3). The spot moves from the left to the middle, with a continuous increasing speed (S-correction). The current through the primary winding of the LOT (LPRIM) flows through the same diodes (D1 and D2). The voltage across this primary winding equals the supply voltage (VB), resulting in a linear current. At a certain moment between t1 and t2, the line output transistor (T) is switched on in order to take over the function of the diodes (D1 and D2). The combination of the diodes and line output transistor functions as a bi-directional switch.

Personal notes

As a total result, at moment t2, the voltage across S-correction capacitor (C4) is slightly increased. The voltage across the bridge capacitor (C3) equals the value at moment t1 and the current in the line deflection coil (LDEFL) and the bridge coil are zero. The spot is in the middle of the screen.

64

HORIZONTAL DEFLECTION Line output stage

A8.0A

Line output stage

+VB

LPRIM

LOT

C1

D1

LDEFL C4 C3

IDEFL

C2

D2

T2

T3

CL 86532033_020.AI 030898

A8.0A

HORIZONTAL DEFLECTION Line output stage

65

t2-t3
At moment t2, the current through the line deflection (LDEFL) and bridge coil (L) reverses, however the slope of these currents are continuous. So from t2 onwards there flows a positive current through both line deflection coil (LDEFL) and bridge coil (L). Basically the situation equals the description for t1-t2, except for: the line output transistor (T) conducts in stead of the diodes (D1 and D2) the low frequent resonance of the S-correction capacitor (C4) and the line deflection coil (LDEFL) causes reduction of the slope of the line deflection current (IDEFL) The spot moves from the middle of the screen to the right. The speed of the spot reduces as moving to the right (S-correction). The current of primary winding of the LOT (LPRIM) is conducted by the line output transistor. At a certain moment between t2 and t3 the line output transistor is switched off, initiating the fly-back (see next section). Measures are taken to synchronize the start of the flyback and the rightmost position on the screen (see line driver section).

Personal notes

66

HORIZONTAL DEFLECTION Line output stage

A8.0A

Line output stage

+VB

LPRIM

LOT

C1

D1

LDEFL C4 C3

IDEFL

C2

D2

T3 T4

CL 86532033_021.AI 030898

A8.0A

HORIZONTAL DEFLECTION Line output stage

67

t3-t4
The fly-back starts at the moment the line output transistor (T) opens. The line deflection current (IDEFL) continues to flow through the fly-back capacitor C1. A parallel resonance between the fly-back capacitor (C1) and line-deflection coil (LDEFL) initiates from moment t3 onwards. Between t3 and t4 all energy stored in the line deflection coil (LDEFL) is moved to fly-back capacitor (C1). Exactly the same is valid for the bridge coil (L) and its fly-back capacitor (C2). Similarly the energy of the LOT (LPRIM) is transferred to the fly-back capacitors (C1 and C2). During the fly-back phase the influence of the S-correction capacitor (C4) and bridge capacitor (C3) is negligible. The spot moves from the rightmost position back to the middle of the screen, at a speed of approx. 5 times the scan speed (t1-t3). To prevent visibility of this fly-back, video processing blanks the video signals during fly-back.

Personal notes

At the moment t4 all energy is stored in the respective capacitors. Consequently currents through coils are zero and voltage across capacitors reached the maximum value.

68

HORIZONTAL DEFLECTION Line output stage

A8.0A

Line output stage

+VB

LPRIM

LOT

C1

D1

LDEFL C4 C3

IDEFL

C2

D2

T4

T5

CL 86532033_022.AI 030898

A8.0A

HORIZONTAL DEFLECTION Line output stage

69

t4-t5
All switches remain opened. During this second phase of the fly-back, all energy in the capacitors is transferred back to the coils, however the current is reversed compared to first part of fly-back period (t3t4). This process continues until the voltage across the diodes is below zero level. At that very moment the diodes (D1 and D2) open and the fly-back is finished. A new scan start. The spot moves (blanked by video processing) from the middle to the leftmost position (see t3-t4).

Personal notes

At the end of the fly-back period (moment t5), the voltage across the S-correction capacitor (C4) equals the supply voltage (VB) and the voltage across the bridge capacitor (C3) equals the dimensioned portion of the supply voltage (VB). All coils conduct the maximal negative current. This condition equals the assumed initial state at the beginning of the analysis. The above analysis assumes that the total operation has no losses. In practice losses occur. These losses are compensated by supply of energy from the supply voltage generator (VB). The basic principle is as follows: During fly back the energy is transferred from the primary winding of the LOT (LPRIM) to the resonance circuits (C1, C2, C3, C4, LDEFL, LBRIDGE). During the scan the energy in the primary winding of the LOT (LPRIM) is restored from the supply voltage generator (VB).

70

HORIZONTAL DEFLECTION Line output stage

A8.0A

Line output stage

5630 3

L4

3630

2621

L7 2624

2615//18//19//25

2697

LDEFL

5621 PANA

2633//34

L6

2622//23

7620

2630//34

6622//23

5624//25

L4

L6

L7

CL 86532033_015.AI 180698

Complete line deflection

The complete line deflection circuitry is more complex compared to the previous described circuitry. Below an overview of all elements is given: Line output transistor (T): item number 7620 Modulator diode D1: item number 6621 Modulator diode D2: item number 6622//6623 (East/West panel) Fly-back capacitor C1: item numbers 2615//2618//2619// 2625 Fly-back capacitor C2: item numbers 2630//2634 (East/ West panel) Bridge capacitor C3: item numbers 2622//2623 (East/West panel) S-correction capacitor C4: item numbers 2629//2630 Bridge coil (L): item numbers 5624//5625 (East/West panel) LOT: item number 5630

Additional components in this circuitry: Additional fly-back capacitors: item numbers 2633//2634, mounted close to line output transistor to prevent high frequent radiation during switching. These capacitors do not influence the operating principle, the value can be transformed in the fly-back capacitors C1 and C2 of the principle operating diagram.

Panorama switching S-correction: item numbers 2697 and 7694 (East/West panel, 16:9 sets only). In 16:9 sets, a panorama mode is available. In this mode the symmetrical nonlinearity is not completely corrected by the S-correction function. To realize this reduced S-correction requirement, an additional S-correction capacitor (2697) is switched (transistor 7694) in parallel to the default S-correction capacitors (2629//2630). This results in an increased capacitance, a lower resonance frequency of the line deflection coil (LDEFL) and S-correction capacitors (2629//2630// 2697) and therefor a less steep S-corrected line deflection current (IDEFL). The panorama mode switching is controlled by the PANORAMA signal. Linearity correction: item numbers 2621, 3620 and 5621. Due to internal impedance of all components, losses in the line deflection stage occur, resulting in asymmetrical behavior of the line deflection current, and consequently, of the position on screen (left versus right hand side of the screen). To compensate for this asymmetrical behavior, a pre-magnetised linearity coil (5621) is added in series of the line deflection coil (LDEFL). The linearity coil (5621) will satirise as function of the deflection current (during interval t2t3) and as a result, scan from left to right, the available voltage across the line deflection coil (LDEFL). To prevent parasitic resonance in the linearity coil (5621), a damping resistor (3630) is added. An additional capacitor (2621) is added to prevent unnecessary dissipation in this resistor. Mannheim suppression: item numbers 2624, 3635//3636// 3637//3639 and 6625+6626. During step wise high load of

3635//36//37//39

2929//30

6625//26

6621

7694

A8.0A

HORIZONTAL DEFLECTION Line output stage

71

the line output stage (high beam current, e.g. horizontal white line), the line deflection energy balance is distorted. In fact, during fly-back, part of the energy stored in the S-correction capacitor (2629//2630//2697) is used to restore the energy of the picture tube (EHT), which might take several horizontal lines. This results an increased fly-back pulse width. There for the position of the horizontal deflection is shifted, resulting in a display offset to the left. This shift is detected by the horizontal phase locked loop, resulting in adjustment of the horizontal drive and consequently the screen shows a ringing behavior of vertical lines (Mannheim effect). To prevent this Mannheim effect, suppression circuitry is added. During the second half of the fly-back period and first half of the scan (t4-t5 and t1-t2) capacitor 2624 is charged via the series resistor (3635//3636//3637//3639). The stored, additional, energy in capacitor (2624) is available during fly-back, where the additional diodes (6625+6626) conduct. This additional energy limits distortion of the energy balance and consequently the visible ringing of vertical lines on the screen. Remarks: The bridge coil (5624//5625) is executed as a transformer. This enables more effective East/West modulation (see next paragraph).

Personal notes

72

HORIZONTAL DEFLECTION Line output stage

A8.0A

Line output stage

5630 VB 3

1 3630 2621

L4

L7
2624 LDEFL 6621 5621 2629//2630 6625//6626 3635//3636// 3637//3639

7620 2633//2634

2615//2618// 2619//2625

2635

6635

L4

L7

CL 86532033_048.AI 160698

For 21" EUR and 27V USA execution, no East/West modulation is required, so the diode modulator is omitted. Both diagrams are given, but not described in detail. 21" EUR (East/West panel not present), changes with respect to the complete circuitry: Modulator diode D2: item number 6635 Fly-back capacitor C2: item numbers 2635 Bridge capacitor C3: not present (short circuit) Bridge coil (L): not present (open)

Personal notes

Additional components in this circuitry: Panorama switching S-correction: not present

A8.0A

HORIZONTAL DEFLECTION Line output stage

73

Line output stage

5630 VB 3

2 3630 2621

2624 LDEFL 7620 2633//2634// 2615//2618// 2619//2625 5621

6621

2629//2630

6625//6626

3635//3636// 3637//3639

CL 86532033_047.AI 160698

27V USA (East/West panel not present), changes with respect to the complete circuitry: Modulator diode D2: not present (short circuit) Fly-back capacitor C2: not present (open) Bridge capacitor C3: not present (short circuit) Bridge coil (L): not present (open)

Personal notes

Additional components in this circuitry: Panorama switching S-correction: not present

74

HORIZONTAL DEFLECTION East/West modulation

A8.0A

East/West modulation

5630 141V

7620 2615//2618// 2619//2625 3679 5680//5682// 5684

LDEFL.

6621

2629//2630

L8
3681 7680

5681 2680//2682 2683//2689 2630//2639 6622//2623

4 1 5624//2625 2

3683//3689

CL 86532063_003.eps 040898

As function of the vertical position, the required line deflection current to scan from leftmost to rightmost position might vary. This is caused by the fact that deflection point, from which the beam is deflected, does not match the middle point of the screen shape (segment of a sphere). In the 21" EUR and 27V USA picture tubes this mismatch is compensated in the line deflection coil design. So, no additional correction circuitry is required. For all other tubes the line deflection coil design does not compensate for the described mismatch, and therefor vertical dependent amplitude modulation of the line deflection current is required. This amplitude modulation is known as East/ West modulation. The basic principle is rather simple. Current is surged from the line deflection circuitry. This results in a reduced voltage across the bridge capacitor (C2), and consequently more voltage across the line deflection coil (LDEFL), resulting in an increased amplitude of the line deflection current (IDEFL). The applied principle is based on the fact that the amplitude of the line deflection current (IDEFL) can be increased, so the line deflection circuitry has to be designed for the minimum amplitude (middle of the screen, minimal picture width - in case 16:9 picture tubes: 4:3 display - and worst case tolerances) and sufficient available voltage across the bridge capacitor (C2) to allow all alignments and picture width setting. In such a design the East/West modulator adjusts the amplitude as function of: Picture width alignment

Vertical position Wide screen switching (e.g. panorama, 14:9 and 4:3 display)

The following components are added to the line deflection circuitry in order to enable East/West modulation: item numbers 2680//2682//2683//2684, 3679, 3681, 3683// 3684, 5680//5682//5684 and 7680. This circuitry converts the East/West drive voltage - E_W_DRIVE -, containing all information on picture width alignment, vertical position dependent amplitude and wide screen modes, into a current surged from the line deflection circuitry. The east/west output transistor 7680 modulates the voltage across buffer capacitor 2680//2682//2683//2684. This buffered voltage determines the surged current. The series resistor 3679 limits the peak drain current of transistor 7680.

The surged current causes a reduction of voltage across 2622/ 2623 and consequently an increased voltage across the line deflection coil (LDEFL), resulting in an increased line deflection current (IDEFL) and an increased amplitude of the horizontal scan. By applying the bridge transformer 5624//5625 in stead of a bridge coil (L), the effect of amplitude modulation is boosted. More modulation current in winding 3-4 of 5624//5625 results in less current in winding 1-2 of the same coils and consequently more voltage across the line deflection coil (LDEFL) and con-

A8.0A

HORIZONTAL DEFLECTION East/West modulation

75

sequently additional increase of line deflection current (IDEFL) and boosted horizontal scan amplitude.

Personal notes
In case of failure in the East/West modulator two situations can be easily distinguished (disconnect East/West protection pin 13, connector M61): Minimal amplitude, not corrected (so wide scan on top and bottom edge of the screen, reduced scan in the middle). In this case most probably the East/West drive is missing (short circuited). Full picture scan. Short-circuit in the East/West modulator (e.g. filter capacitor 2680//2682//2683//2684, East/West output transistor 7680 or bridge coil 5624//5625).

In some occasions only part of the screen is modulated correctly, e.g. 75% of the picture has straight lines, top and bottom or distorted. In the case the available is insufficient. One of the components in the diode modulator or East/West modulator might be deteriorated.

76

HORIZONTAL DEFLECTION Secondary side LOT

A8.0A

Secondary side LOT

2631 +13V

+VB

3628

6629

6630

7629 3616
PROT_IBEAM_EHT_INFO

+VB

3609

3629
12V

EHT

EHT_INFO

3610

2650
*

VG2

10 5 1 6 7620 8 2665 7 5662 3663//3664 -13V 6663//6664 9 11 12 5630 5643 3643 2664 +200V 2656 FF GND_LOT
CL 86532033_043.AI 160698

220n

FOCUS

3645

6627 +30V 2627

5660

3660//3661 6660

3650

+13V 2661//2663

The LOT is used as supply coil to the line deflection circuitry. By using the magnetization energy of this LOT, secondary supply voltage can be derived. Basically two types output voltage can be distinguished: Scan rectified voltages The energy is transferred during the scan period of line deflection. At that moment there hardly any coupling between the line deflection current (IDEFL) and the primary LOT current. Furthermore the scan time is rather long compared to the fly-back time, resulting in rather low internal resistance of the supply voltage. A limitation is the fact that the generated voltage are limited to range from 3 to 30V. Commonly used supply voltages of this type: Frame deflection supply, SCAVEM supply. Fly-back rectified voltages The energy is transferred during the fly-back period of the line deflection. During this period the current of the primary winding of the LOT is coupled with the line deflection current (IDEFL), as a consequences, load fluctuation of these voltage might impact the line deflection current (IDEFL) and cause visible distortion. Due to the small conducting time of the rectifier diode, a high internal impedance results for this type of voltage generators. An advantage is that high voltages can be generated, using a limited number of turns. Common used supply voltages of this nature: EHT, RGB amplifier supply.

ply voltage is adjusted within small tolerance, this is the most efficient way to generated the heater voltage at the specified accuracy. In general all voltages related to screen functions are generated from the secondary side of the LOT. Main advantage: in case of line deflection failure, all screen functions stop automatically. All rectifier circuits consists out of a rectifier diode and ripple capacitor, often combined with a fuse-able resistor to prevent overload of the LOT, spook capacitor across the rectifier diode and series inductance to prevent EMC radiation. In this application the following voltages are supplied from the LOT: +200V supply for RGB amplifiers (pin 9-8): item numbers 2656, 3643, 5643 and 6641 +30V supply for East/West protection (pin 5-8): item numbers 2627, 3645, 3650 and 6627 +13V supply for vertical deflection, SCAVEM and RGB amplifiers (pin 6-8): item numbers 2661//2663, 3660//3661, 5662 and 2660//6660 -13V supply for vertical deflection (pin 7-8): item numbers 2664, 3663//3664, 5662 and 2665//6663//6664 heater / filament supply (pin 11-12)

The heater (filament) voltage is generated as well from the secondary side of the LOT. This voltage is not rectified. The right RMS level is adjusted using series inductance. As the line sup-

A8.0A

HORIZONTAL DEFLECTION Secondary side LOT

77

EHT, Focus and Vg2 supply (pin 10 is bottom end of EHT winding) Focus and VG2 are generated from a tap of the EHT winding.

Personal notes
From the EHT winding, EHT and beam current information is derived. Basically the EHT information is measured on pin 10 (item numbers 2650//3610 and 3608+3609). The fluctuations of the EHT information are used to correct picture width and shift (phase), as these are impacted by EHT fluctuations (lower EHT results in increased picture height and width) and EHT load fluctuation (see Mannheim suppression). The beam current information is derived from the EHT information by filtering (item number 2631, 3616, 3628, 3639, 6629+6630 and 7629) and used to detect overload of the EHT and to consequently activate protection. Remark: In practice there is overlap between EHT information and beam current information. It is hard to differentiate between the two. A mixture of the two is used to correct picture width and shift.

78

HORIZONTAL DEFLECTION Line drive

A8.0A

Line drive

HORIZONTAL DRIVE
+VB

3612// 3613

L4

5610//5611 7620

2611// 2612

3617

+8V

H_DRIVE

3638 7610

2601

HFB

6639

2605

3665 L5

3618

2602

L3

L4

3602

L5

3632

3631

L3

CL 86532033_042.AI 160698

The horizontal drive circuitry has to ensure, together with the horizontal phase lock loop, adequate drive of the line output transistor (7620): Switch off at the end of the scan Switch on during the scan, before the zero crossing of the line deflection current

have an effective discharge of the basis-collector junction during the switch off initiation an additional resistor (3617) is applied. In order to drive this transformer (5610//5611), line driver circuitry is added. Assume the line driver transistor (7610) conducting. In this situation a certain current flows through the primary side of the driver transformer (5610//5611). Switching off the line drive transistor (7610) results in an rapid cut-off of this current, resulting in steep voltage increase across the primary winding of the drive transformer (5610//5611). This peak results in a negative peak on the secondary side of the drive transformer (5610// 5611) and initiates the discharge and switching off process in the line output transistor (7620). To prevent damage of line driver transistor (7610) during this process, a snubber network (2601, 2605 and 3602) - to absorb part of the switching energy - is applied. As soon as the basis-collector junction of the line output transistor (7620) is discharged, the fly-back of the line deflection is initiated. Switching on the line driver transistor (7610), initiated current flow through the primary of the line driver transformer (5610// 5611). The required energy is surged from capacitors 2611// 2612, which are recharged via resistors 3612//3613. In steady state, the amount of energy stored in the driver transformer (5610//5611) during the "on" state of the line deflection transistor (7620) is discharged during the switching off process of the line deflection transistor (7620).

Transistors always have switch on and switch off delays. These delays are dependent on several parameters. In the line output stage these delays are significantly. The dominant delay is the switch off delay (3-5 ms). This delay is varying as function of the actual line deflection current, load conditions of the LOT, temperature, etc.. On the other hand, the start of the fly-back has to be locked to the end of video information. Therefor a phase locked loop is used to ensure a timely switch off command and a synchronised line deflection - video content relation. The switch on moment is less critical. The first half of the scan period is available to switch on the line output transistor, the timing is less critical. Using a 55% duty cycle (switched on time) of the drive signal safeguards timely switch on.

In order to have adequate drive conditions of the line output transistor, a drive transformer (5610//5611) is used. This drive transformer (5610//5611) can be seen as current source, which drives a positive current base current into the transistor during switch on and sinks base current during switch off. In order to

A8.0A

HORIZONTAL DEFLECTION Line drive

79

Finally, the line driver transistor is driven by the H_DRIVE signal (via 2602, 3618 and 3638) from the horizontal phase locked loop. The phase reference for this phase locked loop is derived from the CVBS signal and the horizontal deflection pulse - HFB - (3631, 3632, 3665 and 6639). This phase locked loop aligns the horizontal synchronisation contents of the CVBS signal to the horizontal deflection pulse.

Personal notes

80

Vertical Deflection

**
3731 2735 6700 2731 2732 6735 2U2 ----270K 100K

27V/32V

OTHERS

+13V_+20V

** 3731
+8V

BYD33D 10K 1u 3717 2u2 3732 2700 100n 2729 2735 100K 3729 10K 0V 1N4148 VERT DEFL 7716 BC847B PROTECTOR PROT_E_W_VERT 6739 A8-26

100u

100n 1N4148

100K

* *
+13V

0V6 BUFFER 13V7 6731 3718 0V 7715 BC547B 0V V 4K7 3715 10K 6719 -12V3 13V7 F5 3 FLYB VERTICAL OUTPUT F3 5733 90n 220n 6734 3735 BYD33D 220R M64
1 2

1N4148

A8-27

13V4 3716 10K 6 F6

F2 3709 1K 2709 470p 2705 220p 7 IN+

THERMAL PROTECTION POWER AMPLIFIER OUT 5

7700 TDA8172 2 VSUP

VSUPO FLYBACK GENERATOR

A6-24 0V3 2733

VDRIVE_NEG

1 IN0V9

BZX79-C5V6

3708

2K2

RES

0V9
GND -13V 4

Vertical Deflection

M69
1

2710

470p

3733 10K 2734 100u 3734 3736

-13V

2736

100n 2737

RES

3749 1R5

C-7748 3710 1K 2730 100n

100R

220R

TO VERT. DEFL. COIL

F1 3730 2K2 3R3 3R3 3737 3738 3739 2R2

F4

A6-25

VDRIVE_POS

CL 86532033_026.AI 160698

A8.0A

A8.0A

Vertical Deflection

81

The vertical output amplifier is build up around the deflection processor IC7700. Two types of deflection processors can be used, the TDA 8172 (used in 29" SF CRT) or the TDA 9302H (used in 34"flat SQ CRT). The IC is supplied by the +13V (pin 2) and the -13V (pin 4). The IC is current driven via two balanced sawtooth shaped signals, VDRIVE_NEG (pin 7) and VDRIVE_POS (pin 1). These drive signals are delivered by the sync part IC7150-D. A vertical deflection cycles can be divided in a scan and in a fly-back part.

Personal notes

Scan part
Via the output (pin 5) a differential sawtooth shaped current, superimposed on a common mode current is applied to the vertical deflection coil. The amplifier operates in the linear area due to a feedback loop via 3730.During the scan, the supply voltage of 26V (addition of +13V and -13V) is sufficient to reach the required deflection current.

Fly-back part
During the fly-back part a higher supply voltage as 26V is required. To reach this higher voltage a fly-back voltage generator is used. During the scan, pin 3 is at -13V and electrolytic capacitor 2731 is charged to 26V. When the fly-back has to start, the input current forces pin 5 to go positive. Due to the inductance of the vertical deflection coil , the current will not be able to follow this change of voltage immediately, the same is valid for the feedback voltage. The amplifier comes in open loop and the output will go to approximate 13V. Then the selfinductance voltage will force pin 5 to a voltage level above that of pin 2.This starts the fly-back generator which adds the voltage of capacitor 2731 to the +13V supply voltage. The amplifier is still in open loop, supplied by a voltage of 26V+13V=39V. By using a fly-back generator, the amplifier is only supplied with a high voltage when this is necessary. Thus, power dissipation is reduced considerably compared to an amplifier continuously supplied by 39V. As soon as the deflection current is in accordance with the input current again, the fly-back generator is switched off and the amplifier will be in its linear operating area again.

Vertical fly-back pulse (VFB)

During fly-back pin 3 is at 13V, during scan it is at -13V. Diode 6731 and TS7715 conduct and give a positive going pulse at the emitter of 7715. The VFB pulse is used as a vertical synchronization signal for teletext and OSD.

Vertical deflection protection (PROT_E_W_VERT)

The pulse on pin3 is also rectified by diode 6735. The rectified pulses charges capacitor 2729. If the voltage across 2729 decrease to a certain level , this means there is no correct vertical deflection, transistor 7716 is not conducting anymore and the PROT_E_W_VERT protection signal is changed from 0V in 8V. The set is switched now in protection mode (error code 1)

82

Vertical Deflection White spot suppression

INSTITUTIONAL USA ONLY
M67
1 2

A8.0A

White spot suppression

9738

VBAT

NON USA ONLY

6743 1N4148

2743
VERT/RGB SWITCHING A1-02 +14V 6742 1N4148 6741 12V5 12V8 BC557B 7743 0V 3744

BZX55-C3V3

RGB PULL-UP 0V

100u

12V8 7745 BC547B 3745

3741

3740

2742

100n

10K

10K

BZX79-C6V8 470n

1K

3748

6744

47K

0V7

A7-29 68R RGB_SW_OFF

VERT PULL DOWN 3747 0V 22K

2746 27K

3746

0V9 7748 BC547B

* ITEM NO
3737 3738 3739

29SF 2R7 2R7 2R2

27V 3R3 3R3 3R3

25/28 BLD 3R3 2R7 2R7

32V 3R3 4R7 2R2

35V 3R3 3R3 2R2

24 WIDE 4R7 4R7 3R3

28 WIDE 4R7 4R7 4R7

21 3R3 3R3 ---

CL 86532033_027.AI 160698

On diagram A3 also the so called white spot suppression circuit (7743,7745, 7748) is drawn. The white spot suppression takes care that after switching off, no white spot is visible on the CRT screen. After switching on the capacitor 2742 and 2743 are charged via the +14V via the diodes 6742 and 6743 respectively. Transistor 7743 is cut off and so the transistors 7745 and 7748. After switching off, the +14V will drop rather fast. However 2743 will keep his charge because diode 6743 will block. Transistor 7743 start conducting and so the transistors 7745 and 7748.

Function 7745
If 7745 start conducting, the emitter (RGB_SW_OFF) signal will get positive. This positive voltage is applied via the diodes 6300-6302 to the RGB output signals on diagram A7. This results in a negative pulse on the cathodes of the CRT. This means that the CRT is fully driven and therefore the load is maximum. This means that the energy of all relevant capacitors and coils in the supply part is discharged rapidly.

Function transistor 7748

When transistor 7748 is conducting the VDRIVE_POS signal on pin 1 of the vertical output IC is via resistor 3749 (100R) connected to mass. This means that the vertical deflection is only driven by the VDRIV_NEG signal . This means that the vertical deflection is changed so that the white spot is shifted outside the visible part of the CRT screen. Remark: If 7748 is defect (collector emitter is short circuit) than the vertical deflection stops working properly and the PROT_E_W_VERT control signal gets high and the set comes in the protection mode (error code 1).

A8.0A

TELETEXT + On-Screen Display Teletext function in control microprocessor

83

TELETEXT + On-Screen Display Teletext function in control microprocessor

25 BLK

26 IREF

23 CVBS

DATA SLICER

TELETEXT ACQUISITION

DISPLAY

32, 33, 34, 35 B, G, R, FB

PAGE RAM

OUT
ACQUISITION TIMING DISPLAY TIMING 37, VSYNC 36, HSYNC

I2C

CL 86532033_008.AI 160698

The A8 chassis is designed for several teletext versions: teletext and control functions combined in the control microprocessor separate teletext panel

Acquisition timing
The acquisition timing signals are derived from the CVBS signal.

Teletext acquisition
The teletext acquisition circuit selects the required teletext page from the offered data and stores the selected page in the page RAM.

In A8 sets for the AP region the teletext function is combined in the control microprocessor IC7000 - SAA5497 or SAA5499 Sets with this microprocessor have the capability of decoding and displaying both 525-line and 625-line World System Teletext. The SAA5497 offers 10 page Teletext.

Display
The capabilities of the display are based on level 1 teletext. The display consist of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the page memory. The display block supplies the RGB output signals

Block diagram
The teletext function can be divided into the function described below:

Display timing
The display timing arranges the timing of the RGB signal in order to ensure a stable teletext picture.

Data slicer
The data slicer extracts the digital teletext data from the incoming CVBS signal. This is performed by sampling the CVBS signal and processing the samples to extract the teletext data and clock.

84

TELETEXT + On-Screen Display Hardware interface

A8.0A

Hardware interface

+5VD

3079
+5VD 7000 MICRO PROCESSOR
VSYNC HSYNC FB R G B REFH P14 ALE|PROGN VPP|EAN PSENN

VERT. PULSE INVERTER 4V9 7075 F6 BC847B 3077 0V

37 4V9

10K

9082

36 3V8 35 0V 34 0V 33 0V 32 0V 31 5V 30 5V 29 0V2 3062 28 5V 10K 27 5V 3060 10K 4K7 3063 6073 BAS216 6072 BAS216 6071 BAS216 6070 BAS216 T1a T1b 2070 100n 220n

+5VD

2077

3076

10K

3V8 HOR. FLYBACK INVERTER 7070 BC847B F6 3075 HFB FROM HORIZONTAL OUTPUT

3074

+5V +5VD 7071 BC847B 7072 BC847B 3073 470R 3072 470R 3071 470R 3070 470R T1c 7073 BC847B

10K

0V2

2n7

10K

V FROM VERTICAL DEFLECTION

47K

9063 9064 9061

R_TXT_OSD G_TXT_OSD B_TXT_OSD FBL_TXT_OSD

4055 #

3068

220R 2062

220R 2061

220R 2060

220p 3067

100p 3066

100p 3065

9060

1K 2063

9.2

For the display timing the signals VSYNC and HSYNC are used. The VSYNC signal (pin 37 - IC7000) is derived via TS7075 from the V signal supplied by the vertical deflection circuitry. The VSYNC signal is a signal with active low sync pulses. The HSYNC signal (pin 36 - IC7000) is derived via TS7-70 from the HFB signal supplied by the horizontal output stage. The HSYNC signal is a signal with active low sync pulses. Via the pins 32, 33 and 34 of IC7000 the B, G, R colour signals are supplied respectively to the RGB switch. The output polarity of all four pins is active "High". Via the pin 35 of IC7000 and TS7071/7072/7073 FB (fast blanking) signal is supplied to the RGB switch. Via the fast blanking signal the R, G, B signals are inserted in the television picture.

Personal notes

100p
CL 86532033_018.AI 160698

A8.0A

TELETEXT + On-Screen Display Separate Teletext Panel

85

Separate Teletext Panel

PON VDS

RGBREF B

G R VDDA 38 DRAM REFRESH AND TIMING VDDD(T) 39 10 k 8 DRAM 9 to 12 VDDD(M) 44

COR

35 30 29 43 RESET POWER-ON RESET

31 32 33 34

DISPLAY

27 FRAME

res

24 TO 18 HAMMING DECODER

PACKET 26 PROCESSING ENGINE

MEMORY INTERFACE 52 20 16

SAA5263

48 17 47 18 46 19 45 1-8 51

E/W PDI SA DISLCBD FP DIS8/30 HSMODE DISDSR VSMODE PUINL V0-V7 ME8/30T SDA1 SCL1 SDA2 SCL2

PL

21

TELETEXT ACQUISITION AND DECODING

SYSTEM CONTROLLER

SERIAL-TOPARALLEL CONVERTER

VPS ACQUISITION AND DECODING

WSS ACQUISITION AND DECODING

I2C-BUS INTERFACE

15 14 50 49

25

BLACK

DATA SLICER AND CLOCK REGENERATOR

TELETEXT OR VPS CONTROL

36 INPUT CLAMP AND SYNC SEPARATOR DISPLAY CLOCK GENERATOR

HSYNC

37

VSYNC

26 Iref

ANALOGREFERENCE GENERATOR 22 13 28

ANALOGTO-DIGITAL CONVERTER 23 CVBS1 24 CVBS2

12 MHz CLOCK GENERATOR 42 XTALO 41 XTALI

40

OSCGND

MGL418

VSSA VSSD1 VSSD2

CL 86532033_037.AI 100698

9.3
CL 86532033_037.AI 160698

86

TELETEXT + On-Screen Display Separate Teletext Panel

The circuit description

A8.0A

In case a separate teletext panel is connected to the main board via connectors G05, G06, and G07 and M05, M06 and M07 in the TXT board and main board respectively. G05 is 5 pin for RGB and FB G06 is 6 pin for CVBS and Sync pulses G07 is 4 pin for I2C bus and +5V supply

The 1 Vp-p CVBS input is given at pin 23. Hsync and Vsync comes to pins 36 and 37 respectively and should be negative going. To reduce flickering the teletext display is de-interlaced. The reset pin is 43 and pulse should be active high which is controlled by main TV controller. The clock is derived from the 12 MHz crystal oscillator connected between the pins 41 and 42. The Data Slicer extracts the digital teletext data from the incoming analogue wave form. This is performed by sampling the CVBS wave form and processing the samples to extract the teletext data and clock. Pin 26 is the current reference input and for the correct operation R3025 is connected ground. Together with the blanking signal (pin 35) the RGB outputs (pins 31,32,33) are transmitted to the BIMOS IC IC7150. The diodes prevent 'blooming' of the text, as well as the level of the OSD being pulled down.

Functions TXT circuit

The TXT circuit mainly consists of: IC SAA5262 for TELEETXT Decoding used in NON-EPG sets IC SAA5263 for EPG (Electronic Programming Guide) decoding used for sets with EPG decoding feature

SAA5262 is a stand-alone device that contains application software to support Teletext, OSD, ACI and ATS functionality on an ETT1.10 device which provides 10 pages of Teletext memory. The main TV controller P83C770 will send and receive SAFARI (Stand-Alone Fastext and Remote Interface) commands and responses to and from the device via an I2C bus.

Personal notes

The TELETEXT component with OSD functionality, support Automatic fastext or TOP (table Of Pages) detection, Hit list Mode, List Mode, Subtitle Searching, port control etc. The TXT decoder has a memory of 10 pages. This decreases the waiting time for TXT pages. The content of the memory depends on the system. Several character sets with a geographical coverage are available. For ACI a number of background teletext pages are used to send installation - including System Type and Broadcast Frequency - for a number of broadcast channels, so that they can be installed automatically with limited viewer interaction. The ATS and EPG features are disabled while ACI is active. The ATS component is used to load, sort and fetch ATS tables during the installation phase. There is no display or viewer interaction associated with ATS. ACI and EPG is disabled while ATS is enabled. The EPG in A8 provides the TV viewer with information on the programs that are being broadcast today by the first 20 presets. Its functionality is based on the availability of broadcasters transmitting teletext pages with nexTView data. In regions where no nexTView but still Teletext is broadcast, the A8 EPG feature provides easy access to common teletext pages with program guide.

A8.0A

TELETEXT + On-Screen Display On-Screen Display

87

On-Screen Display

7101 PCA8515P 21 VDD 12 VSS 13 RESET_

FROM UC 7000 EXT/INT DATA SWITCHING BUFFER CHAR SIZE REGISTER/ CONTROL WRITE ADDRESS COUNTER ADDRESS BUFFER SELECTOR DISPLAY CHAR RAM DISPLAY ROM VERTICAL POSITION REGISTER/ COUNTER 5 CONTROL SIGNALS

CONTROL REGISTER P00 17 I/O PORT BUFFERS P01 19 P04|ACM 2

SLC

9 SCL|SCLK 8 SDA|SIN
I 2 C SLAVE RECEIVER OR HIGH-SPEED I/O BUFFER HORIZONTAL POSITION REGISTER/ COUNTER

SDA

14 E 15 HIO_|I2C

AVDD 24

5 C

PLL OSC

INSTRUCTION DECODER INTERNAL

AVSS 23

7 HSYNC 6 VSYNC
CSYNC SEPAR

SYNCHRONOUS

CIRCUIT

CRYSTAL OSCILLATOR

TESTING CIRCUITRY

DISPLAY CONTROL AND OUTPUT STAGE

ACM-VOB2

GVOW1

RVOW0

BVOW2

11

10

16 18 20 1

FBVOB

XTA2O

IVOW3

XTA1I

TST1

TST2

22

R G B FB TO RGB SWITCH 7275

9.4

CL 86532033_017.AI 160698

For sets with the microprocessor SAA5497 the On-Screen Display is generated by a separate panel (see diagram S in the service manual) For other sets the On-Screen Display is generated by the microprocessor IC7000. In the last situation the RGB/blanking signals for the On-Screen Display are fed to the RGB/blanking input of the Video Processing section of IC7150 via the same path as the teletext RGB/ blanking signals.

Vertical and horizontal synchronization signals are connected to pin 8 and 7 respectively. The character output signals RGB and the fast blanking signal are available on the pins 16, 18, 20 and 22 respectively. The four signals are fed to the RDB switch IC7275.

OSD panel
In the first situation the PCA8516 generates the on-screen characters. The on-screen character display generator in IC7101 is controlled by the microprocessor via the I2C bus. The selection for the control via the I2C bus is done by connecting pin 15 of IC7101 to +5V. The SDA data line is connected to pin 8 and the SCL clock line to pin 9. The system clock is determined by a crystal oscillator of 4 MHz.. The X-tal is connected between pins 10 and 11. The OSD oscillator is a PLL oscillator, the capacitor (C2102) for this oscillator is connector to pin 5.

88

TELETEXT + On-Screen Display On-Screen Display

+5V

A8.0A

5350

6u8

3353

3357

BCL IN

TO PIN 22 - IC7150 FROM AVERAGE BEAM CURRENT LIMITER

M12B

EHT_INFO

3350 10K

M13B

7350 BC847B 3352 1K 7352 BF824 7353 BF824

7374 PMBT2369

3356 390R

470R
7356 BC857B

2351

2350

100n

FBL1

3360 4K7 7361 PMBT2369

FROM PIN 35 C

7363 PMBT2369

FBL2

3361

3364

1K

2352

100n

9.5

4K7

FROM e/TS7071/7072/7073

390R

3351

3354

3355

10K

2K2

3358

4u7

2K2

1K

CL 86532033_038.AI 160698

Transparent OSD
Only in European sets the transparent OSD circuitry is present. The polarity of the FBL1 and the FBL2 signals are active high. The FBL1 signal is supplied by pin 35 of the microprocessor IC7000, while FBL2 is supplied during the RGB signals via TS7071/7072/7073. FBL2 is present during the transparent OSD period. During the transparent OSD period TS7363 is conducting. Via the circuit TS7374, TS7352 and TS7353 the EHT_INFO is influenced in such a way that via the Beam Current Limiter input of IC7150 the brightness during the transparent OSD period is reduced while the normal picture remains visible. During the RGB OSD characters the EHT_INFO is not influenced and the brightness remains the same as for the normal picture.

Personal notes

A8.0A

Widescreen view modes Introduction

89

Widescreen view modes Introduction

ADDITIONAL OVERSCAN BLANKING

16:9 ZOOM

4:3

CL 86532033_044.AI 160698

In an A8 set the widescreen modes are created via a combination between hardware circuitry and software (BiMOS) controlled geometry. The involved hardware circuitry is described in the line output stage chapter. The software controlled parts are enabled/ disabled with the "WS" option in the software. The picture is modified in three ways in widescreen sets: Linear or non-linear horizontal picture display Additional blanking Geometry settings

set) the BiMOS changes the blanking time of the picture to prevent the overscan from becoming visible at the edges of the 4:3 picture. This is to make sure that there is a straight vertical separation between the picture and the black bars.

Geometry settings
The picture geometry of the view modes: "wide screen", "zoom 14:9", "zoom 16:9" and "subtitle zoom" is derived from the 4:3 geometry settings (by using offset values). This alignment should be done in the ALIGNMENT - GEOMETRY menu of the SAM. For the picture geometry of the view mode "super wide" the default off set values cannot be used. Instead, a separate set of alignments has to be made via the ALIGNMENT - GEOMETRY SW menu in the SAM.

Linear or non-linear horizontal picture display

In panorama (also called Super Wide) mode, the full scanned picture is non-linear displayed. Distortion is small in the centre of the screen and large at the outer edges. This non-linear display is realized via an additional S-capacitor on the EW PANORAMA PANEL. This S-capacitor is switched via the PANORAMA signal coming from the micro controller. In all other modes, the signal is linear displayed.

Additional blanking
In view modes were the entire picture tube is used the horizontal overscan is outside the visible area of the picture tube. In view modes where only part of the width of the picture tube is used (e.g. "4:3" of "14:9 zoom" view modes on a widescreen

In "14:9 zoom", "16:9 zoom", "subtitle zoom" and "super wide" the vertical position of the picture can be changed with the cursor keys. The change in view mode as well as the change of the vertical position is controlled via the software.

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Widescreen view modes Introduction

A8.0A