Altera SoC Golden System Reference Design User Guide

2013.05.06

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2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Overview
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This document describes Cyclone V SoC FPGA golden system reference design (GSRD). The design demonstrates the Hard Processor System (HPS) features and the ability to communicate between HPS to the FPGA logic via the AXI Bridge interfaces. It is designed to provide a solid foundation of the most essential hardware and software system components for various user designs. It consists of the hardware reference design called Golden Hardware Reference Design (GHRD) and Linux software packages.

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Feature Description
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The GSRD demonstrates the HPS features and the ability of communication between HPS to the FPGA logic via the AXI Bridges interfaces. This design provides guidance and step-by-step flow for hardware developer as well as software developer to kick starts any development with Cyclone V (CV) SoC FPGA development kit. The golden hardware design consists of an ARM Cortex-A9 MPCore Hard Processor System (HPS), 2-bit of user push button inputs, 4-bit of user dipswitch inputs, 4-bit of user IO blinking LED outputs, 64Kbytes on-chip memory, JTAG to Avalon master bridges, interrupt capturer for use with system console and system ID. HPS contains large number of peripherals such as SDRAM Controller, Gigabit Ethernet MAC, QSPI, USB OTG, SDMMC, CAN, SPI Master, UART and I2C interface. The following figure illustrates the GHRD block diagram.

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Feature Description

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Figure 1: GHRD System Architecture

The GHRD has minimum peripheral on the FPGA fabric as HPS has already provided substantial amount of peripheral choice. HPS2FPGA and FPGA2HPS interfaces are set to be 64-bit in data width. The GHRD system also provides an option for hardware designer to be able to access each peripheral in FPGA domain of the system via System-Console through the JTAG Master module. This signal level access is independent of driver readiness of each peripheral.

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Enabled HPS Peripherals

Enabled HPS Peripherals

Only a part of HPS peripherals are enabled in GHRD, specifically the components which have board trace connections in Cyclone V SX SoC Development Board. Following table lists the enabled peripherals. Table 1: Enabled HPS peripherals
Peripheral Remarks

GPIO GPIO GPIO GPIO Ethernet SDMMC USB QSPI SPI UART I2C TRACE

User DIPSW (4 bits), GPI7-10 User Push Button (4 bits), GPI3-6 LED (4 bits), GPIO41-44 Others, (enet_int, CONV_HPS_USB_N) Gbps Ethernet (EMAC1) 4-wire USB1, Set 0 QSPI, 1SS SPI Master (SPIM0) UART0 to USB mini, Set 2 I2C0, Set 1 Trace Port Interface

MPU View
The memory map of system peripherals on FPGA as view by the MPU will sit on top of HPS2FPGA address offset 0xC000_000. Following table describes the offset of each peripheral in FPGA. Table 2: Address offset of peripherals on HPS2FPGA Interface
Peripheral Address offset Size (bytes) Attribute

onchip_memory2_0

0x0

64K

On-chip RAM as scratch pad

The memory map of system peripherals on FPGA as view by the MPU which sit on top of LWHPS2FPGA with base address of 0xFF20_000 is show in following table. Table 3: Address offset of peripherals on LWHPS2FPGA Interface
Peripheral Address offset Size (bytes) Attribute

sysid_qsys
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0x10000

Unique system ID
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JTAG Master View

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Peripheral

Address offset

Size (bytes)

Attribute

led_pio dipsw_pio button_pio jtag_uart

0x10040 0x10080 0x100c0 0x20000

8 8 8 8

LED output display Push button input DIP switch input JTAG UART console

JTAG Master View

There are two JTAG Masters in the design, one for accessing non-secure peripherals in FPGA fabric, and another for accessing secure peripheral in HPS via the FPGA2HPS Interface. Following table describes the address of each peripheral in FPGA via the non-secure JTAG Master view. Table 4: Address of peripherals and interfaces accessible by JTAG Master
Peripheral Address offset Size (bytes) Attribute

sysid_qsys led_pio dipsw_pio button_pio jtag_uart onchip_memory2_0

0x0001_0000 0x0001_0040 0x0001_0080 0x0001_00c0 0x0002_0000 0x0000_0000

8 8 8 8 8 64K

Unique system ID 4 LED outputs 4 dip switch inputs 2 push button inputs JTAG UART console On-chip RAM

Interrupts Routing
HPS exposes 64 interrupt inputs for FPGA logic. Following table illustrates the FPGA peripherals interrupts to the HPS interrupt input interface. Table 5: Interrupt number of FPGA peripherals
Peripheral Interrupt number Attribute

dipsw_pio button_pio jtag_uart

f2h_irq0[0] f2h_irq0[1] f2h_irq0[2]

4 dip switch inputs 2 push button inputs JTAG UART

The interrupts sources are also connected to an interrupt capturer module in the system, which enable system console to make aware of the interrupt status of each peripheral in FPGA.

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Prerequisites
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To use this guide, you must download and install version 13.0 or later of the following software from the Altera Download Center: Altera Quartus II software Altera SoC EDS See SoC EDS and ARM DS-5 Installation in the Altera SoC Embedded Design Suite User Guide for installation details. SoC FPGA Linux Binary Support Package SoC FPGA Linux Source File Support Package

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Setting Up the SoC FPGA CV Development Kit

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1. Make sure that shunts and shorting jumpers are installed as follows: Clock select CLKSELx: Boot select BOOTSELx: J26, J27 set toward the power switch J28, J29: set toward the power switch J30: set away from the power switch Rest of jumper settings: Table 1: Jumper Settings
Number Name Setting

J5 J6 J8 J9 J13 J15 J31

9V JTAG_HPS_SEL JTAG_SEL UART Signals OSC1_CLK_SEL JTAG_MIC_SEL SPI_I2C

Open Open Shorted Open Shorted Open Open

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Setting Up the SoC FPGA CV Development Kit

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Figure 1: Jumper Settings

Figure 2: Jumper Settings

2. Make sure the DIP switches are configured as follows:

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Setting Up the SoC FPGA CV Development Kit

SW1 = all switches set toward the board edge. SW2 = all switches set away from the corner of the board. SW3 = all switches set toward the board edge. SW4 = JTAG ENABLE. Each switch enables a connection to the scan chain when its corresponding switch is set away from the board edge (off). Set for programming the FPGA using the on-board USB-Blaster II = ON/OFF/ON/OFF, leaving the FPGA and MAX connected to JTAG.

3. Use a mini-USB to USB cable to connect the board to the host PC, as follows: For the steps in Hardware Development Flow, connect the cable to USB-Blaster II port on the board to the host PC. For the steps in Software Development Flow, connect the cable to the UART port on the board to the host PC. You may need to install the FTDI D2XX UART-to-USB driver from the Future Technology Devices International website. 4. Apply power to the board from a 19 V power supply, as directed in the Cyclone V SoC FPGA Development Kit User Guide.

Setting Up the SoC FPGA CV Development Kit

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Setting Up the SoC FPGA CV Development Kit

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5. Open a serial terminal program, such as Minicom (for Linux) or PuTTY (for Windows). Set the baud rate to 57.6 kbaud, 8 bits, no parity, 1 stop bit. 6. Attach the network cable to the board and connect to the network port (with DHCP enabled).

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Hardware Development Flow

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Running the GHRD on the Development Kit

Before starting these steps, select a working directory for the hardware reference design. This directory is referred to as <my_ghrd_dir> in the remainder of the user guide. The GHRD is a complete design that you can use to access several peripherals on the development kit. This gives you the first-hand experience on using the development kit. In this exercise you will be using Altera system debugging tool, System Console to control the development kit peripherals. For more information about system console, refer to Analyzing and Debugging Designs with the System Console. The following steps guide you to turn on and off the LED, to read push button values, to send character to console via JTAG-UART connection and to read-write to the on-chip memory. 1. Copy the GHRD from your Altera SoC EDS installation (<Your SoC EDS installation directory>\embedded\examples\hardware\cv_soc_devkit_ghrd) to <my_ghrd_dir>. 2. Launch Quartus II software. Open the GHRD project by clicking File, Open Project in Quartus II. Browse to <my_ghrd_dir> and select soc_system.qpf. Click Open.

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Running the GHRD on the Development Kit

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3. Click Tools, Programmer to launch Quartus II Programmer. Click Auto Detect and select the device part number from the SoC development board (for example, 5CSXFC6C6). 4. Right-click the device part number and click Change File. In the Select New Programming File dialog box, browse to <my_ghrd_dir>\output_files and select soc_system.sof. 5. Check the Program/Configure box and click Start. This will configure the Cyclone V device with the GHRD image.

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Running the GHRD on the Development Kit

6. Click Tools, Qsys to launch Qsys tool. Browse to <my_ghrd_dir> and select soc_system.qsys. Click Open.

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Running the GHRD on the Development Kit

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7. In Qsys, click Tools, System Console. 8. In the TCL Console panel, type pwd. Make sure that the System Console is point to <my_ghrd_dir>. 9. Type source ghrd_sc_script.tcl.

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Exercising LED

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Analyzing and Debugging Designs with the System Console

Exercising LED
You have successfully set up the connection between system console and the development kit. Now lets start with a simple task which is control the LED. 1. 2. 3. 4. 5. LED D5, D6, D7 and D8 are turned on by default. Type led_off to turn off LED D5 to D8. Turn on LED D5 by typing led_on 0x7. Turn on LED D6 by typing led_on 0xb. Turn on LED D7 by typing led_on 0xd. Turn on LED D8 by typing led_on 0xe.

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Reading Push Button Values

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Reading Push Button Values

Next, you turn on the interrupt monitoring in system console to show the interrupt happen when you press a push button. 1. Type button_data_read_clear to clear the parallel I/O (PIO) data register. 2. Type button_intr_enable 0x1 to enable interrupt from push buttons S5. 3. Type irq_monitor_on to start the interrupt monitoring in system console. System console updates the push button interrupt status for every 5 seconds. 4. Press button S5 on the development kit. 5. You should observe the following message in system console. This message shows that interrupt from pressing button S5 is captured.

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Sending Character via JTAG-UART

6. Type irq_monitor_off to turn off interrupt monitoring.

Sending Character via JTAG-UART

You can use system console to write to the JTAG-UART in GHRD and send the character to terminal in your host PC. 1. Open Nios II Command Shell from your ACDS installation. In the command shell, type nios2-terminal to connect your host PC to the development kit JTAG-UART. 2. In system console, type juart_data_write 0x48 and juart_data_write 0x49. 3. You should observe message HI is shown in Nios II Command Shell.

Read-write to On-chip Memory

In order to perform read and write tests to the on-chip memory in the GHRD, perform the following steps. 1. Type mem_rand_test 4 in system console. For demonstration purpose, only four data is written to random addresses in the memory. The command read the four data back and verifies if the contents are correct. 2. You should observe message showing random data is written to random addresses. The end of the test should report four matched data.

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Read-write to On-chip Memory

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3. Close system console.

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Software Development Flow

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Software engineers need to synchronize with hardware engineers on the hardware changes. Altera provides software handoff files which contain the necessary hardware setting (i.e. HPS configuration, external memory setting, Soft IP memory-map and interrupt). This is generated by the Quartus II during the hardware flow and is used by software engineers to regenerate the software. This ensures that the software is always in sync with the latest hardware change. In the GSRD, we will only generate 2nd stage boot software called preloader and optional 3rd stage loader called U-Boot. In the future, user can generate BSPs for later stages as well such as Operating System (i.e. Linux).

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Generating the Preloader

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Figure 1: Software Boot Stages

Boot ROM

Preloader

Boot Loader

Operating System

Generating the Preloader

The preloader binary is built with SoC EDS tools. You need to ensure that you have the SoC EDS installed on your system, as described in "Prerequisites".

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Generating the Preloader

Note: A pre-built preloader can also be found in <my_ghrd_dir>\software\preloader. However, theres a minor issue where the pre-built preloader only works with the DS-5 debugger attached. It is strongly recommended to follow the steps below to build the preloader from the generated source. 1. To launch the Preloader Support Package Generator, type bsp-editor in a Command Shell. 2. The generator starts without loading any .bsp file. To open and modify an existing BSP project, use File->Open and point to the path of an existing .bsp file. To create a new BSP project, use File->New BSP to launch the New BSP GUI. 3. In Preloader setting directory, select the <my_ghrd_dir>\hps_isw_handoff\soc_system_hps_0 directory.

4. Click OK 5. In the next screen, keep every option as default and click Generate. This will generate the new preloader source files in <my_ghrd_dir>/software/spl_bsp directory

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U-boot Image

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6. Open a command shell and browse to <my_ghrd_dir>/software/spl_bsp and type make all 7. You should now see preloader-mkpimage.bin in the same directory.

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Prerequisites on page 1

U-boot Image
1. User can build u-boot.img from SoC EDS at folder software/spl_bsp by typing make uboot
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Linux Images

2. You should now see u-boot.bin under <my_ghrd_dir>/software/spl_bsp/uboot-socfpga

Linux Images
Altera provides Linux BSP support for the Cyclone V SoC Development Kit, including the following components: Linux kernel 3.7 Preloader u-boot version 2012.10 Yocto version 'Danny' Packages for the root file system C compiler tool chain (Linaro-GCC, v4.7)

Yocto is used to build the kernel, the u-boot and the root file system from source. There are many source code packages available under the Yocto project. If you enable a package that is not provided with our BSP, it is downloaded. If your system communicates with the network through a proxy server, make sure the network configuration of your Linux host is ready. We use the pre-built binary Linux images in this documentation. For instructions on how to build Linux images from source, refer to the Linux Getting Started Guide and the Linux BSP User Manual on the Altera Linux Portal.
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Programming Flash
To boot the Linux images on your SoC FPGA development kit, you need to write the required images into one of the three flash devices: SD/MMC, NAND or QSPI. This guide uses the SD/MMC because it is easily removable. 1. Download linux-socfpga-13.02-bin.tar.gz and uncompress into a directory 2. Write the included sd_image.bin file to the SD card using dd utility. For instructions to create an SD image from individual components (Preloader, U-boot, Device Tree, Linux kernel, root file system), if necessary, refer to the the Linux BSP User Manual on the Altera Linux Portal.
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Booting Linux on the SoC FPGA CV Development Kit

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Booting Linux on the SoC FPGA CV Development Kit

1. Insert the SD card 2. Hit warm reset 3. Observe Preloader -> U-Boot -> Linux booting in order on the serial terminal

4. Log in as root with no password

Overview of Software Out-of-Box Experience

Software Out-of-Box Experience (SW OOBE) provides a user a number of pre-built demos with CV SoC development kit and links to related information through the board portal web page. The following subsections describe the pre-built demos included in the GSRD software package. The figure below summarizes the SW OOBE.

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Remote Login to Board Update Portal

Remote Login to Board Update Portal

Board Update Portal is a website hosted by the Lighttpd web server on Embedded Linux running on the HPS. When the CV SoC development kit is powered on, an IP address obtained from DHCP server and a message Hello Tim! will be displayed on the character LCD on the board. A User may access the Board Update Portal (BUP) page by entering the IP displayed on the character LCD as the URL address it to a PC browser in the same network. A User can obtain information on the SoC FPGA, development kit, development tools, link to the Linux portal website and more from the BUP.

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Remote Login to Board Update Portal

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Figure 2: Board Update Portal

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Lighttpd Web Server

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Interacting with CV SoC board from BUP

Interacting with CV SoC board from BUP

From the BUP, a user may interact with the board to blink LEDs with a specified delay and to display a text onto the character LCD. Maximum number of characters accepted is 16 for LCD display (2 x 16 character display) because the board IP address will always remain on the first line of the LCD.

Interacting with CV SoC board via serial/SSH connection

A User may connect to a Linux console running on the HPS via serial connection or network connection.

Over Serial Connection

Make sure the UART port (USB to serial) is connected to the host system with a USB cable. Serial connection settings required are as below: Baud rate : 57600 Data : 8-bit Parity: None Stop: 1-bit Flow control: None

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Over SSH

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Over SSH
A SSH server is started as soon as the Linux boots. A user may use a SSH client on their host machine to connect to the target SoC FPGA using the IP address displayed on the character LCD. root@<IP address displayed on the character LCD>

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Applications Examples

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Applications Examples
A user may run applications (i.e. LED control, push buttons and DIP switches) built into the default Linux root file system from the Linux console. These examples serve as references for users to write their own applications that interact with soft IPs. The source code of these applications can be found at <SoC FPGA Linux Source File Support Package installation directory>/meta-altera/recipes-gsrd/files. You need to execute the BSX file and select the extraction target directory to extract first. In the target Linux root file system, the binaries of these applications sit in /home/root/altera/. Please 'cd' to /home/root/altera to execute these applications. By default, the kernel modules needed for execution of these example applications are added with modprobe when Linux boots up. If users develop their own drivers/kernel modules and the applications dependent on the drivers/kernel modules, then the users will need to add the kernel modules with modprobe before executing the applications. A number of application usages are shown below. the example applications are based on the soft PIO driver in FPGA.

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Applications to Exercise Soft PIO Driver LED control

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Applications to Exercise Soft PIO Driver LED control

Blinking a particular FPGA LED with specified delay: ./blink <LED number> <blink delay in ms> ./blink; help message Toggling a particular FPGA LED ON/OFF: ./toggle <LED number> <0 or 1> ./toggle ; help message Scrolling FPGA LEDs with specified delay: ./scroll <delay in ms> ; if > 0 then scrolling LEDs light ./scroll 0 ; if 0 then read scrolling delay ./scroll -1 ; if < 0 then stop scrolling ./scroll ; help message ; 0 - OFF, 1 - ON

Applications to register interrupt and write simple interrupt service routine

Detect user input from push button / DIP switch: modprobe gpio_interrupt gpio_number=<n> User will need to get the GPIO number from /sys/class/gpio/ by using command 'ls'. E.g. root@socfpga-cyclone5~:# ls /sys/class/gpio/ export gpio246 gpio248 gpio252 From the listing, n can be obtained. The GPIO number may vary for different designs with different device tree entries; this is due to the GPIO numbers are auto-assigned by the kernel. To confirm the n is associated to which peripheral, user needs to match the label of the GPIO chip to the address of push button and DIP switch in device tree (<SoC FPGA Linux Source File Support Package installation directory>/meta-altera/recipes-gsrd/files/socfpga.dts). e.g. root@socfpga-cyclone5~:# cat /sys/class/gpio/gpiochip246 /soc/gpio@0x100c0 In this reference design, DIP switch is at address 0x10080 while the push button is at address 0x100c0. So in this case GPIO number 246 - 247 are allocated to push button 0 - 1.

Hello World Application from HPS

Print Hello SoC FPGA! message from HPS: ./hello

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