HP 6910 Pla 3262 P

A
Compal confidential
Schematics Document
Mobile Merom uFCPGA with Intel
Crestline + ICH8-M core logic
IBT00 LA-3262P Discrete VGA (M64)
2007-08-02
REV:1A
Compal Secret Data
Security Classification
2006/09/25
Issued Date
2006/09/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Compal Electronics, Inc.

Cover Sheet
Size Document Number

Custom LA3262P_DIS__M64
Date:
Rev
1A
Sheet
Tuesday, August 21, 2007

E
of
57
Compal confidential
File Name : LA-3262P
Chimay Discrete
Thermal Sensor
ADM1032ARMZ
Mobile Merom
uFCPGA-478 CPU
P4
P4, 5, 6
Fan conn
P4
H_A#(3..35)
CRT & TV OUT
CK505
Clock Generator
ICS 9LPRS355
FSB
H_D#(0..63)
667/800MHz 1.05V
P16
DDR2 667MHz 1.8V
Intel Crestline MCH
LVDS Panel Interface
DVI (Docking)
BANK 0, 1, 2, 3
(PM) FCBGA 1299
PCIE
P18, 19, 20, 21, 22, 23
USB conn x2
(Docking)
P7, 8, 9, 10, 11, 12
P33
DMI X4
Mini-Card
P25
PCI
CardBus Controller & PCMCIA conn
P34
Azalia
BT Conn
PATA Slave
Mini-Card WWAN
P24, 25, 26, 27
P25
P29
MDC
P31
AD1981HD
Slot 0/Smart Card
RJ45/11 CONN
P32
AMP & Audio Jack

MAX9710
P33
3
P30
1394 port
SPI ROM & Debug port
6in1 Slot
SATA HDD Connector

P28
16Mb*2 or 32Mb*1
P34
LED
P33
Docking CONN.
P36
P30
Multi-bay II Connector
daughter board
P28
LPC BUS
RTC CKT.
P19
TPM1.2
SLB9635TT
Power OK CKT.
P35
SMSC Super I/O

LPC47N217 P35
SMSC KBC 1070
P36
P38
Audio CKT
SPI
P28
SATA Master
mBGA-676
Ricoh R5C853
daughter board
USB conn x3
USB2.0
Intel ICH8-M
P33
FingerPrinter AES1610
P34
USBx1
C-Link
PCI-E BUS
10/100/1000 LAN
Intel 82566MM
P15
P13, 14
Dual Channel
P17
ATI M64S
DDR2-SO-DIMM X2
P37
Power On/Off CKT.
Touch Pad CONN.
P32
P38
TrackPoint CONN.
P38
DC/DC Interface CKT.
COM1
( Docking )
P33
LPT
( Docking )
P33
P38
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
P34
Int.KBD
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK
Title

Block Diagram

Date:
Rev
1A
Sheet

E
of
57
Voltage Rails
O MEANS ON
X MEANS OFF
+5VS
+3VS
power
plane
+2.5VS
+1.8VS
+B
LDO3
+5VALW
+1.8V
LDO5
+3VALW
+5V
+0.9V
State
+1.5VS
+3VM
+1.25VS
+VGA_CORE
+CPU_CORE
CLOCK
+1.05VM
+1.25VM
+VCCP
S0
S3/M1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
Device
IRQ
System Timer
Keyboard
N/A
Serial port (COM2),LAN/Modem
Serial port (COM1)
Audio/VGA
Floppy
Parallel port
System CMOS/Real-time clock
Microsoft ACPI
10
N/A,Momem,LAN
11
Mass strorage control/ PCI simple communication control
12
synactic PS2 port GlidePAD
13
Numeric Data Process
14
Primary IDE interface,HDD
15
Secondary IDE innterface,CD-ROM
16
Mobile Intel Crestline Express Chipset Family
Microsoft UAA Bus Driver for High Definition Audio

Intel 82801H (ICH8 Family) PCI Express Root Port -27D0
PCI Devices
Broadcom NetXtreme Gigabit Ethernet
EXTERNAL
IDSEL#
CARD BUS & 1394
AD22
REQ/GNT#
2
PIRQ
17
C,D,E,G
Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2

Broadcom 802.11b/g WLAN
Intel 82801H (ICH8 Family)USB Universal Host Controll
DMA Channel
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
18
Device
MODEM / LAN
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused
Ricoh R5C853 Gemcore based SmartCard Control

19
Walk-up0 (Right side)
Fingerprint
Reserve
WWAN
Walk-up1 (Left Side)
Walk-up2 (Left Side)
Bluetooth
Reserve
20
Docking
Docking

Intel 82801H (ICH8 Family)USB2 Enhanced Host Controll
21
23

SDA Standard Compliant SD Host Controller
HP Mobile Data Protection Sensor
Compal Secret Data
2006/09/25
Issued Date
Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6

Destination
Ricoh R5C853 Cardbus Control

Ricoh R5C853 Integrates FlashMedia Control
22
USB PORT#
Deciphered Date
2006/09/25
A
Title

Notes List

Date:
Rev
1A
Sheet
of
57
layout note: Change R237 to 649 ohm if using XTP to ITP adapter
XDP Connector
+3VS
R243
XDP_DBRESET#_R
2 @ 1K_0402_5%
+VCCP
JP51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
XDP_BPM#5
XDP_BPM#4
D
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
JP12A
K3
H2
K2
J3
L1
<7> H_ADSTB#1
A6
A5
C4
H_STPCLK#
H_INTR
H_NMI
H_SMI#
<25> H_STPCLK#
<25> H_INTR
<25>
H_NMI
<25>
H_SMI#
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
F1
H_BR0#
IERR#
INIT#
D20
B3
H_IERR#
H_INIT#
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
CONTROL
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
D5
C6
B4
A3
H_DEFER#
H_DRDY#
H_DBSY#
BR0#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A20M#
FERR#
IGNNE#
H5
F21
E1
DEFER#
DRDY#
DBSY#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0#
H_INIT#
C7
H_PWRGOOD_R
XDP_HOOK1
<5> H_PWRGOOD_R
R172
56_0402_5%
2
1
+VCCP
1
+VCCP
<25>
C1099
2
XDP_TCK
H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>
0.1U_0402_16V4Z
conn@
BCLK[0]
BCLK[1]
A22
A21
R143 1
XDP_TMS
R236 1
54.9_0402_1%
XDP_TDO
R1670 1
54.9_0402_1%
XDP_BPM#5
R241 1
54.9_0402_1%
XDP_HOOK1
R1430 1
2 @ 54.9_0402_1%
XDP_TRST#
R237 1
51_0402_1%
XDP_TCK
R239 1
54.9_0402_1%
54.9_0402_1%
CLK_CPU_XDP
CLK_CPU_XDP#
CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>
1K_0402_1%
+VCCP
H_RESET#_R
1 R1431 2 H_RESET#
XDP_DBRESET#_R 2
1 XDP_DBRESET#
200_0402_1%
XDP_TDO
R1432
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
1 R1433 2 0_0402_5%
SAMTE_BSH-030-01-L-D-A
Place R1431 within 200ps (~1") to CPU

C
For Merom, R23 and R34 are 0ohm

For Penryn, R23 and R34 are 100ohm.
Thermal Sensor ADM1032ARMZ

+3VS
XDP_DBRESET# <26>
R410
2
1
68_0402_5%
H_PROCHOT# <49>
C273
+VCCP
0.1U_0402_16V4Z
R23
R34
H_THERMTRIP#
1
1
2 0_0402_5% H_THERMDA
2 0_0402_5% H_THERMDC
CLK_CPU_BCLK
CLK_CPU_BCLK#
R227
10K_0402_5%
1
U16
H_THERMTRIP# <7,23,25>
C264
1
2
11/20 Penryn support to add R23,R34

H CLK
XDP_TDI
H_HIT# <7>
H_HITM# <7>
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
D21
A24 H_THERMDA_R
B25 H_THERMDC_R
<7>
H_LOCK# <7>
H_PROCHOT#
THERMAL
ICH
H_A20M#
H_FERR#
H_IGNNE#
<25> H_A20M#
<25> H_FERR#
<25> H_IGNNE#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H_ADS#
H_BNR#
H_BPRI#
ADS#
BNR#
BPRI#
ADDR GROUP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H1
E2
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
<7>
H_REQ#0
<7>
H_REQ#1
<7>
H_REQ#2
<7>
H_REQ#3
<7>
H_REQ#4
<7> H_A#[17..35]
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
XDP/ITP SIGNALS
<7> H_ADSTB#0
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
VDD
SCLK
ICH_SM_CLK
H_THERMDA
D+
SDATA
ICH_SM_DA
H_THERMDC
D-
ALERT#
THERM_SCI#
THERM#
GND
2200P_0402_50V7K
CLK_CPU_BCLK <15>
CLK_CPU_BCLK# <15>
THERM#
H_A#[3..16]
THERM_SCI# <23,26>
R228
1
+3VS
H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
ADM1032ARMZ-2REEL_MSOP8
10K_0402_5%
Address:100_1100
B
R229
RESERVED
<7>
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
<23> THERM#_VGA
2
<19,23,26,31> ICH_SM_CLK
<19,23,26,31> ICH_SM_DA
0_0402_5%
@
ICH_SM_CLK
ICH_SM_DA
0802 (R1A) add for VGA thermal function
Merom Ball-out Rev 1a

conn@
PWM Fan Control circuit
+VCCP
0308 change design

+3VS
R1255
2 2
@ 56_0402_5%
3
1 OCP#
@ Q85
MMBT3904_SOT23
OCP#
THERM# 1
<26,50>
INB
INA
0_0402_5%
R230
1
2
+3VS
A
conn@
JP8
U24
1
2
3
+5VS
H_PROCHOT#
FAN_PWM
<37>
TC7SH00FU_SSOP5
1
2
3
G1
G2
4
5
ACES_85204-03001
R232
@ 10K_0402_5%
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

Merom(1/3)-AGTL+/XDP

Date:
Rev
1A
Sheet

1
of
57
+VCC_CORE
C1101
B22
B23
C21
BSEL[0]
BSEL[1]
BSEL[2]
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
MISC

conn@
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
200
H_DPRSTP# <7,25,49>
H_DPSLP# <25>
H_DPWR# <7>
H_PWRGOOD <25>
H_CPUSLP# <7>
H_PSI#
<49>
R1436
2
1H_PWRGOOD_R
1K_0402_5%
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL
H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
H_PWRGOOD_R <4>
Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VCCSENSE <49>
VSSSENSE
AE7
VSSSENSE
VSSSENSE <49>

conn@
+VCCP
R1434
2
2
R1435
0_0402_5%
1
1
0_0402_5%
0228 change value

C
1
C1100 +
2
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
330U_D2E_2.5VM_R15
<49>
<49>
<49>
<49>
<49>
<49>
<49>
+1.5VS
0.01U_0402_16V7K
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
C520
AD26
C23
D25
C24
AF26
AF1
A26
<7> H_DSTBN#1
<7> H_DSTBP#1
<7>
H_DINV#1
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
JP12C
R244
27.4_0402_1%
2
1
V_CPU_GTLREF
TEST1
2 @ 1K_0402_5%
TEST2
2 @ 1K_0402_5%
TEST3
T1
@ 0.1U_0402_16V4Z
TEST4
2
TEST5
T2
TEST6
T3
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
+VCC_CORE
<7>
R245
54.9_0402_1%
2
1
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
R355
27.4_0402_1%
2
1
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
DATA GRP 2
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
<7> H_DSTBN#0
<7> H_DSTBP#0
<7>
H_DINV#0
<7> H_D#[16..31]
DATA GRP 1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 0
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
R1264 1
R1265 1
H_D#[32..47]
JP12B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
R1220
54.9_0402_1%
2
1
H_D#[0..15]
DATA GRP 3
<7>
10U_0805_10V4Z
C531
Near pin B26

B
Length match within 25 mils.

The trace width/space/other is
20/7/25.
+VCCP
R1268
1K_0402_1%
2
+VCC_CORE
R1269
100_0402_1%
2
VCCSENSE
R1270
100_0402_1%
1
2
VSSSENSE
V_CPU_GTLREF
R1271
2K_0402_1%
Close to CPU pin AD26

within 500mils.
Close to CPU pin

within 500mils.
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

Merom(2/3)-AGTL+/PWR

Date:
Rev
1A
Sheet

1
of
57
+VCC_CORE
1
Place these capacitors on L8
(North side,Secondary Layer)
D
C899
10U_0805_6.3V6M
C900
10U_0805_6.3V6M
C901
10U_0805_6.3V6M
C902
10U_0805_6.3V6M
C903
10U_0805_6.3V6M
C904
10U_0805_6.3V6M
C905
10U_0805_6.3V6M
C906
10U_0805_6.3V6M
D
JP12D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

conn@
+VCC_CORE
1
(North side,Secondary Layer)
C907
10U_0805_6.3V6M
C908
10U_0805_6.3V6M
C909
10U_0805_6.3V6M
C910
10U_0805_6.3V6M
C911
10U_0805_6.3V6M
C912
10U_0805_6.3V6M
C913
10U_0805_6.3V6M
C914
10U_0805_6.3V6M
+VCC_CORE
1
(Sorth side,Secondary Layer)
C915
10U_0805_6.3V6M
C916
10U_0805_6.3V6M
C917
10U_0805_6.3V6M
C918
10U_0805_6.3V6M
C919
10U_0805_6.3V6M
C920
10U_0805_6.3V6M
C921
10U_0805_6.3V6M
C922
10U_0805_6.3V6M
+VCC_CORE
1
(Sorth side,Secondary Layer)
C923
10U_0805_6.3V6M
C924
10U_0805_6.3V6M
C925
10U_0805_6.3V6M
C926
10U_0805_6.3V6M
C927
10U_0805_6.3V6M
C928
10U_0805_6.3V6M
C929
10U_0805_6.3V6M
C930
C
10U_0805_6.3V6M
Mid Frequence Decoupling
ESR <= 1.5m ohm

Capacitor > 1980uF
Near CPU CORE regulator
+VCC_CORE
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
B
1
C931
330U_D2E_2.5VM_R7
C932
1
C933
C935
@
C936
330U_D2E_2.5VM_R7
@
C937
+
2
330U_D2E_2.5VM_R7
1
+
2
330U_D2E_2.5VM_R7
Place these inside

socket cavity on L8
(North side
Secondary)
+VCCP
C940
0.1U_0402_10V6K
C941
0.1U_0402_10V6K
C942
0.1U_0402_10V6K
C943
0.1U_0402_10V6K
C944
0.1U_0402_10V6K
C945
0.1U_0402_10V6K
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

Merom(3/3)-GND&Bypass

Date:
Rev
1A
Sheet

1
of
57
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
M14
E13
A11
H13
B12
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
E12
D7
D8
H_RS#0
H_RS#1
H_RS#2
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<5>
<5>
<5>
<5>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
<4>
<4>
<4>
<4>
<4>
H_RS#0
H_RS#1
H_RS#2
<4>
<4>
<4>
R1484
CLKREQ#_B
R1441
2 <>
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BH18
BJ15
BJ14
BE16
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP
SM_RCOMP#
BL15
BK14
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BK31
BL31
SMRCOMP_VOH
SMRCOMP_VOL
SM_VREF_0
SM_VREF_1
AR49
AW4
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
0_0402_5%
1
2 R2 THERM_TRIP#
DPRSLPVR
<26,49> DPRSLPVR
G41
L39
L36
J36
AW49
AV20
N20
G36
PM_POK_R
<26> PM_BMBUSY#
<5,25,49> H_DPRSTP#
<13> PM_EXTTS#0
<14> PM_EXTTS#1
11/20 Add R2 for Intel ES2 chipset
+1.8V
THERM_TRIP#
1
2
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
MUXING
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AN47
AJ38
AN42
AN46
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AM47
AJ39
AN41
AN45
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AJ46
AJ41
AM40
AM44
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AJ47
AJ42
AM39
AM43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
<26>
<26>
<26>
<26>
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
<26>
<26>
<26>
<26>
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
<26>
<26>
<26>
<26>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
<26>
<26>
<26>
<26>
AM49
AK50
AT43
AN49
AM50
CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF
CL_CLK0 <26>
CL_DATA0 <26>
M_PWROK <26,41>
CL_RST# <26>
CL_VREF
0.1U_0402_16V4Z 1
R1442
1K_0402_1%
R1443
392_0402_1%
C1106
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
H35
K36
G39
G40
TEST_1
TEST_2
A37
R32
2
CLKREQ#_B
MCH_ICH_SYNC#
CLKREQ#_B <15>
MCH_ICH_SYNC# <26>
R1445
0_0402_5%
A
PLT_RST# <24,28,36>
100_0402_5%
Near B3 pin
Compal Secret Data

2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>
+1.25VM_AXD
R1446
PLT_RST#
2
2
R1444
+1.8V
20_0402_1%
1
1
20_0402_1%
E35
A39
C38
B39
E36
20K_0402_5%
<13>
<13>
<14>
<14>
CRESTLINE_1p0
PLT_RST#_R
<13>
<13>
<14>
<14>
V_DDR_MCH_REF
K44
K45
@ 1K_0402_1%
2
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
R1195
PEG_CLK
PEG_CLK#
R1204
<13>
<13>
<14>
<14>
R1194
B42
C42
H48
H47
<15> MCH_CLKSEL0
<15> MCH_CLKSEL1
<15> MCH_CLKSEL2
T104
T105
<9>
CFG5
T106
<9>
CFG7
<9>
CFG8
<9>
CFG9
T107
T108
<9>
CFG12
<9>
CFG13
T109
T110
<9>
CFG16
T111
T112
<9>
CFG19
<9>
CFG20
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
M_ODT0
M_ODT1
M_ODT2
M_ODT3
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
10K_0402_5%
V_DDR_MCH_REF
DDR
within 100 mils from NB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
CLK
2
2
10K_0402_5%
1
0_0402_5%
C895
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C896
1
R1206
221_0603_1%
2
1
R1210
2
100_0402_1%
R1199
24.9_0402_1%
2
1
C60
1K_0402_1%
R1208
2
1
R1212
2
2K_0402_1%
C1105
R1440
PM_EXTTS#1
R1201
@ 1K_0402_1%
H_SWNG
BG20
BK16
BG16
BE13
<13>
<13>
<14>
<14>
<5>
<5>
<5>
<5>
10K_0402_5%
<5>
<5>
<5>
<5>
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
NC
1K_0402_1%
2007,0125 change
<13,14,48> V_DDR_MCH_REF
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
DMI
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
+VCCP
H_RCOMP
R1438
R1439
PM_EXTTS#0
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
+3VS
0904 add
+VCCP
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
1
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0#
<4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
<4,23,25> H_THERMTRIP#
0.1U_0402_16V4Z
H_VREF
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
<13> DDR_A_MA14
<14> DDR_B_MA14
CRESTLINE_1p0
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
0.01U_0402_25V7K
SMRCOMP_VOL
layout note:
VGATE
BE29
AY32
BD39
BG37
R31
3.01K_0402_1%
H_AVREF
H_DVREF
<26,37>
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
L7
K2
AC2
AJ10
C1103
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
2.2U_0603_6.3V4Z
C1102
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
H_VREF
M7
K3
AD2
AH11
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
PM
B9
A9
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
AW30
BA23
AW25
AW23
<13>
<13>
<14>
<14>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
H_CPURST#
H_CPUSLP#
K5
L2
AD13
AE13
1K_0402_1%
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
B6
E5
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
SMRCOMP_VOH
R1437
AV29
BB23
BA25
AV23
H_RESET#
H_CPUSLP#
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+1.8V
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
H_SCOMP
H_SCOMP#
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
H_SWING
H_RCOMP
W1
W2
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
GRAPHICS VID
B3
C2
H_SCOMP
H_SCOMP#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
ME
R1197
54.9_0402_1%
2
1
H_RESET#
H_CPUSLP#
H_SWNG
H_RCOMP
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
CFG
R1196
54.9_0402_1%
2
1
+VCCP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
C1626
0.1U_0402_16V4Z
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
2.2U_0603_6.3V4Z
C1104
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
For Crestline: 20ohm

For Calero: 80.6ohm
RSVD
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
U15B
0.01U_0402_25V7K
U15A
H_D#[0..63]
<4>
<5>
H_A#[3..35] <4>
HOST
<5>
MISC
Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Date:
Rev
1A
Sheet

1
of
57
<14> DDR_B_D[0..63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
SA_CAS#
BL17
DDR_A_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
SA_RAS#
SA_RCVEN#
BE18
AY20
DDR_A_RAS#
SA_RCVEN#
SA_WE#
BA19
DDR_A_WE#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_A_BS0 <13>
DDR_A_BS1 <13>
DDR_A_BS2 <13>
DDR_A_CAS# <13>
DDR_A_DM[0..7] <13>
DDR_A_DQS[0..7]
<13>
DDR_A_DQS#[0..7]
DDR_A_MA[0..13]
<13>
<13>
DDR_A_RAS# <13>
T5
DDR_A_WE# <13>
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
CRESTLINE_1p0
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BB19
BK19
BF29
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SYSTEM
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
DDR
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U15E
SYSTEM
U15D
DDR
<13> DDR_A_D[0..63]
AY17
BG18
BG36
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
SB_RAS#
SB_RCVEN#
AV16
AY18
DDR_B_RAS#
SB_RCVEN#
SB_WE#
BC17
DDR_B_WE#
DDR_B_BS0 <14>
DDR_B_BS1 <14>
DDR_B_BS2 <14>
DDR_B_CAS# <14>
DDR_B_DM[0..7] <14>
DDR_B_DQS[0..7]
<14>
DDR_B_DQS#[0..7]
<14>
DDR_B_MA[0..13]
<14>
DDR_B_RAS# <14>
T4
DDR_B_WE# <14>
CRESTLINE_1p0
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

CRESTLINE((2/6)-DDR2 A/B CH

Date:
Rev
1A
Sheet

1
of
57
PEGCOMP trace width

and spacing is 20/25 mils.
U15C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
L41
L43
N41
N40
D46
C45
D44
E42
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
G51
E51
F49
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
E44
A47
A45
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TVA_DAC
TVB_DAC
TVC_DAC
F27
J27
L27
TVA_RTN
TVB_RTN
TVC_RTN
M35
P33
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
K33
G35
F33
C32
E33
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
VGA
H32
G32
K29
J29
F29
E29
GRAPHICS
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
TV
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
G44
B47
B45
E27
G27
K27
LVDS
G50
E50
F48
PEGCOMP
+VCCP
PEG_COMPI
PEG_COMPO
N43
M43
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
C1058 1
C1059 1
C1060 1
C1559 1
C1562
C1563
C1560
C1561
C1564
C1361
C1362
C1363
C1364
C1365
C1366
C1367
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
C1062 1
C1063 1
C1066 1
C1067 1
C1368
C1369
C1370
C1371
C1372
C1373
C1374
C1375
C1376
C1377
C1378
C1379
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15
Strap Pin Table

010 = FSB 800MHz
PEG_RXN[0..15] <18>
PCI-EXPRESS
J40
H39
E39
E40
C37
D35
K40
R1176
24.9_0402_1%
1
2
011 = FSB 667MHz
CFG[2:0] FSB Freq select
Others = Reserved
0 = DMI x 2
CFG5 (DMI select)
1 = DMI x 4
CFG6
Reserved
0 = Reserved
CFG7 (CPU Strap)
1 = Mobile CPU
PEG_RXP[0..15] <18>
CFG8 (Low power PCIE)
1 = Low Power mode
(PCIE Graphics Lane Reversal)

CFG[11:10]
1 = Normal Operation
Reserved
00
01
10
11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation(Default)
*
C
Reserved
CFG16 (FSB Dynamic ODT)
0 = Disabled
1 = Enabled
CFG[18:17]
Reserved
0 = No SDVO Device Present
SDVO_CTRLDATA
PEG_M_TXP[0..15] <18>
0 = Reverse Lane
CFG9
PEG_M_TXN[0..15] <18>
0 = Normal mode
1 = SDVO Device Present
CFG19 (DMI Lane Reversal)
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
CFG20 (PCIE/SDVO concurrent)
0 = Only PCIE or SDVO is operational.
J37
CFG5
PAD-NO SHORT 2x2m
CRESTLINE_1p0
CFG5
R1151 1
2 @ 4.02K_0402_1%
<7>
CFG7
R1152 1
2 @ 4.02K_0402_1%
<7>
CFG8
R1451 1
2 @ 4.02K_0402_1%
<7>
CFG9
R1153 1
2 @ 4.02K_0402_1%
<7>
CFG12
R1155 1
2 @ 4.02K_0402_1%
<7>
CFG13
R1156 1
2 @ 4.02K_0402_1%
CFG16
R1157 1
2 @ 4.02K_0402_1%
<7>
1 = PCIE/SDVO are operating simu.
<7>
CFG[17:3] have internal pull up

CFG[19:18] have internal pull down
+3VS
<7>
<7>
CFG19
R1159 1
2 @ 4.02K_0402_1%
CFG20
R1160 1
2 @ 4.02K_0402_1%
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

CRESTLINE((3/6)-VGA/LVDS/TV

Date:
Rev
1A
Sheet

1
of
57
+1.25VS
+1.5VS_TVDAC
+1.25VM_HPLL
1
C1608
0.1U_0402_16V4Z
+1.25VS_PEGPLL
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
M32
L29
VCCD_CRT
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
VCCD_LVDS_1
VCCD_LVDS_2
C1122 2
0.1U_0402_16V4Z
CRESTLINE_1p0
B
AXD
C838
AXF
1
2
C837
C836
C849
VTT
CRT
PLL
A PEG
A LVDS
C40
B40
+1.25VS
R1467
@
1
2
100NH_LQW18ANR10J00D_5%_0805
(link CIS)
+1.5VS
+1.25VM_HPLL
R1464
+3VS_HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
AD51
W50
W51
V49
V50
VCC_RXR_DMI_1
VCC_RXR_DMI_2
AH50
AH51
VTTLF1
VTTLF2
VTTLF3
R1460
1
2
0_0805_5%
+1.25VM
R1466
+VCC_PEG
2
1
MBK2012121YZF_0805
C1134
+1.25VM
2
1
MBK2012121YZF_0805
C1140
0.1U_0402_16V4Z
C1135
22U_0805_6.3VAM
2 C1139 2
22U_0805_6.3VAM
+VCC_DMI
20mils
+VCCP_D
A7
F2
AH1
D12
0.47U_0402_10V4Z~D
C1143
J41
H42
1
2
VCC_HV_1
VCC_HV_2
+1.5VS_TVDAC
+1.25VM_MPLL
0.47U_0402_10V4Z~D
C1142
VCCD_PEG_PLL
VCC_TX_LVDS
A43
0.47U_0402_10V4Z~D
C1141
U48
+1.8V_SM_CK
C1136
VCCA_SM_CK_1
VCCA_SM_CK_2
C25
B25
C27
B27
B28
A28
BK24
BK23
BJ24
BJ23
2
0_0805_5%
0.1U_0402_16V4Z
C1132
BC29
BB29
0.1U_0402_16V4Z
C1131
1U_0603_10V4Z
22U_0805_6.3VAM
C1130
C1226
1U_0402_6.3V4Z
2
1
0_0603_5%
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
+VCCP
R1465
0.1U_0402_16V4Z
2
1U_0603_10V4Z
A SM
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VTTLF
4.7U_0603_6.3V6M
AT22
AT21
AT19
AT18
AT17
AR17
AR16
SM CK
+1.25VM_A_SM_CK
C1129
+1.25VS_DMI
HV
22U_0805_6.3VAM
AJ50
PEG
DMI
R1462
C1128
A CK
150U_D_6.3VM
C1127
VCC_DMI
0904 change
C1124
+V1.25VS_AXF
+VCC_PEG
C1607
1
C1126
POWER
B23
B21
A21
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
C1138
1
2
0_0805_5%
+1.25VM
VCC_AXD_NCTF
10U_0603_6.3V6M
+1.25VM
C1227
+1.25VM_A_SM
0317 change value
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
220U_D2_4VM_R15
VCCA_PEG_PLL
AW18
AV19
AU19
AU18
AU17
AR29
10U_0603_6.3V6M
1
C1606
0.1U_0402_16V4Z
R1461
U51
R1671
1
2
0_0805_5%
250mA
0.1U_0402_16V4Z
20 mils
AT23
AU28
AU24
AT29
AT25
AT30
C1125
0.022U_0402_16V7K
+1.25VS_PEGPLL
TV
VSSA_PEG_BG
D TV/CRT
K49
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
C1123
10U_0603_6.3V6M
C1121
LVDS
0.1U_0402_16V4Z
R1468
1_0402_5%
R1458
1
2
0_0805_5%
C1116
VCCA_PEG_BG
10U_0603_6.3V6M
K50
+3VS_PEG_BG
R1459
2
1
0_0603_5%
+3VS
+1.25VM_AXD
C1120
VSSA_LVDS
C1119
VCCA_LVDS
B41
1U_0402_6.3V4Z
A41
0.1U_0402_16V4Z
VCCA_MPLL
+1.8V
C1115
VCCA_HPLL
AM2
22U_0805_6.3VAM
AL2
+1.25VM_MPLL
R1455
0_0603_5%
+1.8V_SM_CK
L77
2
1
MBK2012221YZF_0805
C1230
+1.25VM_HPLL
22U_0805_6.3VAM
VCCA_DPLLB
+1.25VS
+1.25VS_PEGPLL
C1112
VCCA_DPLLA
1U_0603_10V4Z
B49
H49
2
R1457
0_0603_5%
C1111
VSSA_DAC_BG
2.2U_0603_6.3V4Z
B32
4.7U_0603_6.3V6M
VCCA_DAC_BG
0.47U_0603_10V7K
A30
1
C830
0.1U_0402_16V4Z
C1117
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
330U_D2E_2.5VM_R15
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
4.7U_0603_6.3V6M
A33
B33
1
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
10U_0603_6.3V6M
U15H
VCCSYNC
+1.25VS
+V1.25VS_AXF
+1.25VS_DMI
+VCCP
J32
+VCCP
R1469
2
1
10_0402_5%
+3VS_HV
CH751H-40PT_SOD323-2
2
1
0_0402_5%
R1470
+3VS
0904 change
+VCC_DMI
+1.25VS
L94
1
2
100NH_LQW18ANR10J00D_5%_0805
(link CIS)
C1614
10U_0603_6.3V6M
1
C1615
+VCCP
R84
0_0805_5%
10U_0603_6.3V6M
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

CRESTLINE(4/6)-PWR

Date:
Rev
1A
Sheet
1
10
of
57
+VCCP
U15F
VCC AXM
VCC AXM NCTF
CRESTLINE_1p0
VCC SM
+3VL
+3VS
@ Q121
RHU002N06_SOT323
2
MCHGND5
2
G
100K_0402_5%
1 1
2
2
G
@R1703
@
R1703
100K_0402_5%
MCHGND2
CRACK_GPIO28
2
G
100K_0402_5%
@ R1709
RHU002N06_SOT323
@ Q119
CRACK_GPIO28
100K_0402_5%
1
2
2
1
@ R1711
@R1711
AW45 VCCSM_LF1
BC39 VCCSM_LF2
BE39 VCCSM_LF3
BD17 VCCSM_LF4
BD4 VCCSM_LF5
AW8 VCCSM_LF6
AT6 VCCSM_LF7
1
CRESTLINE_1p0
C813 1U_0603_10V4Z
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
C814 1U_0603_10V4Z
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
C1164 0.47U_0402_10V4Z~D
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
+3VS
@ Q123
RHU002N06_SOT323
+1.05VM
C795 0.22U_0603_10V7K
@ Q118
RHU002N06_SOT323
2
2
2
2
2
2
VCC GFX NCTF
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
1
1
1
1
1
1
C1318 0.22U_0603_10V7K
MCHGND4
2
G
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
C1163 0.1U_0402_16V4Z
MCHGND6
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
VCC GFX
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC_13
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
C1162 0.1U_0402_16V4Z
CRACK_GPIO28
MCHGND1 R112
MCHGND2 R132
MCHGND3 R133
MCHGND4 R122
MCHGND5 R113
MCHGND6 R111
A3
B2
C1
BL1
BL51
A51
+3VS
100K_0402_5%
@R1701
@
R1701
C794
POWER
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
04/10 monitor NB crack

+3VS
1
C808
0.01U_0402_16V7K
C810
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
+1.8V
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
R30
POWER
330U_D2E_2.5VM_R15
22U_0805_6.3VAM
C809
C1161
0.1U_0402_16V4Z
C1155
C1160
0.1U_0402_16V4Z
C1159
0.1U_0402_16V4Z
C1158
0.22U_0402_10V4Z
C1157
0.22U_0402_10V4Z
10U_0603_6.3V6M
C1154
10U_0603_6.3V6M
R1475
1
2
0_0603_5%
+1.05VM
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
22U_0805_6.3VAM
VSS NCTF
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS SCB
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC NCTF
C797
0.1U_0402_16V4Z
C798
0.22U_0402_10V4Z
C796
0.22U_0402_10V4Z
C803
22U_0805_6.3VAM
C806
220U_D2_4VM_R15
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC SM LF
+VCCP
D
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC CORE
U15G
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R1702
CRACK_GPIO28
CRACK_GPIO28 <27,37>
Compal Secret Data
S
2006/09/25
Issued Date
2006/09/25
Deciphered Date
3
Title

CRESTLINE((5/6)-PWR/GND

Date:
Rev
1A
Sheet

1
11
of
57
U15I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U15J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
VSS
CRESTLINE_1p0
CRESTLINE_1p0
A
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

CRESTLINE((6/6)-PWR/GND

Date:
Rev
1A
Sheet

1
12
of
57
+1.8V
+1.8V
V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7]
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D14
Layout Note:
Place near JP34
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D9
DDR_A_D15
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
V_DDR_MCH_REF
DDR_A_D6
DDR_A_D0
DDR_A_DM0
DDR_A_D5
DDR_A_D7
<7,14,48>
C362
DDR_A_DQS#0
DDR_A_DQS0
<7,8> DDR_A_MA[0..14]
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z
DDR_A_D4
DDR_A_D1
<8> DDR_A_DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C363
<8> DDR_A_DM[0..7]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
JP34
<8> DDR_A_D[0..63]
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>
DDR_A_D11
DDR_A_D10
+1.8V
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
<7> DDR_CKE0_DIMMA
DDR_A_BS#2
<8> DDR_A_BS2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
<8> DDR_A_BS0
<8> DDR_A_WE#
+0.9V
DDR_A_CAS#
DDR_CS1_DIMMA#
<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#
M_ODT1
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
C227
C234
C241
C252
C268
C274
C281
C279
C272
C257
C250
C239
C229
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<7>
DDR_A_D35
DDR_A_D32
DDR_A_D40
DDR_A_D44
DDR_A_DM5
DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48
+0.9V
DDR_A_MA1
DDR_A_MA3
RP29 56_0404_4P2R_5% RP26 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA7
2
3
3
2 DDR_A_MA6
4
3
Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"
RP22 56_0404_4P2R_5%
4
1 DDR_A_BS#2
3
2 DDR_CKE0_DIMMA
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7
RP32 56_0404_4P2R_5% RP25 56_0404_4P2R_5%

DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_MA12
RP31 56_0404_4P2R_5% RP28 56_0404_4P2R_5%
1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2
DDR_A_CAS#
DDR_A_WE#
RP33 56_0404_4P2R_5% RP30 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA0
2
3
3
2 DDR_A_BS#1
+3VM
RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%

DDR_CS1_DIMMA# 2
3
4
1 M_ODT0
M_ODT1
1
4
3
2 DDR_A_MA13
DDR_A_MA11
ICH_SMBDATA
ICH_SMBCLK
<14,15,26> ICH_SMBDATA
<14,15,26> ICH_SMBCLK
2.2U_0603_6.3V4Z
DDR_A_BS#0
DDR_A_MA10
DDR_A_D59
DDR_A_D58
56_0404_4P2R_5% RP24 56_0404_4P2R_5%

4
1 DDR_CKE1_DIMMA
2
3
2 DDR_A_MA14
C308
2006/09/25
Issued Date
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204
conn@ FOX_ASOA426-M4R-TR
SO-DIMM A
REVERSE
DDR_A_D20
DDR_A_D21
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <7>
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0
<7>
DDR_A_D39
DDR_A_D38
DDR_A_DM4
DDR_A_D34
DDR_A_D33
DDR_A_D45
DDR_A_D43
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Top side
2006/09/25
Deciphered Date
5
PM_EXTTS#0 <7>
DDR_A_DM2
Compal Secret Data
R1903 56_0402_5%
C311
2
0.1U_0402_16V4Z
DDR_A_MA5
DDR_A_MA8
RP27
1
2
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
R453
10K_0402_5%
2
1
C235
C280
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C242
0.1U_0402_16V4Z
C255
C465
0.1U_0402_16V4Z
C491
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C473
2.2U_0805_16V4Z
C498
2.2U_0805_16V4Z
C458
2.2U_0805_16V4Z
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
R455
10K_0402_5%
2
1
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203
DDR_A_D16
DDR_A_D17
Title

DDRII-SODIMM SLOT1

Date:
Rev
1A
Sheet

1
13
of
57
+1.8V
<8> DDR_B_DQS#[0..7]
+1.8V
<8> DDR_B_D[0..63]
V_DDR_MCH_REF
<8> DDR_B_DM[0..7]
+1.8V
DDR_B_D17
DDR_B_D20
C161
C188
0.1U_0402_16V4Z
C219
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C166
0.1U_0402_16V4Z
C164
C159
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C247
2.2U_0805_16V4Z
C265
C236
2.2U_0805_16V4Z
2.2U_0805_16V4Z
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB
<7> DDR_CKE2_DIMMB
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_B_BS#2
<8> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+0.9V
DDR_B_CAS#
DDR_CS3_DIMMB#
<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#
1
<7>
M_ODT3
M_ODT3
DDR_B_D32
DDR_B_D33
2
C177
C163
C218
C173
C199
C210
C183
C220
C213
C197
C186
C179
C176
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
<8> DDR_B_BS0
<8> DDR_B_WE#
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
RP14
1
2
DDR_B_BS#0
DDR_B_MA10
RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5%

DDR_B_MA14
1
4
4
1
DDR_B_MA11
2
3
3
2
DDR_B_MA0
DDR_B_BS#1
RP16 56_0404_4P2R_5% RP12 56_0404_4P2R_5%

DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2
4
3
4
3
RP10 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2
Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58
RP18 56_0404_4P2R_5% RP13 56_0404_4P2R_5%

DDR_B_RAS#
DDR_B_MA7
1
4
4
1
DDR_CS2_DIMMB# 2
DDR_B_MA6
3
3
2
ICH_SMBDATA
ICH_SMBCLK
+3VM
2.2U_0603_6.3V4Z
C301
C312
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D21
DDR_B_D16
2006/09/25
PM_EXTTS#1 <7>
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <7>
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>
M_ODT2
DDR_B_MA13
M_ODT2
<7>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
SO-DIMM B
STANDARD
R257
1
+3VM
10K_0402_5%
A
Bottom side
2006/09/25
Deciphered Date
5
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_D14
DDR_B_D15
FOX_ASOA426-M4R-TR
conn@
DDR_B_DM1
Compal Secret Data
Issued Date
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
R254
56_0404_4P2R_5% RP9
DDR_B_BS#2
4
1
DDR_CKE3_DIMMB 1
DDR_CKE2_DIMMB
2
3
2
R1743
56_0402_5%
56_0404_4P2R_5%
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
DDR_B_D12
DDR_B_D13
10K_0402_5%
RP19 56_0404_4P2R_5% RP15 56_0404_4P2R_5%

DDR_B_MA4
1
4
4
1
DDR_B_MA2
2
3
3
2
RP23
56_0404_4P2R_5% RP21 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT2
3
4
1
M_ODT3
DDR_B_MA13
1
4
3
2
DDR_B_CAS#
DDR_B_WE#
DDR_B_DQS#6
DDR_B_DQS6
0.1U_0402_16V4Z
+0.9V
DDR_B_MA1
DDR_B_MA3
DDR_B_D48
DDR_B_D49
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203
DDR_B_D6
DDR_B_D7
DDR_B_D10
DDR_B_D11
DDR_B_DM0
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
<7,13,48>
C90
DDR_B_D2
DDR_B_D3
Layout Note:
Place near JP10
DDR_B_D5
DDR_B_D4
C89
DDR_B_DQS#0
DDR_B_DQS0
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z
DDR_B_D0
DDR_B_D1
<7,8> DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
2.2U_0805_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<8> DDR_B_DQS[0..7]
V_DDR_MCH_REF
JP10
Title

DDRII-SODIMM SLOT2
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
14
of
57
FSLC
FSLB
FSLA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
200
PCI
MHz
+3VM
1
R1066
2
0_1206_5% 1
33.3
100
166
100
+3VM_CK505
C1165
10U_0603_6.3V6M
C1166
0.1U_0402_16V4Z
C1167
0.1U_0402_16V4Z
C1168
0.1U_0402_16V4Z
C1169
0.1U_0402_16V4Z
C1170
0.1U_0402_16V4Z
Place close to U7
+1.25VM_CK505
CPU Driven
R1107
Stuff
*(Default)
R1135
R1074
No Stuff
R1086
R1068 0_1206_5%
2
+1.25VM 1
R1083
R1098
R1113
R1128
0.1U_0402_16V4Z
1
R1139
C1173
C1172
667MHz
Stuff
R1086
R1139
R1135
No Stuff
R1083
R1107
R1128
R1113
R1098
R1135
R1139
R1083
R1086
R1098
R1074
R1107
R1113
Stuff
800MHz
No Stuff
@
1
R1078
2.2K_0402_5%
FSA 2
1
<5>
1
R1083
0_0402_5%
CPU_BSEL0
R1139
R1135
R1074
2
+VCCP
+1.25VM_CK505
56_0402_5%
1
MCH_CLKSEL0 <7>
R1079
1K_0402_5%
C1174
2
+3VM_CK505
R1128
2
0.1U_0402_16V4Z
R1086
VDD_PCI
VDD48
VDDPLL3
VDDREF
39
55
VDDSRC
VDDCPU
12
20
26
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
36
49
VDDSRC_IO
VDDCPU_IO
<26> CLKSATAREQ#
+VCCP
CLKREQ#_B
<7>
R1098
@ 1K_0402_5%
FSB
1
R1107
0_0402_5%
CPU_BSEL1
R1105
1K_0402_5%
2 R1692
1
R1693
22_0402_5% 2
12_0402_5% 2
12_0402_5% 1
12_0402_5% 1
12_0402_5% 1
2
475_0402_1%
1 R1097
1 R1114
2 R1140
2 R1110
2 R1141
22_0402_5% 1
2 R1117
<5>
<31,36> CLK_DEBUG_PORT
<35> CLK_PCI_SIO
<36> CLK_PCI_TCG
<37> CLK_PCI_EC
<31> CLK_PCI_PCM
MCH_CLKSEL1 <7>
<24> CLK_PCI_ICH
475_0402_1%1
PCI0/CR#_A
PCI_CLK1 3
PCI1/CR#_B
PCI2_TME 4
PCI2/TME
PCI_CLK3 5
6
PCI4/27_Select
ITP_EN
PCIF5/ITP_EN
CLK_XTAL_IN
CLK_XTAL_OUT
60
+VCCP
R1077
33_0402_5%
2
C373
C374
C375
C376
C378
C379
C380
59
48
SCLK
SDATA
64
63
PCI_STOP#
CPU_STOP#
38
37
CPU0
CPU0#
54
53
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CPU1_F
CPU1#_F
51
50
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
SRC8/ITP
SRC8#/ITP#
47
46
SRC10#
SRC10
35
34
H_STP_PCI# <26>
H_STP_CPU# <26>
SRC11/CR#_H
SRC11#/CR#_G
33
32
SRC9
SRC9#
30
31
@ R1033 1
R_CPU_XDP R1447 1
R_CPU_XDP#
1
R1448 1
@R1143
@
R1143
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
2
2
X2
CLK_CPU_XDP <4>
CLK_PCIE_Rob <31>
CLK_PCIE_Rob# <31>
CLK_CPU_XDP# <4>
CLK_PCIE_DOCK# <39>
CLK_PCIE_DOCK <39>
R1695
CLKREQ#_H
R_CLKREQ#_G
1
2
2
R1694
2
+3VS
R149 10K_0402_5%
475_0402_1%
CPPE# <39>
475_0402_1%
CLKREQ#_G <31>
R150 10K_0402_5%
1
2
+3VS
1
1
CLK_PCIE_MCARD <31>
CLK_PCIE_MCARD# <31>
R_CLKREQ#_F
R_CLKREQ#_E
R1900
2
2
@ R1901
475_0402_1%
CLKREQ#_F
1
CLKREQ#_E
1
475_0402_1%
2
+3VS
R1899 10K_0402_5%
SRC7/CR#_F
SRC7#/CR#_E
44
43
SRC6
SRC6#
41
40
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>
SRC4
SRC4#
27
28
CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
@ R1902 10K_0402_5%
1
2
+3VS
CLKREQ#_F
CLKREQ#_E <19,31>
FSA
10
USB_48MHZ/FSLA
FSB
57
FSLB/TEST MODE
FSC
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
SRC3/CR#_C
SRC3#/CR#_D
24
25
CLK_PCIE_ICH <26>
CLK_PCIE_ICH# <26>
42
GNDSRC
SRC2/SATA
SRC2#/SATA#
21
22
CLK_PCIE_SATA <25>
CLK_PCIE_SATA# <25>
1= Enable SRC0 & 27MHz
GNDPCI
For PCI2_TME, 0 = Overclocking of CPU and SRC Allowed
11
GND48
SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS
17
18
15
GND
19
GND
52
GNDCPU
SRC0/DOT96
SRC0/DOT96#
13
14
23
GNDSRC
29
GNDSRC
CK_PWRGD/PD#
56
58
GNDREF
<26> CLK_48M_ICH
CLK_48M_ICH
5P_0402_50V8C
CLK_14M_ICH
4.7P_0402_50V8C
CLK_PCI_ICH
4.7P_0402_50V8C
CLK_14M_KBC
4.7P_0402_50V8C
CLK_14M_SIO
4.7P_0402_50V8C
CLK_PCI_EC
4.7P_0402_50V8C
CLK_PCI_TCG
4.7P_0402_50V8C
CLK_PCI_PCM
4.7P_0402_50V8C
CLK_PCI_SIO
4.7P_0402_50V8C
CLK_DEBUG_PORT
5P_0402_50V8C
ICH_SMBCLK <13,14,26>
ICH_SMBDATA <13,14,26>
X1
0_0402_5%
C372
NC
PCI3
27_SEL
@R1113
@
R1113
0.1U_0402_16V4Z
1
C1355
C1354
2
0.1U_0402_16V4Z
@ 1K_0402_5%
U7
2
9
16
61
1111 Add CLRP4,CLRP5 for 667/800 FSB select

SHORT CLRP5, NO SHORT CLRP4 -- FSB 800
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667
R1074
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
C1353
C357
0.1U_0402_16V4Z
33.3
FSB Frequency Selet:
C353
C1171
R1128
R1131
1K_0402_5%
<26> CLK_14M_ICH
MCH_CLKSEL2 <7> <35> CLK_14M_SIO
<37> CLK_14M_KBC
2
2
2
R1087
R1088
R1089
+1.25VM_CK505
1
R1135
0_0402_5%
CPU_BSEL2
33_0402_1% 1
33_0402_1% 1
33_0402_1% 1
@R1139
@
R1139
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
0_0402_5%
For 27_SEL, 0 = Enable DOT96 & SRC1,
<5>
@ 1K_0402_5%
1
FSC
R1130
10K_0402_5%
2
1
1 = Overclocking of CPU and SRC NOT allowed

CLK_XTAL_OUT
+3VS
+3VS
+3VS
R1245
10K_0402_5%
14.31818MHZ_16P
@
A
CLK_XTAL_IN
R1690
10K_0402_5%
R1108
10K_0402_5%
R1247
10K_0402_5%
0_0402_5%
0_0402_5%
2
2
27M_CLK <19>
27M_SSC <19>
11/20 For EMI request to install R1687
CK_PWRGD <26>
ICS9LPRS355AKLFT_TSSOP64
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
2
@ R1691
10K_0402_5%
R1246
10K_0402_5%
@
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
Routing the trace at least 10mil

5
1
1
PCI2_TME
27_SEL
R1686
R1687
Title

Clock generator
C505
18P_0402_50V8J
1
C509
18P_0402_50V8J
ITP_EN
2
Y6
R_27MHz
R_27MSSC
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
15
of
57
+CRTVDD
R162
R183
2.2K_0402_5%
2.2K_0402_5%
D_DDCDATA
150_0402_1%
150_0402_1%
2
0315 add
@ R185
@R185
150_0402_1%
1
@
1
@
2
2
2
C333 C355
D20
@ DAN217_SC59
D19
DAN217_SC59
1
3
1
3
JP1
5.6P_0402_50V8D
@ R187
@R187
@ R184
5.6P_0402_50V8D
R549
0_0603_5%
1
2
0_0603_5%
1
2
0_0603_5%
1
2
1
R548
COMP
DDC1_CLK <19>
RHU002N06_SOT323
DAN217_SC59 DAN217_SC59 DAN217_SC59 +3VS

@D3
@
D3
@ D5
@D1
@
D1
R547
<19,39>
Q52
Place close to JP1
TV-Out Connector
LUMA
2
G
D_DDCCLK
<39> D_DDCCLK
layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector
CRMA
DDC1_DATA <19>
RHU002N06_SOT323
Place close to docking connector
<19,39>
Place close to docking connector
<39> D_DDCDATA
Q46
1
2
2.2K_0402_5%
R1922
+CRTVDD
D_VSYNC <39>
<19,39>
1
2
R1921 2.2K_0402_5%
<39>
D_VSYNC
D_HSYNC
R546
2
0_0603_5%
2
G
+3VS
+CRTVDD
SUYIN_070912FR015S207CR
conn@
16
17
D_HSYNC
18P_0402_50V8J
C322
U54
18P_0402_50V8J
C323
SN74AHCT1G125GW_SOT353-5
4VSYNC_G_A
Place close to JP2
0315 add
R545
1
2
0_0603_5%
5
1
2
M_VSYNC
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
U33
SN74AHCT1G125GW_SOT353-5
HSYNC_G_A
4
P
OE#
5
1
P
OE#
C318
18P_0402_50V8J
BLUE_R
18P_0402_50V8J
GREEN_R
R544 BK1608LL560-T_0603
1
2
C316
RED_R
R543 BK1608LL560-T_0603
1
2
18P_0402_50V8J
C317
R542 BK1608LL560-T_0603
1
2
C310
39P_0402_50V8C
3
<19>
C314
39P_0402_50V8C
C313
39P_0402_50V8C
+5VS
2007,0125 change
M_HSYNC
2
JP2
150_0402_1%
@R173
@
R173
<19>
BLUE_R
GREEN_R
RED_R
1
2
R171
0.1U_0402_16V4Z
2007,0125 change
150_0402_1%
1
1
@
R174
150_0402_1%
@
W=40mils
CH491D_SC59
C315
0315 add
0.1U_0402_16V4Z
C359
L_RED
+5VS
D18
2
1.1A_6VDC_FUSE
<39> L_GREEN
+CRTVDD
F1
1
L_BLUE
<39>
+RCRT_VCC
CRT Connector
<39>
+5VS
D4
DAN217_SC59
TV_LUMA
TV_CRMA
TV_COMP
1
2
3
4
5
6
7
conn@
SUYIN_33007SR-07T1-C
5.6P_0402_50V8D
C354
Close to JP1
layout note: TV-out signals should be routed to JP30 then to JP1
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
A
Title

CRT & TVout Connector
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

E
16
of
57
B+_LCD
0802 (R1A) change for preventing 1206 Cap crack
C586
1
LCD POWER CIRCUIT
LCDVDD
+3VALW
Q8
AO3413_SOT23
LCDVDD
4.7U_0805_25V6K
1
100_0402_1%
1
KC FBM-L11-201209-221LMA30T_1210
B+
D
Q5
+3VS
2
G
RHU002N06_SOT323
47K_0402_5%
C29
0.1U_0402_16V7K
ALS_EN <26>
0.1U_0402_16V4Z
<19> VGA_ENAVDD
DDC2_CLK <19>
DDC2_DATA <19>
E_STAR <41>
2
Q6
DTC124EK_SC59
+5VS_INV
C31
LCDVDD
C20
@ 4.7U_0805_10V4Z
4.7U_0805_10V4Z
R502
100K_0402_1%
TXCLK_U+ <19>
TXCLK_U- <19>
TXOUT_U2+ <19>
TXOUT_U2- <19>
TXOUT_U1+ <19>
TXOUT_U1- <19>
TXOUT_U0+ <19>
TXOUT_U0- <19>
Q53
DTA114YKA_SC59
TXOUT_L0- <19>
TXOUT_L0+ <19>
+3V_U43
R1729
@ 0_0402_5%
1
2
TXCLK_L- <19>
TXCLK_L+ <19>
LID_SW#
<26,38> LID_SW#
1
2
<19> OPT_BL_ENA
O
B
Q36
BSS138_SOT23
2
G
R360
7
conn@
+5VS_INV
10K
U43A
SN74LVC08APW_TSSOP14
ACES_88316-4000
+3VS
+5VS
0_0402_5%
2
TXOUT_L2- <19>
TXOUT_L2+ <19>
R1728 1
47K
+3VALW
TXOUT_L1- <19>
TXOUT_L1+ <19>
14
1
100K_0402_5%
<19> BLON_PWM
R102
R501
100K_0402_1%
BKLT_PWM
E_STAR
1M_0402_5%
C28
1
2
R474
L62
R12
2
G
4.7U_0805_25V6K
1 2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R19
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
68P_0402_50V8J
41
42
43
44
45
46
41
42
43
44
45
46
1
C587
1
C1629
JP35
LVDS CONN
0_0402_5%
BKLT_PWM
Support 3V inverter
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

LCD CONN.
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
17
of
57
U80A
PART 1 OF 6
PEG_M_TXP0
PEG_M_TXN0
AC30
AC31
PCIE_RX0P
PCIE_RX0N
PEG_M_TXP1
PEG_M_TXN1
AC29
AB29
PCIE_RX1P
PCIE_RX1N
PEG_M_TXP2
PEG_M_TXN2
AB31
AB30
PCIE_RX2P
PCIE_RX2N
PEG_M_TXP3
PEG_M_TXN3
AA31
AA30
PCIE_RX3P
PCIE_RX3N
PEG_M_TXP4
PEG_M_TXN4
W30
W31
PCIE_RX4P
PCIE_RX4N
PEG_M_TXP5
PEG_M_TXN5
W29
V29
PCIE_RX5P
PCIE_RX5N
PEG_M_TXP6
PEG_M_TXN6
V31
V30
PEG_M_TXP7
PEG_M_TXN7
U31
U30
PCIE_RX7P
PCIE_RX7N
PEG_M_TXP8
PEG_M_TXN8
P30
P31
PCIE_RX8P
PCIE_RX8N
PEG_M_TXP9
PEG_M_TXN9
P29
N29
PEG_M_TXP10
PEG_M_TXN10
P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E
PCIE_TX0P
PCIE_TX0N
AA28
AA27
PEG_M_RXP0
PEG_M_RXN0
C1380
C1381
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP0
PEG_RXN0
PCIE_TX1P
PCIE_TX1N
AA25
AA24
PEG_M_RXP1
PEG_M_RXN1
C1382
C1383
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP1
PEG_RXN1
PCIE_TX2P
PCIE_TX2N
Y28
Y27
PEG_M_RXP2
PEG_M_RXN2
C1384
C1385
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP2
PEG_RXN2
PCIE_TX3P
PCIE_TX3N
Y25
Y24
PEG_M_RXP3
PEG_M_RXN3
C1386
C1387
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP3
PEG_RXN3
PCIE_TX4P
PCIE_TX4N
V28
V27
PEG_M_RXP4
PEG_M_RXN4
C1388
C1389
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP4
PEG_RXN4
PCIE_TX5P
PCIE_TX5N
V25
V24
PEG_M_RXP5
PEG_M_RXN5
C1390
C1391
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP5
PEG_RXN5
PCIE_TX6P
PCIE_TX6N
T28
T27
PEG_M_RXP6
PEG_M_RXN6
C1392
C1393
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP6
PEG_RXN6
PCIE_TX7P
PCIE_TX7N
T25
T24
PEG_M_RXP7
PEG_M_RXN7
C1394
C1395
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP7
PEG_RXN7
PCIE_TX8P
PCIE_TX8N
P28
P27
PEG_M_RXP8
PEG_M_RXN8
C1396
C1397
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP8
PEG_RXN8
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
P25
P24
PEG_M_RXP9
PEG_M_RXN9
C1398
C1399
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP9
PEG_RXN9
N31
N30
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
M28
M27
PEG_M_RXP10
PEG_M_RXN10
C1400
C1401
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP10
PEG_RXN10
PEG_M_TXP11
PEG_M_TXN11
M31
M30
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
M25
M24
PEG_M_RXP11
PEG_M_RXN11
C1402
C1403
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP11
PEG_RXN11
PEG_M_TXP12
PEG_M_TXN12
K30
K31
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
L28
L27
PEG_M_RXP12
PEG_M_RXN12
C1404
C1405
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP12
PEG_RXN12
PEG_M_TXP13
PEG_M_TXN13
K29
J29
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
L25
L24
PEG_M_RXP13
PEG_M_RXN13
C1406
C1407
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP13
PEG_RXN13
PEG_M_TXP14
PEG_M_TXN14
J31
J30
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
J28
J27
PEG_M_RXP14
PEG_M_RXN14
C1408
C1409
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP14
PEG_RXN14
PEG_M_TXP15
PEG_M_TXN15
H31
H30
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
G28
G27
PEG_M_RXP15
PEG_M_RXN15
C1410
C1411
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_RXP15
PEG_RXN15
PCIE_RX6P
PCIE_RX6N
<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
PEG_RXP[0..15]
<9> PEG_RXP[0..15]
PEG_RXN[0..15]
<9> PEG_RXN[0..15]
PEG_M_TXP[0..15]
<9> PEG_M_TXP[0..15]
PEG_M_TXN[0..15]
<9> PEG_M_TXN[0..15]
Clock
CLK_PCIE_VGA
CLK_PCIE_VGA#
<24>
VGA_RST#
AD29
AD30
PCIE_REFCLKP
PCIE_REFCLKN
AC28
AC27
RSVD
RSVD
AG25
PERSTB
Calibration
R1904 1
PCIE_CALRN
AF25
PCIE_CALRP
AE25
R1887 1
PCIE_CALI
AE23
R1737 1
2K_0402_1%
PCIE_1.2V
562_0402_1%
1.47K_0402_1%
M62: R1887-->562 ohm 1%

M72: R1887-->1.27k ohm 1%
216PTAKA13FG M62-S_BGA632
M62: R1737-->1.47k ohm 1%

M72: R1887-->10k ohm 1%
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

M62-S PCIE interface
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
18
of
57
20070719 change for DVI high resolution issue
U80B
U80F
PART 6 OF 6
BLM18PG121SN1D_0603
R1891
2
1
<23>
<23>
<23>
<23>
DPLL_VDDC
1
1
C1435
2
2
1U_0402_6.3V4Z
T88
T89
T90
T91
T92
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
PAD
PAD
PAD
PAD
PAD
T113PAD
<23>
R1760
499_0402_1%
<51>
<15>
VGA_VREF
GPIO11
T114PAD
GPIO13
<23>
POW_SW
27M_SSC
@ R1787 10K_0402_5%
2
1
C2
0.1U_0402_16V4Z
<15,31> CLKREQ#_E
M62S: R1769-->499 ohm 1%

M72S: R1769-->249 ohm 1%
PAD
T97
T115PAD
+3VS
R1791
1K_0402_5%
2
Place those components

as close as U80 within 500
mils.
T98 PAD
T99 PAD
T100PAD
T101PAD
T102PAD
T103PAD
VGA_VREF
AH31
AH30
MPVDD
XIN
XOUT
1
18P_0402_50V8J
C1565 @
18P_0402_50V8J
C1566 @
R1450
82_0402_5%
27M_CLK
R1449 Close to C1565
XIN
XOUT
DPLL_VDDC
DPLL_VDDC
AD11
B
BB
AL26 VGA_BLU
AK26
HSYNC
VSYNC
AK29
AK30
RSET
AJ28
AVDD
AL29
AVSSQ
AH28
VDD1DI
AJ27
VSS1DI
AJ26
AL17
AK17
G2
G2B
AL15
AK15
C1418
1U_0402_6.3V4Z
VGA_CRMA
AJ15
VGA_LUMA
VGA_COMP
AJ14
AE16
AF16
A2VDD
AH14
A2VDDQ
AH16
A2VSSQ
AG16
VDD2DI
AF18
VSS2DI
AE18
R2SET
AG14
DDC3DATA
DDC3CLK
Thermal
Test
AJ17
COMP
AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22
TXCLK_L+ <17>
TXCLK_L- <17>
TXOUT_L0+ <17>
TXOUT_L0- <17>
TXOUT_L1+ <17>
TXOUT_L1- <17>
TXOUT_L2+ <17>
TXOUT_L2- <17>
0906 change
2
2
100N_0402_50V7M
Place Closed to U80
L28
VGA_GRN
C1421
1U_0402_6.3V4Z
VGA_BLU
L31
1
2
HLC0603CSCCR11JT_0603
L34
1
2
L26
1
2
C_RED_L
1
2
HLC0603CSCC39NJT_0603
L35
C_GRN_L
1
2
L27
C_BLU_L
1
2
R1763
1
C237
C193
22P_0402_50V8J
2
C232
@ C195
22P_0402_50V8J
22P_0402_50V8J
RED
<39>
GREEN
<39>
BLUE
<39>
@C245
@
C245
2 10P_0402_50V8J
10P_0402_50V8J
@ C244
10P_0402_50V8J
B
+A2VDD
TV-Out Termination/EMI Filter
C1422
1U_0402_6.3V4Z
L38 1
2
CHB1608U301_0603
COMP
VGA_LUMA
L37 1
2
CHB1608U301_0603
LUMA
<16,39>
L17 1
2
CHB1608U301_0603
CRMA
<16,39>
VDDDI_25
1
1
2
R1793 715_0402_1%
1U_0402_6.3V4Z
C1426
AA8
VGA_CRMA
DVI_DETECT <39>
AJ29
AH29
R1796
2
1
AC5
4.7K_0402_5%
AC4
R1799
2
1
4.7K_0402_5%
AF4
AH4
TS_FDO
DPLUS
DMINUS
AE5
AE4
TESTEN
AH26 2
R1800
AD12
DDC1_DATA <16>
DDC1_CLK <16>
+3VS
DVI_DAT <39>
DVI_CLK <39>
+3VS
ICH_SM_DA <4,23,26,31>
ICH_SM_CLK <4,23,26,31>
VGA_THERMDA
VGA_THERMDC
1
DVI
thermal
Place close to U80
VGA_COMP
C251
2
2
C238
C7
5.6P_0402_50V8D
2
2
C243
<16,39>
C253
C8
5.6P_0402_50V8D
0314 change design
R1779
VGA_THERMDA <23>
VGA_THERMDC <23>
1K_0402_5%
Compal Secret Data
Issued Date
M62S: R1450-->330 ohm 1% > ~ 1.1V
2006/09/25
2006/09/25
Deciphered Date
Close to U80 AJ31 and AJ30 pins

5
TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
Note: TV-out should route to JP30 first then to the JP1 & JP2
on system side.
AE14
PLLTEST
LPVDD
LPVSS
TXCLK_U+ <17>
TXCLK_U- <17>
TXOUT_U0+ <17>
TXOUT_U0- <17>
TXOUT_U1+ <17>
TXOUT_U1- <17>
TXOUT_U2+ <17>
TXOUT_U2- <17>
C1417
CRT Termination/EMI Filter
VDDDI_25
DDC2DATA
DDC2CLK
NC_10
VGA_RED
AL14
AK14
Interface
PLL &
XTAL
+AVDD
2
470_0402_1%
B2
B2B
V2SYNC
H2SYNC
TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
Note: CRT / TV-out should route to JP30 first then to the

JP1 & JP2 on system side.
M_HSYNC <16>
M_VSYNC <16>
1
R1775
AG18
AH18
VGA_ENAVDD <17>
AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23
R2
R2B
HPD1
MPVDD
MPVSS
XTALIN
XTALOUT
AL27 VGA_GRN
AK27
DAC2 (TV/CRT2) Y
PCIE_PVDD
PCIE_PVSS
AJ31
AJ30
G
GB
DDC1DATA
Monitor DDC1CLK
DPLL_PVDD
DPLL_PVSS
AE12
AL28 VGA_RED
AK28
GENERICA
GENERICB
GENERICC
VREFG
<15>
110_0402_1%
1
2
R1449
A9
B9
R
RB
75_0402_1%
AH12
AG12
AG11
75_0402_1%
PCIE_PVDD
Y8
Y7
V8
AC11
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
General
GPIO_12
Purpose
GPIO_13
I/O
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_TRST
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO
AK8
AL8
NC_9
75_0402_1%
+DPLL_PVDD
DAC / CRT
NC_7
NC_8
75_0402_1%
<23>
<23>
GPIO4
GPIO5
GPIO6
Y4
V3
V4
V5
U3
U2
T4
T5
T7
T8
R1
R2
R3
P1
P3
N1
N2
P4
P7
P8
P5
V7
N3
Y5
M4
M5
M7
M8
L8
1U_0402_6.3V4Z
75_0402_1%
GPIO0
GPIO1
+LPVDD
+LPVDD
75_0402_1%
<23>
<23>
+3VS
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
C1436
1U_0402_6.3V4Z
<17> OPT_BL_ENA
R1769
499_0402_1%
DVPCLK
Y1
Y2
Y3
AA2
AA3
AB1
AB2
AB3
AC1
AC3
AD1
AD2
AD3
AF3
AG3
AH3
AG1
AH2
AH1
AJ3
AJ1
AJ2
AK2
AK3
AE11
AF11
LVSSR_1
LVSSR_2
LVSSR_3
LVSSR_4
LVSSR_5
LVSSR_6
LVSSR_7
LVSSR_8
LVSSR_9
LVSSR_10
LVSSR_11
BLON_PWM <17>
AC6
C1552
1U_0402_6.3V4Z
C1416
NC_5
NC_6
AF23
AF21
AL18
AJ22
AJ25
AK18
AK23
AK25
AJ21
AL23
AL25
AA7
DIGON
5.6P_0402_50V8D
2
2
0.1U_0402_16V4Z
W1
LVDDC_1
LVDDC_2
10K_0402_5%
2
R1905
Control VARY_BL
5.6P_0402_50V8D
C6
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
LVDDR_1
LVDDR_2
AJ18
AH20
5.6P_0402_50V8D
C9
V2
V1
W3
Closed to U80
2
5.6P_0402_50V8D
DVPCNTL_MVP_0
DVPCNTL_MVP_1
AJ8
AH9
AH11
AJ11
AK12
AL12
2
C1414
0.1U_0402_16V4Z
AK4
AL3
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
TXVSSR_6
C1415
+TXVDDR
C1428
1U_0402_6.3V4Z
PCIE_1.2V
10U_0603_6.3V6M
PCIE_PVDD
1
SDA
SCL
AJ12
AJ13 +TXVDDR
AK13
AL13
R1765
R1797
AA4
AA5
M
U
L
T
I
M
E
D
I
A
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
+TPVDD
DVALID
&
DVI_TX2- <39>
DVI_TX2+ <39>
1U_0402_6.3V4Z
1
1
AL7
AK7
BLM18PG121SN1D_0603
PCIE_1.2V
AD9
2
2.2K_0402_5%
BLM18PG121SN1D_0603
L87
0.1U_0402_16V4Z +DPLL_PVDD
2
1
+2.5VS
170mA, 20mils 1
1
1
C1427
1U_0402_6.3V4Z
C1585
C1584
2
2
2
10U_0603_6.3V6M
PSYNC
R1746
AF20
AG20
DVI_TX1- <39>
DVI_TX1+ <39>
R1780
1
R1755
VPCLK0
VIPCLK
AL5
R1745
R1764
+3VS
Close to U80
AJ4
AJ5
TPVDD
TPVSS
100_0402_1%
R1752 2.2K_0402_5%
1
2
VPHCTL
AL11
AK11
C1412
1U_0402_6.3V4Z
DVI_TX0- <39>
DVI_TX0+ <39>
DDC2_DATA
DDC2_CLK
AK5
TX2M
TX2P
100_0402_1%
R1742
+LVDDR
+LVDDR
<17>
<17>
VHAD_0
VHAD_1
AL10
AK10
DVI_CLK- <39>
DVI_CLK+ <39>
AL6
AK6
2
0.1U_0402_16V4Z
TX1M
TX1P
R1740
C1437
C1450
2
2
10U_0603_4V6M
V
I
D
E
O
100_0402_1%
C10
AJ9
AJ10
TX0M
TX0P
100_0402_1%
MPVDD
1
AK9
AL9
R1778
1U_0402_6.3V4Z
Integrated TXCM
TXCP
TMDS
VIP / I2C
BLM18PG121SN1D_0603
2
1
L93
VGA_VCORE
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7
VIP Host/External TMDS
AH7
AG9
AF9
AJ7
AG7
AF7
AH6
AG6
Close to U80
LVDS channel
PART 2 OF 6
Title
Size

M62-S CRT/LVDS/TV-OUT
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
19
of
57
U80C
VDD_MEM18
R1801
40.2_0402_1%
B14
A14
B13
E14
B17
A17
C15
G16
E16
C14
A12
B12
B15
C12
D14
G14
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
D30
G25
C26
C21
C5
D6
D2
K3
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
QS_0
QS_1
QS_2
QS_3
QS_4
QS_5
QS_6
QS_7
C30
D23
B26
B21
B6
E7
E2
J2
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
QS_7B
C31
E23
A26
A21
A6
D7
E1
J1
WDQS0
WDQS1
WDQS2
WDQS3
WDQS4
WDQS5
WDQS6
WDQS7
ODT0
ODT1
E20
C11
ODT0
ODT1
CLK0
CLK1
A18
A11
CLKA0
CLKA1
CLK0B
CLK1B
B18
B11
CLKA0#
CLKA1#
RAS0B
RAS1B
G20
D12
RASA0#
RASA1#
CAS0B
CAS1B
D20
E12
CASA0#
CASA1#
CS0B_0
CS0B_1
E18
G18
CSA0_0#
CS1B_0
CS1B_1
G11
E11
CSA1_0#
CKE0
CKE1
D18
G12
CKEA0
CKEA1
WE0b
WE1b
D16
C10
WEA0#
WEA1#
MVREFD
MVREFS
0.1U_0402_16V4Z
L5
L7
J7
R1803
TEST_MCLK
TEST_YCLK
MEMTEST
DRAM_RST
DQMB[3..0] <22>
DQMB[7..4] <22>
RDQS[3..0] <22>
RDQS[7..4] <22>
WDQS[3..0] <22>
WDQS[7..4] <22>
ODT0
ODT1
J5
<22>
<22>
CLKA0#
CLKA1#
<22>
<22>
RASA0#
RASA1#
<22>
<22>
CASA0#
CASA1#
<22>
<22>
CSA0_0#
<22>
CSA1_0#
<22>
CKEA0
CKEA1
<22>
<22>
WEA0#
WEA1#
<22>
<22>
DRAM_RST# <22>
0904 Add
R1804
R1805
4.7K_0402_5%
CLKA0
CLKA1
4.7K_0402_5%
4.7K_0402_5%
<22>
BA0
BA1
BA2
VDD_MEM18
BA[2..0]
MAB[11..0] <22>
R1802
100_0402_1%
1 C1429
F30
F31
MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8
MA_9
MA_10
MA_11
MA_A12
MA_BA0
MA_BA1
MA_BA2
R1807
243_0402_1%
R1806
40.2_0402_1%
VDD_MEM18_REFD
VDD_MEM18_REFS
DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63
MEMORY INTERFACE
A
MDB[31..0]
<22> MDB[31..0]
E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19
C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5
F5
G4
F4
B3
B2
C2
C1
E3
F3
F2
F1
G2
G1
H3
H2
K2
L3
L2
L1
read strobe
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
write strobe
Part 3 of 6
MDB[63..32]
<22> MDB[63..32]
R1808
100_0402_1%
C1430
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
2006/09/25
2006/09/25
Deciphered Date
5
Title

M62-S MEM
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
20
of
57
U80E
U80D
Part 5 of 6
PART 4 OF 6
C1433
2
10U_0603_6.3V6M
C1438
1U_0402_6.3V4Z
1
C1439
C1440
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1U_0402_6.3V4Z
1
C1446
C1447
C1448
2
1U_0402_6.3V4Z
1
R1809
C12
10U_0603_6.3V6M
110mA
C1456
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1U_0402_6.3V4Z
1
C1463
C1464
C1465
1U_0402_6.3V4Z
PJP17
2
10U_0603_6.3V6M
PAD-OPEN 2x2m
PJP18
2
VDD_MEM18
1U_0402_6.3V4Z
1
C1476
J11
J20
J21
L9
VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4
AA9
Y9
V9
T9
VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8
1
C1477
1
C1478
VDD_MEM_CLK0
VDD_MEM_CLK1
C1480
0.1U_0402_16V4Z
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
AF1
AF2
VDDR4_1
VDDR4_2
AE1
AE2
VDDR5_1
VDDR5_2
M2
M3
L4
AE7
NC_1
NC_2
NC_3
NC_4
A10
A19
VDDRH_1
VDDRH_2
B10
B19
VSSRH_1
VSSRH_2
V11
U11
BBN_1
BBN_2
150mA
C1462
10U_0603_6.3V6M
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
AC18
AC16
AC14
AC12
0906 add 10uF

M62_VDDR
C1449
1U_0402_6.3V4Z
VDD_CT
2
0_0603_5%
C1441
1U_0402_6.3V4Z
+2.5VS
C1434
10U_0603_6.3V6M
1U_0402_6.3V4Z
1
C1432
A15
A22
A28
A4
A8
B8
C9
D1
H1
H11
H12
H14
H16
H18
H20
H21
B31
M1
PCI-Express
C1431
1.1A
P
O
W
E
R
Q130
0904 change power rail
R11
P11
+3VS
R1813
100K_0402_5%
BBP_1
BBP_2
PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11
PCIE_VDDC_12
AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23
1.54A
L80
1U_0402_6.3V4Z
1
1
C1442
PCIE_VDDC
1
1
C1443
2
2
10U_0603_6.3V6M
C1444
2
1U_0402_6.3V4Z
1
0_0805_5%
PCIE_1.2V
C1445
0.1U_0402_16V4Z
VGA_VCORE
PAD-OPEN 4x4m
1.5A
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9
VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
J12
J14
J16
J18
VGA_VCORE
1
1U_0402_6.3V4Z
1
C1451
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
VDDCI
1U_0402_6.3V4Z
1
C1481
C1473
C1474
2
1U_0402_6.3V4Z
C1482
1U_0402_6.3V4Z
1
C1483
2
2
0.1U_0402_16V4Z
C1469
2
1U_0402_6.3V4Z
1
C1472
1U_0402_6.3V4Z
1
2
1U_0402_6.3V4Z
C1468
1U_0402_6.3V4Z
1
2
10U_0603_6.3V6M
C1460
2
1U_0402_6.3V4Z
C1471
1U_0402_6.3V4Z
1
C1467
VDD_CORE
C1459
1U_0402_6.3V4Z
1
C1454
2
1U_0402_6.3V4Z
C1458
C1466
C1453
1U_0402_6.3V4Z
1
C1457
1U_0402_6.3V4Z 1
1
C1452
2
1
1
L81
CHB1608U301_0603
C1484
2
10U_0603_6.3V6M
PLACE ALL CAPS ON THIS PAGE CLOSE TO ASIC
2
G
SI2301BDS_SOT23
AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31
PJP19
@PAD-OPEN 2x2m
1U_0402_6.3V4Z
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
Core
10U_0603_6.3V6M
1
I/O Internal
10U_0603_6.3V6M
1
Back Bias
B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9
Memory
I/O
Clock
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
PCI-Express GND
A13
A2
C18
A24
A30
AA1
AA11
AA14
AA17
AA20
AA6
AC2
AC7
AE3
AL4
AD14
AF12
AF14
AD16
AD18
AE6
AG2
AE9
AH25
AK1
AK31
AJ6
AL2
AL30
B1
C13
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
VDD_MEM18
Memory I/O
AA26
AA29
AC26
AD31
AE29
AE30
AE31
F28
G26
G29
G30
G31
H29
J25
J26
L26
L29
L30
L31
M26
M29
P26
R29
R30
R31
T26
U29
V26
Y26
Y29
Y30
Y31
CORE GND
B
@ R1897
0_0402_5%
2
1
<26,31,37,40,41,49,50> PWR_GD
2
G
20K_0402_5%
2
1
VDD_MEM18
Q129
RHU002N06_SOT323
R1898
C1605
0.1U_0402_16V4Z 1
VDD_MEM18
VDD_MEM_CLK0
1
R1879
0_0603_5%
2
1
C1553
1.1A
C1555
2
1U_0402_6.3V4Z
10U_0603_6.3V6M
VDD_MEM_CLK1
0_0603_5%
1
2
R1880
C1557
1.1A
C1558
2
1U_0402_6.3V4Z
2
10U_0603_6.3V6M
Compal Secret Data
Issued Date
2006/09/25
2006/09/25
Deciphered Date
5
Title

M62-S POWER
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
21
of
57
DDR3 VRAM: 8Mx32/16Mx32
FBGA_136P 2 pcs
1
VDD_MEM18
R1816
VREFA
H1
H12
<20>
<20>
<20>
<20>
BA2
CSA0_0#
CKEA0
CASA0#
<20>
WEA0#
<20>
<20>
CLKA0
CLKA0#
VREF
VREF
J2
NC
BA2
CSA0_0#
CKEA0
CASA0#
H3
F4
H9
F9
RAS#
CAS#
WE#
CS#
WEA0#
H4
CKE
CLKA0
CLKA0#
J11
J10
CK
CK#
BA1
G4
BA0
G9
RASA0#
H10
243_0402_1%
R1881 1
2 ZQ01 A4
A9
1
2
VDD_MEM18
R13 1K_0402_5% J3
U4
U9
<20> DRAM_RST#
BA1
BA0
RASA0#
RDQS3
RDQS1
RDQS2
RDQS0
WDQS3
WDQS1
WDQS2
WDQS0
<20> RDQS[3..0]
D3
D10
P10
P3
D2
D11
P11
P2
BA0
BA1
BA2
ZQ
MF
RFU
SEN
RES
0904 Add
RDQS0
RDQS1
RDQS2
RDQS3
WDQS0
WDQS1
WDQS2
WDQS3
<20> WDQS[3..0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
MDB[15..8] <20>
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
<20> DQMB[7..4]
DQMB6
DQMB4
DQMB5
DQMB7
MDB[23..16] <20>
MDB[7..0]
E3
E10
N10
N3
DM0
DM1
DM2
DM3
<20>
H1
H12
VREFB
J2
VDD_MEM18
0904 Add
VREF
VREF
NC
<20>
<20>
<20>
<20>
RASA1#
CASA1#
WEA1#
CSA1_0#
RASA1# H3
CASA1# F4
WEA1# H9
CSA1_0#
F9
RAS#
CAS#
WE#
CS#
<20>
CKEA1
CKEA1 H4
CKE
<20>
<20>
<20>
CLKA1
CLKA1#
BA[2..0]
CLKA1 J11
CLKA1# J10
CK
CK#
BA0 G4
BA1 G9
BA2 H10
BA0
BA1
BA2
A4
A9
J3
U4
U9
ZQ
MF
RFU
SEN
RES
R1830
1
ZQ02
243_0402_1%
<20> DRAM_RST#
<20> RDQS[7..4]
RDQS6
RDQS4
RDQS5
RDQS7
WDQS6
WDQS4
WDQS5
WDQS7
D3
D10
P10
P3
D2
D11
P11
P2
RDQS0
RDQS1
RDQS2
RDQS3
WDQS0
WDQS1
WDQS2
WDQS3
<20> WDQS[7..4]
HY5RS573225AFP-16_FBGA_136P
VRAM@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E1
A1
A12
C1
C4
C9
C12
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
A2
A11
F1
F12
K1
K12
M1
M12
MDB[55..48] <20>
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
1
2
MAB0
K4
MAB1
H2
MAB2
K3
MAB3
M4
MAB4
K9
MAB5 H11
MAB6 K10
MAB7
L9
MAB8 K11
MAB9
M9
MAB10 K2
MAB11 L4
4
MDB[39..32] <20>
Place VREF divider and CAP

close to memory
VDD_MEM18
5
MDB[47..40] <20>
R1819
2.37K_0402_1%
10mil
7
MDB[63..56] <20>
Place close to U81
1
0.1U_0402_16V4Z
C1493
1U_0402_6.3V4Z
VDD_MEM18
1
C1506
C1494
1
C1496
C1503
0.1U_0402_16V4Z
C1504
C1507
1000P_0402_50V7K 10U_0603_6.3V6M
C1508
Place close to U82
VDD_MEM18
VDD_MEM18
RASA0#
R1818 121_0402_1%
1
2
RASA1#
R1820 121_0402_1%
1
2
CASA0#
R1821 121_0402_1%
1
2
CASA1#
R1822 121_0402_1%
1
2
WEA0#
R1824 121_0402_1%
1
2
WEA1#
R1825 121_0402_1%
1
2
CSA0_0#
R1826 121_0402_1%
1
2
CSA1_0#
R1827 121_0402_1%
1
2
CKEA0
R1828 121_0402_1%
1
2
CKEA1
R1829 121_0402_1%
1
2
CLKA0
R1831 60.4_0402_1%
1
2
CLKA0#
R1834 60.4_0402_1%
1
2
CLKA1
R1835 60.4_0402_1%
1
2
CLKA1#
R1836 60.4_0402_1%
1
2
1U_0402_6.3V4Z
1
C1516
0.1U_0402_16V4Z
1
C1519
C1520
C1512
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1517
0.1U_0402_16V4Z
1
1
C1498
10U_0603_6.3V6M
1
C1499
0.1U_0402_16V4Z
10U_0603_6.3V6M
1
C1513
C1515
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
10U_0603_6.3V6M
2006/09/25
2006/09/25
Deciphered Date
5
0.1U_0402_16V4Z
C1511
VDD_MEM18
VDD_MEM18
1U_0402_6.3V4Z
C1502
C1497
1U_0402_6.3V4Z
0.1U_0402_16V4Z
VREFA
1 C1490
0.1U_0402_16V4Z
R1823
5.49K_0402_1%
VDD_MEM18
0.01U_0402_16V7K
E1
A1
A12
C1
C4
C9
C12
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
A2
A11
F1
F12
K1
K12
M1
M12
U11
U2
A3
A10
G1
G12
J1
J12
L1
L12
U3
U10
HY5RS573225AFP-16_FBGA_136P
VRAM@
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MDB[31..24] <20>
1 C1489
0.1U_0402_16V4Z
R1817
5.49K_0402_1%
DM0
DM1
DM2
DM3
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
VREFB
DQMB3 E3
DQMB1 E10
DQMB2 N10
DQMB0 N3
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
<20> DQMB[3..0]
<20> MAB[11..0]
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
Place VREF divider and CAP

close to memory
U11
U2
MAB4 K4
MAB5 H2
MAB6 K3
MAB9 M4
MAB0 K9
MAB1H11
MAB2 K10
MAB11 L9
MAB10K11
MAB3 M9
MAB8 K2
MAB7 L4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
<20> MAB[11..0]
<20>
<20>
<20>
U82
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
A10
G1
G12
J1
J12
L1
L12
U3
U10
U81
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
2.37K_0402_1%
10mil
Title

M62-S VRAM
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
22
of
57
+3VS
10K_0402_5%
2
R1844
1
GPIO0
<19>
10K_0402_5%
2
R1847
1
GPIO1
<19>
R1853
D
GPIO5
R1855
1
GPIO6
DESCRIPTION OF RECOMMENDED SETTING
PIN
GPIO0
TX_PWRS_ENB
TX_DEEMPH_EN
10K_0402_5%
2
1
10K_0402_5% @
2
STRAPS
FULL SWING
internal pull down
Closed to U80
1
1
Transmitter De-emphasis Enable
GPIO1
RECOMMENDED
internal pull down
<19>
GPIO4
DEBUG_ACCESS
<19>
PLL_IBIAS_RD
Strap to set the debug muxes to bring out

DEBUG signals even if registers are inaccessible
internal pull down
GPIO[6:5]
+2.5VS
C1586
10U_0603_6.3V6M
R1857
1
GPIO11
<19>
10K_0402_5%
2
R1859
1
GPIO13
<19>
@ R1869
1
10K_0402_5%
2
@ R1870
1
0 1 0 X
No ROM , with 64M frame buffer
L83
2
1
BLM18PG121SN1D_0603 1
VRAM_ID0 <19>
1
R1883
10K_0402_5%
C1572
10U_0603_6.3V6M
2
10K_0402_5%
10K_0402_5%
L84
2
10K_0402_5%
HYN@ R1871
1
VRAM_ID 0, 1, 2, 3
VRAM_ID2 <19>
128M@ R1872
1
DVPDATA
(20,21,22,23)
VRAM_ID[0:3]
1
2
R1885 10K_0402_5%
SAM@
2
+LPVDD
20mA, 10mils
VRAM_ID1 <19>
1
R1884
+LVDDR
2
C1570
0.1U_0402_16V4Z
0 0 0 X
No ROM , with 128M frame buffer

GPIO
[9,13,12,11]
280mA, 20mils
1
C1569
10U_0603_6.3V6M 2
ROMIDCFG[3:0]
VDDDI_25
C1592
2 1U_0402_6.3V4Z
L82
2
1
BLM18PG121SN1D_0603 1
internal pull down

10K_0402_5%
2
110mA,20mils
1
GPIO6-->0
Bias Currentfor the PCIE PHY PLL
GPIO5-->1
10K_0402_5% @
2
BLM18PG121SN1D_0603
2
1
L89
1
VRAM_ID3 <19>
1
2
R1886 10K_0402_5%
64M@
Samsung 8Mx32 1.8V
0 0 0 0
Samsung 16Mx32 1.8V
0 0 0 1
Hynix 8Mx32 1.8V
0 0 1 0
Hynix 16Mx32 1.8V
0 0 1 1
2
1
BLM18PG121SN1D_0603 1
C1575
10U_0603_6.3V6M
C1578
10U_0603_6.3V6M
VDD_MEM18
60mA, 10mils
BLM18PG121SN1D_0603
2
1
Closed to U80
L85
ZZZ5
+TPVDD
+TXVDDR
100mA, 20 mils
C1580
0.001U_0402_50V7M
ZZZ4
C1594
10U_0603_6.3V6M
Samsung VRAM group
C1595
L86
2
1
BLM18PG121SN1D_0603 1
0.1U_0402_16V4Z
Hynix VRAM group
Samsung@
Hynix@
C1581
10U_0603_6.3V6M
+AVDD
100mA, 20mils
VGA Thermal Sensor ADM1032ARMZ

Closed to U80
+3VS
C1599
0.1U_0402_16V4Z
2
2
R1893
10K_0402_5%
1
1
VDD
VGA_THERMDA
D+
VGA_THERMDC
2200P_0402_50V7K THERM#_VGA
<19> VGA_THERMDA
C1600
2
1
<19> VGA_THERMDC
R1894
+3VS
1
@
R1906
1
10K_0402_5%
2
DTHERM#
SCLK
ICH_SM_CLK
SDATA
ICH_SM_DA
ALERT#
THERM_SCI#
GND
BLM18PG121SN1D_0603
2
1
U84
L88
THERM_SCI# <4,26>
+A2VDD
120mA, 20mils
C1588
10U_0603_6.3V6M
ADM1032ARMZ REEL_MSOP8
0_0402_5%
2
<4,19,26,31> ICH_SM_CLK
<4,19,26,31> ICH_SM_DA
ICH_SM_CLK
ICH_SM_DA
+3VS
R1896
<4,7,25> H_THERMTRIP#
1
10K_0402_5%
2
G
0802 (R1A) add for VGA thermal function
Q31
RHU002N06_SOT323
2
G
RHU002N06_SOT323
Q30
THERM#_VGA <4>
Compal Secret Data
Issued Date
2006/09/25
2006/09/25
Deciphered Date
5
Title

M62-S Filters / Strap
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
23
of
57
+3VS
1
R1514
1
R1515
1
R1516
1
R1517
1
R1518
1
R1519
1
R1520
1
R1521
1
R1585
1
R1748
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
PCI_DEVSEL#
1
R1522
1
R1523
1
R1524
1
R1525
1
R1526
1
R10
2
R189
1
R1530
1
R1531
1
R1532
1
R1533
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
1
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_PIRQA#
PCI_STOP#
PCI_TRDY#
<31> PCI_AD[0..31]
U26B
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
MBAY_DET#
MDC_DIS
+3VS
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQG#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
F9
B5
C5
A10
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
<31> PCI_PIRQC#
<31> PCI_PIRQD#
PCI
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
A4
D7
E18
C18
B19
F18
A11
C10
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C17
E15
F16
E17
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
AG24
B10
G7
Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
ICH8M REV 1.0
MDC_DIS
PCI_REQ2# <31>
PCI_GNT2# <31>
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#
R1527
1
8.2K_0402_5%
PCI_PIRQE#
F8
MBAY_DET#
G11
F12
PIRQH#
B3
2
1
0_0402_5%
R188
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
<31>
<31>
<31>
<31>
PCI_IRDY# <31>
PCI_PAR <31>
PCI_DEVSEL# <31>
PCI_PERR# <31>
PCI_SERR# <31,37>
PCI_STOP# <31>
PCI_TRDY# <31>
PCI_FRAME# <31>
PCI_PLTRST# <31>
CLK_PCI_ICH <15>
PCI_PME#
2
+3VALW
PCI_PIRQE#
MBAY_DET#
PCI_PIRQG#
ACCEL_INT
0301 change
<31>
<28>
<31>
<31>
0601 change
PCI_REQ3#
P
6
VGA_RST#
VGARST#
PLT_RST#
O
7
<18>
14
+3V_U43
VGARST# <26>
PLT_RST# <7,28,36>
U43B
PCI_GNT3#
R1534
@
1K_0402_5%
Boot BIOS Strap
+3VALW
PCI
2
R1051
0_0402_5%
1
LPC
@ 10_0402_5%
@ 8.2P_0402_50V
1
U59
Y
PLT_RST#
PLT_RST# <7,28,36>
@ TC7SH08FU_SSOP5
R1057
0_0402_5%
1
R191
100K_0402_5%
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
PCI_RST# <28,31>
R192
100K_0402_5%
C1177
PCI_RST#
J35
PAD-NO SHORT 2x2m
1
A
2 2
R1537
R1536
@
1K_0402_5%
R1535
1K_0402_5%
CLK_PCI_ICH
PCI_PLTRST#
SPI_CS1#_R
Place closely pin B10
<26> SPI_CS1#_R
@ TC7SH08FU_SSOP5
+3VALW
PCI_GNT0#
U56
Y
A16 swap override Strap

Low= A16 swap override Enble
PCI_GNT3# High= Default*
SPI
PCI_PCIRST#
Boot BIOS Location
SPI_CS#1
PCI_GNT0#
Title

ICH8(1/4)-PCI/INT
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
24
of
57
+3VS
R1538
GATEA20
10K_0402_5%
R1539
KB_RST#
R1540
1
330K_0402_1%
2 LAN100_SLP
R1542
1
1M_0402_5%
2 SM_INTRUDER#
R1543
1
330K_0402_1%
2 ICH_INTVRMEN
+VCCP
R1541
RTCX1
RTCX2
ICH_RTCRST#
AF23
RTCRST#
ICH_INTVRMEN
LAN100_SLP
ICH_RTCX1
R1733
1
<29> LAN_RXD0
<29> LAN_RXD1
<29> LAN_RXD2
ICH_RTCX2
10M_0402_5%
1
<29> LAN_TXD0
<29> LAN_TXD1
<29> LAN_TXD2
C516
15P_0402_50V8J
32.768KHZ_12.5P_MC-146
1
R1935
1K_0402_5%
SHORT PADS
CLRP2
2 24.9_0402_1%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
1
1
1
1
1
1
2
2
2
2
2
2
R1558 33_0402_5% 1
R1559 33_0402_5% 1
<38> HDA_SDOUT_MDC
<32> HDA_SDOUT_CODEC
R1560
10K_0402_5%
IDE_LED#
2
1
R1549 1
R1551
R1550
R1553
R1554
R1555
R1556
<38> HDA_BITCLK_MDC
<32> HDA_BITCLK_CODEC
<32> HDA_SYNC_CODEC
<38> HDA_SYNC_MDC
<32> HDA_RST#_CODEC
<32,38> HDA_RST#_MDC
<32> HDA_SDIN0
<38> HDA_SDIN1
Y4
2
2
D22
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
C21
B21
C22
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
D21
E20
C20
LAN_TXD0
LAN_TXD1
LAN_TXD2
HDA_BITCLK
GLAN_COMP
HDA_BITCLK
HDA_SYNC
HDARST#
HDA_SDIN0
HDA_SDIN1
HDA_SDOUT
2
PAD T38
SATA_LED#
CHP202U_SC70
Q144
<28> SATA_RXN0_C
<28> SATA_RXP0_C
<28> SATA_TXN0
<28> SATA_TXP0
3900P_0402_50V7K
SATA_TXN0 C1179 1
2 SATA_TXN0_C
SATA_TXP0 C1180 1
2 SATA_TXP0_C
+3VS
R1561
10_0402_5%
@
GLAN_CLK
LAN_RSTSYNC
AH21
+1.5VS
B24
<30> ENERGY_DET
3900P_0402_50V7K
<31,37> GREEN_BATLED#
2007,0125 change
C1181
@ 10P_0402_25V8K
<15> CLK_PCIE_SATA#
<15> CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_SATA
R1564
+5VS
+3VS
D25
C25
GLAN_DOCK#/GPIO13
GLAN_COMPI
GLAN_COMPO
AJ16
AJ15
HDA_BIT_CLK
HDA_SYNC
AE14
HDA_RST#
AJ17
AH17
AH15
AD13
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AE13
HDA_SDOUT
AE10
AG14
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
AF5
AH5
AH6
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AG3
AG4
AJ4
AJ3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AF2
AF1
AE4
AE3
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AB7
AC6
SATA_CLKN
SATA_CLKP
AG1
AG2
SATARBIAS#
SATARBIAS
LPC_FRAME#
LDRQ0#
LDRQ1#/GPIO23
G9
E6
LPC_DRQ0#
A20GATE
A20M#
GATEA20
H_A20M#
DPRSTP#
DPSLP#
AF26
AE26
H_DPRSTP_R#
FERR#
AD24
H_FERR#
CPUPWRGD/GPIO49
AG29
H_PWRGOOD
IGNNE#
AF27
H_IGNNE#
INIT#
INTR
RCIN#
AE24
AC20
AH14
H_INIT#
H_INTR
KB_RST#
NMI
SMI#
AD23
AG28
H_NMI
H_SMI#
IDE_LED#
2
CH751H-40_SC76
MB2_LED#1
D16
2
CH751H-40_SC76
56_0402_5%
R1544
@
1
56_0402_5%
R1546
@
1
56_0402_5%
PAD
GATEA20 <37>
H_A20M# <4>
H_DPRSTP#
1
0_0402_5%
2
R1548
H_DPRSTP# <5,7,49>
H_DPSLP# <5>
H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>
within 2" from R1557
H_INIT# <4>
H_INTR <4>
KB_RST# <37>
+VCCP
C
H_NMI <4>
H_SMI# <4>
STPCLK#
AA24
H_STPCLK#
AE27
THRMTRIP_ICH#
TP8
AA23
R1552
56_0402_5%
H_STPCLK# <4>
1
R1557
24_0402_1%
H_THERMTRIP# <4,7,23>
PD_D[0..15] <28>
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
DA0
DA1
DA2
AA4
AA1
AB3
PD_A0
PD_A1
PD_A2
DCS1#
DCS3#
Y6
Y5
PD_CS1#
PD_CS3#
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
W4
W3
Y2
Y3
Y1
W5
placed within 2" from ICH8M
+3VS
PD_A0
PD_A1
PD_A2
<28>
<28>
<28>
PD_IORDY# R1562 1
PD_IRQ R1563 1
2 4.7K_0402_5%
2 8.2K_0402_5%
B
PD_CS1# <28>
PD_CS3# <28>
PD_IOR#
PD_IOW#
PD_DACK#
PD_IRQ
PD_IORDY#
PD_DREQ#
PD_IOR# <28>
PD_IOW# <28>
PD_DACK# <28>
PD_IRQ <28>
PD_IORDY# <28>
PD_DREQ# <28>
BATT1
CR2032 RTC BATTERY
+RTCVCC
JP42
ACES_85205-0200
+3VL
BATT1.1
SATA_LED# 1
D15
H_DPSLP#
LPC_DRQ#0 <35>
THRMTRIP#
D14
R981 W=20mils
2
R976
1
2
1
W=20mils
3
1
2
W=20mils
0_0402_5%
1K_0402_5%
DAN202U_SC70
2
IDE_LED# <31>
LPC_FRAME# <35,36,37>
T39
AF13
AG26
ICH8M REV 1.0
C4
24.9_0402_1%
Within 500 mils

R88
10K_0402_5%
R90
10K_0402_5%
<28> MB2_LED#
INTVRMEN
LAN100_SLP
GLAN_CLK
FWH4/LFRAME#
H_DPRSTP#
<35,36,37>
1
2
<29> GLAN_CLK
<29> LAN_RSTSYNC
AF25
AD21
RTC
LPC
CLRP1
SHORT PADS
INTRUDER#
LAN / GLAN
CPU
C1178
1U_0603_10V4Z
11/20 For RTC Accuracy fail to change
SM_INTRUDER# AD22
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
IHDA
E5
F5
G8
F6
IDE
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
AG25
AF24
H_FERR#
ICH_RTCX1
ICH_RTCX2
R1545
20K_0402_5%
C528
15P_0402_50V8J
LPC_AD[0..3]
U26A
+RTCVCC
+3VS
10K_0402_5%
+RTCVCC
SATA
W=20mils
conn@
C665
1U_0603_10V4Z
XOR CHAIN ENTRANCE STRAP:RSVD

+3VS
2
@
R1567
1K_0402_5%
1
HDA_SDOUT_CODEC
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

ICH8(2/4)_LAN,HD,IDE,LPC

Date:
Rev
1A
Sheet

1
25
of
57
TP7
AJ8
AJ9
AH9
AE16
AC19
AG8
AH12
AE11
AG10
AH25
AD16
AG13
AF9
AJ11
AD10
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
<24>
PAD T48
Cap_RST#_SB
GPIO38
GPIO39
IDE_RESET#
2
1 R1591
@ 0_0402_5%
2
R1632
<28> IDE_RESET#
8.2K_0402_5%
1
<32>
SB_SPKR
SB_SPKR
ICH_RSVD
ICH_RSVD
AJ21
SPKR
MCH_SYNC#
TP3
1
1
C2
AJ25 PM_SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
F22
AF19
CL_DATA0 <7>
CL_DATA1 <31>
CL_VREF0
CL_VREF1
D24
AH23
CL_RST#
AJ23
AJ27
AJ24
AF22
AG19
<7>
<31>
C1184
CL_RST#
XMIT_OFF
CB_IN#
1
2
R1738
0_0402_5%
0.1U_0402_16V4Z
<7>
C1185
XMIT_OFF <31>
2 SB_SPKR
@ 10K_0402_5%
1
R1723
2
2
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SPI_SI
SPI_SO
1
2
PCIE_RXN5
F27
PCIE_RXP5
F26
1C1609 PCIE_C_TXN5 E29
C1610
PCIE_C_TXP5
E28
1
PERN5
PERP5
PETN5
PETP5
GLAN_RXN
GLAN_RXP
1 C1186 GLAN_TXN_C
1 C1187 GLAN_TXP_C
D27
D26
C29
C28
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
2 R1605
2 R1606
2 R1607
SPI_CLK_R
SPI_CS0#_R
SPI_CS1#_R
C23
B23
E22
SPI_CLK
SPI_CS0#
SPI_CS1#
0_0402_5%
0_0402_5%
2
2
1 R1640
1 R1641
SPI_SI_R
SPI_SO_R
D23
F21
SPI_MOSI
SPI_MISO
R352 1
2
0_0402_5%
CB_IN#
1
R1599
USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
+3VALW
DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
USB
T26
T25
Y23
Y24
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
USBRBIAS#
USBRBIAS
F2
F3
ISO_PREP#
2
CH751H-40_SC76
1
R1575
@ 10_0402_5%
1
DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_14M_ICH
R1574
@ 10_0402_5%
1
C1182
@ 4.7P_0402_50V8C
CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
C1183
B
@ 4.7P_0402_50V8C
R1569 10K_0402_5%
1
2
DMI_IRCOMP
1
2
+1.5VS
R1016
Within 500 mils
24.9_0402_1%
USB20_N0
USB20_N0 <34>
USB20_P0
USB20_P0 <34>Right side
USB20_N1
USB20_N1 <36>
USB20_P1
USB20_P1 <36>Fingerprint
PM_RSMRST#
PM_RSMRST#
RSMRST circuit
R1908
0_0402_5%
2
1
0619 change
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USBRBIAS
1
R1019
<34>
<34>Left side
<34>
<34>Left side
<34>
<34>Bluetooth
<39>
<39>Dock1
<31>
<31>WWAN
<39>
<39>Dock2
<37> RSMRST_EC
@ BAV99DW-7_SOT363
R1909
@ 2.2K_0402_5%
PM_RSMRST#
D68B
@ MMBT3906_SOT23
Q137
D68A @
BAV99DW-7_SOT363
R1751
@ 2.2K_0402_5%
2
22.6_0402_1%
ICH8M REV 1.0
Compal Secret Data
1
HDD_HALTLED 2
G
Q114
RHU002N06_SOT323
3
1
2
1
2
2
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
Place closely pin AG9
CLK_48M_ICH
HDD_HALTLED# <31>
10K_0402_5%
D57
PERN4
PERP4
PETN4
PETP4
Y27
Y26
W29
W28
Place closely pin G5
Within 500 mils
R1008
10K_0402_5%
H27
H26
G29
G28
1
1
1
0_0402_5%
2
R161
10K_0402_5%
2
2
2
2
PCIE_RXN4
PCIE_RXP4
1 C708 PCIE_C_TXN4
1 C709 PCIE_C_TXP4
15_0402_5%
15_0402_5%
15_0402_5%
BT_OFF
<37> GPIO29
+3VS
R1007
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<31> WXMIT_OFF#
+3VALW
2007,0125 change
GLAN_RXN
GLAN_RXP
GLAN_TXN
GLAN_TXP
+5VS
PERN3
PERP3
PETN3
PETP3
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>
<39>
<39>
<39>
<39>
1ICH_SMB_CLK
Q29
RHU002N06_SOT323
K27
K26
J29
J28
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
<34>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ICH_SMB_DATA
<4,19,23,31> ICH_SM_CLK
PERN2
PERP2
PETN2
PETP2
V27
V26
U29
U28
PCIE_RXN2
PCIE_RXP2
1 C710 PCIE_C_TXN2
C711
PCIE_C_TXP2
1
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
2.2K_0402_5%
R205
Q26 RHU002N06_SOT323
Q45
RHU002N06_SOT323
12
<36>
<36>
<17>
GLAN
+3VS
<4,19,23,31> ICH_SM_DA
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
<36> SPI_CLK
<36> SPI_CS0#
<36> SPI_CS1#
<24> SPI_CS1#_R
CABLE_DETECT <30>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<31>
<31>
<31>
<31>
<29>
<29>
<29>
<29>
ICH_SMB_CLK <31>
+3VM
2.2K_0402_5% R207
ALS_EN# 2
G
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
ICH_SMB_DATA <31>
Q25
RHU002N06_SOT323
ALS_EN
J36
Dock
2.2K_0402_5%
R204
Q24
RHU002N06_SOT323
330_0402_5%
R1598
453_0402_1%
0316 change design
M27
M26
L29
L28
Robson
PERN1
PERP1
PETN1
PETP1
PCI-Express
Direct Media Interface
GPIO11_SB
RHU002N06_SOT323
Q143
<31>
change
<31>
WLAN <31>
<31>
1
P27
P26
N29
N28
SPI
+3VM
R433
High -->No boot
10K_0402_5%
+3VALW
PAD-SHORT 2x2m
2007,0125 change
1
2
R1596
3.24K_0402_1%
U26D
11/06 follow UMA SI-2 design
2.2K_0402_5% R206
AMT ADP_PRES <37>

LAN_WOL_EN <40>
low-->default
+3VS
IN2
ICH_RSVD
1K_0402_5%
+3VS
CL_VREF0_ICH
CL_VREF1_ICH
1
O
R1592
453_0402_1%
2
0.1U_0402_16V4Z
0612 Change GPIO pin assignment
R1928
3.24K_0402_1% R1588
1
2
+3VM
PM_SLP_M# <37,40,47,48,52>
F23
AE18
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9
+3VM_LAN
IN1
ICH_LOW_BAT#
2
1
LOW_BAT# <37>
CH751H-40PT_SOD323-2
D22
ON/OFFBTN#
2
+3VL
ON/OFFBTN# <38> 1
R1722
R1630
100K_0402_5%
AH20
1
2
LAN_RST# <41>
0_0402_5%
AG27 EC_RMRST# 1
2 PM_RSMRST#
R1586
100_0402_5%
CK_PWRGD_R 1
E1
2 CK_PWRGD
CK_PWRGD <15>
R148
0_0402_5%
M_PWROK
E3
M_PWROK <7,41>
AE21
CL_CLK0
CL_CLK1
+3VALW
@
R1757
100K_0402_5%
PM_PWROK <37>
1
2 R1583
10K_0402_5%
DPRSLPVR <7,49>
SLP_S3#
<29,30,39> LED_LINK_LAN#
2 HDD_HALTLED
8.2K_0402_5%
<30,32,39> PREP#
SLP_M#
SATA
GPIO
Clocks
CLPWROK
ICH8M REV 1.0
+3VALW
SN74AHC1G08DCKR_SC70
U92
DPRSLPVR
RSMRST#
2 VRMPWRGD
0_0402_5% R146
@ C1620
0.22U_0402_10V4Z
USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4
AD9
MCH_ICH_SYNC# AJ13
<7> MCH_ICH_SYNC#
PM_PWROK
AJ14
CK_PWRGD
S4_STATE# <34>
AE23
LAN_RST#
<38> Cap_RST#_SB
<15> CLKSATAREQ#
<39>
DOCK_ID
+3VS
VGARST#
LAN_PHYPC_R
ALS_EN#
GPIO18
GPIO20
AH27 S4_STATE#
<29,32,33,37,39,40,47,48,49,50,51,52>
<40,48>
<40,48>
2 CK_PWRGD
@ 0_0402_5% R147
VRMPWRGD
AJ22
OCP#
RUNSCI_EC#
ISO_PREP#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
Q20
RHU002N06_SOT323
T14 PAD
DPRSLPVR/GPIO16
PWRBTN#
<49> CLK_EN#
1
1
SPI_CS1#
2
0_0402_5%
SMB
AJ20
ICH_SUSCLK
CLK_14M_ICH <15>
CLK_48M_ICH <15>
0_0402_5%
1
R1927
1
R15
1
2 VRMPWRGD
@R145
@
R145
0_0402_5%
SST_CTL
PAD T15
<4,50>
OCP#
<37> RUNSCI_EC#
<39> ISO_PREP#
<17,38> LID_SW#
1
2
R349@
SLP_S3#
SLP_S4#
SLP_S5#
1
2
G
<29> LAN_PHYPC
100K_0402_5%
2 DPRSLPVR
1
WAKE#
SERIRQ
THRM#
11/20 For detect CPU and system power saving
D3
AG23
AF21
AD18
S4_STATE#/GPIO26
CLK_14M_ICH
CLK_48M_ICH
VGATE
STP_PCI#/GPIO15
STP_CPU#/GPIO25
AE17
AF12
AC13
ICH_PCIE_WAKE#
SIRQ
THERM_SCI#
SUSCLK
SMBALERT#/GPIO11
CLKRUN#/GPIO32
<31> ICH_PCIE_WAKE#
<31,35,36,37> SIRQ
<4,23> THERM_SCI#
<7,37>
BMBUSY#/GPIO0
AH11
<31,35,36,37> PM_CLKRUN#
11/20 solve auto-turn on
SUS_STAT#/LPCPD#
SYS_RESET#
<21,31,37,40,41,49,50> PWR_GD
NPCI_RST# <35,37>
GPIO37
AG9
G5
R1767
1
0_0402_5%
CLK14
CLK48
MB_PWR <28>
HDD_HALTLED
R179
RI#
AJ12
AJ10
AF11
AG11
<15> H_STP_PCI#
<15> H_STP_CPU#
10K_1206_8P4R_5% RP56
2
1 WXMIT_OFF#
R1944
10K_0402_5%
2
@ R1568
PM_BMBUSY#
AG12
@R1727
@
R1727
1
2GPIO11_SBAG22
0_0402_5%
H_STP_PCI#
AE20
R_STP_CPU#
AG18
<7> PM_BMBUSY#
1
1
F4
AD15
XDP_DBRESET#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
@
R1581
@
R1580
2
2
+3VM
AF17
10K_0402_5%
@ R434
10K_0402_5%
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
Power MGT
10K_0402_5%
10K_0402_5%
10K_1206_8P4R_5% RP55
<29,32,33,37,39,40,47,48,49,50,51,52>
5
4 USB_OC#7
6
3 USB_OC#8
7
2 USB_OC#9
8
1 USB_OC#0
R1604
1
ICH_RI#
+3VS
0904 change
U26C
AJ26
AD19
AG21
AC17
AE19
4
3
2
1
CL_RST#1
<36> LPC_PD#
<4> XDP_DBRESET#
2 LINKALERT#
@ 10K_0402_5%
LID_SW#
2
10K_0402_5%
1ICH_LOW_BAT#
8.2K_0402_5%
2ICH_PCIE_WAKE#
1K_0402_5%
ICH_RI#
2
10K_0402_5%
2LAN_PHYPC
10K_0402_5%
2XDP_DBRESET#
1K_0402_5%
2S4_STATE#
10K_0402_5%
1 XMIT_OFF
10K_0402_5%
1 USB_OC#5
10K_0402_5%
5
6
7
8
2.2K_0402_5%
2.2K_0402_5%
2 ICH_SMB_CLK
2 ICH_SMB_DATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
11/20 For detect CPU and system power saving
LAN_PHYPC_R
2
R1930
SYS
GPIO
+3VALW
R1573
R1572 <31>
2
1
2
1
+3VALW
<37> ME_EC_CLK1
<37> ME_EC_DATA1
R1570
R1571
1
1
10K_0402_5%
10K_0402_5%
+3VALW
1
R1587
1
R1593
2
R1594
1
R1584
1
R1597
1
R1603
1
R1589
1
R1631
2
R1608
2
R1609
1
@ 0_0402_5%
<41> VCC_IDL
MISC
GPIO
Controller Link
2 SIRQ
10K_0402_5%
2 PM_CLKRUN#
8.2K_0402_5%
2 GPIO39
10K_0402_5%
2 THERM_SCI#
8.2K_0402_5%
2CLKSATAREQ#
10K_0402_5%
2 GPIO37
8.2K_0402_5%
2 GPIO18
8.2K_0402_5%
2 VGARST#
8.2K_0402_5%
2 GPIO20
8.2K_0402_5%
2 IDE_RESET#
8.2K_0402_5%
2 NPCI_RST#
8.2K_0402_5%
2 MB_PWR
8.2K_0402_5%
2 ALS_EN#
8.2K_0402_5%
2 PM_BMBUSY#
8.2K_0402_5%
OCP#
2
10K_0402_5%
1
R1576
1
R1578
1
R1579
1
@ R1582
1
R1600
1
R1595
1
R1601
1
R1602
1
R1617
1
R11
1
R3
1
R6
1
R16
1
R9
1
R1590
10K_0402_5% R1929
1
2
+3VALW
+3VS
2006/09/25
Issued Date
2006/09/25
Deciphered Date
3
Title

ICH8(3/4)_PM,USB,GPIO

Date:
Rev
1A
Sheet

1
26
of
57
U26E
1U_0603_10V4Z
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
AC10
AC9
VCC1_5_A[11]
VCC1_5_A[12]
AA5
AA6
VCC1_5_A[13]
VCC1_5_A[14]
G12
G17
H7
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
F1
L6
L7
M6
M7
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
0.1U_0402_16V4Z
W23
VCC1_5_A[25]
F17
G18
VCCLAN1_05[1]
VCCLAN1_05[2]
F19
G20
VCCLAN3_3[1]
VCCLAN3_3[2]
A24
VCCGLANPLL
2
+1.5VS
+3VM
1
1
+1.5VS
R1365
CHB1608U301_0603
2
1
C1224
10U_0805_10V4Z
4.7U_0805_10V4Z
R1371
A26
A27
B26
B27
B28
2
1
CHB1608U301_0603
C1225
1 +1.5VS
C1228
+3VS
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
B25
VCCGLAN3_3
GLAN POWER
2.2U_0603_6.3V4Z
C1223
0.1U_0402_16V4Z
VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2
T30
T31
VCCSUSHDA
AD11
VCCSUS1_05[1]
VCCSUS1_05[2]
J6
AF20
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
AC18
AC21
AC22
AG20
AH28
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
F20
G21
C1214
2
2
+3VALW
+3VALW
C1222
4.7U_0603_6.3V6M
T19
+3VM
2
CRACK_GPIO28
@
R1716
100K_0402_5%
1U_0603_10V4Z 1
ICHGND3
+3VL
+3VS
+3VS
@ Q124
RHU002N06_SOT323
ICHGND4
2
G
S
@ R1718
CRACK_GPIO28
@
R1717
D
ICHGND2
2
G
@ Q125
RHU002N06_SOT323
CRACK_GPIO28
@ R1719
ICHGND1
2
G
@ Q126
RHU002N06_SOT323
100K_0402_5%
2
G
@ Q127
RHU002N06_SOT323
R1715
D
ICH8M REV 1.0
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
ICHGND1
A1
1
2
R138
0_0402_5%
A2
A28
A29 ICHGND2
1
2
R152 0_0402_5%
AH1
AH29
AJ1 ICHGND3
1
2
R153 0_0402_5%
AJ2
AJ28
AJ29 ICHGND4
1
2
R137 0_0402_5%
B1
B29
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
ICH8M REV 1.0

+3VS
+3VS
G22 VCCCL1_05_ICH
A22
1
+3VALW
C1215
VCCCL1_5
+3VS
0.1U_0402_16V4Z
VCCSUS3_3[01]
VCCCL3_3[1]
VCCCL3_3[2]
0.1U_0402_16V4Z
1
T28
T29
AC16 VCCSUS1_5_ICH_1
T17
VCCSUS1_5_ICH_2
J7
T18
C3 0.1U_0402_16V4Z
VCCCL1_05
+3VS
0.1U_0402_16V4Z
C1218
C1220
AC12
C1207
C1217
VCCUSBPLL
USB CORE
0.1U_0402_16V4Z
VCCHDA
VCCSUS1_5[2]
VCC1_5_A[18]
VCC1_5_A[19]
D1
+1.5VS
C1219
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
VCCSUS1_5[1]
AC7
AD7
+1.5VS
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
100K_0402_5%
1 1
2
C1216
AC1
AC2
AC3
AC4
AC5
ATX
+1.5VS
B
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
10U_0805_10V4Z
C1212
C1211
C1213
1U_0603_10V4Z
VCCSATAPLL
C1210
AJ6
AE7
AF7
AG7
AH7
AJ7
0.1U_0402_16V4Z
C1209
+1.5VS
ARX
1U_0603_10V4Z
AA3
U7
V7
W1
W6
W7
Y7
C1208
0.1U_0402_16V4Z
CHB1608U301_0603
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS
AC8
AD8
AE8
AF8
(DMI)
C1205
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
R1366
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
0.1U_0402_16V4Z +3VS
1
0.1U_0402_16V4Z +3VS
(SATA)
1
+3VS
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
2
0.1U_0402_16V4Z
AD2
C1204
C1200
AF29
VCC3_3[02]
+VCCP
0.1U_0402_16V4Z
C1203
20 mils
1
VCC3_3[01]
C1202
ICH_V5REF_SUS
AC23
AC24
0.1U_0402_16V4Z
CH751H-40_SC76
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
4.7U_0603_6.3V6M
D56
10_0402_5%
R29
AE28
AE29
C1201
R1611
C
VCCA3GP
+5VALW +3VALW
VCCDMIPLL
+1.25VS
0.47U_0402_6.3V6K
C1190
22U_0805_6.3VAM
+1.5VS
10U_0805_10V4Z
C1198
C1199
ICH_V5REF_RUN
100K_0402_5%
20 mils
CHB1608U301_0603
R1370
0.01U_0402_16V7K
2
2.2U_0603_6.3V4Z
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
10U_0805_10V4Z
CH751H-40_SC76
100_0402_5%
C1197
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
0.1U_0402_16V4Z
100K_0402_5%
1
2
D55
C1196
R1610
C1195
C1193
+3VS
+5VS
220U_D2_4VM
C1194
+
2
CHB1608U301_0603
V5REF_SUS
C1192
40 mils
G4
CORE
+1.5VS
ICH_V5REF_SUS
10U_0805_10V4Z
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C1206
V5REF[1]
V5REF[2]
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
C1229
VCCRTC
A16
T7
VCCP_CORE
0.1U_0402_16V4Z
U26F
AD25
ICH_V5REF_RUN
R1372
A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6
+VCCP
IDE
PCI
20 mils
VCCPSUS
VCCPUSB
C1189
0.1U_0402_16V4Z
C1188
0.1U_0402_16V4Z
+RTCVCC
Title

ICH8(4/4)_POWER&GND

Date:
Rev
1A
Sheet

1
27
of
57
Multi Bay II connector
+3V_U43
1
conn@
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
9
SATA_TXP0 <25>
SATA_TXN0 <25>
SATA_RXN0
SATA_RXP0
3900P_0402_50V7K
3900P_0402_50V7K
PLT_RST_B# 2
R1036
2 C474
2 C475
1
1
SATA_RXN0_C <25>
SATA_RXP0_C <25>
<24,31> PCI_RST#
10
1
0_0402_5%
O
B
R1037
conn@ JP5
C641 0.1U_0402_16V4Z
R301
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
1 ODD_RST#
33_0402_5%
S1
S2
S3
S4
S5
S6
S7
GND
RX+
RXGND
TXTX+
GND
14
<26> IDE_RESET#
JP45
U43C
1
@ 0_0402_5%
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C1232
1
C1234
+5VS
1
C1236
1
C1233
C1235
1U_0402_6.3V4Z
boss
boss
0.1U_0402_16V4Z
24
23
26
25
GND
GND
close SATA connector
1000P_0402_50V7K
OCTEK_SAT-22DD1G
+3VS
1
RR72
4.7K_0402_5%
MBAY_DET#
1
<24> MBAY_DET#
C628
0.1U_0402_16V4Z
55
56
57
58
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
ODD_RST#
PD_D8
PD_D7
PD_D9
PD_D6
PD_D10
PD_D5
PD_D11
PD_D4
PD_D12
PD_D3
PD_D13
PD_D2
PD_D14
PD_D1
PD_D15
PD_D0
PD_DREQ
PD_D[0..15]
<25>
PD_DREQ# <25>
PD_IOR#
PD_IOW#
PD_IOR#
PD_IOW#
PD_IORDY
PD_DACK#
PD_IRQ
PD_IORDY# <25>
PD_DACK# <25>
PD_IRQ
<25>
PD_A1
PD_A1
<25>
PD_A0
PD_A2
PD_CS#1
PD_CS#3
MB2_LED#
PD_A0
PD_A2
PD_CS1#
PD_CS3#
MB2_LED#
<25>
<25>
<25>
<25>
<25>
<25>
<25>
+5VS_MB
MBAY_DET#
R1032
0_0402_5%
2
JAE_WM2M054JKB
+5VS
+5VS
1
2
3
1
R83
470K_0402_5%
C640
4
1
D
MB_PWR
Q38
RHU002N06_SOT323
2
C624
10U_0805_10V4Z
1
C625
2
0.1U_0402_16V4Z
2
220K_0402_5% 1C633
R93
0.1U_0402_16V4Z
2
2
G
3
<26>
8
7
6
5
10U_0805_10V4Z
+5VS_MB
Q92
AO4407_SO8
+5VS_MB
+5VS_MB
R98
1
C626
1
C627
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1 2
100_0402_5%
2
G
Q39
RHU002N06_SOT323
+3V_U43
Place close to JP29

ZZZ3
14
ZZZ2
13
PLT_RST_B#
2006/09/25
2006/09/25
Deciphered Date
5
PCB-MB
PLT_RST_B# <31,35,36>
Compal Secret Data
Issued Date
11
U43D
Audio-wire
12
<7,24,36> PLT_RST#
A
Title

HDD & CDROM

Date:
Rev
1A
Sheet

1
28
of
57
11/20 Enable ACBS (power management for NIC)

@R1612
@
R1612
1
+3VM
0_1206_5%
2
40 mils
S
R1613
1M_0402_5%
1000P_0402_50V7K 3
+3VM_LAN
1
SI2301BDS_SOT23
Q102
C1243
C1242
4.7U_0603_6.3V6M
1
1
2
100K_0402_5%
1
1
4.7U_0603_6.3V6M
C1244
R1730
0_0402_5%
C1245
0.1U_0402_16V4Z
XTAL1
XTAL2
near U74
470P_0402_50V7K
C1248
470P_0402_50V7K
D1
F3
F1
JTXD0
JTXD1
JTXD2
<25>
<25>
<25>
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_RXD0
LAN_RXD1
LAN_RXD2
D3
D2
C1
JRXD0
JRXD1
JRXD2
LAN_KBIAS_P
LAN_KBIAS_N
LED_LINK_LAN#
LED_ACT_LAN#
<30,39> LED_ACT_LAN#
G7
H7
C1251
C1252
GLAN_RXP-NC
GLAN_RXN-NC
KBIAS_P-RBIAS100
KBIAS_N-RBIAS10
A4
B4
A5
LED0-LINK_UP_N
LED1-ACT_LED_N
LED2-SPEED_LED_N
B8
B9
MDI_PLUS[0]-TDP
MDI_MINUS[0]-TDN
+V1.0_LAN_M
470P_0402_50V7K
C1253
C
H5
H6
GLAN_TXP-NC
GLAN_TXN-NC
GLCI
C490
0.1U_0402_16V4Z
GLAN_RXP_CH2
1
2
GLAN_RXN_C J2
1
2
C1319
0.1U_0402_16V4Z
GLAN_TXP
J4
GLAN_TXN
H4
GLAN_TXP
GLAN_TXN
20 mils
1
VSSA[17]-NC
VSSA[16]-NC
VSSA[15]-VSSA2
VSSA[14]-VSS
VSSA[13]-NC
VSSA[12]-VSS
VSSA[11]-VSS
VSSA[10]-VSS
VSSA[09]-VSS
VSSA[08]-VSS
VSSA[07]-VSS
VSSA[06]-VSS
VSSA[05]-VSS
VSSA[04]-VSS
VSSA[03]-VSSR
VSSA[02]-NC
VSSA[01]-VSS
VSS[04]-VSS
VSS[03]-VSSP
VSS[02]-VSS
VSS[01]-NC
J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8
F4
E1
C4
A1
VDD1P0[03]-VCCA
VDD1P0[02]-VCCT
VDD1P0[01]-VCCR
F7
E8
D7
VCCF1P0-VCC
E5
0.1U_0402_16V4Z 470P_0402_50V7K
+3VM_LAN
4.7U_0603_6.3V6M1
C1255
C1258
+V1.0_LAN_M
R1618
2
+V1.0M_LAN
2
C1254
+1.8VM
Q106
BCP69_SOT223
4
2
0.1U_0402_16V4Z
LAN_CTRL_18
2
C1256
LAN_TXD0
LAN_TXD1
LAN_TXD2
R1616
C1250
10N_0603_50V7K
JRSTSYNC
LAN_TXD0
LAN_TXD1
LAN_TXD2
LCI
E3
<25>
<25>
<25>
<25> LAN_RSTSYNC
GLAN_RXP
GLAN_RXN
XTAL2-X2
XTAL1-X1
R1615 33_0402_5%
U74
GLANCLK E2
1
2
JKCLK-JCLK
<25> GLAN_CLK
C1249
<26>
<26>
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
1.4K_0402_1%
C1247
+1.8VM_LAN
2
G
SLP_S3#
@ Q105
RHU002N06_SOT323
<26>
<26>
C1246
@ Q104
RHU002N06_SOT323
<26,32,33,37,39,40,47,48,49,50,51,52>
2
G
<37,44,45,46,50> ADP_PRES
20 mils
0.1U_0402_16V4Z
Q103
BSS138_SOT23
2
G
<26> LAN_PHYPC
R1614
1
C1257
10U_0805_10V4Z
0.1U_0402_16V4Z
0_0603_5%
LAN_MDI1P
LAN_MDI1N
D9
D8
MDI_PLUS[1]-RDP
MDI_MINUS[1]-RDN
<30> LAN_MDI2P
<30> LAN_MDI2N
LAN_MDI2P
LAN_MDI2N
F9
F8
MDI_PLUS[2]-NC
MDI_MINUS[2]-NC
<30> LAN_MDI3P
<30> LAN_MDI3N
LAN_MDI3P
LAN_MDI3N
H8
H9
MDI_PLUS[3]-NC
MDI_MINUS[3]-NC
A7
B7
IEEE_TEST_P-NC
IEEE_TEST_N-NC
1
@ R1622
LAN_KBIAS_P
2
649_0402_5%
1
@ R1623
LAN_KBIAS_N
619_0402_5%
1
R1621
IEEE_TEST_P
2IEEE_TEST_N
@ 0_0402_5%
closed to E6 pin
R1625
2
1.4K_0603_1%
1
J6
J7
E7
E6
B5
1
R1627
A6
C5
B6
2
100_0402_5%
VCCFC1P0-VCC
H3
VCC3P3[02]-VCCP
VCC3P3[01]-VCC
F2
B3
+3.3V_LAN
VCC1P8[04]-NC
VCC1P8[03]-NC
VCC1P8[02]-NC
VCC1P8[01]-NC
G5
F5
D5
C2
+1.8VM_LAN 1
VCC1P0-VCCA2
G4
+V1.0_LAN_M
VCC[02]
VCC[01]
E4
D4
R1620
RSVD_J6-NC
RSVD_J7-NC
JTAG
RBIAS_P-NC
RBIAS_N-NC
RSVD_B5-NC
RSVD_A6-ADV10/LAN_DIS_N
RSVD_C5-NC
TEST_EN
RU82566DM B0 Q870 BGA 81P
1
C1263
T68 PAD
T70 PAD
XTAL1
XTAL2_R 1
25MHZ_20P_1BG25000CK1A
27P_0402_50V8J
C1264
XTAL2
+3VM_LAN
1U_0402_6.3V4Z
C1612
1U_0402_6.3V4Z
0.1U_0402_16V4Z
2
C1357
4.7U_0603_6.3V6M
1
C1356
B1
V1P_OUT
CTRL_10-NC
CTRL_18-NC
LAN_CTRL_10
LAN_CTRL_18
THERM_D_P-NC
THERM_D_N-NC
A2
A3
LAN_THERM_D_P
LAN_THERM_D_N 1
@ R1628
4
2
2
1
1
C1360
C3
B2
+V1.0M_LAN
BCP69_SOT223
+1.8VM
V1P_OUT
2
0_0402_5%
1
+V1.0_LAN_M
Q128
+3VM_LAN
0_0603_5%
2
R1734
V1P0_OUT-NC
@
1
Y9
0_0603_5%
R1619
1
2
C1611
2
1
LAN_CTRL_10
10N_0603_50V7K
1
<30> LAN_MDI1P
<30> LAN_MDI1N
JTAG_TCK-ISOL_TCK
JTAG_TDI-ISOL_TI
JTAG_TDO-TOUT
JTAG_TMS-ISOL_EXEC
LAN_MDI0P
LAN_MDI0N
MDI
<30> LAN_MDI0P
<30> LAN_MDI0N
10U_0805_10V4Z
C1359
0.1U_0402_16V4Z
C1358
2
0_0603_5%
G1
H1
G3
G2
R1629
200_0402_5%
2
+3VM_LAN
PAD T69
PAD T71
1
2
@ R1634 200_0402_5%
+3VM_LAN
Compal Secret Data
R1936
30_0402_5%
2006/09/25
Issued Date
27P_0402_50V8J
2006/09/25
Deciphered Date
2007,0125 change
4
Title

Intel 82566 Nineveh
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
29
of
57
12
TD4-
MX4-
13
MDO0-
LAN_MDI0P
11
TD4+
MX4+
14
MDO0+
10
TCT4
MCT4
15
MCT0
MX3-
16
MDO1-
MX3+
17
MDO1+
RJ-45 CONN.
T66
LAN_MDI0N
LAN ENERGY DET
+1.8VM
TRM_CT
TD3-
+3VM
2 R269
1
75_0402_1%
200K_0402_5%
100K_0402_5%
1.5K_0402_5%
02/27 change
2 R270
1
75_0402_1%
LAN_MDI0P 2
1000P_1808_3KV7K
LAN_MDI1P 2
C1267
MDO2+
TCT2
MCT2
21
LAN_MDI3N 3
TD1-
MX1-
22
MDO3-
MX1+
23
MDO3+
MCT1
24
MCT3
TRM_CT
TD1+
TCT1
2
10K_0402_5%
ED_VREF
R1638
0.01U_0402_16V7K
C1268
100K_0402_5%
U75
IN+
O
IN-
R1639
1.87K_0402_1%
4 1
2
R51
ENERGY_DET <25>
0_0402_5%
2 R271
1
75_0402_1%
LMV331IDCKRG4_SC70-5~D
20
R69 1
ED_ACT
10P_0402_50V8J
MX2+
MCT2
LAN_MDI3P 2
2
1
C329
0.1U_0402_16V4Z
TD21+
1:1
2
1
C328
0.1U_0402_16V4Z
TRM_CT
1:1
LAN_MDI2P 5
R55 1
2
10K_0402_5%
MDO2-
C1265
0.1U_0402_16V4Z
MCT1
19
18
MX2-
MCT3
TD2-
TCT3
0.01U_0402_16V7K
2
LAN_MDI2N 6
C1266
R1637
TRM_CT
C344
1
2
@ R1636
R1635
2
1
C327
0.1U_0402_16V4Z
TD3+
1:1
LAN_MDI1P 8
LAN_MDI1N 9
1:1
2
1
C330
0.1U_0402_16V4Z
CAP closed to LAN_MDIO bus
C320
1
2
2 R272
1
75_0402_1%
1000P_1808_3KV7K
24HST1041A-3_24P
@D73
@
D73
MDO3+
0.1U_0402_16V4Z 1
2 C56
0.1U_0402_16V4Z 1
2 C54
0.1U_0402_16V4Z 1
2 C50
0.1U_0402_16V4Z 1
2 C49
R50 1
R63 1
R45 1
R48 1
R42 1
R44 1
R40 1
R41 1
2
2
2
2
2
2
2
2
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
LAN_MDI0N
LAN_MDI0P
LAN_MDI1N
LAN_MDI1P
LAN_MDI2N
LAN_MDI2P
LAN_MDI3N
LAN_MDI3P
MDO1+
MDO1-
<29>
<29>
<29>
<29>
<29>
<29>
<29>
<29>
MDO3-
APL5301-18BC-TRL_SOT23-5
Layout Notice : Place

termination as close as
Intel 82566 as possible
@ D74
MDO2+
MDO0+
MDO0-
Note: MDO[3..0]+/- signals should route to JP4 first then to JP30.

2
JP4
R266 2
+3VM_LAN_LED
1 300_0402_5%
LED_ACT_LAN#
<29,39> LED_ACT_LAN#
@ C1625
330P_0402_50V7K
<39>
MDO3-
<39>
MDO3+
<39>
MDO1-
<39>
MDO2-
<39>
MDO2+
<39>
MDO1+
<39>
MDO0-
<39>
MDO0+
R265 2
+3VM_LAN_LED
Yellow LED-
PR4-
PR4+
MDO1-
PR2-
MDO2-
PR3-
MDO2+
PR3+
MDO1+
PR2+
MDO0-
PR1-
MDO0+
PR1+
1 300_0402_5%
11
12
MDO2SHLD1
MDO3+
DETECT PIN1
16
9
CABLE_DETECT <26>
DETCET PIN2
10
SHLD1
15
APL5301-18BC-TRL_SOT23-5
B
C579
0.1U_0402_16V4Z
Green LED+
Green LEDFOX_JM36113-P1122-7F
conn@
@C1624
@
C1624
330P_0402_50V7K
Yellow LED+
14
MDO3-
LED_LINK_LAN#
13
20 mils
+3VM_LAN
+3VM_LAN_LED
D
Q60
AO3413_SOT23
R525
A
1
<26,32,39> PREP#
100K_0402_5%
2
G
Q61
RHU002N06_SOT323
Compal Secret Data
Issued Date
2006/09/25
2006/09/25
Deciphered Date
5
Title

Magnetic & RJ45/RJ11
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
30
of
57
B/B connector with PCI / LED / FIR / SC interface
0824 Add +1.5VS_WLAN
Mini-Express Card---WLAN
0811 Isolate SLOT power from SYSTEM power.

+1.5VS_WLAN
+3VALW
<24> PCI_CBE#2
<24> PCI_IRDY#
<26,35,36,37> PM_CLKRUN#
<24,37> PCI_SERR#
<24> PCI_PERR#
<24> PCI_CBE#1
HDD_HALTLED#
<26> HDD_HALTLED#
+3VL
<36,38>
<25,37>
<37>
<37,38,39>
<25>
WL_BLUE_LED#
GREEN_BATLED#
AMBER_BATLED#
LED_STB#
IDE_LED#
WL_BLUE_LED#
GREEN_BATLED#
AMBER_BATLED#
LED_STB#
IDE_LED#
+1.5VS
+3VS
+5VS
101
GND
GND
102
PCI_PIRQG#
PCI_PIRQD#
PCI_REQ2#
PCI_PLTRST#
CLKREQ#_E
PCI_PIRQE#
PCI_PIRQC#
PCI_RST#
PCI_GNT2#
SIRQ
PWR_GD
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCM_SPK
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD15
C293
C294
C538
C542
JP44
ICH_PCIE_WAKE#
CH_DATA
CH_CLK
1
2 CLKREQD#_MC
R1336
0_0402_5%
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
<15> CLK_PCIE_MCARD#
<15> CLK_PCIE_MCARD
0906 Remove debug resistors

R1348
PCIE_RXN2
1
PCIE_RXP2
1
R1349
<26> PCIE_RXN2
<26> PCIE_RXP2
0_0402_5%
PCIE_C_RXN2
2
PCIE_C_RXP2
2
0_0402_5%
PCIE_TXN2
PCIE_TXP2
<26> PCIE_TXN2
<26> PCIE_TXP2
+3VS_WLAN
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
0821 Change +3VS to +3VS_WLAN
IRRX
<35>
IRTXOUT <35>
IRMODE <35>
SC_CD#
<34>
SC_CLK
SC_RST
<34>
<34>
0622 change to support AMT
+3VS
2
2
2
2
20_0603_5%
0_0603_5%
55
56
53
GND1GND2
54
C540
XMIT_OFF
+3VS
ACCELEROMETER
2
+3VALW
0_0402_5%
2
+3VS_WWAN
0_0402_5%
CH1 CH4
Vn
Vp
R517
@ 100K_0402_5%
XMIT_OFF#
D
2
G
Q58
@ RHU002N06_SOT323
1
+3VS_ACL
R1355
2
@ 0_0805_5%
0_0402_5%
R1356
+3VS_ACL_IO
+3VS_ACL
1
2
0_0603_5%
C994
CH2 CH3
0313 change design
GND
VPP
I/O
DET
VCC
RST
CLK
M_WXMIT_OFF#
2
CH751H-40_SC76
1
2
3
8
9
<4,19,23,26> ICH_SM_DA
UIM_PWR
UIM_RST
UIM_CLK
+3VS_ACL_IO
INT/RDY
GND
16
SDD
RES
15
14
SDA/SDI/SPC
GND
VDD_IO
VDD
13
RES
12
C996
10U_0805_10V4Z
+3VS_ACL
R1362
<4,19,23,26> ICH_SM_CLK
+3VS_ACL
C960
10K_0402_5%
2
1
R1359
SCL/SPC
+3VS_ACL
0_0402_5%
6
CS
VDD
11
NC
RES
10
GND
0619 Follow ST Demo circuit
R1357
0619 Follow ST Demo circuit
+3VS_ACL_IO
0_0402_5%
8
TAITW_PMPAT6-06GLBS7N14N0
CK
R1391
0_0402_5%
2006/09/25
Issued Date
2006/09/25
Deciphered Date
C
LIS3LV02DL-TR _LGA16
Must be placed in the center of the system.
Compal Secret Data
2007,0125 change
0821 Delete SW1,C986,R521,D65,R200
0_0402_5%
1
UIM_PWR
R1361
C554
4.7U_0805_10V4Z
GND
GND
@ R1923
C995
0.1U_0402_16V4Z
<24> ACCEL_INT
DAN217_SC59 +3VS
@D13
@
D13
4
5
6
7
U64
0811 Reserve for SIM card does not meet rise time and a pull-up resistor is needed.
@ 0.01U_0402_16V7K
10K_0402_5%
@ R1913
0_0402_5%
+3VALW
S DIO(BR) NUP4301MR6T1 TSOP-6
UIM_VPP
UIM_DATA
D66
@ R1754
0_0402_5%
54
1
D64
CH751H-40_SC76
JP50
WW_LED# <36>
WW_LED# <36>
WL_LED# <36>
WP_LED# <36>
2WP_LED#
0627 Add 0 ohm on PIN 42,46
2
+3VS
U72
0821 Change +3VS to +3VS_WWAN
<26> WXMIT_OFF#
2WW_LED#
0811 HP request
0811 Pins 37 and 43 connect to GND and remove +1.5VS
WW_LED#_R
1
WL_LED#
WP_LED#_R
1
R1422
0.1U_0402_16V4Z
MOLEX 67910-0002 52P

conn@
C544
M_WXMIT_OFF#
WW_LED#
ICH_SMB_CLK <26>
ICH_SMB_DATA <26>
D72
USB20_N8 <26>
USB20_P8 <26>
PLT_RST_B# <28,35,36>
+3VALW
+3VM
0612 change power plane
+3VS_WWAN
1
R1071
1
R1073
0_0402_5%
2
2
0_0402_5%
1
1
4.7U_0805_10V4Z
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
1
@R1382
@
R1382
1
R1383
R1363
@ R1364
+3VS_WWAN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
0.01U_0402_16V7K
C295
XMIT_OFF#
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WWAN
R82
1
2
0_1206_5%
GND1GND2
MOLEX 67910-0002 52P
<24>
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
DIP1
DIP2
C959
+3VS
JP46
53
CH751H-40_SC76
0811 Isolate SLOT power from SYSTEM power.
+1.5VS_WLAN
@ 10K_0402_5%
PCI_AD[0..31]
+1.5VS_WLAN
+3VS_WLAN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
R516
0731 Install R1383 and no install R1382, do not support wake on WWAN card
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
SC_DATA <34>
PCI_AD[0..31]
+1.5VS
0811 No install R1418,R1358,R1359,R1360
<26>
+3VALW
0821 Install R1364
conn@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
0627 PIN37,43 connected to GND

PIN39,41 connected to +3VS
ACES_88394-1A71
Mini-Express Card--WWAN
0.1U_0402_16V4Z
+SC_PWR
SC_DATA
R197
R195
R194
<26> CL_CLK1
<26> CL_DATA1
<26> CL_RST#1
PCI_CBE#0 <24>
SC_CLK
SC_RST
R71
1
2
0_1206_5%
PCI_PAR <24>
SC_CD#
1
2
0_1206_5%
0.1U_0402_16V4Z
<26> ICH_PCIE_WAKE#
<34> CH_DATA
<34> CH_CLK
<15> CLKREQ#_G
PCI_FRAME# <24>
PCI_TRDY# <24>
PCI_STOP# <24>
PCI_DEVSEL# <24>
+3VS_WLAN
C533
4.7U_0805_10V4Z
PCM_SPK <32>
IRRX
IRTXOUT
IRMODE
C954
1
+3VS
4.7U_0805_10V4Z
R72
0.1U_0402_16V4Z
PCI_PIRQG# <24>
PCI_PIRQD# <24>
PCI_REQ2# <24>
PCI_PLTRST# <24>
CLKREQ#_E <15,19>
PCI_PIRQE# <24>
PCI_PIRQC# <24>
PCI_RST# <24,28>
PCI_GNT2# <24>
SIRQ
<26,35,36,37>
PWR_GD <21,26,37,40,41,49,50>
PCI_AD13
PCI_AD11
PCI_AD9
PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
0.01U_0402_16V7K
+3VS_WLAN
<34>
<34>
<24> PCI_CBE#3
XTPB0XTPB0+
CLK_PCI_PCM
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_CBE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_CBE#2
PCI_IRDY#
PM_CLKRUN#
PCI_SERR#
PCI_PERR#
PCI_CBE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
<15> CLK_PCI_PCM
0915 Change 1394 signals
XTPB0XTPB0+
<26>
<26>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
<26> PCIE_RXN4
<26> PCIE_RXP4
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
CLK_PCIE_Rob#
CLK_PCIE_Rob
R37
0_0402_5%
PCIE_RXN4 2
NF_RXN
1
PCIE_RXP4 2
NF_RXP
1
R36
0_0402_5%
PCIE_TXN4
PCIE_TXN4
PCIE_TXP4
PCIE_TXP4
<15> CLK_PCIE_Rob#
<15> CLK_PCIE_Rob
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
55
56
XTPA0XTPA0+
XTPA0XTPA0+
DIP1
DIP2
JP13
<34>
<34>
Title

Mini-Card/Mini-PCI/Accelerometer
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

E
31
of
57
V_CODEC
VDDA_CODEC
SLP_S3#
+5VAMP<26,29,33,37,39,40,47,48,49,50,51,52>
R329
U18
0.1U_0402_16V4Z 150K_0402_1%
R330
S
MONO_IN
2
0.1U_0402_16V4Z
+ C548
C377
22U_B_10V
C552
1U_0603_10V4Z
C551
100P_0402_50V8J
R456
IN
OUT
ADJ
EN
49.9K_0402_1% 1
GND
MIC5205BM5_SOT23-5
1
2
R258
0_0805_5%
0.01U_0402_16V7K
C553
+ C309
2
R457
22U_B_10V
C307
0.1U_0402_16V4Z
1
0.01U_0402_16V7K
1
143K_0402_1%
2
Q35
RHU002N06_SOT323
1
C430
10K_0402_5%
2
G
<31> PCM_SPK
1
R341
1
10K_0402_5%
C390
1
2
VDDA_CODEC
1
Place R258 between DGND & AGND & close to U14
R350
RHU002N06_SOT323
0_1206_5%
2
1
C417
1
C148
2
C402
1
U14
0.1U_0402_16V4Z
GND
GNDA
10U_0805_10V4Z
T24
R370
R375
R369
R374
<39> DLINE_IN_L
<39> DLINE_IN_R
2
1
2
1
1
2
1
2
PAD
16
MIC3
MONO_OUT
37
L_HP
R_HP
2 1U_0603_10V4Z
DLINE_IN_RC_R
24
LINE_IN_R
R_HP
2
R1038
<33>
MIC1
MIC1
<33>
MIC2
MIC2
T23
PAD
T25
PAD
1
C204
1
C205
R231
1
1
T26
PAD
MIC1_C
2
1U_0603_10V4Z
MIC2_C
2
1U_0603_10V4Z
SENSE_A
SENSE_B
2
2.2K_0402_1%
2
@ 0_0402_5%
18
CD_L
20
CD_R
19
CD_GND
21
MIC1
22
MIC2
13
34
SENSEA
SENSEB
<25> HDA_RST#_CODEC
11
<25> HDA_SYNC_CODEC
10
<25> HDA_SDOUT_CODEC
EAPD
L53 1
2
FBM-L10-160808-301-T_0603
PAD
2
20K_0402_1%
SENSE_A_B <33>
0_0402_5%
R1916
2
R1917
10K_0402_5%
2
LINE_OUTR <33>
L_HP
1
R972
LINE_OUTL <33>
41
SENSE_A_A <33>
BIT_CLK
SDATA_IN
T20
PAD
1
@ 33_0402_5%
<33>
<33>
1
C1064
HDA_BITCLK_CODEC
HDA_SDIN0_CODEC
@ 10P_0402_25V8K
<25>
R373 1
33_0402_5%
HDA_SDIN0 <25>
@
@
PORT_A_SNS <33>
GPIO_0
GPIO_1
GPIO_2
GPIO_3
VREF
27
MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D
PCBEEP
28
29
30
32
12
N/C
N/C
N/C
NC
NC
31
33
40
45
46
AVSS1
AVSS2
26
42
RESET#
SYNC
SDATA_OUT
47
EAPD
48
SPDIFO
4
7
DVSS1
DVSS2
R168
R167
R136
R32
43
44
2
3
1
1
1
1
2
2
2
2
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
4.7K_0402_5%
PREP#
PORT
PLACE TO
MONO_OUT
PORT A
HP OUT, DOCK HP LO
PORT B
M/B MIC
PORT C
DOCK LI
C416
PORT D
M/B SPK
0.1U_0402_16V4Z
PORT E
PORT F
Internal MIC
<26,30,39>
AUD_REF
T27
T13
T12
T11
MONO_IN
T7
T8
T10
T6
T9
1
PAD
PAD
PAD
PAD
C424
1U_0603_10V4Z
PAD
PAD
PAD
PAD
PAD
AD1981HDJSTZ-REEL_LQFP48
VDDA_CODEC
SENSE_A_C
2
10K_0402_1%
1
C977
@ 1U_0402_6.3V4Z
2
G
Q97
R974
@ 0_0402_5%
LINE_OUTR
39
T22
LINE_IN_SENSE
LINE_IN_SENSE <39>
C978
0.1U_0402_16V4Z
Issued Date
2006/09/25
2006/09/25
Deciphered Date
100K_0402_5%
Compal Secret Data
R988
2
LINE_OUTL
36
HP_LOUT_L
2N7002_SOT23
35
LINE_OUT_R
HP_LOUT_R
LINE_OUT_L
AUX_R
LINE_IN_L
R969
2.67K_0402_1%
AUX_L
15
MIC4
R169
SENSE_B
14
23
2
39.2K_0402_1%
1
R1915
10K_0402_5%
0.1U_0402_16V4Z
17
1
R970
C3
0.47U_0402_10V4Z~D
2
@
C393
10U_0805_10V4Z
DLINE_IN_RC_L
VDDA_CODEC
1
R973
2 1U_0603_10V4Z
R980
@ 0_0402_5%
2 1U_0603_10V4Z
<33,37>
1
2
0_0805_5%
C426 1
VDDA_CODEC
RHU002N06_SOT323
@ Q142
1
HP_L_JACK <33>
C175
6.04K_0402_5% DLINE_IN_R_L C423 1

2K_0402_5%
6.04K_0402_5% DLINE_IN_R_R C422 1
2K_0402_5%
2007,0125 change
SENSE_A
C425 1
INT_MIC
PAD
1
C156
T21
2 1U_0603_10V4Z
<33> INT_MIC
3 3
C147
0.1U_0402_16V4Z
0.1U_0402_16V4Z +3VS_CODEC
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
C395
DVDD2
1
0.1U_0402_16V4Z
R159
DVDD1
2
C431
+3VS
38
1
0.1U_0402_16V4Z
HP_R_JACK <33>
Q139@
RHU002N06_SOT323
R1399
25
2
C427
VDDA_CODEC
0_0603_5%
2
AVDD1
1
0.1U_0402_16V4Z
AVDD2
V_CODEC
2
C409
RHU002N06_SOT323
@ Q141
L_C_HP
1K_0402_5%
@R70
@
R70
<33>
10K_0402_5%
R1914
R1400
2
Place close to U14
D RHU002N06_SOT323
Q140@
1
2
300K_0402_5%
@ R62
1
2 2
10K_0402_5% G
+5VS
+3VS
Q138
@
@
1
@ R61
3 3
R_C_HP
Q68
RHU002N06_SOT323
<33>
0_0402_5%
1
D
4.7U_0603_6.3V6M
@C4
@
C4
1
2
0.1U_0402_16V4Z 150K_0402_1%
2
G
SB_SPKR
R35
1
D
2
G
<26>
10K_0402_5%
@
R57
R359
1
2
G
10K_0402_5%
C396
1
2
Title
AC97 CODEC AD1981B

Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:

G
Sheet
32
H
of
57
AMP. FOR INTERNAL SPEAKER

+5VALW
17
L_SPK-
NC1
NC2
NC3
NC4
3
10
13
16
C471
1
0.01U_0402_16V7K
JJ_MIC_REF
MAX9710ETP_QFN20
MIC_REF
Place close to U14 audio CODEC
R426
1
-
U27B
TLV2462_SO8
<32>
MIC1
<32>
MIC2
MIC_REF
2
G
100K_0402_5%
R251
100K_0402_5%
<39> DOCK_HPS#
D
2
G
1
1
S
0.1U_0603_50V4Z
2
2
Q44
C527
R255
2.2U_0603_6.3V4Z
EXT_MICA_2
R_HP
L_HP
MIC1
MIC2
MIC_SENSE
R_HP
L_HP
C441
0.1U_0402_16V4Z
TLV2462_SO8
O
1 C57210K_0402_5%
J_MIC1
68P_0402_50V8J
C489
1
2
100P_0402_50V8J
R414
1
2
R427
47K_0402_5%
C492
4.7U_0805_10V4Z 1
2
R1424
1
0_0402_5%
JJ_MIC_REF
2
R1423
1
@ 0_0402_5%
J_MIC_REF
JJ_MIC_REF
R429
47K_0402_5%
J_VDDA_CODEC
100K_0402_5%
U46B
ACES_87213-1200
DLINE_OUT_L
C536 100K_0402_5%
conn@
JP9
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
<39> DLINE_OUT_L
<39> DLINE_OUT_R
VDDA_CODEC
<32>
<32>
VDDA_CODEC
R423
R211
1
47K_0402_5%
VDDA_CODEC
<32> SENSE_A_A
U46A
R428
4.7U_0805_10V4Z 1
Q48
RHU002N06_SOT323
2
G
1 2
C493
D
1
2
L58
EXT_MICA_1 1
2
0.22U_0603_10V7K
J_VDDA_CODEC
R995
100K_0402_5%
<32> PORT_A_SNS
2
R978
100_0402_5%
47K_0402_5%
4.7U_0805_10V4Z
C276
1
2
100K_0402_5%
VDDA_CODEC
EXT_MICA
1 C982
J_VDDA_CODEC
VDDA_CODEC
VDDA_CODEC
Q49
RHU002N06_SOT323
100P_0402_50V8J
R413
1
2
C248
100P_0402_50V8J
Q32
RHU002N06_SOT323
<32>
C488
1
2
Place close to JP15

D
INT_MIC
INT_MIC
AMP. FOR EXTERNAL MICROPHONE
2
G
A_SD
SHDN
4.7U_0805_10V4Z
OUTL-
68P_0402_50V8J
2
1
2 LINE_C_R_OUTL
15K_0402_5% 10 dB
L_SPK+
1 C226
U27A
TLV2462_SO8
VDD
PVDD1
PVDD2
19
3K_0402_5%
<37>
14
MUTE
L57
C231
R388
INT_MIC_4
2
1
2INT_MIC_3
1
2 1
2
3K_0402_5%
1
0.22U_0603_10V7K
10K_0402_5%
C571
R193
2INT_MIC_1
R_SPK-
2
2
Q28
@ RHU002N06_SOT323
2
OUTL+
R196
1
1
100K_0402_5%
12
8
18
2 10K_0402_5%
1
@ 0_0402_5%
2
G
EAPD
OUTR-
PGND1
PGND2
PGND3
PGND4
PGND5
2
R1421
6
11
15
20
21
MUTE_LED#
R1406
R1407
2
1
0_0402_5%
R430 1
SLP_S3#
@ 1200P_0402_50V7K
VDDA_CODEC
1
2 LINE_C_R_OUTR
15K_0402_5% 10 dB
R_SPK+
OUTR+
INL
10K_0402_5%
10 dB
<32,37>
C585
1
2
2 1U_0603_10V4Z
VDDA_CODEC
PACDN042_SOT23~D
INT_MIC_2
1
2
C1044
BIAS
MIC_REF
ACES_85205-0200
Keep 10 mil width

R1405
LINE_C_R_OUTL
0.1U_0402_16V4Z
<26,29,32,37,39,40,47,48,49,50,51,52>
INR
conn@
JP36
0.1U_0402_16V4Z
U39
R1411
LINE_C_OUTL 1
C502
1
2
LINE_OUTL
2
2
1U_0603_10V4Z
10K_0402_5%
<32>
LINE_C_R_OUTR
C539
R1410
LINE_C_OUTR 1
C503
1
2
+
2
10 dB
0.1U_0402_16V4Z
1
C660
EXT_MICB
@C526
@
C526
C275
1
2
L61
R210
EXT_MICB_1 1
2
0.22U_0603_10V7K
10K_0402_5%
EXT_MICB_2
6
1
C470
C575
68P_0402_50V8J
1U_0603_10V4Z
2
RHU002N06_SOT323
TLV2462_SO8
3
C662
@
150U_D_6.3VM
O
-
J_MIC2
0_1206_5%
<32> LINE_OUTR
680P_0402_50V7K
R190
1
2
2
1
C446
100P_0402_50V8J
10U_0805_10V4Z
C230
1
2
D62
C659
10U_0805_10V4Z
C249
100P_0402_50V8J
AMP. FOR INTERNAL MICROPHONE

Place close to U14 audio CODEC
+5VAMP
R443
C1098
0.1U_0402_16V4Z
VDDA_CODEC
2
60.4_0805_1%
CHB1608B121_0603
R_CR_HP 1
R_CRL_HP
2
L52
J_DLINE_OUT_R
J_DLINE_OUT_L
<32>
R445
Vn
Vp
CH2 CH3
100P_0402_50V8J
2
100P_0402_50V8J
1
1
C514
C507
2
1
SUYIN_010030FR006G101ZL_6P
conn@
C564
1K_0402_1%
MIC_SENSE
2
C984
0.1U_0402_16V4Z
R418
470P_0402_50V7K
Place close to U14
J_VDDA_CODEC
1
2
3
4
2
470_0402_5%
1
2
R425
470_0402_5%
conn@
1
2
3
4
1
2
3
4
5
6
1
2
3
4
5
6
J_MIC1
Place close to JP24
C487
EXT_MICB
EXT_MICA
R421
3.9K_0402_1%
1
C486
10U_0805_10V4Z
J_MIC_REF
conn@ JP28
1
2
3
4
5
6
Place close to JP15
100P_0402_50V8J
ACES_87213-0600
B
1
2
3
4
5
6
J_R_HP
J_L_HP
J_DLINE_OUT_L
J_DLINE_OUT_R
J_VDDA_CODEC
2006/09/25
Issued Date
Deciphered Date
L46
CHB1608B121_0603
1
2
L47
CHB1608B121_0603
C508
470P_0402_50V7K
3
6
2
1
1
C522
470P_0402_50V7K
SUYIN_010030FR006G101ZL_6P
conn@
10U_0805_10V4Z
2006/09/25
C
8
7
Compal Secret Data
5
4
J_MIC2
J_MIC_SENSE
ACES_87213-0600
C518 E&T_3801-04
JP15
J_MIC_SENSE
R424
3.9K_0402_1%
1
2
conn@ JP27
2
2
100P_0402_50V8J
A
+3VS
JP21
1
C506
2
G
S
@ S DIO(BR) NUP4301MR6T1 TSOP-6

L_SPK+
L_SPKR_SPK+
R_SPK-
C563
R446
1K_0402_1%
CH1 CH4
Q50
RHU002N06_SOT323
3
6
2
1
L_CRL_HP
470P_0402_50V7K
U73
1
Place close to JP24

1
<32>
L_C_HP
L51
L_CR_HP 1
CHB1608B121_0603
R979
47K_0402_5%
<32> SENSE_A_B
R253
1
2
60.4_0805_1%
R_C_HP
8
7
<32> HP_L_JACK
150U_D_6.3VM
J_R_HP 1
2
C577
J_L_HP
1
2
C581
150U_D_6.3VM
JP24
5
R261
1
<32> HP_R_JACK
Title

AMP & Audio Jack
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet
E
33
of
57
Left side
Left side
USB CONNECTOR 1
USB CONNECTOR 0
+5VALW
USB_VCCA
USB_VCCA
U57
+
2
<26>
<26>
0_0603_5%
USB20_N4 1
USB20_P4 1
0_0603_5%
USB20_N4
USB20_P4
USB20_P4
USB20_N4
1
2
3
4
GND
GND
GND
GND
1
2
3
4
5
6
7
8
0_0603_5%
USB20_N5_R
1
USB20_P5_R
1
0_0603_5%
SUYIN_020173MR004S558ZL
R606
2USB20_N5
2USB20_P5
R607
USB20_N5 <26>
USB20_P5 <26>
1
R4
0_0805_5%
USB20_P5
USB20_N5
0904 change for EMI
+5VALW
10K_0402_5%
1
2
3
4
GND
GND
GND
GND
0904 change for EMI
R163
1
2
3
4
5
6
7
8
0_0805_5%
R73
S4_STATE
1
R604
2USB20_N4_R
2USB20_P4_R
R605
conn@JP25
conn@
JP25
D52
PJDLC05_SOT23~D
R56
G548A2P1U
conn@
D51
PJDLC05_SOT23~D
1
W=100mils
8
7
6
5
OUT
OUT
OUT
OC#
C519
1000P_0402_50V7K
4.7U_0805_10V4Z
GND
IN
IN
EN#
C515
0.1U_0402_16V4Z
C550
C567
150U_D_6.3VM
1
2
3
4
JP23
0_0805_5%
Right side USB CONNECTOR 0

1394 connector
+5VALW
11/06 fix DB2 1394 can not detect issue
USB_VCCC
U65
TPS2061IDGN_MSOP8~N
4.7U_0805_10V4Z
JP26
W=60mils
8
7
6
5
1
1
+
2
0_0603_5%
C521
1000P_0402_50V7K
OUT
OUT
OUT
OC#
C517
0.1U_0402_16V4Z
C558
GND
IN
IN
EN#
C569
150U_D_6.3VM
1
2
3
4
<26>
<26>
USB20_N0
USB20_P0
0_0603_5%
R617
2USB20_N0_R
2USB20_P0_R
R614
1
1
1
2
3
4
5
6
7
8
conn@
C
1
2
3
4
GND
GND
GND
GND
2007,0125 change
conn@
JP19
<31>
<31>
<31>
<31>
XTPB0XTPB0+
XTPA0XTPA0+
XTPB0XTPB0+
XTPA0XTPA0+
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
1
1
1
2
2
2
2
R1697
R1696
R1699
R1698
R_XTPB0R_XTPB0+
R_XTPA0R_XTPA0+
+5VALW
1
R164
+5VALW
USB20_P0
USB20_N0
10K_0402_5%
1
2
3
4
5
6
7
8
XTPB0XTPB0+
XTPA0XTPA0+
GND
GND
GND
GND
R1
D
D61
PJDLC05_SOT23~D
conn@ JP22
+3VAUX_BT
R562
USB20_P6_R
USB20_N6_R
2
2
@ R458 1
@R458
@R459
@
R459 1
2
2
1 0_0402_5%
1 0_0402_5%
USB20_P6
USB20_N6
R586
1K_0402_5%
1K_0402_5%
USB20_P6 <26>
USB20_N6 <26>
BT_LED <36>
CH_DATA <31>
CH_CLK
<31>
1
2
3
4
5
6
7
8
2
<26> S4_STATE#
G
Q132
RHU002N06_SOT323
S4_STATE
S4_STATE
<36>
AMP_440168-2
10K_0402_5%
ACES_87212-0800
D53
@ PACDN042_SOT23~D
SMART Card connector
+SC_PWR
BT Connector
1
SC_CLK
SC_RST
+3VALW
C367
+3VAUX_BT
Q51
3
SC_DATA <31>
2
1
SC_DATA
SI2301BDS_SOT23
0.1U_0402_16V4Z
SC_CD#
SC_CLK <31>
SC_RST <31>
+SC_PWR
SC_CD#
<31>
conn@
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
1
2
3
4
5
6
7
8
9
10
C306
R518
1U_0603_10V4Z
100K_0402_5%
C546
JP3
1
2
3
4
5
6
7
8
9
10
ACES_85203-1002
1
C549
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
1
C545
0.01U_0402_16V7K
<26>
BT_OFF
R454
1
2
47K_0402_5%
C556
1
2
0.1U_0402_16V4Z
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
5
Title

USB & BT Connector
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
34
of
57
+3VS
RP3
DCD#1
RI#1
CTS#1
DSR#1
1
2
3
4
8
7
6
5
+5VS
2
4.7K_1206_8P4R_5%
IRRX
1
2
R76
1K_0402_5%
D36
CH751H-40_SC76
+5VS_PRN
<26,37> NPCI_RST#
<28,31,36> PLT_RST_B#
+3VS
10K_1206_8P4R_5%
R120
SIO_IRQ
1
2
R121
10K_0402_5%
SIO_DPIO45
1
2
10K_0402_5%
2 0_0402_5%
2 @ 0_0402_5%
2 10K_0402_5%
1
1
1
+3VS
1
R67
<25,36,37> LPC_FRAME#
<25> LPC_DRQ#0
15
16
LFRAME#
LDRQ#
17
18
PCI_RESET#
LPCPD#
PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#
<26,31,36,37> PM_CLKRUN#
<15> CLK_PCI_SIO
<26,31,36,37> SIRQ
2
10K_0402_5%
CLK_14M_SIO
<15> CLK_14M_SIO
SIO_GPIO40
PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ
R119
CARD_ID#
LPC_FRAME#
LPC_DRQ#0
SIO_RST#
SIO_PD#
+3VS
1
LAD0
LAD1
LAD2
LAD3
10K_0402_5%
<39>
SER_SHD
R68
1
EXPCRD_RST#
EXPCRD_RST#
<39> EXPCRD_RST#
10K_0402_5%
R77
PID0
CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#
CLK14
23
24
25
27
28
29
30
31
32
33
34
35
36
40
62
63
64
1
2
3
4
5
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRRX2
IRTX2
IRMODE/IRRX3
37
38
39
IRRX
INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#
41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61
LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#
VTR
VCC
VCC
VCC
VCC
7
11
26
45
54
FIR
CLOCK
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23
8
22
43
52
+3VS
1
19
20
21
6
RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#
SERIAL I/F
R108
R109
R99
10
12
13
14
VSS
VSS
VSS
VSS
PARALLEL I/F
SIO_GPIO12
SIO_GPIO10
SIO_GPIO44
SIO_GPIO43
1
2
3
4
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
GPIO
RP6
8
7
6
5
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC I/F
U8
<25,36,37>
<25,36,37>
<25,36,37>
<25,36,37>
POWER
10K_0402_5%
RXD1
<39>
R64
1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
1K_0402_5%
2
<39>
<39>
<39>
<39>
<39>
<39>
<39>
RP51
IRRX
<31>
IRTXOUT <31>
IRMODE <31>
LPD3
LPD2
LPD1
LPD0
RP52
C84
C88
C76
1
2
3
4
8
7
6
5
4.7K_1206_8P4R_5%
LPTINIT# <39>
LPTSLCTIN# <39>
LPD0
<39>
LPD1
<39>
LPD2
<39>
LPD3
<39>
LPD4
<39>
LPD5
<39>
LPD6
<39>
LPD7
<39>
LPTSLCT <39>
LPTPE
<39>
LPTBUSY <39>
LPTACK# <39>
LPTERR# <39>
LPTAFD# <39>
LPTSTB# <39>
8
7
6
5
4.7K_1206_8P4R_5%
LPD7
LPD6
LPD5
LPD4
RP53
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
1
2
3
4
8
7
6
5
4.7K_1206_8P4R_5%
RP54
1
2
3
4
LPTSTB#
LPTAFD#
LPTERR#
8
7
6
5
4.7K_1206_8P4R_5%
R480
LPTSLCTIN#
LPTINIT#
4.7K_0402_5%
R481
1
2
+3VS
1
2
3
4
4.7K_0402_5%
C57
LPC47N217_STQFP64
R79
3
Base I/O Address

0 = 02Eh
* 1 = 04Eh
PID1
2
3
10K_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
R80
1
SIO_GPIO11
10K_0402_5%
R100
SIO_GPIO40
CLK_PCI_SIO
CLK_14M_SIO
10K_0402_5%
R81
@ 10_0402_5%
2
R96
@ 10_0402_5%
1
C94
@18P_0402_50V8J
C70
@10P_0402_25V8K
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
A
Title

SUPER I/O LPC47N217
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

E
35
of
57
BIOS ROM
Debug port
20mils
R1945
2
+3VM
<26>
SPI_CS0#
0.1U_0402_16V4Z
D
SPI_SI
VCC
SPI_WP#
HOLD
SPI_CS0#
2 R1290 SPI_CLK_0 6
2 R1294 SPI_SI_0
VSS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
B+
<37> STB_LED#
<37> CAPS_LED#
<37> NUM_LED#
<37,41> VCC1_PWRGD
SPI_CLK_L
SPI_CS0#
SPI_SI_L
SPI_SO_L
SPI_SO_L01
SPI_SO
2
15_0402_5%
SPI_SO
<26>
WIESO_G6179-100000_8P
20mils R1288
1
SPI0 (16M*1)
R1794
2 SPI_HOLD#_0
3.3K_0402_5%
R1924
0_0402_5%
SPI_CLK_L
VCC
SPI_WP#
SPI_HOLD#_0
HOLD
SPI_CS1#
2 R1296 SPI_CLK_1 6
2 R1295 SPI_SI_1
SPI_WP#
@R1724
@
R1724
0_0402_5%
SPI_CS1#
@ 47_0402_5%
SPI_CLK_L
1
@ 47_0402_5%
SPI_SI_L
1
<26>
SPI_SI
SPI_SI
<26>
SPI_CLK
<26>
R170
CLRP3
R201
R202
0_0402_5%
SPI_CLK
1
2
1
1
SPICLK
SPICS0#
2SPISI
2SPISO
SPI_HOLD#_0
SPI_CS1#
2
0_0402_5%
SHORT PADS
0_0402_5%
0_0402_5%
Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved
ACES_87216-2404_24P
conn@
0907 Add 0 ohm for SPI
0629 Change Pin3 to Pin23, change Pin24 to GND

@ R1297
SPI_SO_L11
2
15_0402_5%
SST25LF080A_SO8-200mil
Q
@
C
VSS
SPI_SO_L
U67
8
0_0402_5%
2
R1795
20mils
C993
0.1U_0402_16V4Z
R1287
3.3K_0402_5%
SPI_SI_L
+3VM
+3VM
@ R118 0_0402_5%
1
2
@ R123 0_0402_5%
1
2
<25,35,37>
<25,35,37>
<25,35,37>
<25,35,37>
R1291
Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
<25,35,37> LPC_FRAME#
+3VS
<7,24,28> PLT_RST#
SPI_HOLD#_0
C989
47_0402_5%
1
47_0402_5%
1
SPI_CLK
+3VM
JP52
0_0402_5%
U66
2007,0125 change
SPI1 (16M*1)
0821 SPI1 no install

0906 SPI1 install
+3VS
47K
TPM1.2
Q75
DTA114YKA_SC59
10K
+3VS+3VALW
BT_LED
2
18P_0402_50V8J
C1057 1
2
TPM_XTALI
1
3
12
R1381
32.768KHZ_12.5P_1TJS125BJ2A251
IN
NC 2
1
4
SLB9635TT_TSSOP28
OUT
NC
WP_LED# <31>
Y8
TPM_XTALO
C1056 1
10M_0402_5%
R505
100K_0402_5%
1
T42
Q89 @
DTA114YKA_SC59
WL_LED
10K
2
G
<34>
47K
WL_BLUE_LED# <31,38>
1
Q79
RHU002N06_SOT323
+3VS
1
R1378
@ 4.7K_0402_5%
TPM_32K_CLK <37>
0_0402_5%
2
@ 0_0402_5%
PAD
NC
NC
NC
4
11
18
25
R1409
2
6
TPM_XTALO
TPM_XTALI 1
R101
PAD
T41
WL_LED# <31>
Q78
RHU002N06_SOT323
2
G
3
2
GPIO2
GPIO
0_0402_5%
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
14
13
LPC_PD# <26>
XTALO
XTALI
TPM
SLB 9635 TT 1.1
LPC_PD#
R1379 2
21
22
16
27
15
7
28
9
8
CLK_PCI_TCG
<15> CLK_PCI_TCG
LPC_FRAME#
<25,35,37> LPC_FRAME#
PLT_RST_B#
<28,31,35> PLT_RST_B#
SIRQ
<26,31,35,37> SIRQ
PM_CLKRUN#
<26,31,35,37> PM_CLKRUN#
1
2
+3VS
R1380
@ 4.7K_0402_5%
LPCPD#
TESTB1/BADD
TEST1
LAD0
LAD1
LAD2
LAD3
2
Q88
DTA114YKA_SC59
4.7K_0402_5%
26
23
20
17
10K
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
0.1U_0402_16V4Z
R1377
GND
GND
GND
GND
<25,35,37>
<25,35,37>
<25,35,37>
<25,35,37>
BLUE
47K
VDD
VDD
VDD
U69
Base I/O Address

+3VS
0 = 02Eh
* 1 = 04Eh
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
WW_LED# <31>
+3VS
C1052
VSB
C1053
24
19
10
0.1U_0402_16V4Z
1
1
C1054
C1055
Mini-PCIE Card LED
R504
100K_0402_5%
18P_0402_50V8J
0.1U_0402_16V4Z
+3VS
R1941
JP38
SI2301BDS_SOT23
+3VALW
Q145
3
ACES_85205-0400
conn@
10K_0402_5%
@
+3V_FP
D54
@ PACDN042_SOT23~D
1
2
3
4
R1334
R1335
<26> USB20_N1
<26> USB20_P1
1
2
3
4
0_0402_5%
2
1 USB20_N1_R
2
1USB20_P1_R
0_0402_5%
S4_STATE <34>
Compal Secret Data
2006/09/25
Issued Date
C206
+3V_FP
Finger printer
Deciphered Date
2006/09/25
5
Title

TCG/BIOS ROM/PS2/LED/SW
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
36
of
57
1070@
2
1
0_0603_5% R1477
+3VL
PWR1
1
2
1
0_0603_5% R1478
1021@
+3VS
C39
0.1U_0402_16V4Z
1
C37
0.1U_0402_16V4Z
1
C52
0.1U_0402_16V4Z
C51
0.1U_0402_16V4Z
C36
0.1U_0402_16V4Z
C34
4.7U_0805_10V4Z
0_0402_5%
2
1 PWR_GD
+3VL
1021@ R1642
R1646
2
1
+3VS
1070@ 0_0402_5%
1
T32 T33
0.1U_0402_16V4Z
C75 PAD
PAD
1070@
2
PM_SLP_M#
2/22 change
1
2
R38
0_0402_5%
GPIO30
R141 1
+3VL
D
10K_0402_5%
R580
1
2 TP_DATA
10K_0402_5%
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
<38>
<38>
<39>
<39>
<39>
<39>
10K_1206_8P4R_5%
+3VS
TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
<26,31,35,36> PM_CLKRUN#
<26,31,35,36> SIRQ
<15> CLK_PCI_EC
<26> RUNSCI_EC#
R1289
<25,35,36>
<25,35,36>
<25,35,36>
<25,35,36>
2RUNSCI_EC#
10K_0402_5%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<25,35,36> LPC_FRAME#
<26,35> NPCI_RST#
<50>
ADP_PS1
CLK_PCI_EC
R74
120K_0402_5%
@ 2M_0402_5%
R75
2
1
R86
1
IN
NC
OUT
55
57
54
76
CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
51
50
48
46
LAD[3]
LAD[2]
LAD[1]
LAD[0]
LPC_FRAME#
52
53
45
LFRAME#
LRESET#
LPCPD#/GPIO23
70
71
XTAL1
XTAL2
68
VCC0
@R1925
@
R1925 0_0402_5%
1
2
+RTCVCC
+3VL
18P_0402_50V8J
C349
0_0402_5%
1
2
@ R1926
1
2
0_0402_5%
2
R1942
1U_0603_10V4Z
C661
18P_0402_50V8J
C350
@ 10P_0402_50V8J
Y2
1
C80
NC
@ 10_0402_5%
2
PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#
CRY1
CRY2
IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT
Power Mgmt/SIRQ
LPC
Bus
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8
7
6
5
1
2
3
30
31
32
33
34
43
44
1
2
3
4
AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
CAP
1
2
3
4
8
7
6
5
4.7K_1206_8P4R_5%
PM_SLP_M# <26,40,47,48,52>
GPIO29
EAPD
2 0_0402_5%
1
PCI_SERR# <24,31>
1070@
10U_0805_10V4Z
C1289
2
93
98
99
100
126
15
49
1
2
0_0402_5% R1726
<26>
<32,33>
BIOS debug port

Place under KB area
AMT ADP_PRES <26>

+3VL
R575
OUT0
OUT1/IRQ8#
124
125
KBC_PWR_ON
GREEN_BATLED#
OUT7/SMI#
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1
123
122
121
120
118
BATSELB_A#
KBRST#
A_SD
FAN_PWM
CHGCTRL
GPIO01
GPIO02
GPIO03
GPIO04/KSO14
GPIO05/KSO15
107
79
80
81
83
GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD
85
86
87
RSMRST_EC
CRACK_BGA
EC_GPIO9
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M
88
89
90
91
92
101
102
AB2A_DATA R156
AB2A_CLK R155
AB2B_DATA R140
AB2B_CLK R154
BATCON
THM_MAIN#
A20M
GPIO20/PS2CLK
GPIO21/PS2DAT
GPIO24/KSO16
GPIO27
103
105
4
74
KB_RST#
<25>
CH751H-40_SC76
@ ACES_85201-0602
2
2
R581 1
2
10K_0402_5%
T37
1
+3VL
THM_MAIN# 1 R600
2
210K_0402_1%
ADP_PS1
1
2
R538
@ 100K_0402_5%
EC_GPIO27 1 R33
2
100K_0402_5%
+3VL
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
BATCON <45>
THM_MAIN# <43>
1
1
1
1
EC_GPIO27 2
EC_GPIO9
CRACK_BGA
THM_MBAY# <43>
ON/OFFBTN_KBC# <38>
LOW_BAT# <26>
KSO14
<38>
KSO15
<38>
RSMRST_EC <26>
4.7K_0402_5% R20 1
4.7K_0402_5% R18 1
Cap_DAT <38>
Cap_CLK <38>
ME_EC_DATA1 <26>
ME_EC_CLK1 <26>
1
+3VL
D6 CH751H-40_SC76
2
GATEA20 <25>
R282
C92
CLK_14M_KBC 1
NUM_LED# <36>
SLP_S3# <26,29,32,33,39,40,47,48,49,50,51,52>
PAD
1
2
3
4
5
6
VCC1_PWRGD
D7
1
A_SD
<33>
FAN_PWM <4>
CHGCTRL <44,45>
THM_MBAY#
ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15
NUM_LED#
SLP_S3#
JP43
KBC_PWR_ON <46>
10K_0402_5%
GREEN_BATLED# <25,31>
BATSELB_A# <45>
+3VL
RP60
General Purpose I/O Interface
TP_CLK
2 1
10_0402_5% 10P_0402_25V8K
@
@
Pin1 250 -- TEST Pin ( NC !! )

Pin57 250 -- MODE
ADP_PRES <29,44,45,46,50>
D10 CH751H-40_SC76
R25
Access Bus Interface
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC2
35
36
38
40
41
42
R578
1
AB1A_DATA
AB1A_CLK
111
112
AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK
109
110
AB1B_DATA
AB1B_CLK
73
Cap_INT
108
59
75
60
78
77
61
EA#
CLK_14M_KBC
32K_CLK
PM_POK
PWR_GD
VCC1_PWRGD
PGM Strap/GPIO25
Miscellaneous
TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
KSI[0..7]
AGND
<38>
VCC1
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
Pin3 250 : KSO12/OUT8/KBRST

+5VS
+3VL
RP1
CRACK_BGA
EA Strap#/GPIO26/KSO17
CLOCKI
32KHZ_OUT/GPIO22
RESET_OUT#/GPIO06
PWRGD
VCC1_PWRGD
24MHZ_OUT/GPIO19/WINDMON
TEST PIN
69
FWP#
AB1A_DATA <43>
AB1A_CLK <43>
Cap_INT
<38>
CLK_14M_KBC <15>
Pin50 250 -- 24MHz_Out

TEST
1
Pin52 250 -- XOSEL
R977
PM_POK <49>
PWR_GD <21,26,31,40,41,49,50>
VCC1_PWRGD <36,41>
ADP_PS0 <50>
+3VL
2
300_0402_5%
JP31
Pin91 250 -- nDMS_LED
DMS_LED#/GPIO10
BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX
116
113
115
114
PM_POK
10K_0402_5%
AB1B_DATA <43>
AB1B_CLK <43>
ADP_ID
<50>
AMBER_BATLED# <31>
STB_LED# <36>
CAPS_LED# <36>
AMBER_BATLED#
STB_LED#
CAPS_LED#
R58
R59
R60
+3VL
VCC1_PWRGD
2 100K_0402_5% NUM_LED#
2 100K_0402_5% STB_LED#
2 100K_0402_5% CAPS_LED#
1
1
1
R62 250@
NC
NC
NC
NC
NC
NC
29
28
27
26
25
24
23
22
10K_1206_8P4R_5%
Remove from daughter board
1
2
3
4
5
6
@ ACES_85201-0602
KBC1070_VTQFP128
62
63
64
65
66
67
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSI7
KSI6
KSI5
KSI4
72
8
7
6
5
VCC1
VCC1
VCC1
VCC1
VCC1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18
SMSC_1070_TQFP-128P
21
20
19
18
17
16
13
12
10
9
8
7
6
5
Keyboard/Mouse Interface
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
RP59
11
37
47
56
104
82
117
KSO[0..13]
KSO[0..13]
39
58
84
106
14
U47
<38>
10K_1206_8P4R_5%
1
2
3
4
94
95
96
97
127
128
KSI0
KSI3
KSI2
KSI1
NC
NC
NC
NC
NC
NC
8
7
6
5
119
PWR1
RP58
1
2
3
4
For KBC debugging used.
C1317
0.1U_0402_16V4Z
32.768KHZ_12.5P_1TJS125BJ2A251
11/20 for solve PM_PWROK glitch on power up
U87
STB_LED#
A1
GND
100K_0402_5%
3
A
A2
Y1
VCC
Y2
LED_STB# <31,38,39>
+3VALW
+3VL
FWP#
0.1U_0402_16V4Z
R29
1
<21,26,31,40,41,49,50> PWR_GD
<49> PGOOD_PU19
+3VL
U89
0_0402_5%
R1810
IN1
PM_PWROK <26>
IN2
NC7WZ07P6X_NL_SC70-6
C58
1
AGND FILTER
VGATE <7,26>
R28
32K_CLK
R91
0_0402_5%
R97
2 @ 0_0402_5%
ADP_EN
FWP#
2
1
@ 1K_0402_5%
TEST
2
1
@ 1K_0402_5%
EA#
<50>
TPM_32K_CLK <36>
R78
R27
1
1K_0402_5%
4
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
3
Title

LPC47N1021
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

1
37
of
57
SWITCH BOARD.
220P_0402_50V4Z
2
220P_0402_50V4Z
2
0622 change
@ R21
0_0402_5%
Cap_RST#
1
2
Cap_CLK <37>
Cap_INT <37>
WL_BLUE_LED# <31,36>
1
2
3
4
5
6
7
8
LID_SW#
1
2
3
4
5
6
7
8
LID_SW#
LED_STB#
ON/OFF#
KSI[0..7]
JP6
<17,26>
ON/OFF#
LID_SW#
Aces_85203-08421-11
@ D81
0829 Change to WL_BLUE_LED#
WL,Vol up,Vol down,Mute,Present button
On/off ,information button

+3VS
CP1
HDA_SDOUT_MDC
<25> HDA_SDOUT_MDC
R1313 HDA_SYNC_MDC
2
1HDA_SDIN1_MDC
33_0402_5%
<25> HDA_SYNC_MDC
<25> HDA_SDIN1
1
3
5
7
9
11
KSO9
KSI6
KSI7
KSI1
+3VS
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
2
4
6
8
10
12
0_0402_5%
HDA_BITCLK_MDC <25>
4
3
2
1
4
3
2
1
5
6
7
8
100P_1206_8P4C_50V8
CP5
KSO6
KSO3
KSO12
KSO13
5
6
7
8
100P_1206_8P4C_50V8
4
3
2
1
5
6
7
8
100P_1206_8P4C_50V8
TYCO_1-179396-2~D
CP7
KSI3
KSO5
KSO1
KSI0
Connector for MDC Rev1.5
0620 RESERVE FOR MDC
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
CP6
KSO2
KSO4
KSO7
KSO8
5
6
7
8
CP3
KSI2
KSO0
KSI5
KSI4
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
4
3
2
1
100P_1206_8P4C_50V8
HDA_BITCLK_MDC
HDA_RST#_MDC_R
R1753
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
C5
11/06 follow UMA SI-2 design change

JP32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
conn@
FOX_GB1SV301-160K-7F
0.1U_0402_16V4Z 1
MDC 1.5 Conn.
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
LED_STB# <31,37,39>
PJDLC05_SOT23~D
ACES_85203-1002
conn@
KSO[0..15]
JP18
Cap_RST#
KSI[0..7]
+3VALW
@JP20
@
JP20
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
C1
10P_0402_50V8K
@
+3VS
2
4
6
8
10
KSO[0..15]
<37>
2
+3VL
2007,0125 change
<37>
R30
10K_0402_5%
Cap_DAT
ON/OFF#
0901 Change Cap_RST#_SB to SB GPIO28
<37>
INT_KBD CONN.
LED_STB#
C750
Cap_RST#_SB <26>
Cap_INT
1
3
5
7
9
C749
1
conn@
4
3
2
1
CP2
KSO14
KSO11
KSO10
KSO15
5
6
7
8
100P_1206_8P4C_50V8
Power button
TrackPoint CONN.
+3VL
4
3
2
1
5
6
7
8
100P_1206_8P4C_50V8
T/P BOARD.
+5VS
1U_0603_10V4Z
1U_0603_10V4Z
C321
SP_DATA
0.1U_0402_16V4Z
2
G
Q70
RHU002N06_SOT323
ON/OFFBTN#
SP_CLK
conn@
R8
1
2
100K_0402_5%
TP_DATA
TP_CLK
@ PACDN042_SOT23~D
TP_DATA
TP_CLK
+5VS
1
2
3
4
5
6
7
8
C319
0.1U_0402_16V4Z
ACES_87212-0800
D67
TP_DATA
TP_CLK
100K_0402_5%
1
C11
+5VS
ACES_87153-0801L
ON/OFFBTN_KBC# <37>
JP17
<37>
<37>
I
G
13
1
SP_CLK
conn@
D58
PJDLC05_SOT23~D
ON/OFFBTN# <26>
D42
CH751H-40_SOD323
C23
ON/OFF#
ON/OFFBTN_KBC#
+3VALW
3
14
P
2
<39>
100K_0402_5%
U5F
SN74LVC14APWLE_TSSOP14
R26
2
O 12 1
2
4
6
8
1
1
R22
ON/OFF#
1
3
5
7
SP_DATA
100K_0402_5%
+5VS
JP14
R536
Compal Secret Data
Issued Date
2006/09/25
Deciphered Date
2006/09/25
Title

MDC/KBD/ON_OFF/LID
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet
38
of
57
+5VALW
DOCK CONN. 184PIN
R529
100K_0402_5%
JP29
VIN
10P_0402_50V8J
1000P_0402_50V7K
2
SLP_S5#_5R
<40>
SLP_S5
1000P_0402_50V7K
DOCK_MOD_RING
DOCK_MOD_TIP
Q65
2
G
SWAP
JP30A
22P_0402_50V8J
ON/OFF#
MDO2+
MDO2-
<30>
<30>
MDO0+
MDO0-
<16>
D_VSYNC
<16>
D_HSYNC
<16> D_DDCDATA
<16> D_DDCCLK
<19> DVI_DETECT
P1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
<35>
LPTACK#
<35>
LPTBUSY
<35>
LPTPE
<35>
LPTSLCT
<35>
LPD7
<35>
LPD6
<35>
LPD5
<35>
LPD4
<35>
LPD3
<35>
LPD2
<35>
LPD1
<35>
LPD0
<35> LPTSLCTIN#
<35>
LPTINIT#
DOCKVIN
ON/OFF#
MDO2+
MDO2MDO0+
MDO0-
0314 change
R1404
DOCK_RED
1
2
DOCK_GRN
1
2
DOCK_BLU
1
2
R1428
R1429
<16,19> COMP
HLC0603CSCCR11JT_0603 <16,19> CRMA
HLC0603CSCCR11JT_0603 <16,19> LUMA
D_DDCDATA
D_DDCCLK
DVI_DETECT
RED
GREEN
BLUE
<32> LINE_IN_SENSE
<50> ACOCP_EN#
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
<35>
<35>
<35>
LPTSTB#
LPTAFD#
LPTERR#
DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
LPTSTB#
LPTAFD#
LPTERR#
DETECT
MDO3+
MDO3-
MDO3+
MDO3-
<30>
<30>
MDO1+
MDO1-
MDO1+
MDO1-
<30>
<30>
PWR_LED
1
R515
DVI_CLK
DVI_DAT
SLP_S5#_5R
1K_0402_5%
DVI_CLK
DVI_DAT
DVI_TX2-
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#
<19>
<19>
DVI_TX2- <19>
DVI_TX2+
DVI_TX2+ <19>
DVI_TX1-
DVI_TX1- <19>
<26>
DVI_TX1+
USB20_N7
DVI_TX1+ <19>
DVI_CLK-
DVI_CLK- <19>
DVI_CLK+
USB20_P9
<35>
SER_SHD
<35> EXPCRD_RST#
DVI_TX0- <19>
DVI_TX0+
USB20_P7
USB20_N9
<26>
DVI_CLK+ <19>
DVI_TX0-
<26>
<26>
SER_SHD
EXPCRD_RST#
DETECT
DVI_TX0+ <19>
DOCK_ADP_SIGNAL
DOCK_ID
DOCK_ID <26>
+3VS
R1387
DOCK_ID
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
GND
GND
GND
GND
GND
GND
178
180
182
174
171
170
P2
167
KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#
KBD_DATA <37>
KBD_CLK <37>
CPPE#
<15>
PS2_DATA <37>
PS2_CLK <37>
DOCK_HPS# <33>
DLINE_IN_L
DLINE_IN_R
DLINE_IN_L <32>
DLINE_IN_R <32>
DLINE_OUT_L
DLINE_OUT_R
DLINE_OUT_L <33>
DLINE_OUT_R <33>
PCIE_TXP5
PCIE_TXP5 <26>
PCIE_TXN5
PCIE_RXP5_DOCK
PCIE_TXN5 <26>
1 R1346 2PCIE_RXP5
0_0402_5%
1 R1347 2PCIE_RXN5
0_0402_5%
PCIE_RXN5_DOCK
CLK_PCIE_DOCK
PCIE_RXP5 <26>
PCIE_RXN5 <26>
CLK_PCIE_DOCK <15>
CLK_PCIE_DOCK#
CLK_PCIE_DOCK# <15>
PREP#
VA_ON#
176
169
175
179
181
177
PREP#
GND
GND
GND
GND
GND
GND
165
G2
1K_0402_5%
+5VS
<26,30,32>
C59
0.1U_0402_16V4Z
C678
1
ADP_SIGNAL
2
@ 22U_1206_10V4Z
DOCK_MOD_RING
R1401
DOCK_ADP_SIGNAL 1
R66
@ 10K_0402_5%
JAE_SP03-14588-PCL03
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
<38>
<30>
<30>
LED_ACT_LAN#_DOCK
LED_LINK_LAN#_DOCK
<19>
<19>
<19>
G1
173
22P_0402_50V8J
conn@
conn@
172
166
RING
TIP
168
DOCK_MOD_TIP
3
22P_0402_50V8J
2
E-T_3800-02_2P
RHU002N06_SOT323
JP30B
C1630
DOCK_RED
1
C1631
DOCK_GRN
1
C1632
DOCK_BLU
1
conn@
2
1
BLUE
10P_0402_50V8J
C748
1
L10
KC FBM-L18-453215-900LMA90T_1812
2
1
DOCKVIN
1
1
C72
C73
GREEN
C747
10P_0402_50V8J
1
C746
RED
JAE_SP03-14588-PCL03
1K_0402_1%
D59
@ PACDN042_SOT23~D
3
Closed to JP30
+3VS
+3VS
U52
5
<19>
<16>
BLUE
L_BLUE
L_BLUE
ISO_PREP#
<26> ISO_PREP#
1
2
A
B
OE
+3VS
<19>
GREEN
<16> L_GREEN
VCC
L_GREEN
1
2
A
B
ISO_PREP#
OE
GND
GND
FSA66P5X_SC70-5
<19>
<16>
RED
L_RED
10K_0402_5%
100P_0402_50V8J
PWR_LED
1
1
2LED_LINK_LAN#_DOCK
0_0402_5%
100P_0402_50V8J
@ C1628
2
1
<31,37,38> LED_STB#
<26,29,32,33,37,40,47,48,49,50,51,52>
B
SLP_S3#
2
G
Q59
RHU002N06_SOT323
S
LED_LINK_LAN# <26,29,30>
GND
R526
Compal Secret Data
2006/09/25
Issued Date
3
Q63
RHU002N06_SOT323
2
G
OE
C1627
R1938
LED_LINK_LAN#_DOCK_R
A
B
+3VALW
1
2
LED_ACT_LAN#_DOCK
@
2
LED_ACT_LAN# <29,30>
L_RED
ISO_PREP#
R1937
1
2
0_0402_5%
Q62
RHU002N06_SOT323
2
G
R527
2
1
10K_0402_5%
LED_ACT_LAN#_DOCK_R
D
VCC
+3VM_LAN
FSA66P5X_SC70-5
FSA66P5X_SC70-5
U50
U51
VCC
2006/09/25
Deciphered Date
C
Title

Docking CONN.
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

E
39
of
57
+3VALW to +3VM Transfer
+1.25VM to +1.25VS Transfer
+3VALW
10U_0603_6.3V6M
C254
330U_D2E_2.5VM_R15
C1272
1
<26> LAN_WOL_EN
1
C128
+1.8V to VDD_MEM18 Transfer
Discharge circuit-2 for V-M
+1.8V
VDD_MEM18
2
+1.05VM
+1.25VM
0904 Add
U85
+3VM
C120
0.01U_0402_25V7Z
2
S
1
Q110
BSS138_SOT23
@R630
@
R630
100K_0402_5%
10U_0603_6.3V6M
C1619
0.1U_0402_16V4Z
@
@D76
@
D76
2
G
R631
470_0402_5%
1
1SS355_SOD323
1
2
R469
C132
0.01U_0402_25V7Z
SI4800DY_SO8
2 10U_0603_6.3V6M
R17 0_0402_5%
RUNON
1
2 +3VS_ON
2
SLP_S3 2
G
Q18
1 2
J34
SHORT PADS
0.1U_0402_16V4Z
1
2
3
4
R1940
100K_0402_5%
2007,0125 change
C121
8
7
6
5
C127
10U_0603_6.3V6M
470_0402_5%
1
BSS138_SOT23
Q116
U13
330K_0402_5%
C1275
0.1U_0402_16V4Z
Q108
BSS138_SOT23
+3VALW
B+
S
S
S
G
R470
Add
2
G
2
G
<26,37,47,48,52> PM_SLP_M#
LAN_WOL_EN#
+3VS
D
D
D
D
C1274
PM_SLP_M
2
2
+3VALW
8
7
6
5
SI4800DY_SO8
2
R1647
100K_0402_5%
+3VALW to +3VS Transfer
1
2
3
4
S
S
S
G
SI4800DY_SO8
2 10U_0603_6.3V6M
2
0_0402_5%
RUNON 1
2+1.25VS_ON
R1918
1
1SS355_SOD323
0.1U_0402_16V4Z
C1616
1
2
0.1U_0402_16V4Z
2
@ D75
@
0904
R139
D
D
D
D
C1271
R1643
100K_0402_5%
1
2
3
4
S
S
S
G
C1270
D
D
D
D
C1273
1
10U_0603_6.3V6M
+3VALW
U77
8
7
6
5
+1.25VS
8
7
6
5
+3VM
U78
B+
+1.25VM
R632
RHU002N06_SOT323
C1602
R633
2
G
Q112
RHU002N06_SOT323
1 2
1 2
LAN_WOL_EN#
LAN_WOL_EN#
S
RUNON
2
G
Q113
RHU002N06_SOT323
S
S
S
G
0.1U_0402_16V4Z
1
1
SI4800DY_SO8
2 10U_0603_6.3V6M
470_0402_5%
Q111
RHU002N06_SOT323
+5VALW to +5VS Transfer
2
G
3
LAN_WOL_EN#
470_0402_5%
1 2
47_0603_5%
D
D
D
D
1
2
3
4
C1601
330U_D2E_2.5VM_R15
C1604
2
1
2+1.8VS_ON
10K_0402_5%
R1919
D77
1
2
2
10U_0603_6.3V6M
C1617
0.001U_0402_50V7M
11/20 for ATI power sequence to install
1SS355_SOD323
+5VALW
C1603
+5VS
U9
0.1U_0402_16V4Z
SLP_S3#
100K_0402_5%
SLP_S3# 2
G
Q19
RHU002N06_SOT323
SLP_S4
D
<26,48> SLP_S4#
R135
2
G
Q23
RHU002N06_SOT323
R1895
100K_0402_5%
<39>
1
R129
100K_0402_5%
SLP_S5
SLP_S5
470_0402_5%
2
G
Q22
RHU002N06_SOT323
2
G
Q131
RHU002N06_SOT323
SLP_S3
SLP_S5#
<26,48> SLP_S5#
1 2
SLP_S3
<26,29,32,33,37,39,47,48,49,50,51,52>
R125
0904 Add
C1618
0.1U_0402_16V4Z
@
VDD_MEM18
+5VALW
@ D78
1SS355_SOD323
+3VL
+3VL
10U_0603_6.3V6M
C77
R1920
2+5VS_ON
1
0_0402_5%
1
RUNON
C71
SI4800DY_SO8
2 10U_0603_6.3V6M
1
2
3
4
S
S
S
G
D
D
D
D
8
7
6
5
C86
Discharge circuit-1
+1.8V
+1.8V
0.1U_0402_16V4Z
2
0_0402_5%
Q17
S
RHU002N06_SOT323
Q47
S
470_0402_5%
SLP_S3 2
G
R116
470_0402_5%
1 2
SLP_S3 2
G
1 2
Q27
R130
470_0402_5%
PWR_GD <21,26,31,37,41,49,50>
2
G
R151
SLP_S3 2
G
Q21
SLP_S3 2
G
2
G
Q16
Q90
4
S
RHU002N06_SOT323
RHU002N06_SOT323
2006/09/25
Issued Date
RHU002N06_SOT323
Compal Secret Data
2006/09/25
Deciphered Date
B
2
0_0402_5%
SLP_S5 1
2
@ R110 0_0402_5%
RHU002N06_SOT323
RHU002N06_SOT323
SLP_S4 1
R107
R1310
+5VS
470_0402_5%
+1.5VS
SLP_S5 1
@R1312
@
R1312
2
0_0402_5%
470_0402_5%
1 2
SLP_S4 1
R1311
C93
4
1 2
+1.5VS
R134
2
0.1U_0402_16V4Z
+2.5VS
470_0402_5%
R186
C184
+VCCP
+1.5VS
1
0.1U_0402_16V4Z
+3VS
+0.9V
+VCCP
+VCC_CORE
C91
Title

DC/DC Circuits
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet

E
40
of
57
PWR_OK circuit
1
@ 130K_0402_5%
1
2
C26
VCC1_PWRGD <36,37>
R1939
C32
1000P_0402_50V7K
1219 Add Schmitt Trigger to eliminate glitch and pull down resistor
49.9K_0402_1%
0_0402_5%
1
2
100K_0402_5%
R128
R1943
U5C
0.1U_0402_16V4Z
R14
+2.5VS
@ 100K_0402_5%
R5
1
2
VDD_MEM18
U5D
100K_0402_5%
14
PWR_GD <21,26,31,37,40,49,50>
LM393M_SO8 SHORT PADS
+3VL
10K_0402_5%
2 1
2 R1747
DDR_PGOOD 1
CH751H-40_SC76
14
+3VL
R24
VREF_393 2
J38
D69
R115
150K_0402_1%
R289
2
1
U91A
+3VS
20K_0402_5%
2
1
232K_0402_1%
R288
2
1
10K_0402_5%
2
+5VS
+3VL
R47
+5VALW
R285
VCCP_POK
D71
<52>
10K_0402_5%
2
1
+1.25VS
KBC PWR_OK circuit
+3VS
1M_0402_5%
R126
2
1
CH751H-40_SC76
1
2
Energy Star for CPU 1114 Add

+3VALW
R117
2
IN-
+5VALW
2
1
5
P
NC
M_PWROK <7,26>
LM393M_SO8
2
1
FM3
FM4
H1
HOLEA
FM5
CF10
1
CF11
1
CF12
1
CF13
1
H7
H8
HOLEAHOLEA
H9
HOLEA
H17
HOLEC
H18
HOLED
H19
H20
HOLED HOLED
H21
HOLED
H22
HOLED
H23
HOLED
H24
HOLED
H25
HOLED
H6
HOLEA
CF14
CF6
H5
HOLEA
CF9
1
H15
H16
HOLEC HOLEC
LAN_RST circuit
H4
HOLEA
CF8
1
H3
HOLEA
CF7
1
H2
HOLEA
1
1
FM2
1
FM1
1
C33
1000P_0402_50V7K
R39
56.2K_0402_1%
R178
1
1.24VREF
R49
10K_0402_5%
1000P_0402_50V7K
8
VREF_393
@R1934
@
R1934
100K_0402_5%
C1613
10K_0402_5%
1
2
76.8K_0402_1%
R1912
1
+3VM
@ C1623
2
0.1U_0402_16V4Z
U91B
M_PROK
R198
U90 @
SN74LVC1G14DCKR_SC70-5
4
VCC_IDL <26>
R1911
10K_0402_5%
1
2
<52>
1M_0402_5%
2
1
20K_0402_5%
CH751H-40_SC76
@ R52
20K_0402_5%
@C1622
@
C1622
2
0.1U_0402_16V4Z
DDR_PGOOD 1
100K_0402_5%
2
1
2
@R53
@
R53
1
LMV331IDCKRG4_SC70-5~D
+3VALW
R199
20K_0402_5%
D70
1
O
@ R1933
2
1.24VREF
@U88
@
U88
IN+
+VCC_CORE
MMBT3904_SOT23
+3VALW
@ R46
10K_0402_5%
20K_0402_5%
@R1931
@
R1931
2
1
@ D80
CH751H-40_SC76
1
Q134
2
B
+3VALW
Q133
RHU002N06_SOT323
<17>
+3VALW
2
1
1 2
2
1
3.3K_0402_5%
E_STAR
1M_0402_5%
@ R43
1
2
G
R284
+0.9V
DDR_PGOOD
1.8PGOOD
0_0402_5%
2
<48>
R1910
10K_0402_5%
11/20 Enable ACBS (power management for NIC)
O
U5A
H34
HOLED
H35
HOLED
H36
HOLED
H37
HOLED
H33
HOLED
H32
HOLED
H28
HOLED
H27
HOLED
H14
HOLEB
H13
HOLEB
H12
HOLEB
H11
HOLEB
C992
0.1U_0402_16V4Z
2
14
R1350
1
2
100K_0402_1%
3
1
O
7
2
2
C990
H10
HOLEB
CH751H-40_SOD323
0.1U_0603_50V4Z
14
R1732
2
1
120K_0402_5%
D60
+3VM
C991
0.1U_0402_16V4Z
+3VL
Need be tune to
10msec time delay
+3VL
LAN_RST# <26>
U5B
Compal Secret Data
2
Issued Date
2006/09/25
Deciphered Date
2006/09/25
Title

POK CKT
Size
Document Number
Rev
1A
LA3262P_DIS__M64
Date:
Sheet
41
of
57
+1.25VM
AC
Adapter
in
APL5912
LDO
(1.05V)
VIN
VS
+1.05VS
+3VS
G965
LDO
(2.5V)
Page46
Page37
Page41
+5VALWP
+1.25VM
SWITCH
ACOK
APL5912
LDO
(1.05V)
MAINPWON
+3VALWP
ENBL2 ENBL1
+1.05VM
+2.5VS 1A
Page46
4A
+5VS
B+
MAX8734A
DC/DC
(3V/5V)
+5VALWP
VMB
VIN
ISL6269
DC/DC
(VDD_CORE)
B+
PWR_GD
B+
VDD_CORE
VCC
SHDN#
Page45
4A
Page40
VS
+1.8VS
APL5912
LDO
(PCIE_VDD)
+3VLP 0.1A
PCIE_VDD
ISL6260 &ISL6208
DC/DC
(CPU_CORE)
Page43
Page45
BQ24703
Charger
MAX8743
DC/DC
(1.05V/1.5V)
B+
Page38
+1.5VSP 4.2A
CPU_CORE
( 44A)
SLP_S3#
ENBL1/ENBL2
Page41
+1.25VM
8A
+5VALWP
BATSELB_A
Battery
Selector
Circuit
BATSELB_A#
Battery A
6 Cell
Page39
VCC
Battery B
8 Cell
B+
VMB
SWITCH
SWITCH
SWITCH
Battery
Connector
Page37
A
VMB_A
VMB_B
Battery
Connector
Page37
B
SLP_S5#
TPS51116
DC/DC
(+1.8VP/+0.9VSP)
S3/S5
+1.8VP 7A
+0.9VP 2A
Page42
BATT
Title
BATT_A
POWER BLOCK DIAGRAM

BATT_B
Size
Date:
Document Number
Rev
Sheet
42
1
of
57
ADP_SIGNAL
PCN1
GND2
GND1
PWR2
ADPIN
FOX_JPD113E-LB103-7F
AB/I_A
PC2
1000P_0402_50V7K
GND3
4
3
PR1
@15K_0402_5%
PWR1
PC4
1000P_0402_50V7K
2
1
GND4
PC3
100P_0402_50V8J
2
1
VIN
PL1
SMB3025500YA_2P
GND5
SINGAL
GND6
PC1
100P_0402_50V8J
<44>
VMB_A
BATT_A
PL2
PCN2
PR2
1
1M_0402_1%
GND
EC_SMD_A
EC_SMC_A
PC5
1000P_0402_50V7K
2
3
4
5
SMD
SMC
RES
TS
BATT+
FBM-L18-453215-900LMA90T_1812
1
2
PC6
0.01U_0402_50V4Z
+3VL
TYCO_C-1746706_6P
PR3
1K_0402_5%
PR10
210K_0402_1%
AB1A_DATA <37>
EC_SMC_A1
AB1A_CLK <37>
EC_SMD_A1
PC145
220P_0402_25V8K
THM_MAIN# <37>
PC144
220P_0402_25V8K
PC143
220P_0402_25V8K
PR4
PR5
100_0402_5% 100_0402_5%
VMB_B
GND
EC_SMD_B
EC_SMC_B
AB/I_B
TS_B
PC8
1000P_0402_50V7K
PC9
0.01U_0402_50V4Z
SUYIN_20163S-06G1-K
PR7 1
2
1K_0402_5%
1
2
+3VL
PR9
PR11
210K_0402_1%
1K_0402_5%
BATT_B
2
3
4
5
SMD
SMC
B/I
TS
PL3
FBM-L18-453215-900LMA90T_1812
1
2
BATT+
PCN3
PR14
100_0402_5%
PR15
THM_MBAY# <37>
100_0402_5%
EC_SMD_B1
AB1B_DATA <37>
EC_SMC_B1
AB1B_CLK <37>
Compal Secret Data
Issued Date
2005/03/10
Deciphered Date
2006/03/10
A
Title

BATTERY CONN

Date:
Rev
Sheet

D
43
of
57
VIN
P2
BATT
PQ2
AO4407_SO8
P4
3
2
1
1
2
1
2
DH_CHG
PQ7
FDS4435_SO8
1
PR32
3K_0402_1%
2
1
PR31
3K_0402_1%
PC22
29
PD8
SKS30-04AT_TSMA
PC20
10U_1206_25V6M
10UH_PCMB104T-100MS_6A_20%
CV=12.6V(6 CELLS LI-ION)

16.8V(8 CELL LI-ION)
CC=3A for 2.4AHr
CC=3.57A for 2.55AHr
Icharger=3A
CELLSEL# =0,Vcharger= 12.6V
CELLSEL# =1,Vcharger= 16.8V
5
6
7
8
LX_CHG
PC19
4.7U_0805_25V6K
BATT
PR28
0.015_1206_1%
1
2
PL5
6
1
17
23
14
PC200
4.7U_0805_25V6K
BATSET
BATDEP
GND
NC4
NC3
PC17
1U_0805_25V4Z
1
2
1
2
PC198
4.7U_0805_25V6K
1
2
18
20
PGND
VS
VHSP
ACDRV#
0.1U_0402_16V7K
1
BATT
1
PR44
5.62K_0603_0.1%
BATT
1 2
+3VL
1
1 2
PR35
150_0402_1%
PR380
100K_0603_0.1%
+3VL
PR384
100K_0402_5%
CELLSEL#
PU5
REF
ANODE
1.24VREF
CATHODE
NC
NC
PQ11
RHU002N06_SOT323
2
G
RHU002N06_SOT323
AB/I_A
1
2
2
G
330K_0402_5% <50>
PR383
200K_0402_1% S
PR360
2.8K_0603_0.1%
2
G
S
PQ8 RHU002N06_SOT323
2
G
2
D
2
1
RHU002N06_SOT323
PQ111 3
2
2
<43>
PR48
10K_0402_1%
<45>
2
1
PQ10
ACDET 2
G
2
G
I_A#
CFET_B
<45,50>
CELLSEL#
Compal Secret Data
Issued Date
2005/03/10
Deciphered Date
2006/03/10
APL1431LBBC_SOT23-5
A
PR386
3
PQ110
RHU002N06_SOT323
AC_CHG
33K_0402_1%
2
2
<45>
PR49
100_0402_5%
1
VL
PR54
PR51
@47K_0402_1%
AC_CHG
LM393M_SO8
ALARM
2
100K_0402_5%
PC28
100P_0402_50V8J
PC27
@0.1U_0402_16V7K
BQ24703VREF
7
Airline detector
High 17.521V
Low 16.871V
1
2
8
-
PU3B
PR47
PC29
22P_0402_50V8J
2
1
2
1M_0402_5%
PR385
330K_0402_5%
PR381
7.68K_0603_0.1%
PR382
25.5K_0402_1%
2
PR43
4.7K_0402_5%
RHU002N06_SOT323
PQ112 3
+3VL
PR42
196K_0402_1%
2
1
10K_0603_1%
COMP
NC1
NC2
LM393M_SO8
PR46
PR45
130K_0402_1%
PR50
7
10
11
PU4
SN74LVC1G17DBVR_SOT23-5
ADP_PRES <29,37,45,46,50>
O 4
NC 1
+3VL
ENABLE
ACSEL
ALARM
SRSET
ACSET
ACPRES
IBAT
VREF
25
22
21
16
15
12
24
PC26
4.7U_0805_10V6K
5
G
5
28
19
2
3
27
13
4
ACDRV#
VCC
PWM#
SRP
SRN
BATP
BATDRV#
SE_CHG-
1
2
2
1
PR37
10K_0402_1%
1
ACN
ACP
ACDET
SE_CHG+
150P_0402_50V8J
PC24
2
1
1
2
1
8
9
26
BQ24703_QFN28
PC25
0.1U_0402_16V7K
PU3A
PR39
2.15K_0402_1%
1
2
100K_0603_1%
PR36
2
1
PR40
2
VL
12.4K_0603_1%
AC detector
High 11.689V
Low
9.879V
330K_0402_5%
PC23
PR34
1
3
+3VL
1U_0603_10V6K
2
1
+3VL
PC21
4.7U_0805_10V4Z
2 PR27
1
+3VL
100K_0402_5%
BQ24703VREF
PR29
137K_0402_1%
2
1
PC18
1
2
ACDET
P2
PC15
4.7U_0805_25V6K
1
2
PU2
PR26
191K_0402_1%
PR23
0_0402_5%
2
1
PD5
RLZ16B_LL34
2 PR25
1
1K_0402_1%
ALARM
PR33
PR30
80.6K_0402_1%
100K_0402_1%
2
1
CHGCTRL
AC_CHG
1U_0603_10V6K
1SS355_SOD323
<37,45>
<50>
SRSET
ADP_EN# <50>
PC14
4.7U_0805_25V6K
PC16
1U_0603_10V6K
1
2
PR24
1K_0402_1%
PD7
2
CHG_B+
PR397
@0_0402_5%
PL4
FBM-L11-322513-151LMAT_1210
1
2
PR22
100_0402_1%
PR21
150K_0402_5%
PR17
0_0402_5%
1
2
<29,37,45,46,50>
<50>
ACN
4.7U_0805_25V6K
PC43
2
1
PR396
0_0402_5%
ADP_PRES 1
2
BATCAL#
8
7
6
5
4
2
1
1 2
1
PR399
@150K_0402_5%
2
G
PQ131
@RHU002N06_SOT323
PQ93
RHU002N06_SOT323
ADP_PRES
ACDRV#
P2
PR20
0.015_2512_1%
1
2
B+
PR398
@200K_0402_5%
PR19
1
2
0_0402_5%
2
G
3
1
2
3
PR16
200K_0402_5%
<50>
8
7
6
5
PR343
220K_0402_5%
8
7
6
5
PQ4
AO4407_SO8
1
2
3
0.1U_0603_16V7K
2
1
47K
47K
PC13
47P_0402_50V8J
1
2
2
PR18
1
PC12
1
PQ5
DTA144EUA_SC70
1
1
2
3
47K_0402_5%
2
PQ3
AO4407_SO8
Title

Charger

Date:

D
Rev
Sheet
44
of
57
+3VL
LATCH
2
G
BATT
D
PQ16
RHU002N06_SOT323
2
G
ADP_PRES <29,37,44,46,50>
PR75
1
+3VL
PQ28
2
G
<44,50>
BATCON
1
BATT_IN
4
1
1
3
2
2
1
PR67
470K_0402_5%
PR72
470K_0402_5%
BATT_B
PD15
1
PR73
4.7K_0402_5%
SX34-40_SMA
PQ29
RHU002N06_SOT323
2
G
RHU002N06_SOT323
BATT_IN 2
G
2
G
<37>
RHU002N06_SOT323
SN74LVC1G17DBVR_SOT23-5
Compal Secret Data
Issued Date
2005/03/10
Deciphered Date
2006/03/10
A
1
2
3
2
8
7
6
5
PQ30
PU13
O
NC
8
7
6
5
CFET_B
5
1
2
PR77
100K_0402_5%
RB715F_SOT323
P
2
PQ22
AO4407_SO8
PQ25
AO4407_SO8
2
1SS355_SOD323
PQ31
CFET_B
BATT_A
2
1
1
3
PD16
CFET_B
CFET_A
PR66
470K_0402_5%
3
2
1
RHU002N06_SOT323
3
10K_0402_5%
CFET_B#
PD14
1SS355_SOD323
PD17
5
6
7
8
PQ26
PMBT2222_SOT23
2
4
G
ADP_PRES
5
6
7
8
1
2
3
1
O
C
2
B
PR74
10K_0402_5%
1
5
IN2
PQ94
RHU002N06_SOT323
IN1
PU12
PR64
4.7K_0402_5%
3
2
1
PR68
470K_0402_5%
BATSELB_A#
SX34-40_SMA
PQ21
AO4407_SO8
PQ24
AO4407_SO8
PR69
220K_0402_5%
1
2
PQ27
RHU002N06_SOT323
1
RHU002N06_SOT323
BATT
AC_CHG
1
PR63
10K_0402_5%
PD13
RHU002N06_SOT323
PQ23
BATT_IN 2
G
2
G
2
PQ20
2
G
1
2
PR71
10K_0402_1%
1
<44>
S
10K_0402_5%
5
P
NC
A
G
PU11
Y 4
PQ19
RHU002N06_SOT323
+3VL
3
2
G
IN2
PD12
1
+3VL
2
1K_0402_5%
PR344
470K_0402_5%
PR342
IN1
2
PC34
220P_0402_50V7K
3
PR70
470K_0402_5%
0.047U_0402_16V7K
PC35
1
2
5
BATSELB_A
PR62
470K_0402_5%
1SS355_SOD323
PR65
PU10
5
P
A
G
NC
BATSELB_A#
PU9
PQ17
RHU002N06_SOT323
BATT_IN 2
G
PQ18
PMBT2222_SOT23
1
PR61
470K_0402_5%
+3VL
+3VL
<37> BATSELB_A#
PU8
Y
CFET_A
1000P_0402_50V7K
1
RLZ6.2C_LL34
2
B
PC180
PD11
2
1
NC
5
A
+3VL
CHGCTRL
PR58
1.5M_0402_5%
BATT_IN
PD10
1SS355_SOD323
P
2
G
2
0_0402_5%
1000P_0402_50V7K
3 1
+3VL
3
PQ15
RHU002N06_SOT323
1
2
PR60
22K_0402_5%
PC33
D RHU002N06_SOT323
1
2
PR59
22K_0402_5%
PQ14
BATSELB_A#
PR56
PQ13
RHU002N06_SOT323
1000P_0402_50V7K
1
2
100_0402_5%
RB715F_SOT323
2
G
74LVC1G02_04_SOT353
PR55
1
3
INA
74LVC1G02_04_SOT353
PQ12
RHU002N06_SOT323
BATSELB_A
PD9
BATT_B
4
INA
PU6
INB
PC32
1
1
4
0.1U_0603_50V4Z
PC30
1
INB
PC31
PU7
ALARM
2
PR57
47K_0402_5%
<44>
+3VL
BATT_A
@0.1U_0402_10V6K
+3VL
Title

Battery selector

Date:

D
Rev
Sheet
45
of
57
+3.3V/+5V
B+
BST5B
BST3B
PR97
499K_0402_1%
5
6
7
8
PR95
0_0402_5%
+3VLP
+3VALWP
+3VLP
D
D
D
D
100K_0402_5%
PR242
1
+
2
+3VL
PJP1
2
PC49
150U_B2_6.3VM
2
2 1
1
PGOOD
PR94
@3.57K_0402_1%
PRO#
+3VALWP
1
2
G
S
S
S
7
2
PR98
100K_0402_5%
PAD-OPEN 2x2m
PC52
0.1U_0603_50V4Z
PQ36
RHU002N06_SOT323
4
3
2
1
DH3
10
LDO3
25
GND
23
+3VL
28
26
24
27
22
DL3
LX3
VL
PL8
4.7UH_SIQB745-4R7_4A_30%
1
2
MAINPWON
PC50
0.22U_0603_10V7K
PC48
0.1U_0603_50V4Z
REF
PC51
4.7U_0805_10V4Z
2
1
PR90
47K_0402_5%
2
1
2VREF_1999 1
2
PR89
0_0402_5%
12
1
2
0_0402_5%
2VREF_19998
PR91
PR93
1
2
@0_0402_5%
11
1
2 2
1
PR87
PR84
499K_0402_1% 100K_0402_1%
2
PR86
PR83
499K_0402_1% 200K_0402_1%
V+
2 1
1
2
ILIM3
PC44
1U_0805_25V4Z
17
LX5
PU14
DL5
ILIM5
OUT5 MAX8734EEI_QSOP28
FB5
BST3
N.C.
DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD
VCC
DH5
15
19
21
9
1
BST3A
PR96
0_0402_5%
PC46
2
1
0.1U_0603_50V4Z
BST5
16
6
4
3
2
1
B++
2
1
+
2
PR92
0_0402_5%
PC47
150U_B2_6.3VM
1
2
PC197
22U_0805_6.3VAM
PR88
@10.2K_0402_1%
DL5
PQ127
AO4468_SO8
PR82
0_0402_5%
+5VALWP
5
6
7
8
4
3
2
1
PC40
0.1U_0603_50V4Z
2VREF_1999
14
TON
BST5A
20
LD05
<50>
18
PC45
4.7U_0805_10V4Z
2
1
S
S
S
G
1
2
3
4
LX_5V
13
VL
D
D
D
D
PQ126
AO4468_SO8
PL7
4.7UH_SIQB745-4R7_4A_30%
D
D
D
D
G
S
S
S
1
2
2
1
2
PQ35
AO4468_SO8
8
7
6
5
LX_5V
PR80
47_0402_5%
DH5
B++
PC42
4.7U_0805_25V6K
1
2
D
D
D
D
8
7
6
5
PR79
0_0402_5%
1
2
3
4
VL
PQ34
AO4468_SO8
S
S
S
G
B++
PD18
CHP202U_SC70
PC39
10U_1206_25V6M
PC38
2200P_0402_50V7K
2
1
B++
PC37
0.1U_0603_50V4Z
1
2
PC41
2200P_0402_50V7K
PC36
0.1U_0603_50V4Z
1
2
PL6
FBM-L11-322513-151LMAT_1210
2
G
1
RHU002N06_SOT323
PQ37
2
G
KBC_PWR_ON <37>
RHU002N06_SOT323
PQ77
2
G
ADP_PRES <29,37,44,45,50>
S
4
Compal Secret Data
2005/03/01
Issued Date
2006/03/01
Deciphered Date
Title
3.3V / 5V
D
Size
B
Date:
Document Number
Rev
1A
LA3262P_DIS__M64
Sheet

E
46
of
57
PL9
FBM-L11-322513-151LMAT_1210
2
1
PR99
0_0402_5%
1
2
PC58
4.7U_0805_25V6K
1
2
28
1
CS1
OUT1
FB1
11
ON1
OUT2
FB2
ON2
15
14
12
+1.25VMP
DH_1.25V_2
PC61
22
9
BST2
DH2
LX2
DL2
CS2
PR104
0_0402_5%
2
DH_1.25V_1
LX_1.25V
DL_1.25V
PC66
220U_B2_2.5VM
LX1
DL1
19
18
17
20
16
PL11
3.3UH_SIQB74-3R3RF_4.8A_30%
PC62
0.1U_0603_50V4Z
1
PR105
2.49K_0402_1%
DH1
27
24
21
LX_1.5V
DL_1.5V
26
VDD
UVP
DH_1.5V_1
BST1
VCC
25
PR102
0_0402_5%
1
2
1
+
2
1
2
1
1SS355_SOD323
PR118
100K_0402_1%
PC70
@0.001U_0402_50V7M
PR117
100K_0402_1%
2
PC69
0.22U_0603_10V7K
PR120
0_0402_5%
PR116
PR114
20K_0402_1%
1
@0_0402_5%
PD31
2
2
VCC_MAX8743
1
PR108
0_0402_5%
PR113
20K_0402_1%
2
1
2VREF
PC71
@0.001U_0402_50V7M
PR123
0_0402_5%
13
3
ILIM2
ILIM1
REF
SKIP
6
GND
10
MAX8743EEI_QSOP28
1
1SS355_SOD323
<26,29,32,33,37,39,40,48,49,50,51,52> SLP_S3#
7
5
PGOOD
TON
OVP
23
PD30
PR107
10K_0402_1%
PR111
10K_0402_1%
DH_1.5V_2
PR103
2.2_0402_5%
1
2
SI4914_SO8
VCC_MAX8743
4
V+ 1U_0805_25V4Z
2
1
PR101
0_0402_5%
PU15
PR106
5.1K_0402_1%
1
2
PC64
2.2U_0603_6.3V6K
1
+
2
8
7
6
5
D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K
BST_1.5V_1
PC60
0.1U_0603_50V4Z
2
1
BST_1.5V_2
1
2
3
4
BST_1.25V_1
PC63
220U_B2_2.5VM
3.3UH_SIQB74-3R3RF_4.8A_30%
1
2
3
4
BST_1.25V_2
PC59
0.1U_0603_50V4Z
PL10
2
PQ39
PC55
4.7U_0805_10V4Z
D/K
D/K
D/K
D/K
PR100
20_0603_5%
PC57
2200P_0402_50V7K
1U_0805_25V4Z
PC56
PD19
8
7
6
5
CHP202U_SC70
S/A
S/A
S/A
G
+1.5VSP
PQ40
AO4712_SO8
B+
+5VALW
8
7
6
5
PC53
2200P_0402_50V7K
2
1
1
2
3
4
S
S
S
G
D
D
D
D
PQ38
AO4468_SO8
PC54
10U_1206_25V6M
MAX8743_B+
PM_SLP_M# <26,37,40,48,52>
1
PR121
0_0402_5%
+3VALW
PJP11
PAD-OPEN 2x2m
+2.5VS
+1.5VS
+5VALW
(4A,160mils ,Via NO.=8)
PAD-OPEN 3x3m
PR243
GND
GND
GND
GND
PR244
13.7K_0603_1%
1
4
PC135
10U_0805_6.3V6M
G965-18P1U_SO8
(4.5A,180mils ,Via NO.= 9)

PAD-OPEN 4x4m
PJP5
ADJ
PR245
12K_0402_1%
47K_0402_5%
1
2
PJP16
PAD-OPEN 4x4m
1
2
+3VALWP
+VCCP
(4A,160mils ,Via NO.= 8)
+3VALW
PC170
0.1U_0402_16V7K
PAD-OPEN 4x4m
PJP2
<26,29,32,33,37,39,40,48,49,50,51,52> SLP_S3#
+1.05V_VCCP
+5VALWP
VO
EN
PJP3
VIN
PJP6
+1.5VSP
PC134
10U_0805_6.3V6M
PU26
+0.9VP
+1.25VMP
PJP8
4
+0.9V
+1.25VM
PAD-OPEN 4x4m
PAD-OPEN 3x3m
Compal Secret Data
Issued Date
PJP15
+1.05VMP
+1.05VM
Deciphered Date
2006/03/10
PAD-OPEN 2x2m
A
2005/03/10
Title

2.5VALW/1.5VS/1.25VMP

Date:

D
Rev
Sheet
47
of
57
DDR_B+
PL12
FBM-L11-322513-151LMAT_1210
2
1
VBST
VTT
DRVH
22
VTTGND
LL
20
DRVL
19
G
S
S
S
4
3
2
1
PGND
18
CS
16
V5FILT
14
PGOOD
13
S5
11
DL_1.8V
2
C
PL13
1
+
PQ46
AO4712_SO8
PC78
330U_D2E_2.5VM_R15
1
14.3K_0603_1%
PR128
2
PC82
4.7U_0805_10V4Z
2
V5IN
Thermal pad
S3
+5VALWP
PR131
2
10
@0_0402_5%
SLP_S5# <26,40>
PR132
1 0_0402_5%
SLP_S4# <26,40>
PR133
15
17
VDDQSET
CS_GND
9
B
VDDQSNS
PR130
3_0402_5%
2
1
PC80
22P_0402_50V8J
TPS51116RGE_QFN24
COMP
4
3
2
1
VTTREF
PR129
20K_0603_1%
MODE
GND
PC83
0.001U_0402_50V7M
25
+5VALW
0.033U_0402_16V7K
PR127
0_0402_5%
2
VTTSNS
+1.8V
G
S
S
S
PC79
22U_0805_6.3VAM
PC81
<7,13,14> V_DDR_MCH_REF
PC73
10U_1206_25V6M
D
D
D
D
2.2UH_IHLP-2525CZ-01_8A_+-20%
LX_1.8V
21
B+
DH_1.8V_2
5
6
7
8
24
VLDOIN
PC74
0.1U_0603_50V4Z
BST_1.8V_2 1
2
PC72
2200P_0402_50V7K
2
1
5
6
7
8
D
D
D
D
23
PR125
0_0402_5%
BST_1.8V_1
1
2
PR126
0_0402_5%
DH_1.8V_1
1
2
PU17
NC
NC
PC76
10U_0805_10V4Z
+0.9VP
PQ45
AO4468_SO8
PC75
10U_0805_10V4Z
12
1
2
PR124
0_1206_5%
+1.8V
@0_0402_5%
SLP_S3# <26,29,32,33,37,39,40,47,49,50,51,52>
PR134
1 @0_0402_5%
SLP_S4# <26,40>
PR387
PM_SLP_M# <26,37,40,47,52>
2005/03/10
Deciphered Date
10K_0603_0.1%
PR135
2
PR317
0_0402_5%
1.8PGOOD <41>
A
2006/03/10
Title
5
+3VALW
PC85
@0.001U_0402_50V7M
2
PR294
100K_0402_5%
Compal Secret Data
Issued Date
1 0_0402_5%
1
1
2
A
PC84
@0.001U_0402_50V7M

1.8V/0.9VS
Size
B
Date:
Document Number
Rev
LA3262P_DIS__M64
Sheet
1
48
of
57
PR148
0_0402_5%
2
1
PC105
0.22U_0603_16V7K
1
2
DL_CPU1
+VCCP
<26> CLK_EN#
SLP_S3#
DH_CPU2
LX_CPU2
GND
DPRSTP#
499_0402_1%
2 PR174 1
0_0402_5%
1
2
PR328
PD44
@1SS355_SOD323
1
2
@100_0402_5% 2
1
PR178
PC185
0_0402_5%
@0.1U_0402_16V7K
PR318
@27.4_0402_1%
PC118
2
1
2
1
PC119
1000P_0402_50V7K
2
1
PSI#
PGD_IN
38
CLK_EN#
FCCM
24
35
VR_ON
12
VSEN
13
RTN
11
VDIFF
10
FB
ISL6208CRZ-T_QFN8
@4.7_1206_5%
1
2
1
0_0402_5%
25
ISEN3
21
PC112
4.7U_1206_25V6K
2
1
PC148
47U_25V_M
.36UH_MPC1040LR36_ 24A_20%
1
PR177
PWM3
PC111
2200P_0402_50V7K
2
1
PC110
0.01U_0402_50V4Z
2
1
PGOOD
CS_GND
41
40
39
18
VIN
DPRSLPVR
ISEN2
ISEN2
LGATE
+5VS
DL_CPU2
+VCC_CORE
2
PWM PHASE
PC113
10U_1206_25V6M
PR170
10K_0402_1%
1
2
PC117
0.22U_0603_16V7K
2
1
PR167
10_0402_1%
1
BOOT
FCCM UGATE
D
D
D
D
VCC
PL17
8
7
6
5
37
22
PWM2
PR173
5.11K_0402_1%
2 PR175
@0_0402_5%
VSUM
VO
<21,26,31,37,40,41,50> PWR_GD
VID0
VID1
VID2
VID3
VID4
VID5
VID6
36
9,32,33,37,39,40,47,48,50,51,52>
VO
2 PR172
0_0402_5%
H_PSI#
VSUM
<5>
<37> PM_POK
@0_0402_5%
PR349
1
2 2
1
PC191
@4.7_1206_5%
@680P_0603_50V7K
2 PR171
<7,26> DPRSLPVR
D
PWM2
26
S
S
S
G
28
29
30
31
32
33
34
PC116
0.22U_0603_16V7K
1
2
PU20
5
IRF7832Z_SO8
PQ57
2 PR169
0_0402_5%
ISEN1
PU19
PR1611
2
0_0402_5%
2 PR163 1
0_0402_5%
2 PR165 1
0_0402_5%
2 PR168 1
0_0402_5%
2 PR162 1
0_0402_5%
2 PR164 1
0_0402_5%
2 PR166 1
0_0402_5%
<5,7,25> H_DPRSTP#
23
1
2
3
4
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
ISEN1
1
2
3
4
SOFT
0.015U_0402_16V7K
<5>
<5>
<5>
<5>
<5>
<5>
<5>
2 PR154
3
2
1
NTC
8
7
6
5
27
D
D
D
D
2
1
PC115
2
1 470KB_0402_5%_ERTJ0EV474J
PWM1
S
S
S
G
RBIAS
PQ54
SI7840DP_SO8
IRF7832Z_SO8
PQ56
NTC
3V3
20
VSS
3
PH2
PWM1
PR157
0_0402_5%
2
1
BST_CPU2_1
2 PR160 1
4.22K_0603_1%
VR_TT#
ISL6260CRZ-T_QFN40
PC114
1U_0603_10V6K
PR159 1
2
147K_0402_1%
PR153
5.11K_0402_1%
+CPU_B+
BST_CPU2_2
<4> H_PROCHOT#
19
PR370
68_0402_5%
0.01U_0402_16V7K
PR158
0_0402_5%
2
1
PC107
0.22U_0603_16V7K
2
1
PR150
10_0402_1%
+5VS
VDD
NTC
+VCC_CORE
PR151
10K_0402_1%
1
2
PGOOD_PU19 <37>
PC109
2
1
PC190
@680P_0603_50V7K
1
PR155
1.91K_0603_1%
1
IRF7832Z_SO8
PQ53
1
2
3
4
PR152
10_0603_5%
2
+3VS
PC108
1U_0603_10V6K
2
1
+5VS
ISL6208CRZ-T_QFN8
1
2
3
4
LGATE
IRF7832Z_SO8
PQ52
PL16
PR347
LX_CPU1
.36UH_MPC1040LR36_ 24A_20%
2 2
GND
FCCM UGATE
8
7
6
5
PWM PHASE
8
7
6
5
DH_CPU1
D
D
D
D
D
D
D
D
BOOT
S
S
S
G
VCC
S
S
S
G
PU18
5
B+
3
2
1
BST_CPU1_1
PC104
1U_0603_10V6K
2
1
0.01U_0402_25V7K
PC106
2
1
PR149
10_0603_5%
4
BST_CPU1_2
+5VS
PC103
10U_1206_25V6M
+CPU_B+
PL15
FBM-L18-453215-900LMA90T_1812
1
2
PC102
4.7U_1206_25V6K
2
1
PC100
0.01U_0402_50V4Z
2
1
PQ50
SI7840DP_SO8
PC101
2200P_0402_50V7K
2
1
+CPU_B+
PC127
1
1
2
PC122
@1000P_0402_50V7K
PR185
1.96K_0402_1%
1
PR189
@1K_0402_1%
PR191
1K_0402_1%
2
1
PR179,PR180 are for test need when M/B is without CPU

R1269,R1270 are same funtion with PR179,PR180
Layout Note: Use27.4 Ohm(PR318,PR319) routing for Vssense and
Vccsense
PR190
6.34K_0603_1%
2
1
10KB_0603_5%_ERTJ1VR103J
1000P_0402_50V7K
PR188
2
1
6.98K_0402_1%
VSUM
VO
PC125
1
220P_0402_25V8K
17
0.1U_0402_16V7K
1
2
2 PR187
51K_0603_1%
PC121
0.022U_0402_16V7K
VSUM
PH3
PC124
2
VW
PC123
0.22U_0603_16V7K
1
2
2 PR184 1
1.2K_0402_1%
PR183
2
1
0_0402_5%
PR181
2
1
11.5K_0402_1%
PC126
2
1
PR182
PC120
180_0603_1% 1800P_0402_50V7K
2
1
1
2
COMP
DROOP
PR319
@27.4_0402_1%
2
1
OCSET
14
<5> VSSSENSE
VO
1000P_0402_50V7K
16
PR179
@10_0402_1%
PR186
4.53K_0402_1%
2
1
DFB
15
<5> VCCSENSE
+VCC_CORE
330P_0402_50V7K
Compal Secret Data
2005/03/10
Issued Date
Deciphered Date
2006/03/10
Title
CPU_CORE
8
Size
C
Date:
2
Document Number
Rev
LA3262P_DIS__M64
Sheet
49
1
of
57
PQ71
2
G
2
1SS355_SOD323
S
S
PR252
220K_0402_5%
<29,37,44,45,46>
<44>
PR234
3.48K_0402_1%
G
8
+3VS
PR227
10K_0402_5%
PU24B
O
4
PQ63
MMBT3904_SOT323
LM393M_SO8
1 2
2
B
<37>
7
ADP_PS1
<37>
LM393M_SO8
ADP_EN
PR233
100K_0402_5%
1
2
<37>
PR232
21K_0603_1%
1
2
ADP_PS0
PR226 +5VS
1M_0402_5%
1
2
1
1
PR228
21K_0603_1%
1
D
PR222
71.5K_0402_1%
PR225
@100K_0402_5%
PQ95
RHU002N06_SOT323
<44>
SRSET
PU24A
PR218
10K_0402_5%
PR220
10K_0402_5%
1
2
+5VS
PR219
1M_0402_5%
1
2
1
470K_0402_5%
+3VS
1
<44>
PC133
0.1U_0603_16V7K
2
1
ADP_EN#
2
1
ACN
PQ64
RHU002N06_SOT323
2
1SS355_SOD323
2005.8.20
1SS355_SOD323
PD24
RHU002N06_SOT323
+3VS
2
1
2
G
2
G
PD23
2
G
2
2
1
+3VS
PD26
ADP_SIGNAL
<39> ACOCP_EN#
LM393M_SO8
1
2
2 2
PR255
1
BATCAL#
PR230
47K_0402_5%
PR231
220K_0402_5%
2
1
PR239
220K_0402_5%
2
1
47K
PD27
1SS355_SOD323
PC146
1U_0603_10V6K
<37>
PU25B
2
G
PQ65
@RHU002N06_SOT323
PR241
10K_0402_1%
PC128
1U_0805_25V4Z
2
1
P
G
4
PC131
2
1
0.01U_0402_16V7K
1 2
PR253
210K_0402_1%
<4,26>
PQ60
RHU002N06_SOT323
2
SLP_S3#
+3VL
8
+
<46>
PD28
1SS355_SOD323
2
1
5
2
1
3
2
80.6K_0402_1%
1
S
2
G
PR216
VIN
PR237
47K_0402_5%
1
2
PR240
0_0402_5%
2
1
OCP#
1
2
8
4
LM393M_SO8
PR238
1M_0402_5%
1
2
PR258
29.4K_0402_1%
PR254
150K_0402_5%
<44>
VIN
LX_5V
2
0_0402_5%
PR221
10K_0402_5%
<26,29,32,33,37,39,40,47,48,49,51,52>
PQ70
DTA144EUA_SC70
VIN
PR211
P
O
G
PC147
3900P_0402_50V7K
PU25A
3.9K_0402_5%
PR214
ADP_ID
PR235
10K_0402_1%
2
PR203
200K_0603_1%
PR265
47K_0402_5%
PD25
+3VL
PR208
10_0402_5%
ADP_PRES
PR224
226K_0402_1%
PR236
100K_0402_1%
I_A#
LM393M_SO8
PQ74
<44>
2
G
RHU002N06_SOT323
VIN
PR257
10K_0402_5%
PU21A
<44,45>
1SS355_SOD323
PR229
1M_0402_5%
1
2
PR205
2
1
PR260
39.2K_0402_1%
1
1
2
G
CFET_B
PR223
137K_0402_1%
B
PQ113
RHU002N06_SOT323
1
3
PQ62
NDS0610_NL_SOT23-3
VIN
1K_0402_5%
PR261
1M_0402_1%
PQ61
C MMBT3904_SOT323
2
B
<29,37,44,45,46>
ADP_PRES
E
PR217
2
G
47.5K_0402_1%
PQ92
1
2
RHU002N06_SOT323
ADP_SIGNAL
2
0_0402_5%
1
2
PR215
470K_0402_5%
2
APL1431LBBC_SOT23-5
LM393M_SO8
PD22
@CH751H-40_SOD323
1
2
PWR_GD
<21,26,31,37,40,41,49>
2
G
S
3
7
PR207
3.9K_0402_5%
RHU002N06_SOT323
PQ73
1
NC
ANODE
1 2
1
2
7.87K_0402_1%
PR206
NC
PR212
0_0402_5%
<29,37,44,45,46> ADP_PRES
PR201
3
PR210
0.1U_0402_16V7K
PC132
2
1
CATHODE
215_0603_1%
1
2
PU23
PC130
1U_0805_50V4Z
PC129
0.027U_0603_16V7K
REF
LM358A_SO8
B+
8
0
PR199
10K_0402_1%
2
PR200
100K_0603_0.5%
2
6.81K_0402_1%
2
1
PR202
2K_0402_5%
3
2
1
PQ58
MMBT3906_SOT23
1
10K_0402_5%
PU21B
PR197
2
PD21
CH751H-40_SOD323
100K_0402_5%
PU22B
PR192
133K_0402_1%
PR256
PR193
1
2
PR195
2
LM358A_SO8
PR194
330K_0402_5%
2
1
P4
0_0402_5%
8
P
2
PR196
0_0402_5%
0
G
PU22A
+5VS
PR259
1M_0402_1%
PQ72
+5VS
NDS0610_NL_SOT23-3
PD20
CH751H-40_SOD323
1
2
+5VS
+3VS
PR251
220K_0402_5%
1
47K
Compal Secret Data
2005/03/10
Issued Date
Deciphered Date
2006/03/10
3
Title

ADP_OCP

Date:
Rev
Sheet
1
50
of
57
B+_VGA
PQ78
AO4468_SO8
D
D
D
D
VGA_BOOT1
2 PC151
0.1U_0402_16V7K
4
3
2
1
2
PR346
0_0402_5%
+
2
VGA_LG
PC157
330U_D2E_2.5VM_R9
1
PD29
VDD_CORE
1
VDDP
PQ79
AO4712_SO8
D/K
D/K
D/K
D/K
PR353
1
2
19.6K_0402_1%
1
2
PC168
1U_0603_10V6K
G
S/A
S/A
S/A
11
10
@SX34_SMA
BST
5
6
7
8
FB
3
13
15
14
PGD
NC
LX
ILIM
2
PL19
4
3
2
1
TPAD
PGND
12
DL
17
7
VOUT
VSSA
1UH_IHLP-2525CZ-01_11A_+-20%
VGA_LX
DH
PC169
1U_0603_10V6K
NC
16
TON
VCCA
PR345
470K_0402_5%
VGA_UG
PU29
EN/PSV
PR367
10_0402_5%
+5VALW
PC155
@0.1U_0402_16V7K
PR393
@100K_0402_5%
G
S
S
S
VGA_BOOT 1
PD43
1SS355_SOD323-2
+5VALW
5
6
7
8
PC159
1000P_0402_50V7K
PR350
0_0402_5%
2
<26,29,32,33,37,39,40,47,48,49,50,52> SLP_S3#
PR351
1M_0402_5%
+5VALW
PC153
4.7U_1206_25V6K
1
2
PC152
10U_1206_25V6M
B+
PL18
FBM-L11-322513-151LMAT_1210
2
1
SC411MLTRT_MLPQ16_4x4
VGA_VCORE
+5VALW
PR354
1
10K_0402_1%
2
1
2
+5VALW
2
PR357
0_0402_5%
VIN
VOUT
VOUT
FB
PC161
10U_1206_6.3V6M
VIN
PCIE_1.2V
PC162
22U_0805_6.3VAM
APL5913-KAC-TRL_SO8
PC171
@0.1U_0402_16V7K
EN
+1.8V
PC160
1U_0603_10V6K
<26,29,32,33,37,39,40,47,48,49,50,52> SLP_S3#
POK
VCNTL
GND
(For M62S
POW_SW= "0": VDD_CORE=1.1V
"1": VDD_CORE=0.95V
PR355 change to 11K and PR392 change to 33.2K)
PR356
10K_0402_1%
PU31
For M64S
POW_SW= "0": VDD_CORE=1.2V
"1": VDD_CORE=1V
+3VS
1
2
S PQ120
RHU002N06_SOT323
2
G
10K_0402_5%
PC196
1U_0603_10V6K
PR355
9.76K_0402_1%
PR358
49.9K_0402_1%
PC164
47P_0402_50V8J
PC154
33P_0402_50V8J
PR391
1
1
RHU002N06_SOT323
PQ121
2
G
<19> POW_SW
PR392
24.9K_0402_1%
PR390
100K_0402_5%
SET TO 1.2V FOR M62S,M71S (R342= 49.9K)

SET TO 1.1V FOR M72S (R342 = 39.2K)
PR359
100K_0402_1%
Compal Secret Data
Issued Date
2005/03/10
2006/03/10
Deciphered Date
5
Title

VDD_CORE

Date:
Rev
Sheet

1
51
of
57
B+_VGA
1
2
PC199
4.7U_0805_25V6K
PQ47
1
2
3
4
12
LX
11
ILIM
10
8
7
6
5
+1.05V_VCCP
SI4914_SO8
PR141
1
2
18.2K_0402_1%
LX6269
1
2
PL14
3.3UH_SIQB74-3R3RF_4.8A_30%
DL
VOUT
VDDP
D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K
PC142
220U_B2_2.5VM
DH
FB
PGD
NC
<41> VCCP_POK
UG
BST
TPAD
PGND
PC90
0.1U_0402_16V7K
13
15
14
NC
EN/PSV
VSSA
TON
16
VCCA
17
7
PU28
BOOT1
PC97
1U_0603_10V6K
PR136
2
0_0402_5%
PC186
47P_0402_50V8J
+5VALW
PR137
@10K_0402_5%
2
PR249
47K_0402_5%
BOOT
1SS355_SOD323
1
<26,29,32,33,37,39,40,47,48,49,50,51> SLP_S3#
PC89
4.7U_0805_25V6K
2
PD42
1SS355_SOD323-2
PC95
1000P_0402_50V7K
2
2
PD45
1
1
PR368
1M_0402_5%
PR142
10_0402_5%
+5VALW
PC91
1U_0603_10V6K
1
+
2
SC411MLTRT_MLPQ16_4x4
LG
PR144
1
2
11K_0402_1%
2
PC96
33P_0402_50V8J
PR147
10K_0402_1%
+5VALW
+3VALW
EN
VOUT
VOUT
FB
PC138
10U_0805_6.3V6M
+1.05VMP
PC141
22U_0805_6.3VAM
PC140
27P_0402_50V8J
PR247
47K_0402_1%
APL5915KAI-TRL_SO8
VIN
2
PR292
0_0402_5%
VIN
<26,37,40,47,48> PM_SLP_M#
POK
VCNTL
2
PR323
0_0402_5%
GND
<41> M_PROK
+1.25VM
PC139
1U_0603_10V6K
PR293
@10K_0402_1%
PU27
PR248
150K_0402_1%
A
Compal Secret Data
Issued Date
2005/03/10
2006/03/10
Deciphered Date
5
Title

+1.25VMP/+1.05V_VCCP

Date:
Rev
Sheet

1
52
of
57
Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
43
Title
Date
Request
Owner
Issue Description
Solution Description
Cut in
DCIN/
BATTERY CONN
2006/09/07 HP R.L.
Charger
ADP_OCP
Change charger control from HW to FW
50
ADP_OCP
2006/10/12 HP R.L.
Identify 65W adapter as "light"
Change PR223 from 180K to 147K
DB2
51
VDD_CORE
/PCIE_VDD
2006/10/12 HP R.L.
Change VGA chipset from ATi M62S to M64S
Change PR355 from 11K to 9.76K

Change PR392 from 33.2K to 24.9K
DB2
52
+1.25VMP/
+1.05V_VCCP
2006/10/12 HW
For HW's requirement, fine tune +1.05V_VCCP sequence
Change PR249 from 0 to 47K

Add PC186 as 47pF
Install PD45
DB2
51
VDD_CORE
/PCIE_VDD
2006/10/12 PWR
Fine tune PCIE_VDD

DB2
51
VDD_CORE
/PCIE_VDD
2006/11/08 HW
Fine tune the GPU "Power Play" sequence
Add PC196 as 1uf
VDD_CORE
/PCIE_VDD
2006/11/08 HW
Fine tune the power sequence of PCIE_VDD
Change PU31 pin5, 9 source from VDD_MEM18 to +1.8V
44
Charger
2006/11/08 PWR
Base on "Energy STAR" spec, reduce S5 and S3

power consumption (AC mode)
Uninstall PQ11
SI
10
48
1.8V/0.9V
2006/11/08 HP
Add PM_SLP_M# sequence
Add PR387
SI
11
52
+1.25VMP/
+1.05V_VCCP
2006/11/20 HW
For HW's requirement, fine tune +2.5VS sequence
Change PR243 to 47K,

Change PC170 to 0.1uF
SI
12
52
+1.25VMP/
+1.05V_VCCP
2007/2/28
HW
Tony J
Fine tune the +2.5VS power level to 2.57V (typ)
SI2
13
50
ADP_OCP
2007/2/28
HP R.L.
System identity
SI2
14
44
Charger
2007/3/1
PWR
Francis H
Reserve circuit for testing Energy STAR
Reserve PR397, PR398, PR399 and PQ131

Add PR396 as 0 ohm.
PV
15
51
VDD_CORE
/PCIE_VDD
2007/3/1
PWR
Francis H
MOSFET change for M64s (original design is for M72)
Change PQ78 from IRF7413Z to AO4468

Change PQ79 from IRF8113 to AO4712
Change PR353 from 6.81K to 19.6K
PV
16
50
ADP_OCP
2007/4/12
HP R.L.
Fine tune system OCP setting for battery spec
Change
Change
Change
Change
MV
44
46
47
Charger
3.3V/5V
1.5VS/1.25VM
+1.25VMP/
1.8V/0.9V
2007/7/30
VDD_CORE
/PCIE_VDD
+1.25VMP/
+1.05V_VCCP
HP R.L.
Change some MLCCs size from 1206 to 0805
1. Change PC14 from 10u_1206 to 4.7u_0805

Add PC198 as 4.7u_0805
2. Change PC89 from 10u_1206 to 4.7u_0805
Add PC199 as 4.7u_0805
3. Change PC15, PC19, PC42 and PC58 from 4.7u_1206
to 4.7u_0805
4. Change PC79, PC141, PC162 and PC197
from 22u_1206 to 22u_0805
5. Change PC134, PC135 and PC138 from 10u_1206
to 10u_0805
Charger
TI
For TI's suggestion, add 4.7u at VCC pin
Add PC200 as 4.7u_0805
6
8
44
50
51
Tony J
Francis H
Tony J
Tony J
DB1B
All the related components
SI
SI
C
Francis H
17
48
51
52
18
44
Tony J
2007/7/30
PR210
PC129
PR203
PC131
from
from
from
from
422 to 215
.22u to .027u
604K to 200K
.027u to .01u
MP
MP
Title
PIR
Size
Document Number
Date:
5
Rev
Sheet

1
53
of
57
Item
<2006.09.11>
Fixed Issue
Reason for change
PAGE
Dseign issue (Lost VRAM RST pin)
20, 22
Modify List
M.B. Ver.
Add DRAM_RST# from VGA to VRAM
0.2
Dseign issue (LVDS channel error)
19
Swapped LVDS upper and lower channel
0.2
Dseign issue (HSYNC & VSYNC error)
19
Swapped VSYNC & HSYNC each other
0.2
isolate ESD to CPU core via USB and 1394 conn's pin
34
Add R4, R73 and R56
0.2
Follow ATI design suggestion for VDDR4, VDDR5
21
change and reserve two jopens for +1.8VS and +3VS power rails
0.2
Follow ATI design suggestion for DPLL_VDDC
21
delete R1892
0.2
follow ATI power sequence
40
Add +1.25VS, +3VS, +5VS and VDD_MEM18 delay circuits.
0.2
3
4
<2006.10.14>
C
RGB signal EA failed and CRT
display garbage
RGB signal EA failed and CRT
display garbage
16, 19
Change CRT circuit from MAX9511 to RLC circuit.

39
<2006.11.20>
0.3
Change CRT circuit from MAX9511 to RLC circuit.
0.3
Add Q/Switch circuit.
follow ATI power sequence
21
install R1898 aand C1605, uninstall R1897
0.3
Increase VDD_MEM18 via holes
23
VDD_MEM18 no power noise, remove 1206 size resister.
0.3
Cancel Kill switch function on Chimay
28
uninstall JP53, R1906, R1736 and Q136
0.3
change 1394 bus route on board
31
re-define JP13 pins' assignment
0.3
implement one 4MB SPI chip
36
add R1794, R1795, R1924
0.3
implement 30pins KBC connector
38
re-define KBC connector JP6 pins assignment
0.3
HP request, support Penryn CPU
Add R23, R34
0.4
For Intel ES2 Crestline thermtrip pin.
Add R2
0.4
For EMI request enable 27MHz_SSC
15
install
For Intel ES2 NB 800/667M Hz issue
15
Add CLRP4, CLRP5 to select FSB speed.
For RTC Accuracy fail to change
25
4
5
6
For detect CPU and system power saving
R1687
0.4
0.4
0.4
Change C528, C516 to 15pf
26
Add some components
0.4
Solve auto-turn on
26
install R1590 pull up to +3valw, uninstall R1727
0.4
Enable ACBS (power management for NIC)
29
install Q102, uninstall R1612, Q104, Q105
0.4
30
Change R1639 value to 1.87k
2006/09/25
2006/09/25
Deciphered Date
Title
HW PIR
5
Compal Secret Data
Issued Date
0.4

Custom
Date:
Rev
1A
LA3262P_DIS__M64
Sheet

1
54
of
57
Item
<2006.11.20>
Fixed Issue
10
Reason for change
PAGE
Add Energy Star for CPU schematics
11
41
Modify List
M.B. Ver.
reserve R1931, R1934, R1933, C1622, U88, U90, R43,
0.4
R46, R52, R53, C1623, D80
41
Change R1732 pin2 from +3VM_Lan to +3VM
38
MDC power change to +3vs
0.4
HP request
12
13
<2007.01.25>
Follow ATI power sequence
40
Install D77, C1617, change R1919 to 10K
0.4
For HP request
40
Add R1940 and pull up +3valw
0.5
For 3VL/VCC1_PWRGD glitch change
41
Add U5C and R1939 pull down
0.5
For KBC VCC2 connection to 3VS
37
install R1646, C75
0.5
For HP request
25
For HP request to install BGA CRACK components
27
0.4
Add Q144 and R1935 instead of D75
0.5
0.5
12
For solving Power wireset interfere Fan
38
change JP20 connector Footprint
0.5
For Intel Crestline thermtrip shutdowm
Reserve 0.1uf *1 for THERMTRIP#
0.5
For possible Leak during ACBS on PREP# signal
26
Change pull up to +3valw
0.5
For HP request to change Line-in BOM
32
R370, R369 change to 6.04k, R374, R375 change to 2.00k
0.5
10
For SIM connector supply chain
31
SIM connector footprint change
0.5
11
For LMV331 supply chain, change to LMV393
41
change U76 & U86 to U91
0.5
For EMI changes for VGA CRT
16
Install C310,C313,C314,R542,R543,R544
0.5
13
For EMI changes for LED_LAN_DOCK
33
Add R1805,R1806
0.5
14
For HP request, change R1780.1 to UIM_PWR
31
change R1780.1 to UIM_PWR
0.5
15
For Intel NIC crystal design
29
Add R1936
16
For G-Sensor LED
26
HDD_HALTLED (R15) pull down
0.5
17
For Intel new design
26
Remove pull ups for STP_PCI# and STP_CPU#
0.5
18
For HP request
36
Add CLRP6 for SPI ROM
19
For VGA wavy isse
17
Change C586 to 10uf_1206, add C1629 10uf_1206
12
30ohm value
0.5
uninstall R1581, R1580

0.5
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
Title
HW PIR
5
0.5

Custom
Date:
Rev
1A
LA3262P_DIS__M64
Sheet

1
55
of
57
Item
<2007.02.14>
Fixed Issue
Reason for change
PAGE
Add FP power supply circuit for Vista
41
Modify List
M.B. Ver.
reserve R1931, R1934, R1933, C1622, U88, U90, R43,
0.4
R46, R52, R53, C1623, D80
41
Change R1732 pin2 from +3VM_Lan to +3VM
38
MDC power change to +3vs
0.4
HP request
Follow ATI power sequence
0.4
40
Install D77, C1617, change R1919 to 10K
0.4
For HP request
40
Add R1940 and pull up +3valw
0.5
For 3VL/VCC1_PWRGD glitch change
41
Add U5C and R1939 pull down
0.5
For KBC VCC2 connection to 3VS
37
install R1646, C75
0.5
For HP request
25
For HP request to install BGA CRACK components
27
Add Q144 and R1935 instead of D75
0.5
0.5
12
For solving Power wireset interfere Fan
38
change JP20 connector Footprint
0.5
For Intel Crestline thermtrip shutdowm
Reserve 0.1uf *1 for THERMTRIP#
0.5
For possible Leak during ACBS on PREP# signal
26
Change pull up to +3valw
0.5
For HP request to change Line-in BOM
32
R370, R369 change to 6.04k, R374, R375 change to 2.00k
0.5
10
For SIM connector supply chain
31
SIM connector footprint change
0.5
11
For LMV331 supply chain, change to LMV393
41
change U76 & U86 to U91
0.5
For EMI changes for VGA CRT
16
Install C310,C313,C314,R542,R543,R544
0.5
13
For EMI changes for LED_LAN_DOCK
33
Add R1805,R1806
0.5
14
For HP request, change R1780.1 to UIM_PWR
31
change R1780.1 to UIM_PWR
0.5
15
For Intel NIC crystal design
29
Add R1936
16
For G-Sensor LED
26
HDD_HALTLED (R15) pull down
0.5
17
For Intel new design
26
Remove pull ups for STP_PCI# and STP_CPU#
0.5
18
For HP request
36
Add CLRP6 for SPI ROM
19
For VGA wavy isse
17
Change C586 to 10uf_1206, add C1629 10uf_1206
12
30ohm value
0.5
uninstall R1581, R1580

0.5
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
Title
HW PIR
5
0.5

Custom
Date:
Rev
1A
LA3262P_DIS__M64
Sheet

1
56
of
57
Item
<2007.08.02>
Fixed Issue
Reason for change
Solve VGA can not thermal shutdown and
prevent Cap crack to change Cap size
Solve VGA can not thermal shutdown and
PAGE
KB dissolve
Modify List
M.B. Ver.
Add R229 (non-install) and contact to THERM#_VGA
1A
17
C1629 & C586 size change from 1206 to 0805
1A
23
Add R1906 (non-install) and R1896 install
1A
KB dissolve
Add Q30 & Q31

4
25
Prevent GPIO33 leakage
Change Q144 to CHP202U_SC70
1A
5
6
7
8
9
10
11
12
B
13
14
15
16
17
18
A
19
Compal Secret Data
2006/09/25
Issued Date
2006/09/25
Deciphered Date
Title
HW PIR
2

Custom
Date:
Rev
1A
LA3262P_DIS__M64
Sheet

1
57
of
57

HP 6910 Pla 3262 P

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A

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Tuesday, August 21, 2007

CRT & TV OUT

DDR2 667MHz 1.8V

Intel Crestline MCH

LVDS Panel Interface

(PM) FCBGA 1299

P18, 19, 20, 21, 22, 23

P7, 8, 9, 10, 11, 12

CardBus Controller & PCMCIA conn

P24, 25, 26, 27

Slot 0/Smart Card

AMP & Audio Jack

SPI ROM & Debug port

SATA HDD Connector

SMSC Super I/O

SMSC KBC 1070

Power On/Off CKT.

Touch Pad CONN.

DC/DC Interface CKT.

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Tuesday, August 21, 2007

S5 S4/ Battery only

S5 S4/AC & Battery

Serial port (COM2),LAN/Modem

Serial port (COM1)

System CMOS/Real-time clock

Mass strorage control/ PCI simple communication control

synactic PS2 port GlidePAD

Numeric Data Process

Primary IDE interface,HDD

Secondary IDE innterface,CD-ROM

Mobile Intel Crestline Express Chipset Family

Microsoft UAA Bus Driver for High Definition Audio

Broadcom NetXtreme Gigabit Ethernet

CARD BUS & 1394

Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2

Ricoh R5C853 Gemcore based SmartCard Control

Walk-up0 (Right side)

Walk-up1 (Left Side)

Walk-up2 (Left Side)

Intel 82801H (ICH8 Family)USB Universal Host Controll

Intel 82801H (ICH8 Family)USB Universal Host Controll

Compal Secret Data

Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6

Ricoh R5C853 Cardbus Control

Intel 82801H (ICH8 Family)USB Universal Host Controll

Compal Electronics, Inc.

Size Document Number

Tuesday, August 21, 2007

Place R1431 within 200ps (~1") to CPU

For Merom, R23 and R34 are 0ohm

Thermal Sensor ADM1032ARMZ

11/20 Penryn support to add R23,R34

H_THERMDA, H_THERMDC routing together,

0802 (R1A) add for VGA thermal function

Merom Ball-out Rev 1a