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Sub-System Design

CMOS VLSI Design

Introduction
Large systems are composed of sub-systems, known as Leaf-Cells The most basic leaf cell is the common logic gate (inverter, nand, ..etc) Structured Design
High regularity Leaf cells replicated many times and interconnected to form the system

Logical and systematic approach to VLSI design is essential

CMOS VLSI Design

Some Architectural Issues


Engineering time is exponential as complexity increases

CMOS VLSI Design

Good Design Methodology


1. Define Requirements 2. Partition overall architecture into appropriate sub-systems 3. Consider communication paths in order to develop sensible interrelationships between subsystems 4. Draw a floor-plan of how the system is to map onto silicon and iterate above as appropriate 5. Aim for regular structures so that design is largely a matter of replication 6. Lay-out each cell (stick diagram) 7. Carry out design rule checks 8. Simulate performance of each cell / subsystem

CMOS VLSI Design

Switch Logic
Switch logic is based on pass transistor or on transmission gate . Pass transistor logic is similar to logic arrays based on relay contacts

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Pass transistor and Transmission gates

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Gate (restoring )Logic


The Inverter Two input nMOS, CMOS and BiCMOS Nand Gates . Fig 6.3 Fig 6.4 , 6.5 and 6.6 a-c Fig 6.6 (d )

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Two significant factors about nMOS Nand gate


nMOS Nand gate area requirements are considerably greater than those of nMOS Inverter. nMOS Nand gate delays are also increased in direct propagation to the no of inputs added

Nand =ninv

CMOS VLSI Design

Two input nMOS, CMOS and BiCMOS Nor Gates

CMOS VLSI Design

Stick diagrams(nMOS and CMOS)symbolic form of BiCMOS

CMOS VLSI Design

CMOS VLSI Design

Other Forms of CMOS Logic


Pseudo nMOS Logic Dynamic CMOS Logic. Clocked CMOS (C2MOS)Logic. CMOS domino logic. n p CMOS Logic.

CMOS VLSI Design

Pseudo nMOS Logic

CMOS VLSI Design

CMOS VLSI Design

Pseudo-nMOS Inverter when driven from similar Inverter

CMOS VLSI Design

CMOS VLSI Design

Dynamic CMOS Logic.

CMOS VLSI Design

Type three arrangement

CMOS VLSI Design

Clocked CMOS (C2MOS)Logic


Two Input Nor gate

CMOS VLSI Design

Inverter

CMOS VLSI Design

CMOS domino logic

CMOS VLSI Design

CMOS domino logic(conti)


Such logic structures can have smaller areas than conventional CMOS logic. Parasitic capacitances are smaller so higher operating speeds are possible Operation is free of glitches since gate can make 1 or 0 transisions Only non inverting structures are possible because of the presence of the inverting buffers , Charge distribution may be a problem and must be considered CMOS VLSI Design

n p CMOS Logic.

CMOS VLSI Design

Examples of Structured design (combinational Logic) A Parity Generator

CMOS VLSI Design

Parity generator-structured design approch

CMOS VLSI Design

Parity generator basic one-bit cell

CMOS VLSI Design

Stick diagrams (parity generator)

CMOS VLSI Design

Bus Arbitration Logic for n-line BUS

CMOS VLSI Design

Bus arbitration logic and truth table

CMOS VLSI Design

CMOS VLSI Design

Stick diagram-bus arbitration logic

An
An-1

CMOS VLSI Design

CMOS VLSI Design

Bus arbitration logic-structured design

CMOS VLSI Design

Bus arbitration logic-structured design


CMOS VLSI Design

Multiplexers(data selectors)

Selector logic circuit

CMOS VLSI Design

Switch logic implementations of a four-way mux

CMOS VLSI Design

Four-way n-switch based mux layout

CMOS VLSI Design

General logic function block(2 variables)

CMOS VLSI Design

CMOS VLSI Design

Two phase clocking

Non overlapping clks

CMOS VLSI Design

2 clk conti..
1-2 chosen correctly it avoids race condition. Clk generated will be slow 1-2 are non symmetrical. To optimize the design,clks can overlapped.

CMOS VLSI Design

Two-Phase Clock Timing new data applied to CL2


previous data latched into M2

f1
f2

Tf1
Tf12 Tf2 Tf21 clock overlap d-Tf12 clock period T

f1

tmin > d Tf12 tmax < T + d Tf12


Spring 2006 CMOS VLSI Design

[Prentice Hall] EE 5324 - VLSI Design II - Kia 52

Two phase clock generator using D flip-flops

Frequency is half in each D-FF.


CMOS VLSI Design

Simple two phase clock generator

Minimum under lap period is generated by two inverter.


CMOS VLSI Design

Waveforms for two-phase clock generator

CMOS VLSI Design

Two-phase clock generator(with complementary outputs)for BiCMOS logic implementation

CMOS VLSI Design

Two-phase clock generator(with complementary outputs)for BiCMOS logic implementation

npn inside to drive large capacitance


CMOS VLSI Design

Mask layout for Two-phase clock generator(with complementary outputs)for BiCMOS logic implementation

CMOS VLSI Design

Waveforms for circuit BiCMOS Logic

CMOS VLSI Design

Charge storage
gate

Channel

CMOS VLSI Design

Simple stored charge model

CMOS VLSI Design

Dynamic register element

Basic inverting dynamic storage cells A.nMOS pass transistor switched B.CMOS Transmission gate switched

CMOS VLSI Design

Non inverting dynamic storage cells

A.nMOS pass transistor switched B.CMOS Transmission gate switched

CMOS VLSI Design

Dynamic shift register

CMOS VLSI Design

Shift Registers: Idea


Shift registers are used for iteratively shifting data Used in pipelining, bit-by-bit processing, etc.

f
D1
D D1

f
D2
D2

f
D3
D3

f
D1

f
D2

f
D3

Problem?

When clock goes high, the data will traverse all the shift registers chain in one clock cycle! Solution: use non overlapping clocks f1 and f2. f1 used by odd gates, f2 by even gates (use xmission gates after D1, D2, D3). EE 5324 - VLSI Spring 2006 CMOS VLSI Design
Design II - Kia 65

Four-bit dynamic shift registers(nMOS and CMOS)

CMOS VLSI Design

stick diagrams for shift register cells

CMOS VLSI Design

Other system considerations


The use of buses to interconnect subsystem and circuit must be carefully considered -current carrying capacity of Al

CMOS VLSI Design

Mask layout for nMOS and CMOS register cells

CMOS VLSI Design

Passive bus-nMOS or CMOS

CMOS VLSI Design

Active bus (not CMOS)

CMOS VLSI Design

Pre charged bus-nMOS case

CMOS VLSI Design

Pre charged bus-CMOS case

CMOS VLSI Design

Power dissipation for CMOS and BiCMOS circuits

CMOS VLSI Design

Current and power determination for nMOs and Pseudo nMOS logic is similar. For Complementary circuit, short current pulses are negligible compared with charge and discharge of capacitors. Overall dissipation is composed of two terms.
1.pI the dissipation due to the leakage current II through an off

transistor. Consequently ,for n transistors PI=n.IIVDD . Where II=0.1nA,at room temp. 2. Ps is the dissipation due to energy supplied to charge and discharge the capacitances associated with each switching circuit PS=CLVDD2F

3.The total power dissipation PT=PI+PS


CMOS VLSI Design

The average current may be deduced Power dissipation for bipolar devices can be simply modeled by P=vccXIc

CMOS VLSI Design

Current limitations for VDD and GND rails

CMOS VLSI Design

Electromigration
The exchange of momentum between electrons and metal lattice atoms can cause physical voids or cracks at grain boundaries These defects grow under stress and eventually cause an open circuit

CMOS VLSI Design

SUBSYSTEM DESIGN PROCESSES


Unit-6

CMOS VLSI Design

OBJECTIVE
Design of digital subsystem using a top-down approach. Microprocessor as example Step-by-step nature of structured design

CMOS VLSI Design

Some general considerations good design include


1. Lower unit cost. 2. Higher reliability. 3. Lower power dissipation. lower weight, and lower volume. 4. Better performance-particularly in terms of speed power product. 5. Enhanced repeatability. 6. The possibility of reduced design/development periods.

CMOS VLSI Design

Some problems associated design are


1.How to design large complex system in a reasonable time and with reasonable effort. 2.The nature of architecture best suited to take full advantage of VLSI and the technology. 3.The testability of large/complex systems once implemented in silicon. Problem 1and 3 can reduced if two things are practiced * Approach the design in top-down manner and with adequate CAD to do the job. partition the system sensibly, aming for simple interconnection . * Design testability into the system from the outset and can be prepared to devote a significant proportion (30%) of the total chip for diagnostic facilities.
CMOS VLSI Design

An illustration of design processes


Structured design begins with the concept of hierarchy. It is possible any complex function into less complex sub functions(top-down design ). As a systems complexity increases, its organization changes as different factors become relevant to its creation. Coupling can be used as a measure of how much sub modules interact. It is crucial that components interacting with high frequency be physically proximate,
CMOS VLSI Design

An illustration of design processes conti..


Concurrency should be exploited it is desirable that all gates on the chip do useful work most of the time. Adaptation to a new process must occur in a short time In presenting a design the design process uses - conventional circuit symbols. -logic symbols. -stick diagrams. -any mixture of logic symbols and stick diagrams that is convenient at a particular stage. -mask layouts. -architectural block diagrams. -floor plans
CMOS VLSI Design

Basic digital processor structure

CMOS VLSI Design

Communications strategy for data path

CMOS VLSI Design

CMOS VLSI Design

Subunits and basic interconnections for data path

CMOS VLSI Design

Basic bus architectures

Sequence(1)first operand from registers to ALU operand is stored there. (ii)Second operand from registers to ALU. operands are added(etc). (iii)The result is passed through shifter and stored in the registers
CMOS VLSI Design

Basic bus architectures

Sequence(i)Two operands(A and B) are sent from register(s) to ALU and are operated upon and the result(s)is stored in ALU. (ii)Result is passed through the shifter and stored in the registers
CMOS VLSI Design

Basic bus architectures

Sequence the two operands(A and B)are sent from the registers. Operated upon . And the shifted result(s)returned to another register all in the same clock period.

CMOS VLSI Design

Tentative floor plan for 4-bit data path

CMOS VLSI Design

CMOS VLSI Design

Precautions during design of data path or control path


1. Metal can cross poly silicon or diffusion without any significant effect. 2. Whenever poly silicon crosses diffusion a transistor will be formed. This includes the second poly layer for processes that have two. 3. Whenever lines touch on the same line an interconnection is formed. 4. Simple contacts can be used to join diffusion or poly to metal. 5. Buried contact or a butting contact to join poly to diffusion.
CMOS VLSI Design

6. In some process a second metal layer is available. this can cross over any other layers and is conveniently employed for power rails. 7.First and second metal layers may be joined using via. 8. Each layer has particular electrical properties which must be taken into account. 9.For CMOS layouts , p-and n-diff wires must not directly join each other ,nor may they cross either a p-well or an n-well boundary.

CMOS VLSI Design

The design of a 4-bit shifter

CMOS VLSI Design

Shifter must have


Input from a four-line parallel data bus, Four lines for the shifted data, Means of transferring input data to output lines with any shift from zero to three bits inclusive.

CMOS VLSI Design

4X4 crossbar switch

CMOS VLSI Design

4X4 crossbar switch/Simple n-bit Shifter


Quadratic number of transistors One switch per path in2 in1 in3 in4

out1 out2

out3
out4
Spring 2006 CMOS VLSI Design 99

CMOS VLSI Design

Barrel Shifter
A3
Sh1

B3

Bit 3 wrapped around

A2
Sh2

B2 Data Wire B1
Sh3

A1
A0

Control Wire

B0

Area dominated by wiring

Sh0

Sh1

Sh2

Sh3
CMOS VLSI Design

ONE POSSIBLE STICK DIAGRAM FOR 4x4 barrel shifter

CMOS VLSI Design

A3 A2 A1 A0

Sh0

Sh1

Sh2

Sh3

Barrel Shifter: Layout

Buffer

CMOS VLSI Design

Barrel shifter standard cell 2-mask layout

CMOS VLSI Design

Observation

CMOS VLSI Design

Bounding box for 4X4 barrel shifter

CMOS VLSI Design

CMOS VLSI Design

CMOS SUBSYSTEM PROCESSESS

CMOS VLSI Design

SOME OBSERVATION ON THE DESIGN PROCESS


1. First and foremost, try to put requirements into words(an if, then, else approach often helps ) so that the most appropriate architecture or logic can be evolved. 2. If a standard cell (or cells) can be arrived at, then the actual detailed design work is confined to relatively small areas of simple circuitry(leaf-cells).such cells can usually have their performance simulated with relative ease so that an idea of the performance of the complete subsystem may be deduced. 3. If generality as well as regularity is achieved then, for example ,any size of shifter can be build up by simple replication and butting together of the standard cell(s). 4. Design is largely a matter of the topology of communication rather than detailed logic circuit design.
CMOS VLSI Design

5.Once standard cell layout are designed ,overall area calculations can be precisely made(not forgetting to allow for any necessary links or other external terminations).thus accurate floor plan areas may be allocated. 6.VLSI design methodology for MOS circuits is not hard to learn. 7.The design rules are simple and straightforward in application. 8.A structured and orderly approach to the system design is highly beneficial and becomes essential for large systems.
CMOS VLSI Design

REGULARITY
Regularity=total number of transistors on the chip/ Number of transistors circuits that must be designed in detail

CMOS VLSI Design

Design of ALU subsystem

CMOS VLSI Design

Design of ALU subsystem The main unit is 4-adder circuit. Adopted for subtract and logical operations.

ALU is clocked all operations in one clock cycle.

Shifter is un-clocked.

CMOS VLSI Design

4-bit data path for processor (block diagram)

CMOS VLSI Design

Design of a 4-bit adder

CMOS VLSI Design

Truth table for binary adder

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Adder element

CMOS VLSI Design

Multiplexer(n-switches)-based adder logic with stored and buffered sum output

CMOS VLSI Design

CMOS version of adder logic

CMOS VLSI Design

CMOS adder element

CMOS VLSI Design

CMOS VLSI Design

Multiplexer cell with or without cut

CMOS VLSI Design

nMOS (butting contact) inverter

CMOS VLSI Design

nMOS (buried contact) inverter

CMOS VLSI Design

CMOS inverter design

CMOS VLSI Design

Approximate bounding box and floor plan for CMOS adder

CMOS VLSI Design

4-BIT ADDER

CMOS VLSI Design

4-bit adder outline

CMOS VLSI Design

Implementing ALU function with adder

CMOS VLSI Design

4-bit ALU

CMOS VLSI Design

Further consideration of adder

CMOS VLSI Design

Symmetrical adder cell arrangement

CMOS VLSI Design

The pass/generate concept

An adder element based on the pass/generate concept


CMOS VLSI Design

Manchester carry-chain element

CMOS VLSI Design

Cascaded Manchester carry-chain elements with buffering

CMOS VLSI Design

Adder enhancement techniques

CMOS VLSI Design

Carry select adder structure(6-bit)

CMOS VLSI Design

Diagrammatic representation of carry skip adder

CMOS VLSI Design

Structure of a 24-bit carry skip adder

CMOS VLSI Design

Worst case carry propagation for carry skip adder

CMOS VLSI Design

Possible implementation of the block propagation concept

CMOS VLSI Design

Carry look-ahead(CLA) adders

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

A 16-bit, 4X4 block CLA adder

CMOS VLSI Design

Generation of carry out(from 4-bits and carry in)

CMOS VLSI Design

Four cell Manchester carry-chain

CMOS VLSI Design

Comparison of adder enhancement techniques

CMOS VLSI Design

Adder cells with alternate input/output arrangement

Vdd

CMOS VLSI Design

2-way multiplexer showing multiplexer cell

CMOS VLSI Design

32-bit carry-select adder

CMOS VLSI Design

32-bit carry look ahead adder

CMOS VLSI Design

Multipliers

CMOS VLSI Design

Serial-parallel multiplier

CMOS VLSI Design

Arrangement of a 4-bit serialparallel multiplier

CMOS VLSI Design

Braun array

CMOS VLSI Design

Twos complement multiplication using the Baugh-wooley method

CMOS VLSI Design

4-bit Braun multiplier

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Pipelined multiplier array

CMOS VLSI Design

4-bit Baughwooley multiplier

CMOS VLSI Design

Systolic array multiplier

CMOS VLSI Design

Multiplier structure

CMOS VLSI Design

Basic cell

CMOS VLSI Design

Modified Booths algorithm

CMOS VLSI Design

Modified Booths Multiplication

CMOS VLSI Design

Booth encoder

CMOS VLSI Design

Wallace tree multipliers

CMOS VLSI Design

Wallace tree elements

CMOS VLSI Design

Recursive decomposition of the multiplication

CMOS VLSI Design

Example of Wallace tree approach

CMOS VLSI Design

8-bit input multiplier arrnement

CMOS VLSI Design

Daddas method

CMOS VLSI Design

END

CMOS VLSI Design