Lecture41,42&43 Timing

Analysis
Jagannadha Naidu K
Sequencing Methods
Flip-flops
Pulsed Latches
F
l
i
p
-
F
l
o
p
s
F
l
o
p
L
a
t
c
h
F
l
o
p
clk

p
clk clk
L
a
t
c
h
L
a
t
c
h

p

p

1

1

2
2
-
P
h
a
s
e

T
r
a
n
s
p
a
r
e
n
t

L
a
t
c
h
e
s
P
u
l
s
e
d

L
a
t
c
h
e
s
Combinational Logic
Combinational
Logic
Combinational
Logic
Combinational Logic
L
a
t
c
h
L
a
t
c
h
T
c
T
c
/2
t
nonoverlap
t
nonoverlap
t
pw
Half-Cycle 1 Half-Cycle 1
Timing Diagrams
F
l
o
p
A
Y
t
pd
Combinational
Logic
A Y
D Q
clk
clk
D
Q
L
a
t
c
h
D Q
clk
clk
D
Q
t
cd
t
setup
t
hold
t
ccq
t
pcq
t
ccq
t
setup
t
hold
t
pcq
t
pdq
t
cdq Latch/Flop Hold Time
t
hold
Latch/Flop Setup Time
t
setup
Latch D->Q Cont. Delay
t
cdq
Latch D->Q Prop. Delay
t
pdq
Latch/Flop Clk->Q Cont. Delay
t
ccq
Latch/Flop Clk->Q Prop. Delay
t
pcq
Logic Cont. Delay
t
cd
Logic Prop. Delay
t
pd
Contamination and
Propagation Delays
Max-Delay: Flip-Flops
F
1
F
2
clk
clk clk
Combinational Logic
T
c
Q1 D2
Q1
D2
t
pd
t
setup
t
pcq
( )
setup
sequencing overhead
pd c pcq
t T t t +
14243
Max Delay: Pulsed Latches
T
c
Q1 Q2 D1 D2
Q1
D2
D1

p

p
Combinational Logic
L
1
L
2
t
pw
(a) t
pw
> t
setup
Q1
D2
(b) t
pw
< t
setup
T
c
t
pd
t
pdq
t
pcq
t
pd
t
setup
( )
setup
sequencing overhead
max ,
pd c pdq pcq pw
t T t t t t +
14444244443
Min-Delay: Flip-Flops
hold cd ccq
t t t
CL
clk
Q1
D2
F
1
clk
Q1
F
2
clk
D2
t
cd
t
hold
t
ccq
Min-Delay: Pulsed Latches
hold cd ccq pw
t t t t +
CL
Q1
D2
Q1
D2

p
t
pw

p
L
1

p
L
2
t
cd
t
hold
t
ccq
Hold time increased
by pulse width
Time Borrowing
In a flop-based system:
Data launches on one rising edge
Must setup before next rising edge
If it arrives late, system fails
If it arrives early, time is wasted
Flops have hard edges
In a latch-based system
Data can pass through latch while transparent
Long cycle of logic can borrow time into next
As long as each loop completes in one cycle
Time Borrowing Example
L
a
t
c
h
L
a
t
c
h
L
a
t
c
h
Combinational Logic
Combinational
Logic
Borrowing time across
half-cycle boundary
Borrowing time across
pipeline stage boundary
(a)
(b)
L
a
t
c
h
L
a
t
c
h
Combinational Logic
Combinational
Logic
Loops may borrow time internally but must complete within the cycle

1

1

2
How Much Borrowing?
Q1
L
1

2
L
2

1

2
Combinational Logic 1
Q2 D1 D2
D2
T
c
T
c
/2
Nominal Half-Cycle 1 Delay
t
borrow
t
nonoverlap
t
setup
borrow setup pw
t t t
Pulsed Latches
Clock Skew
We have assumed zero clock skew
Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing
Skew: Flip-Flops
F
1
F
2
clk
clk clk
Combinational Logic
T
c
Q1 D2
Q1
D2
t
skew
CL
Q1
D2
F
1
clk
Q1
F
2
clk
D2
clk
t
skew
t
setup
t
pcq
t
pdq
t
cd
t
hold
t
ccq
( )
setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
+ +
+
144424443
Skew: Latches
Q1
L
1

2
L
2
L
3

1

1

2
Combinational
Logic 1
Combinational
Logic 2
Q2 Q3 D1 D2 D3
( )
( )
sequencing overhead
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
2
,
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
T
t t t t

+
+ +
123
2-Phase Latches
( )
( )
setup skew
sequencing overhead
hold skew
borrow setup skew
max ,
pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
+ +
+ +
+
1444442444443
Pulsed Latches
Safe Flip-Flop
Past years used flip-flop with nonoverlapping clocks
Slow nonoverlap adds to setup time
But no hold times
In industry, use a better timing analyzer
Add buffers to slow signals if hold time is at risk
D

2
X
Q
Q

2
Summary
Flip-Flops:
Very easy to use, supported by all tools
Pulsed Latches:
Fast, some skew tol & borrow, hold time risk