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EXPERIMENT-1 AIM- Design Of Universal Gates SOFTWARE USED- XILINX ISE 8.1 (A) AND Gate

AND Gate Schematic

AND gate RTL Schematic

AND Gate Test Bench Waveform

(A) AND Gate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end andgate; architecture Behavioral of andgate is begin process(a,b) begin if (a='1' and b='1') then c<='1'; else c<='0'; end if; end process; end Behavioral;

(B) OR Gate

OR Gate Schematic

OR Gate RTL Schematic

OR Gate Test Bench Waveform

(B) OR Gate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity orgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC); end orgate; architecture or_df of orgate is begin y<=a or b; end or_df;

(C) NOT Gate

NOT gate Schematic

NOT Gate RTL Schematic

NOT Gate Test Bench Waveform

(C) NOT Gate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity notgate is Port ( a : in STD_LOGIC; y : out STD_LOGIC); end notgate; architecture not_df of notgate is begin y<= not a; end not_df;

EXPERIMENT-2 AIM- Design Of Universal Gates SOFTWARE USED- XILINX ISE 8.1 (A) NAND Gate

Nand Gate Schematic

NAND Gate RTL Schematic

NAND Gate Test Bench Waveform

EXPERIMENT-2 AIM- Design Of Universal Gates SOFTWARE USED- XILINX ISE 8.1 (A) NAND Gate
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity nandgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC); end nandgate; architecture nand_df of nandgate is begin y<= a nand b; end nand_df;

(B) NOR Gate

NOR Gate Schematic

NOR Gate RTL Schematic

NOR Gate Test Bench Waveform

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(B) NOR Gate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity norgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC); end norgate; architecture nor_df of norgate is begin y<=a nor b; end nor_df;

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EXPERIMENT-3 AIM- Design Of 2:1 Multiplexer SOFTWARE USED- XILINX ISE 8.1

2:1 Multiplexer Schematic

2:1 Multiplexer Schematic Contituent

2:1 Multiplexer RTL Schematic

2:1 Multiplexer Test Bench Waveform

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EXPERIMENT-3 AIM- Design Of 2:1 Multiplexer SOFTWARE USED- XILINX ISE 8.1
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux_2_1 is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); s : in STD_LOGIC; y : out STD_LOGIC); end mux_2_1; architecture Behavioral of mux_2_1 is begin process(s,a) begin if s='0' then y<=a(0); else y<= a(1); end if; end process; end Behavioral;

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EXPERIMENT-4 AIM- Design Of 2to 4 Decoder SOFTWARE USED- XILINX ISE 8.1

Schematic Of 2 to 4 decoder

Constituent Of 2 to 4 Decoder

RTL Schematic Of 2 to 4 Decoder

Testbench Waveform Of 2 to 4 Decoder

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EXPERIMENT-4 AIM- Design Of 2to 4 Decoder SOFTWARE USED- XILINX ISE 8.1

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity decoder2_4 is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2_4; architecture Behavioral of decoder2_4 is begin with a select y <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when others ; end Behavioral;

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EXPERIMENT-5 AIM- Design Of half Adder, Full Adder, Half Subtractor and Full Subtractor SOFTWARE USED- XILINX ISE 8.1 (A) Half Adder

Half Adder Schematic

RTL Schematic Of Half Adder

Constituent Of Half Adder

Test Bench waveform Of Half Adder 16

EXPERIMENT-5 AIM-Design of Half Adder, Full Adder, Half Subtractor and Full Subtractor SOFTWARE USED- XILINX ISE 8.1 (A) Half Adder
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfadder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end halfadder; architecture ha_df of halfadder is begin s<= a xor b; c<= a and b; end ha_df;

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(B) Full Adder

Full Adder

RTL Schematic Of Full Adder

Full Adder Constituent

Full Adder Constituent

Full Adder Test Bench Waveform 18

(C) Full Adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end fulladder; architecture Behavioral of fulladder is begin s<= a xor b xor cin; c<= (a and b) or (b and cin) or (a and cin); end Behavioral;

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EXPERIMENT-6 AIM-Design of 3:8 Decoder SOFTWARE USED-XILINX ISE 8.1

3:8 Decoder Schematic

3:8 Schematic Constituent

3:8 Decoder RTL Schematic

3:8 Decoder Test Bench Waveform 20

EXPERIMENT-6 AIM- Design of 3:8 decoder SOFTWARE USED- XILINX ISE 8.1

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity decoder3_8 is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end decoder3_8; architecture dec3_8df of decoder3_8 is begin with a select y <= "00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when others ; end dec3_8df;

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