v

LIST OF FIGURES
Figure No. Page No.
1.1 BGFSB Design 02
1.2 1 Bit ALU Design 03
3.1 CMOS Full Adder 08
3.2 Two dynamic NAND gates sharing same clock 10
3.3 Output waveforms of two dynamic NAND gates sharing same clock 11
3.4 Domino Full Adder 12
3.5 Split Path Data Driven Dynamic Logic Full adder 13
3.6 Complementary Pass Transistor Logic Adder 14
3.7 Transmission Gate Full Adder 15
3.8 Transmission Function Full Adder 16
3.9 10 Transistor Based Full Adder 16
3.10 14Transistor Based Full Adder 17
3.11 Hybrid Full Adder 18
3.12 XOR-XNOR 6T Gate 19
3.13 3T XOR Gate 20
3.14 Modified Hybrid Full Adder (8T) 20
4.1 1 Bit ALU 21
4.2 Inverter with BGFSB Method 22
4.3 Inverter without BGFSB Method 22
5.1 Block Diagram of 4-Bit ALU 23
5.2 Ripple Carry Adder 26
6.1 14 T Adder 28
6.2 14 T Adder Simulation 29
6.3 10 T Adder 30
6.4 10 T Adder Simulation 31
6.5 AND Gate 32
6.6 AND Gate Simulation 32
6.7 4:1 Mux 33
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6.8 4:1 Mux Simulation 34
6.9 OR Gate 35
6.10 OR Gate Simulation 35
6.11 XOR Gate 36
6.12 XOR Gate Simulation 36
6.13 Inverter 37
6.14 Inverter Simulation 37
6.15 1 Bit ALU 38
6.17 8 Bit ALU 39
6.18 8 Bit ALU Simulation 40
6.19 16 Bit ALU 42
6.20 16 Bit ALU Simulation 43
6.21 32 Bit ALU 47
6.22 32 Bit ALU Simulation 48
6.23 NMOS WITH SOURCE AT SUBSTRATE 54
6.24 PMOS WITH SOURCE AT SUBSTRATE 54
6.25 Mux 55
6.26 Mux Simulation 56
6.27 AND Gate 57
6.28 AND Gate Simulation 58
6.29 Inverter 59
6.30 Inverter Simulation 60
6.31 OR Gate 61
6.32 OR Gate Simulation 62
6.33 14T Adder 63
6.34 14T Adder Simulation 64
6.35 10T Adder 65
6.36 10T Adder Simulation 66
6.37 1 Bit ALU 67
6.38 8 Bit ALU 68
6.39 8 Bit ALU Simulation 69
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6.40 16 Bit ALU 71
6.41 16 Bit ALU Simulation 72
6.42 32 Bit ALU 76
6.43 32 Bit ALU Simulation 77



























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LIST OF TABLES

Page No.
TABLE 3.1 Full Adder 09
TABLE 5.1 ALU Operation 26
TABLE 6.1 Adder Comparison 84
TABLE 6.2 ALU Comparison 84