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+
(
+
(
=
(
Iq
Id
Gq
Gd
Gq
Gd
Gq
Gd
u
u
i
i
L
L
i
i
dt
d
L
u
u
0
0
e
e
I
G
G
u
dt
i d
L u + =
Grid mode controller design
u
Id
e
G
L
i
d
Ls+R
1
e
G
L
i
q
Ls+R
1
u
Iq
u
Gd
u
Gq
i
d
*
e
G
L
u
Id
*
PI reg.
e
G
L
i
q
*
i
d
i
q
u
Gd
u
Gq
u
Iq
*
PI reg.
Controller Plant
Active Rectifier control structure
C
D
C
U
Y
u
I
ACG
s
a
,s
b
,s
c
VLT
5022
POWER
STAGE
LCL
filter
i
A,B,C
I
ACG
u
A,B,C
I
ACG
U
DC
D
A
D
A
D
A
SVM
2
3
PLL
U
X
u
I
ACG
dq
ab
cc
-eL
eL
u
d
u
u
I
ACG
i
d
u
I
ACG
i
q
u
I
ACG
i
q
*
=0
u
I
ACG
U
DC
*
*
u
I
ACG
i
d
*
u
I
ACG
V
DC
controller
Av
q
u
I
ACG
Av
d
u
I
ACG
u
d
*
u
I
ACG
u
q
*
u
I
ACG
i
d
controller
i
q
controller
u
q
GRID
filter
Grid connected
Model of the LCL filter
L
G
C
F
L
I
u
Ia
u
Ib
u
Ic
u
Ga
u
Gb
u
Gc
a)
R
D
L
G
L
I
u
I
u
G
i
I
i
G
C
F
R
D
b)
i
C
u
C
G I G
G I I
i z i z u
i z i z u
22 21
12 11
+ =
+ =
D
F
D
F
G
D
F
D
F
I
R
s C
z R
s C
s L z
R
s C
z R
s C
s L z
+ = + + =
+ = + + =
1
),
1
(
)
1
( ,
1
21 22
12 11
u
I
L
I
s
1
L
G
s
1
C
F
s
1
+R
D
u
G
i
G
i
I
u
C
LCL filter design
Bode Diagram
Frequency (Hz)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-40
-30
-20
-10
0
10
20
10
2
10
3
-90
-60
-30
0
undamped LCL
damped LCL
L
L
I
[mH]
1.25
L
G
[mH]
1.5
C
F
[F]
6
R
D
[O]
4
Q
c
<5%
Z
T
<10%Z
b
e
res
<0.5e
sw
) (
) (
) (
s u
s i
s H
I
I
=
% 10
) (
) (
<
sw
I
sw
I
u
i
e
e
% 20
) (
) (
<
sw
I
sw
G
i
i
e
e
Current attenuation
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-20
-10
0
10
20
i
i
[
A
]
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-20
-10
0
10
20
i
g
[
A
]
t [s]
Current controller design
s L L s L L C R s C L L
s C R
s u
s i
s G
G I G I F D F G I
F D
I
G
+ + + +
+
= =
) ( ) (
1
) (
) (
) (
2 3
)
`
Z =
s
s G
z z G
) (
) 1 ( ) (
1
Root locus
Root Locus
Real Axis
I
m
a
g
A
x
i
s
-1 -0.5 0 0.5 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.57e4
1.41e4
1.26e4
1.1e4
9.42e3
7.85e3
6.28e3
4.71e3
3.14e3
1.57e3
1.57e4
1.41e4
1.26e4
1.1e4
9.42e3
7.85e3
6.28e3
4.71e3
3.14e3
1.57e3
System: f o
Gain: 4.8
Pole: 0.511 + 0.301i
Damping: 0.7
Overshoot (%): 4.6
Frequency (rad/sec): 3.73e+003
Bode Diagram
Frequency (Hz)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-20
-15
-10
-5
0
5
System: f z
Frequency (Hz): 674
Magnitude (dB): -3.06
10
1
10
2
10
3
-360
-270
-180
-90
0
System: f z
Frequency (Hz): 208
Phase (deg): -45.5
-2 0 2 4 6 8
x 10
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
time (s)
i
(
A
)
Kp=4.8
Ti=8 ms
DC-link controller design
) 1 (
) ( ) ( ) (
0
+
= =
s T s C
e K
s H s H s H
ei DC
s
DC
I DC O
t
k
DC
=0.7, T
et
=4.8ms
S
f
1
0
= t
( ) 02 . 0 4
0
= + = t
et I
T T
47 . 0
) ( 2
0
=
+
=
t
et DC
DC
P
T K
C
K
C
DC
>>(T
ei
+t
0
), optimal symmetry criterion
Root locus
Root Locus
Real Axis
I
m
a
g
A
x
i
s
-200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0
-400
-300
-200
-100
0
100
200
300
400
400
300
200
100
400
300
200
100
0.8
0.54
0.38 0.26 0.19 0.13 0.085 0.04
0.8
0.54
0.38 0.26 0.19 0.13 0.085 0.04
System: f o
Gain: 0.35
Pole: -55.1 + 90.6i
Damping: 0.52
Overshoot (%): 14.8
Frequency (rad/sec): 106
System: f o
Gain: 0.469
Pole: -66 - 123i
Damping: 0.473
Overshoot (%): 18.6
Frequency (rad/sec): 140
Bode Diagram
Frequency (rad/sec)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-40
-30
-20
-10
0
10
System: f z
Frequency (rad/sec): 178
Magnitude (dB): -3.01
10
1
10
2
10
3
-180
-135
-90
-45
0
System: f z
Frequency (rad/sec): 82.3
Phase (deg): -45
Kp=0.35
Ti=20 ms
Standalone control structure
C
D
C
U
Y
u
I
ACG
s
a
,s
b
,s
c
VLT
5022
POWER
STAGE
LCL
filter
i
A,B,C
I
ACG
u
A,B,C
I
ACG
U
DC
D
A
D
A
D
A
SVM
2
3
PLL
U
X
u
I
ACG
u
d
u
u
I
ACG
U
DC
*
*
u
I
ACG
U
DC
controller
Av
d
u
I
ACG
u
d
*
u
I
ACG
i
d
controller
u
d
voltage
controller
u
q
*
=0
local grid
PI
lim
u
d
*
u
I
ACG
i
lim
*
u
I
ACG
abc/dq
current limit
i
d,q
u
I
ACG
DC link
chopper
control
PWM
R
DC
Stand-alone
Main voltage controller design
G G D F G I D F G G D F I G F I
G G D F
I
G
Z Z R C L L s R C L Z R C L s L C L
Z s Z R C
u
u
+ + + + + + +
+
=
) ( ) ) ( (
2
Root locus
Root Locus
Real Axis
I
m
a
g
A
x
i
s
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.57e4
1.41e4
1.26e4
1.1e4
9.42e3
7.85e3
6.28e3
4.71e3
3.14e3
1.57e3
1.57e4
1.41e4
1.26e4
1.1e4
9.42e3
7.85e3
6.28e3
4.71e3
3.14e3
1.57e3
System: f o
Gain: 0.323
Pole: 0.393 + 9.61e-009i
Damping: 1
Overshoot (%): 0
Frequency (rad/sec): 4.67e+003
Bode Diagram
Frequency (Hz)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-25
-20
-15
-10
-5
0
System: f z
Frequency (Hz): 246
Magnitude (dB): -3.02
10
2
10
3
-360
-270
-180
-90
0
System: f z
Frequency (Hz): 131
Phase (deg): -44.8
Kp=0.1
Ti=0.29 ms
Bode Diagram
Frequency (Hz)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-25
-20
-15
-10
-5
0
System: f z
Frequency (Hz): 1.64e+003
Magnitude (dB): -9.33
10
2
10
3
-360
-270
-180
-90
0
System: f z
Frequency (Hz): 76.5
Phase (deg): -45.2
1% load
nominal load
Hz f
bw
76 =
DC-link voltage limiter
) 1 (
) ( ) ( ) (
0
+
= =
s T s C
e K
s H s H s H
et DC
s
O
I DC O
t
483 . 0 7 . 0
5 . 14
1 1
= = =
DC
G
O
K
Z
K
T
et
=2.1ms, t
0
=0.2ms
( ) ms T T
et I
092 . 0 4
0
= + = t
C
DC
>>(T
ei
+t
0
), optimal symmetry criterion
Root-locus
Root Locus
Real Axis
I
m
a
g
A
x
i
s
-450 -400 -350 -300 -250 -200 -150 -100 -50 0
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1e+003
800
600
400
200
1e+003
800
600
400
200
0.8
0.56
0.4 0.28 0.2 0.14 0.09 0.04
0.8
0.56
0.4 0.28 0.2 0.14 0.09 0.04
System: f o
Gain: 0.787
Pole: -130 + 201i
Damping: 0.543
Overshoot (%): 13.1
Frequency (rad/sec): 239
Bode Diagram
Frequency (Hz)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-20
-15
-10
-5
0
5
System: f z
Peak gain (dB): 4.1
At f requency (Hz): 30.5
10
1
10
2
-180
-135
-90
-45
0
System: f z
Frequency (Hz): 29.3
Phase (deg): -45.1
Kp=0.79
Ti=0.092 ms
DC-link choper operation
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
700
710
720
730
740
750
760
duty__cycle
U
d
c
[
V
]
U
CHOPP MIN
U
CHOPP MAX
U
DC MAX
max
_ _
_
_ d
U U
U U
cycle duty
MIN CHOPP MAX CHOPP
MIN CHOPP DC
=
DC
BRnom
U
U
cycle duty = _
R
DC
Phase angle detection
x
y
u
x
u
y
u
O
d
q
x
y
u
u
1
tan
= O
e
0
cos( )
E
u
I
ACG
e
g
sin
sin( -O)
E
u
I
ACG
PI
sin
sin( )
O
O = AO ~ O ) sin(
2 2
) sin(
y x
y
u u
u
+
=
2 2
) cos(
y x
x
u u
u
+
=
Kp=80
Ti=1 s
Simulation in grid mode
Steady state simulation
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-30
-20
-10
0
10
20
30
t [s]
i
a
[
A
]
u
a
/
1
0
[
V
]
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-30
-20
-10
0
10
20
30
t [s]
i
a
[
A
]
u
a
/
1
0
[
V
]
Grid mode
Generating mode
Ideal phase voltage 2% 5
th
+ 1% 7
th
harmonics
Simulation in stand-alone mode
Steady state simulation
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-30
-20
-10
0
10
20
30
t [s]
i
a
[
A
]
u
a
/
1
0
[
V
]
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-300
-200
-100
0
100
200
300
t [s]
u
a
,
u
b
,
u
c
[
V
]
phase voltages and current at nominal power using resistive load
Stand-alone mode
Transient simulation
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-300
-200
-100
0
100
200
300
t [s]
u
a
,
u
b
,
u
c
[
V
]
0.06 0.07 0.08 0.09 0.1 0.11 0.12 0.13 0.14
-30
-20
-10
0
10
20
30
t [s]
i
a
[
A
]
u
a
/
1
0
[
V
]
Stand-alone mode
System startup Half of nominal load to nominal load
Implementation
IM
15kW
1500rp
m
T
M
*
s
a
,s
b
,s
c
VLT
5022
SCALAR
CONTROL
3x400V/50Hz
GRID
IG
11kW
1000rp
m
VLT
5022
VECTOR
CONTROL
VLT
5022
POWER
STAGE
LCL
filter
C
DC
C
i
A,B,C
u
A,B,C
U
D
C
D
A
D
A
D
A
D
A
D
A
D
A
SVM
Data
acquisition
&
transformati
D
A
DSPACE 1103
u
q
*
P
*
Generator
control
T
e
e
Grid connected
AR control
Standalone
control
Main control
U
DC
*
U
DC
U
dq
I
dq
U
AC
*
U
DC
*
U
dq
I
dq
u
d
*
e
?*
u
dSPACE 1103
MPPC 604e at 633Mhz
TMS320F240
16xADC-16 4s 10V
4xADC-12 800 ns 10V
8xDAC-14 bit -6 s 10
7x IE interface
32xI/0
TDE software
Combined control
ControlDesk
Steady state operation
Grid mode
Measured conditions
U
DC
=650V
U
AC
=220V
P=11.28kW
PF=0.998
I
THD
=6.7%
U
THD
=2%
Rectifying mode Generating mode
Transient operation
Grid mode
Nominal load system startup
Disturbance rejection
Steady state operation
Stand-alone mode
Resistive load
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-400
-300
-200
-100
0
100
200
300
400
U
a
,
U
b
,
U
c
[
V
]
t [s]
Ua
Ub
Uc
Ua Ub Uc
Measured conditions
U
DC
=700 V
U
AC
=230 V
P=11 kW
I
AC
=16.4 A
I
THD
=3.4 %
U
THD
=3.4 %
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-30
-20
-10
0
10
20
30
i
a
,
i
b
,
i
c
[
A
]
t [s]
ia
ib
ic
ic
ib
ia
Steady state operation
Stand-alone mode
3-phase diode bridge
Measured conditions
U
DC
=700 V
U
AC
=230 V
P=11 kW
I
AC
=16.6 A
I
THD
=25 %
U
THD
=10 %
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-400
-300
-200
-100
0
100
200
300
400
U
a
[
V
]
t [s]
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-25
-20
-15
-10
-5
0
5
10
15
20
25
i
a
[
A
]
t [s]
Transient operation
0 0.1 0.2 0.3 0.4 0.5
580
600
620
640
660
680
700
720
740
U
d
c
*
,
U
d
c
[
V
]
t [s]
Udc
Udc*
0 0.1 0.2 0.3 0.4 0.5
0
50
100
150
200
250
300
350
U
d
*
,
U
d
[
V
]
t [s]
Stand-alone mode
Full load applied on the
half of produced power
Transient operation
Stand-alone mode
Short-circuit startup
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
-3
-50
-40
-30
-20
-10
0
10
20
30
40
i
a
,
i
b
,
i
c
[
A
]
t [s]
ia
ib
ic
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
-3
-50
0
50
100
150
200
250
300
U
d
*
,
U
d
[
V
]
t [s]
Ud*
Ud
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
-3
0
5
10
15
20
25
30
35
40
45
i
d
[
A
]
t [s]
u
G
500F
32O
Automatic mode switch
Idle mode
Grid mode
Stand-alone mode
I-SA
I-GM
GM-I SA-I
GM-SA
I-GM:U
G
and /PLLe and /TRIP and START
I-SA:/U
G
and /TRIP and START
GM-I: TRIP or STOP
SA-I: TRIP or STOP or PLLe
GM-SA: PLLe
-0.02 -0.01 0 0.01 0.02 0.03 0.04
-400
-300
-200
-100
0
100
200
300
400
U
a
,
U
b
,
U
c
[
V
]
t [s]
Ua
Ub
Uc
Grid mode to Stand-alone mode transition
-0.02 -0.01 0 0.01 0.02 0.03 0.04
-25
-20
-15
-10
-5
0
5
10
15
20
25
i
a
,
i
b
,
i
c
[
A
]
t [s]
ia
ib
ic
-0.02 -0.01 0 0.01 0.02 0.03 0.04
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
e
t
h
e
t
a
,
P
L
L
e
t [s]
etheta
PLLe
nominal load
Stand-alone mode to Grid mode transition
-0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
-400
-300
-200
-100
0
100
200
300
400
U
a
,
U
b
,
U
c
[
V
]
t [s]
Ua
Ub
Uc
-0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
-30
-20
-10
0
10
20
30
40
i
a
,
i
b
,
i
c
[
A
]
t [s]
ia
ib
ic
-0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
e
t
h
e
t
a
,
P
L
L
e
t [s]
etheta
PLLe
dt
t di
L t u
L
L
) (
) ( =
Conclusion
Vector based control of DC/AC converter with near
unity power factor was succesfully designed,
simulated, implemented and verified.
LCL filter was designed, implemented and tested
Two different control strategies were implemented
according to the operating modes
A common controller design procedure is used to
tune controller parameters
PLL is designed to detect phase angle
Two different control strategies are implemented
and tested in dSPACE.
Automatic mode detection and switching betwen
modes can be implemented