-- Company: BUAP

-- Engineer: Nicolas Quiroz

--
-- Create Date: 10:24:00 08/29/2013
-- Design Name: Decodificador de binario a 7 segmentos
-- Module Name: Dec2to7 - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Dec2to7 is
Port ( dato : in STD_LOGIC_VECTOR (3 downto 0);
Habi : out STD_LOGIC_VECTOR (3
downto 0);
segmentos : out STD_LOGIC_VECTOR (7 downto 0));
end Dec2to7;

architecture Behavioral of Dec2to7 is

begin
habi <= "0011";
segmentos <= "11000000" when dato = "0000" else --0
x"f9" when dato = "0001" else --1
x"A4" when dato = "0010" else
--2
x"B0" when dato = "0011" else
--3
x"99" when dato = "0100" else
--4
x"92" when dato = "0101" else
--5
x"82" when dato = "0110" else
--6
x"F8" when dato = "0111" else
--7
x"80" when dato = "1000" else
--8
x"90" when dato = "1001" else
--9
x"88" when dato = "1010" else
--A
x"83" when dato = "1011" else
--B
x"C6" when dato = "1100" else
--C
x"A1" when dato = "1101" else
--D
x"86" when dato = "1110" else
--E
x"8E"; --F


end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mef is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
rw : in STD_LOGIC;
last : in STD_LOGIC;
rdsig : out STD_LOGIC;
wrsig : out STD_LOGIC;
done : out STD_LOGIC);
end mef;

architecture Behavioral of mef is
type STATE_TYPE is (ST1_IDLE, ST2_READING, ST3_WRITING, ST4_WAITING);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

begin
COMB: process (CURRENT_STATE, START, RW, LAST)
begin
NEXT_STATE <= ST1_IDLE; --ESTADO DEFAULT
DONE <= '0'; --SALIDAS
RDSIG <= '0';
WRSIG <= '0';
case (CURRENT_STATE) is
when ST1_IDLE =>
if START = '0' then
NEXT_STATE <= ST1_IDLE;
elsif RW = '1' then
NEXT_STATE <= ST2_READING;
else
NEXT_STATE <= ST3_WRITING;
end if;
when ST2_READING =>
RDSIG <= '1'; --SALIDA
if LAST = '0' then
NEXT_STATE <= ST2_READING;
else
NEXT_STATE <= ST4_WAITING;
end if;
when ST3_WRITING =>
WRSIG <= '1'; --SALIDA
if LAST = '0' then
NEXT_STATE <= ST3_WRITING;
else
NEXT_STATE <= ST4_WAITING;
end if;
when ST4_WAITING => --when others =>
DONE <= '1'; --SALIDA
NEXT_STATE <= ST1_IDLE;
end case;
end process;

SEC: process (CLK, RST)
begin
if (RST = '1') then
CURRENT_STATE <= ST1_IDLE;
elsif (CLK'event and CLK = '1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;

end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Timer is
Port ( rst : in STD_LOGIC;
clk50MHz : in STD_LOGIC;
clk1S : inout STD_LOGIC);
end Timer;

architecture Behavioral of Timer is
signal cuenta : integer;
signal i_clk: std_logic;

begin

-- *************** 1 seg ***************
process(rst, clk50MHz )
begin
if (rst='1') then cuenta <= 0;
elsif (clk50MHz'event and clk50MHz = '1') then
if (cuenta = 25000000) then
cuenta <= 0;
i_clk <= '1';
else
cuenta <= cuenta + 1;
i_clk <= '0';
end if;
end if;
end process;

--seal de Reloj de un segundo
process(rst, i_clk)
begin
if (rst='1') then
clk1S <= '0';
elsif (rising_edge(i_clk)) then
clk1S <= not clk1S;
end if;
end process;

end Behavioral;