Netbook Acer Aod270

1
ZE7 Block Diagram (Intel Cedar Trail-M Platform)

HDMI CONN
DC(3.5W) & DC(6.5W)

(32nm)
DDI1
1366x768
LVDS/eDP CONN
P2
400 / 640MHz
P17
CLK Gen.
SLG8LV631V
Cedarview-M
DDI0
HDMI 1.3a
01
DDR III,800/1066 MT/s
Micro-FCBGA8
(22x22mm)
Channel A
UNBUFFERED
DDRIII SODIMM
RC-B/F
CLK2/3, H=4
P4
LVDS 18bit,SC
1366x768
0ohm
P18
DAC
1920x1200
VGA CONN
P5~9
P18
x2 DMI Gen1
RTL8105TA-VC-CG
PCIE Gen1
Tigerpoint (NM10)
P22
1.5W
Mini card2
vFBGA
P25
(360 balls,17x17mm)
P22
Mini card1
P25
RTS5209-GR
CARDREADER
MM-SIM CARD
5 IN1 CARDREADER
USB interface
module
6
0 SATA II I/F
P19
Mobile 2.5" HDD
SD3.0, MS, MS PRO,

P26
xD, MMC
P24
USB PORT
P21
Left
P20
P25
P26
MIC In Jack
Analog MIC
Speaker Header (2W)
Audio CODEC
Realtek 271X P20
HD AUDIO I/F
RJ45 CONN
USB 2.0
P10~15
USB PORT
USB PORT
Right Down
Right Up
P21
CCD
P21
P18
EC
Nuvoton NPCE791L
P27
BATTERY CHAGER
P29
SYSTEM
5V/3V PCU
CPU Core
Gfx Core
DDR 1.5VSUS P32
Discharge/+1.8V/
+3.3V_PRIME P34
Keyboard
P19
Touch Pad
SPI Flash
P27
P19
Charger
PWM FAN
P29
P6
Thermal Protection
P30
+1.05V
P35
P33
Quanta Computer Inc.
http://hobi-elektronika.net
P31
PROJECT : ZE7
Size
Document Number
Date:
1
Rev
C3C
Block Diagram
Wednesday, August 31, 2011
7
Sheet
1
8
of
42
CLK GEN (CLK)
02
+3V
VDD_CLK_3.3V
+1.5V
VDD_CLK_1.5V
R219 1
2 2.2/J_6
L27
PBY160808T-301Y-N/2A/300ohm_6
L32
PBY160808T-301Y-N/2A/300ohm_6
D
C285
Place close to L32
C278
10U/10V_8
C254
.1U/10V_4
C225
C277
C224
.1U/10V_4
.1U/10V_4
10U/10V_8
<20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress

D
C242
.1U/10V_4
Place close to L27
.1U/10V_4
0.1uF near every power pin

U12
VDD_IO can be ranging from 1.05V to 3.3V.

+1.05V
VDD_CLKIO_1.05V
R221
L28
2A/300ohm_6
*0/short_6
Place close to L28
C228
C229
C249
C253
10U/10V_8
.1U/10V_4
.1U/10V_4
.1U/10V_4
CG_XOUT
CG_XIN
VDD_CORE_1.5
23
VDD_PCI_3.3
VDD_CORE_1.5
45
14
VDD_48M_3.3
PCI_STOP#
CPU_STOP#
36
42
PM_STPPCI# [13]
PM_STPCPU# [13]
From SB
CPU_0
CPU_0#
53
52
CLK_MCH_BCLK [6]
CLK_MCH_BCLK# [6]
To CPU (Host CLK)
100 MHz
CPU_1
CPU_1#
50
49
CLK_DDR3_REFCLK [8]
CLK_DDR3_REFCLK# [8]
To CPU (DDR3 IO CLK)
100 MHz
SRC_1/CPU_ITP
SRC_1/CPU_ITP#
44
43
CLK_PCIE_LANP
CLK_PCIE_LANN
To LAN (LAN)
100 MHz
SRC_2
SRC_2#
41
40
CLK_PCIE_MNC_P
CLK_PCIE_MNC_N
SRC_3
SRC_3#
38
37
CLK_PCIE_MPC_P [25]
CLK_PCIE_MPC_N [25]
To Mini Card 1 (WLAN)
SRC_4
SRC_4#
34
33
CLK_PCIE_DMIP
CLK_PCIE_DMIN
To CPU (DMI CLK)
100 MHz
SRC_5
SRC_5#
32
31
CLK_PCIE_MMC_P [26]
CLK_PCIE_MMC_N [26]
To Card Reader (MMC)
100 MHz
SRC_6
SRC_6#
28
27
DOT96/SRC7
DOT96#/SRC7#
18
19
30
VDD_SRC_IO_1.05
35
VDD_SRC_IO_1.05
48
VDD_CPU_IO_1.05
3
4
CG_XIN
VDD_REF_3.3
1
2
13
54
C238
33P/50V_4
SMBDT1
SMBCK1
[4,13,25] SMBDT1
[4,13,25] SMBCK1
Y2 14.318MHZ
7
8
NC
NC
NC
NC
XTAL_OUT
XTAL_IN
SDA
SCL
Load Capacitance=20p
1
C236
33P/50V_4
FSB
15
CG_XOUT
[10] CLKUSB_48
<Layout note>
Crystal place within 500mil of CK505
[13] 14M_ICH
33/J_4
USB_48M
R293
33/J_4
FSC
R296
R304
R291
[12] PCLK_ICH
[27] LCLK_EC
[25] PCLK_DEBUG
+3V
R312
22/J_4
22/J_4
33/J_4
USB48_2
REF/FSC
10
PCIF/ITP_EN
33M_SEL
11
25MHz/PCI_2/SEL_33MHz
R310
*100K_4
17
ITP_EN
R311
*20K/J_4
USB48_1/FSB
<20110110> CFG input hardware strapping to allocate PLL assignment.

LOW = Both CPU and SRC clock drive from PLL3
HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
Contains 100k pull-down resistor.
12
16
22
24
39
51
56
VSS_PCI
VSS_48M
VSS_LCD
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF
57
Thermal Pad
<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.
LCD_CLK
LCD_CLK#
20
21
SATA
SATA#
26
25
PM_STPPCI#_R
PM_STPCPU#_R
DREFCLK_R
DREFCLK#_R
R251
R229
R299
R300
*0/J_4
*0/J_4
*0/J_4
*0/J_4
[22]
[22]
[25]
[25]
[5]
[5]
To Mini Card 2 (3G/Wimax) 100 MHz <20101109> Place R235/ R241/ R248/ R254 close to U13
100 MHz
CLK_PCIE_ICH [10]
CLK_PCIE_ICH# [10]
To SB (DMI CLK)
100 MHz
DREFCLK [5]
DREFCLK# [5]
To CPU (PLL CLK)
96 MHz
DREFSSCLK [5]
DREFSSCLK# [5]
To CPU (DPLSS CLK)
100 MHz registers and logics of the display interface and therefore
CLK_PCIE_SATA [11]
CLK_PCIE_SATA# [11]
To SB (SATA CLK)
100 MHz
<20110110> DPL_REFSSCCLK is used to drive internal

needs to be present at all times.
<20100819> Add 475ohm resistors to prevent current leakage

CLKREQ_A#
CLKREQ_B#
CLKREQ_C#
47
46
29
CLKREQ_LAN#_R
CLKREQ_MPC#_R
CLKREQ_MMC#_R
CKPWRGD/PD#
55
HWPG
R204
R199
R284
475/F_4
475/F_4
475/F_4
CLKREQ_LAN# [22]
CLKREQ_MPC# [25]
CLKREQ_MMC# [26]
HWPG
C357
*0.1U/10V_4
SLG8LV631V
[13,16,27]
Control SRC_1 Register B5b6 for CLKREQ_A#

0 = SRC1, 1=SRC2
Control SRC_3 Register B5b4 for CLKREQ_B#
0 = SRC3, 1=SRC4
Control SRC_5 Register B5b3 for CLKREQ_C#
0 = SRC5, 1=SRC6
<20110221> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes
will change to 25MHz after flash BIOS and restart in first time issue.
+3V
+3V
A
+3V
R313
*10K/J_4
R306
10K/J_4
1 = Pin 43/44 as CPU_ITP
R301
10K/J_4
R295
*10K/J_4
ITP_EN
0 = Pin 43/44 as SRC_1
FSC FSB
0
0
0
1
1
1
1
0
+3V
33M_SEL
1 = Pin 11 as 33MHz
0= Pin 11 as 25MHz
<EMI>
Frequency
133MHz
166MHz
200MHz
100MHz <20100720_Sam> Keep 100MHz as default.
R289
10K/J_4
R259
*10K/J_4
FSC
R317
*10K/J_4
R318
10K/J_4
USB_48M
C280
ITP_EN
C259
PM_STPPCI#_R
R250
10K/J_4
PM_STPCPU#_R
R230
10K/J_4
CLKREQ_MPC#_R
R213
10K/J_4
CLKREQ_MMC#_R
R279
10K/J_4
CLKREQ_LAN#_R
R212
10K/J_4
*10P/50V_4
*10P/50V_4
A
+3V
FSB
C279
*10P/50V_4
FSC
C245
*10P/50V_4
FSB
33M_SEL
C266
*10P/50V_4
PROJECT : ZE7
Size
Document Number
Rev
C3C
CLOCK GENERATOR
Date:
5
Sheet

1
of
42
03

PROJECT : ZE7
Size
Rev
C3C
Reserved
Date:
Document Number
Sheet
1
of
42
DDR_STD(DDR)
DIMM0 H=4mm
2.48A
M_A_DQ[63:0]
[8] M_A_A[15:0]
Populate rules: populate

SODIMM1 first
Strictly follow the mapping
between clock/control signal
groups and SODIMMs, as
well as SMB address. Other
configurations/mappings will
not
be supported by MRC
+3V DESIGN
NOTE:
ADDRESS-(A2)H
R150
10K/J_4
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
M_A_BS0
M_A_BS1
M_A_BS2
M_CS#2
M_CS#3
M_CLK2
M_CLK2#
M_CLK3
M_CLK3#
M_CKE2
M_CKE3
M_A_CAS#
M_A_RAS#
M_A_WE#
[2,13,25] SMBCK1
[2,13,25] SMBDT1
R151
*10K/J_4
R170
10K/J_4
[8]
[8]
[8]
M_ODT2
M_ODT3
M_A_DM[7:0]
[8] M_A_DQS[7:0]
[8] M_A_DQS#[7:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
DIMM1_SA0
DIMM1_SA1
SMBCK1
SMBDT1
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
W E#
SA0
SA1
SCL
SDA
116
120
ODT0
ODT1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
PC2100 DDR3 SDRAM SO-DIMM

(204P)
JDIM1A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
+3V
C179
C178
.1U/10V_4
.1U/10V_4
04
+1.5VSUS
[8]
[8] DDR3_DRAMRST#
+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM
JDIM1B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
1
126
VREF_DQ
VREF_CA
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
PC2100 DDR3 SDRAM SO-DIMM

(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
+0.75V_DDR_VTT
VTT1
VTT2
203
204
GND
GND
205
206
DDR3-DIMM0_H=4_STD
<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON
DDR_VREF_CA
+1.5VSUS
R198
R191
1K/F_4
*0/J_4 +SMDDR_VREF
+SMDDR_VREF_DIMM
R205
DDR3-DIMM0_H=4_STD
+SMDDR_VREF
+SMDDR_VREF_DIMM_R
0/J_4
C194
C205
R208
1K/F_4
.1U/10V_4
0.1U/50V_6
<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ
<20100827> Add by DG request
Place these Caps near DIMM0
+1.5VSUS
+0.75V_DDR_VTT
R149
*0/J_4 +SMDDR_VREF
1K/F_4 +SMDDR_VREF_DQ0_R
R148
+SMDDR_VREF_DQ0
R146
C172
C200
C190
C185
0/J_4
C176
+1.5VSUS
C160
10U/6.3V_6 *10U/6.3V_6
*10U/6.3V_6
1U/6.3V_4
C166
R147
1K/F_4
1U/6.3V_4
.1U/10V_4
C171
C169
C193
.1U/10V_4
.1U/10V_4 .1U/10V_4
C163
C168
C198
C199
C197
C196
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
0.1U/50V_6
+ C203
*330U/2V_7343
LAYOUT NOTE: PLACE CAPS

NEAR DIMM-0
+SMDDR_VREF
+0.75V_DDR_VTT
+1.5VSUS
+SMDDR_VREF_DQ0
C191
C162
C173
C164
C165
C161
C192
+SMDDR_VREF_DIMM
C175
C184
1U/6.3V_4
1U/6.3V_4
C189
C170
C167
C216
C214
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4

.1U/10V_4
2.2U/6.3V_6
.1U/10V_4
PROJECT : ZE7
2.2U/6.3V_6
Size
Rev
C3C
DDRIII SO-DIMM-0
Date:
Document Number
Sheet
1
of
42
Cedar View (CPU)
R397
R398
U24C
*1K/J_4
*1K/J_4
05
+3V
CEDARVIEW
REV = 1.10
Level Shifter For HDMI
DDI0_AUXP
DDI0_AUXN
T33
T31
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
TX2_HDMI+
TX2_HDMITX1_HDMI+
TX1_HDMITX0_HDMI+
TX0_HDMITX3_HDMI+
TX3_HDMI-
TX2_HDMI+
TX2_HDMITX1_HDMI+
TX1_HDMITX0_HDMI+
TX0_HDMITX3_HDMI+
TX3_HDMI-
C66
C67
C61
C68
C43
C44
C41
C42
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
T3
T9
eDP: 7", 3 via, 2.7Gbps
R68
R62
+3V
*2.2K/J_4
*eDP@2.2K/J_4
[18] DDI1_AUX_DP
[18] DDI1_AUX_DN
+1.5V
R32
0/J_6
C55
DDI1_TX0_DP
DDI1_TX0_DN
DDI1_TX1_DP
DDI1_TX1_DN
DDI1_TX2_DP
DDI1_TX2_DN
DDI1_TX3_DP
DDI1_TX3_DN
T11
T7
1U/6.3V_4
R45
DDI0_TXP0
DDI0_TXN0
DDI0_TXP1
DDI0_TXN1
DDI0_TXP2
DDI0_TXN2
DDI0_TXP3
DDI0_TXN3
H15
J15
DDI1_DDC_SCL
DDI1_DDC_SDA
F25
G27
DDI1_AUX_DP
DDI1_AUX_DN
D10
C10
D26
DDI1_TX0_DP
DDI1_TX0_DN
DDI1_TX1_DP
DDI1_TX1_DN
DDI1_TX2_DP
DDI1_TX2_DN
DDI1_TX3_DP
DDI1_TX3_DN
E11
F11
J11
H11
F13
E13
J13
K13
H_RSVD_TP_H17
H_RSVD_TP_J17
J17
H17
BREF1.8V
EXT_BANDGAP
E15
F15
H21
F22
[13] ACZ_BITCLK_CPU
[13] ACZ_SYNC_CPU
[13] ACZ_SDINO
[13] ACZ_SDOUT_CPU
DDI0_HPD
G2
G3
F3
F2
D4
C3
B7
A7
R42
33/J_4 ACZ_SDINO_R
E22
F21
E21
[13] ACZ_RST#_CPU
D14
C14
CRT_RED
CRT_GREEN
CRT_BLUE
B12
B11
C11
CRT_IRTN
CRT_IREF
D12
A13
CRT_DDC_DATA
CRT_DDC_CLK
E29
E27
DPL_REFSSCCLKP
DPL_REFSSCCLKN
F17
E17
CRT_HSYNC
CRT_VSYNC
CRT_IREF R408
681/F_6
CRT_DDC_SDA
CRT_DDC_SCL
R414
150/F_4
DREFSSCLK [2]
DREFSSCLK# [2]
DREFCLK_R1
DREFCLK#_R1
R406
R405
*0/J_4
*0/J_4
DREFCLK [2]
DREFCLK# [2]
DDI1_HPD
DDI1_TXP0
DDI1_TXN0
DDI1_TXP1
DDI1_TXN1
DDI1_TXP2
DDI1_TXN2
DDI1_TXP3
DDI1_TXN3
RSVD_TP_J17
RSVD_TP_H17
BREF18V
BREFREXT
LVDS_CLKP
LVDS_CLKN
AZIL_BCLK
AZIL_SYNC
H2
H3
LVDS_VREFH
LVDS_VREFL
LVDS_TXP0
LVDS_TXN0
LVDS_TXP1
LVDS_TXN1
LVDS_TXP2
LVDS_TXN2
LVDS_TXP3
LVDS_TXN3
AZIL_RST#
2.37K/F_4
<20100818_Jerry> If you implement XDP, you need the PU 2.2K
+3V
R426
R428
<20110610> Remove PU resistor for Intel update.

<20110630> Stuff R38/ R39 PU resistor. Intel will fixed EDID issue by VGA driver and vbios
R61
*0/short_6
*0/short_6
+3V
G10
H10
F8
E8
H7
H8
G5
G6
TXLOUT0+
TXLOUT0TXLOUT1+
TXLOUT1TXLOUT2+
TXLOUT2-
H4
J4
TXLCLKOUT+ [18]
TXLCLKOUT- [18]
R39
2.2K/J_4
LCD_CLK
R38
2.2K/J_4
LCD_DATA
[18]
[18]
[18]
[18]
[18]
[18]
G22
E25 LBKLT_EN
F29 INT_LVDS_DIGON_Q
PANEL_BKLTCTL
PANEL_BKLTEN
PANEL_VDDEN
AZIL_SDI
AZIL_SDO
*2.2K/J_4
*2.2K/J_4
LCD_CLK [18]
LCD_DATA [18]
E10 LIBG
F10
LVDS_IBG
LVDS_VBG
<20110110> DPL_REFSSCCLK is used to drive internal

registers and logics of the display interface and therefore
needs to be present at all times.
T51
T52
G24
H24
LVDS_DDC_CLK
LVDS_DDC_DATA
DDI1_AUXP
DDI1_AUXN
[18]
[18]
[18]
LAYOUT NOTE: PLACE THESE 3 RESISTORS

CLOSE TO PIN
R415
150/F_4
F28
E24
LVDS_CTRL_CLK
LVDS_CTRL_DATA
DDI1_DDC_SCL
DDI1_DDC_SDA
R413
150/F_4
[18]
[18]
R52
R48
RSVD_TP_H15
RSVD_TP_J15
[18]
[18]
CRT_R
CRT_G
CRT_B
B9
A9
DPL_REFCLKP
DPL_REFCLKN
IHDA
<20101125_Colt> Please follow PDG, we will

doing BOM stuff changing in next version CRB
7.5K/F_4
H22
H_RSVD_TP_H15
H_RSVD_TP_J15
DDI1_HPD#
[18] DDI1_HPD#
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
DDI0_TX2_DP
DDI0_TX2_DN
DDI0_TX1_DP
DDI0_TX1_DN
DDI0_TX0_DP
DDI0_TX0_DN
DDI0_TX3_DP
DDI0_TX3_DN
DDI0_AUXP
DDI0_AUXN
CRT_HSYNC
CRT_VSYNC
DDI
HDMI_DDI0_HPD#
[17] HDMI_DDI0_HPD#
D
C8
B8
DDI0_DDC_SCL
DDI0_DDC_SDA
VGA
H25
J22
[17] DDI0_HDMI_SCL
[17] DDI0_HDMI_SDA
LVDS
HDMI: 7.5", 4 via, 1.65 Gbps
<EMI>
C50
*220P/50V_4
+3V
INT_LVDS_PWM [18]
C51
*220P/50V_4
R58
2.2K/J_4
CRT_DDC_SDA
R56
2.2K/J_4
CRT_DDC_SCL
R65
*10K/J_4
<EMI>
3 OF 6
C58
C65
*220P/50V_4
*220P/50V_4
CDV_22MM_REV1P10
LCD Panel Power (LDS)
U24A
CEDARVIEW
REV = 1.10
+3V
C329
U20
ECPWROK
TC7SH08FU
4
INT_LVDS_DIGON_Q
.1U/10V_4
INT_LVDS_DIGON
[18]
L3
L2
M3
M2
N2
N1
P2
P3
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
N9
N8
T2
[2] CLK_PCIE_DMIP
[2] CLK_PCIE_DMIN
DMI_REF1.5V
R360
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
DMI
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
DMI_REFCLKP
DMI_REFCLKN
DMI_REF1P5
RSVD_TP_R8
RSVD_TP_R7
DMI_RCOMP
K6
K5
L5
L6
L9
L8
N5
N6
R8
R7
T1
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
DMI_REF1.5V_R
R445
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
7.5K/F_4
100K_4
R450
+1.5V
R355
DMI_REF1.5V
<20101109> Add DMI_REF1.5V to follow CRB v0.7
*0/short_4
1 OF 6
*0/J_4
C354
1U/10V_4
CDV_22MM_REV1P10
B
<20101109> Add C354 to follow CRB v0.7
For HDMI deep color mode support

(HDM)
LCD Panel Backlight (LDS)

+3V
ECPWROK
ECPWROK
LBKLT_EN
<20100727_Sam> Customer must to use 27MHz due to

accuracy concerns(<1000ppm) from Intel silicon
perspective.
.1U/10V_4
TC7SH08FU
4
<20110414> Pull up at EC side

+3V
LAYOUT NOTE: PLACE CLOSE TO PIN

INT_LVDS_BLON
[18]
DREFCLK_R1
DREFCLK#_R1
[8,13,16,27]
<20110414> Unstuff Thermal Sensor and related circuit.
C48
U2
THERMAL SENSOR (THM)
R53
THERMAL_SCL
R115
*2K/F_4
R51
R410
0/J_4
*0/J_4
[6,13,27]
SCL
33P/50V_4
1M/J_4
C335
33P/50V_4
ALERT# Pull Up Value
Alert temperature point
2K
ohm
75 degree
7.5K ohm
90 degree
10.5K ohm
100 degree
14K ohm
105 degree
18.7K ohm
110 degree
THERMAL_SDA R119
*0/J_4
ALERT#
2ND_MBCLK
[27]
2ND_MBDATA [27]
+3V
GND
*0/J_4 THERM_ALERT#_1 3
2nd source: BG627000289 (ZYG)
Y3
R385
R111
SDA
VDD
C148
*0.1U/16V_4
*NCT7717U
27MHz/+-20PPM_20PF
C334
THERM_ALERT#
*0/J_4
U5
1
2
R409
0/J_4
100K_4
*
*
R114
C155
*0.1U/16V_4
C154
*0.1U/16V_4
C156
*4.7U/6.3V_6
PROJECT : ZE7
Size
Document Number
Date:
Rev
C3C
Cedarview DMI/Display
5
Sheet
1
of
42
Cedar View (CPU)
06
U24D
CEDARVIEW
REV = 1.10
2.2K/J_4
2.2K/J_4
<20100811_Jerry>can be NC but please reserve 2.2K pull

low as CRB. can be removed later depends on CRB
validation status.
<20101019>Stuff R74 R71 for using 0xFFFE_0000
as Punit microbase address
HV_GPIO_RCOMP
MV_GPIO_RCOMP
SMI#
NMI/LINT1
RSVD_C18
STPCLK#
B18
C22
C18
D22
DPRSTP#
DPLSLP#
CPUSLP#
C21
B21
B22
INIT#
INTR/LINT0
A23
D20
THERMTRIP#
RSVD_L11
B20
L11
H_THRMTRIP#
PBE#
C20
H_FERR#_R
PROCHOT#
PWRGOOD
RESET#
DBR#
A19
D23
G30
E30
H_PROCHOT_R#
H_PW RGD
PLTRST#
PRDY#
PREQ#
H29
G29
H_BPM4_PRDY#
H_BPM5_PREQ#
HPLL_REFCLK_P
HPLL_REFCLK
J19
K19
CLK_MCH_BCLK
CLK_MCH_BCLK#
RSVD_E19
RSVD_F19
E19
F19
HV_GPIO_RCOMP
MV_GPIO_RCOMP
R386
H_SMI# [11]
H_NMI [11]
H_A20M# [11]
H_STPCLK# [11]
*0/short_4
ICH_DPRSTP# [13]
H_DPSLP# [13]
CPUSLP# [11]
H_INIT# [11]
H_INTR [11]
+1.05V
R400
*0/short_4
H_FERR#
XDP_TCLK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
R5
R6
W25
W26
N24
N25
+1.05V
XDP_TDI
XDP_TDO
XDP_TMS
R449
R459
R470
51/J_4
51/J_4
51/J_4
XDP_TCLK R446
XDP_TRST# R448
51/J_4
51/J_4
C25
C24
B25
D24
B24
TCLK
TDI
TDO
TMS
TRST#
SVID_ALERT#
SVID_CLK
SVID_DATA
RSVD_R5
RSVD_R6
RSVD_W25
RSVD_W26
RSVD_N24
RSVD_N25
RSVD_K21
RSVD_L22
RSVD_L24
CDV_22MM_REV1P10
[11]
R377
XDP_DBRESET_N_CDV
R33
H_PW RGD [13,16]

PLTRST# [13,16,22,25,26,27]
1K/J_4
+3V
*0/short_4
H_PROCHOT#
[31]
<20110520>Need confirm with Intel
+1.8V
H_BPM4_PRDY#
T43
T44
R442
H_BPM5_PREQ#
CLK_MCH_BCLK [2]
CLK_MCH_BCLK# [2]
*51/J_4
R443
51/J_4
C268
Host CLK 100/133 MHz
.1U/10V_4
+1.05V
R399
75/J_4
T45
T46
T47
T48
T49
<20100811_Jerry>please use 100+/-5% as in PDG.
R381
100/J_4
R69
49.9/F_4
CPU
R72
49.9/F_4
K24
K23
RSVD_L26
RSVD_L27
RSVD_K28
RSVD_K25
RSVD_J28
RSVD_K26
RSVD_K27
RSVD_H27
RSVD_K30
RSVD_L29
RSVD_L30
RSVD_K29
RSVD_J31
RSVD_H30
ICH
R74
R71
L26
L27
K28
K25
J28
K26
K27
H27
K30
L29
L30
K29
J31
H30
B16
D18
C16
R416
110/F_4
VR_SVID_ALERT# [31]
VR_SVID_CLK [31]
VR_SVID_DATA
[31]
K21
L22
L24
4 OF 6
125 Degree Protection(CPU)
CPU FAN CTRL(THM)
+1.05V
3
IMVP_PW RGD
[27,31] IMVP_PW RGD
+5V
+3V
+5V
+3V
Q2
2N7002K
R509
R507
R512
10K/J_4
10K/J_4
10K/J_4
R505
R514
THERM_ALERT#
R17
1K/J_4
[27]
From CPU
Shutdown System Power Immediately
Q1
1
3
METR3904-G
H_THRMTRIP#
SYS_SHDN#
CPUFAN#
CPUFAN#
*0/short_6
C365
*0/J_4
1
Q43
0.1U/16V_4
CN18
FANSIG
[5,13,27]
[27]
+5V_FANVCC
FANSIG
FAN_PW M_CN
3
METR3904-G
EC PWM SIGNAL
4 6
3 5
2
1
FAN CONN
[30,35]
To System Power
For EMI
R16
*0/short_4
PM_THRMTRIP# [11]
FAN_PW M_CN
FANSIG
To Tiger Point
C368
*220P/50V_6
C372
*220P/50V_6
PROJECT : ZE7
Size
Rev
C3C
Cedarview Miscellaneous
Date:
Document Number
W ednesday, August 31, 2011
Sheet
1
of
42
Cedar View (CPU)

LAYOUT NOTE: place close to VCCADDR pin
CEDARVIEW
REV = 1.10
C92
*1U/10V_4
C116
1U/10V_4
V_1.05_CORE_EAST
V_1.05_CORE_RSENSE
V_1.05_VCCDDR
C129
*1U/10V_4
C130
1U/10V_4
V_1.05_VCCDDR
C128
1U/10V_4
VCCCKDDR_VSM
[8] VCCDDRAON_1.5
R134
C149
For Deep Standby
2.2U/6.3V_6
C153
C146
2.2U/6.3V_6
C152
2.2U/6.3V_6
2.2U/6.3V_6
R419
*0/short_6
+1.05V
VCCADP_1.05
C56
R77
+1.05V
C82
1U/10V_4
R55
+3.3V_PRIME
*0/short_6
C59
R384
+1.8V
B5
C6
D6
K17
L18
C336
47U/6.3V_8
47U/6.3V_8
C91
R47
*0/short_6
C54
V_1.05_CORE_RSENSE
R94
VCCAGPIO_3.3
D30
D31
VCCADAC_1.8
B13
2.2U/6.3V_4
0.2A/600ohm_6
<20100830> Add Farrite bead for VCCDAC low pass filterC337
+3.3V_PRIME
AJ6
AK6
V_1.05_CORE_EAST L19
VCCAGPIO_1.5
L16
VCCAGPIO_1.8
N18
*0.1U/10V_4
*0/short_6
*0/short_6
C93
1U/10V_4
*0/J_6 VCCADP0_1.5
VCCADP1_1.5
R54
R31
R46
W11
W13
*0/short_6
C83
1U/10V_4
+1.5V
+1.8V
W8
W9
AH14
AH19
AK23
AK5
AL11
AL16
AL21
AG31
VCCDDRAON_1.5
*NS3@0/short_8
N30
N31
V4
VCCALVDS_1.8
VCCDLVDS_1.8
1U/10V_4
H5
J1
V_1.05_CORE_EAST L21
VCCAZILAON_3.3
B29
A30
VCCSFRMPL_1.5
VCCDMPL_1.05
AA18
AA11
2.2U/6.3V_4
*0/short_6
C139
*2.2U/6.3V_4
<20101125_Colt> Please follow PDG, we will doing BOM

stuff changing in next version CRB
VCCPLLCPU0_1.05
VCCPLLCPU1_1.05
B27
C29
B30
VCCAHPLL_1.05
B26
VCCRAMXXX_1
VCCRAMXXX_2
VCCRAMXXX_3
VCCACKDDR_1
VCCACKDDR_2
VCCADLLDDR_1
VCCADLLDDR_2
CPU
<20101126_Colt> Please follow PDG to

placehold the 0805 capacitor
VCCCKDDR_1
VCCCKDDR_2
V_SM_1
V_SM_2
V_SM_3
V_SM_4
V_SM_5
V_SM_6
V_SM_7
V_SM_8
VCCADP_1
VCCADP_2
VCCADP_3
VCC_CPU_01
VCC_CPU_02
VCC_CPU_03
VCC_CPU_04
VCC_CPU_05
VCC_CPU_06
VCC_CPU_07
VCC_CPU_08
VCC_CPU_09
VCC_CPU_10
VCC_CPU_11
VCC_CPU_12
VCC_CPU_13
VCC_CPU_14
VCC_CPU_15
VCC_CPU_16
VCC_CPU_17
VCC_CPU_18
VCC_CPU_19
VCC_CPU_20
VCC_CPU_21
VCC_CPU_22
VCC_CPU_23
VCC_CPU_24
VCC_CPU_25
VCC_CPU_26
VCC_CPU_27
VCC_CPU_28
VCC_CPU_29
P18
P19
P21
P28
P29
P30
R22
R23
R24
R25
R26
R27
T19
T21
T29
T30
T31
U22
U23
U24
U25
U26
U27
V18
V19
V21
V28
V29
V30
VCCSFRMPL_1.5
1U/10V_4
*1U/10V_4
VCC_GFX_01
VCC_GFX_02
VCC_GFX_03
VCC_GFX_04
VCC_GFX_05
VCC_GFX_06
VCC_GFX_07
VCC_GFX_08
VCC_GFX_09
VCC_GFX_10
VCC_GFX_11
VCCAGPIO_LV
VCCAGPIO_REF
VCCAGPIO_DIO
VCCAGPIO_1
VCCAGPIO_2
VCCADAC
VCCALVDS
VCCDLVDS
VCCDIO
VCCAZILAON_1
VCCAZILAON_2
VCCSFRMPL
VCCDMPL
VCCADMI_1
VCCADMI_2
VCCADMI_3
VCCADMI_PLLSFR
VCCFHV_1
VCCFHV_2
VCCFHV_3
VCC_CPUSENSE
VSS_CPUSENSE
VCCPLLCPU0
VCCPLLCPU1_1
VCCPLLCPU1_2
*1.5VPLL@0/short_6
VCC_GFXSENSE
VSS_GFXSENSE
VCCAHPLL
VCCTHRM_1
VCCTHRM_2
N11
N13
P11
P13
R10
R9
T11
T13
U10
V11
V13
22U/6.3V_8
+1.5V
L18
*1.05VPLL@10uH/100mA_8
22U/6.3V_8
C126 C100 C105 C118 C101 C125 C106 C103 C112
1U/10V_4
*1U/10V_4
*1U/10V_4
22U/6.3V_8
C134
1U/10V_4
+1.05V
C142
*10U/6.3V_8
22U/6.3V_8
R29
VCCADP0_1.5
LAYOUT NOTE: PLACE

ONE 1U CAP ON BOT LAYER
*1.5VPLL@0/short_6
+1.5V
L3
*1.05VPLL@10uH/100mA_8
C52
1U/10V_4
+1.05V
C28
*10U/6.3V_8
R36
VCCADP1_1.5
*1.5VPLL@0/short_6
+1.5V
L4
*1.05VPLL@10uH/100mA_8
C53
1U/10V_4
1.05V (0.76V~1.05V)
1.98A
LAYOUT NOTE:
+1.05V
C29
*10U/6.3V_8
PLACE
TWO CAPS ON BOT LAYER
VCCGFX
VCCADP0_SFR
VCCADP1_SFR
DMI
R112
+VCC_CORE
VCCADDR_1
VCCADDR_2
VCCADDR_3
VCCADDR_4
DDR
AA14
AA16
W16
W18
POWER
C141
*1U/10V_4
PLL
C120
1U/10V_4
07
Default stuff 1.5VPLL, Intel verify whether

1.05VPLL is ok or not
1.1V (0.75V~1.18V)
5.95A
U24E
V_1.05_CORE_RSENSE
C352
*22U/6.3V_8
+1.5VSUS
Cedar View PLL Power
Cedar View LVDS Power
C95
C98
C117
C94
C115
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
22U/6.3V_8
BOM structure
C60
1U/10V_4
C88
1U/10V_4
B4
C5
A4
K4
VCCADMI_1.05
V16
T16
V_1.05_CORE_RSENSE
w/LVDS: stuff R436/ C345/ L38/ C75

w/EDP: unstuff R436/ C75
change L38/ C345 to 0ohm
VCCADMI_1.5
R423
*0/short_6
+1.05V
R456
*0/short_6
+1.5V
+1.8V
VCCDLVDS_1.8
VCCALVDS_1.8
V14
M28
M30
CPUVCC_SENSE [31]
CPUVSS_SENSE [31]
U8
U7
GTVCC_SENSE [31]
GTVSS_SENSE [31]
N16 V_1.8_RSENSE
K2
R437
BOM@0.1uH/300mA_6
C75
LVDS@4.7u/6.3V_6
*0/short_6
L38
R436
LVDS@0/J_6
C345
BOM@1U/10V_4
+1.8V
C350
*1U/10V_4
VCCPLLCPU0_1.05 R40
*0/J_6 VCCPLLCPU1_1.05
LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR

+1.5VSUS
2nd source: CV01001MN32
VCCCKDDR_VSM
R489
*NS3@0/short_8
C359
+1.05V
VCCPLLCPU0_1.05
C31
4.7u/6.3V_6
5 OF 6
10uH/100mA_8
+1.05V

C362
10U/6.3V_8
<2010/9/27>Reserve 0805 footprint for farrite bead

CV01001MN16 due to co-layout issue.
C40
1U/10V_4
CDV_22MM_REV1P10
VCCPLLCPU1_1.05
1U/6.3V_4
L6
10uH/100mA_8

L11
V_1.05_VCCDDR
C45
4.7u/6.3V_6
C46
1U/10V_4
R89
*0/short_6
+1.05V
D
V_1.05_CORE_RSENSE
R440
*0/short_6
+1.05V
VCCAHPLL_1.05
C32
4.7u/6.3V_6
10uH/100mA_8
L10
C49
1U/10V_4
PROJECT : ZE7
Size
Document Number
Rev
C3C
CedarView Power
Date:
1
Sheet
8
of
42
Cedar View (CPU)
<Layout note>
PLACE RESISTORS AND CAP CLOSE TO CPU DDR_VREF PIN
+SMDDR_VREF
1K/F_4
R492
*0/J_4
R483
*0/short_4
R493
1K/F_4
C360
0.1U/16V_4
<20100810_Jerry> Please refer to Cedar Trail CPET HW section(#454349),

it is to implement Deep Standby. And please waiting the whitepaper for implementation detail.
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
[4]
[4]
[4]
M_A_WE#
M_A_CAS#
M_A_RAS#
[4]
[4]
[4]
M_A_BS0
M_A_BS1
M_A_BS2
[4]
[4]
M_CS#2
M_CS#3
[4]
[4]
M_CKE2
M_CKE3
[4]
[4]
M_ODT2
M_ODT3
[4]
[4]
[4]
[4]
AK14
AK16
AJ14
AJ16
AK18
AH18
AJ18
AK20
AJ20
AH20
AJ12
AK21
AJ21
AJ8
AH22
AJ22
DDR3_MA0
DDR3_MA1
DDR3_MA2
DDR3_MA3
DDR3_MA4
DDR3_MA5
DDR3_MA6
DDR3_MA7
DDR3_MA8
DDR3_MA9
DDR3_MA10
DDR3_MA11
DDR3_MA12
DDR3_MA13
DDR3_MA14
DDR3_MA15
M_A_WE#
M_A_CAS#
M_A_RAS#
AH10
AJ10
AJ11
DDR3_W E#
DDR3_CAS#
DDR3_RAS#
M_A_BS0
M_A_BS1
M_A_BS2
AK12
AH13
AK22
DDR3_BS0
DDR3_BS1
DDR3_BS2
M_CS#2
M_CS#3
AH12
AH8
AK11
AK8
DDR3_CS#0
DDR3_CS#1
DDR3_CS#2
DDR3_CS#3
M_CKE2
M_CKE3
AH23
AJ24
AK24
AH24
DDR3_CKE0
DDR3_CKE1
DDR3_CKE2
DDR3_CKE3
M_ODT2
M_ODT3
AK10
AK7
AL9
AJ7
DDR3_ODT0
DDR3_ODT1
DDR3_ODT2
DDR3_ODT3
M_CLK2
M_CLK2#
M_CLK3
M_CLK3#
AG15
AF15
AF17
AG17
AD17
AC17
AC15
AD15
DDR3_CK0
DDR3_CK#0
DDR3_CK1
DDR3_CK#1
DDR3_CK2
DDR3_CK#2
DDR3_CK3
DDR3_CK#3
DDR3_DRAMRST#_R
AK25
DDR3_DRAMRST#
DDR_VREF
AJ27
AL28
DDR3_VREF
DDR3_VREF_NCTF
AC19
AB19
DDR3_REFP
DDR3_REFN
M_CLK2
M_CLK2#
M_CLK3
M_CLK3#
*
[2] CLK_DDR3_REFCLK
[2] CLK_DDR3_REFCLK#
<20100817_Jerry>DELAY_VR_PWRGOOD on CDV should be connected to the XDP_PWRGOOD

because the SV folks expressed a preference on using PWROK over PWRGOOD for CDV.
This has changed from PNV to CDV.
DDRAM_PWROK
DELAY_VR_PWRGD_CDV
T53
[5,13,16,27]
R99
ECPWROK
M_ODTPU
M_CMDPU
M_DQPU
121/F_4
R98
100/F_4
<20110520>Change 12.1K to 121ohm to follow CRBv1.5

B
R485
<20110520>Change 10K to 100ohm to follow CRBv1.5
274/F_4
R488
C361
22.6/F_4
M_A_DQ[63:0]
CEDARVIEW
R482
08
U24B
[4] M_A_A[15:0]
[7] VCCDDRAON_1.5
R484
*0.01U/25V_4
33.2/F_4
AA5
W7
REV = 1.10
DDR3_DRAM_PW ROK 1.5V

DDR3_VCCA_PW ROK 1.5V
AJ26
AJ25
AK27
DDR3_ODTPU
DDR3_CMDPU
DDR3_DQPU
AB11
AB13
AF19
AG19
RSVD_TP_AB11
RSVD_TP_AB13
RSVD_TP_AF19
RSVD_TP_AG19
DDR3
<20100811_Jerry> R485 please follow CRB schematic. (274ohm)
[4] M_A_DM[7:0]
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
Y28
AB26
AE30
AB21
AG11
AG2
AB8
AA3
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_DQ32
DDR3_DQ33
DDR3_DQ34
DDR3_DQ35
DDR3_DQ36
DDR3_DQ37
DDR3_DQ38
DDR3_DQ39
DDR3_DQ40
DDR3_DQ41
DDR3_DQ42
DDR3_DQ43
DDR3_DQ44
DDR3_DQ45
DDR3_DQ46
DDR3_DQ47
DDR3_DQ48
DDR3_DQ49
DDR3_DQ50
DDR3_DQ51
DDR3_DQ52
DDR3_DQ53
DDR3_DQ54
DDR3_DQ55
DDR3_DQ56
DDR3_DQ57
DDR3_DQ58
DDR3_DQ59
DDR3_DQ60
DDR3_DQ61
DDR3_DQ62
DDR3_DQ63
Y30
Y29
AC30
AC31
W 31
W 28
AB28
AB30
AA24
AA22
AE27
AE26
AB27
AA25
AD25
AD27
AD29
AE29
AJ30
AK29
AD28
AD30
AG30
AJ29
AE24
AG24
AD22
AC21
AG27
AG25
AG21
AE21
AD13
AD11
AG8
AG7
AG13
AE13
AD10
AF8
AH2
AG3
AD2
AD3
AH4
AK3
AE2
AD4
AD7
AD6
AA6
AB5
AE8
AE5
AB9
AA8
AB2
AB4
W4
V3
AC2
AB3
Y2
W1
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR3_DQS0
DDR3_DQS1
DDR3_DQS2
DDR3_DQS3
DDR3_DQS4
DDR3_DQS5
DDR3_DQS6
DDR3_DQS7
AA30
AB24
AF30
AE22
AG10
AF4
AB6
Y3
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DDR3_DQS#0
DDR3_DQS#1
DDR3_DQS#2
DDR3_DQS#3
DDR3_DQS#4
DDR3_DQS#5
DDR3_DQS#6
DDR3_DQS#7
AA31
AB25
AF29
AF22
AF10
AF3
AB7
AA2
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
[4]
M_A_DQS[7:0]
[4]
M_A_DQS#[7:0]
[4]
CDV_22MM_REV1P10
DRAM Reset (CPU)
2 OF 6
<20110727>Connect DDRAM_PWROK between CDV and RT8207L to meet JEDEC timing spec
+1.5VSUS
<20110520>Need to confirm with Intel if
we need to add series 100ohm resistor
R537
[4] DDR3_DRAMRST#
C159
0.1U/16V_4
+1.5VSUS
<20110607>Keep original design first for DRAMRST#

R538
*1K/F_4
*0/short_4
<20110707_Nick> Please un-stuff 1K pull up
DDR3_DRAMRST#_NS
R539
*0/short_4
<20110607>Keep original design first for DRAMRST#
VCCDDRAON_1.5
R100
10K/J_4
DDR3_DRAMRST#_R
R474
[27,32] DDRAM_PWROK
<20110707_Nick> Please stuff 100K pull down
DDRAM_PWROK
R97
*0/J_4
100K/J_4
<20110727> Add C159 to suppress glitch
C388
*1U/10V_6
PROJECT : ZE7
<20110727> Reserve C388 for RC delay
Size
Rev
C3C
CedarView DDR
Date:
Document Number
Sheet
1
of
42
09
Cedar View (CPU)
U24F
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CEDARVIEW
REV = 1.10
GND
A11
A16
A21
A25
AA1
AA10
AA13
AA19
AA21
AA23
AA26
AA27
AA29
AA7
AA9
AB15
AB17
AB23
AB29
AC1
AC10
AC11
AC13
AC22
AC28
AC4
AD19
AD21
AD24
AD26
AD5
AD8
AE1
AE10
AE11
AE15
AE17
AE19
AE3
AE31
AF11
AF13
AF21
AF24
AF28
AF7
AG22
AG5
AH26
AH28
AH6
AH9
AJ2
AJ3
AK13
AK19
AK28
AK9
AL13
AL19
AL23
AL25
AL7
B10
B14
B19
B23
C12
C26
C30
C7
D19
D28
D8
D9
E2
E5
E7
F24
F4
G1
G11
G13
G15
G17
G19
G21
G31
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_CDVDET
VSSA_CRTDAC
H19
H26
H28
H6
J10
J2
J21
J30
K11
K15
K3
K7
K8
K9
L1
L10
L13
L23
L25
L31
L7
M29
M4
N10
N14
N19
N21
N22
N23
N26
N27
N28
N4
N7
P14
P16
P4
T14
T18
T3
U5
U6
U9
V2
W10
W14
W19
W2
W21
W22
W23
W24
W27
W30
W5
W6
Y4
A27
A29
A3
AH1
AJ1
AJ31
AK1
AK2
AK30
AK31
AL2
AL29
AL3
AL30
AL5
B2
B3
B31
C1
C2
C31
E1
L14
D13
6 OF 6
CDV_22MM_REV1P10
PROJECT : ZE7
Size
Document Number
Rev
C3C
CedarView GND/ Deep Standby

Date:
1
Sheet
of
42
10
Tiger Point (CLG)

TGP
U22B
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
C96
C90
.1U/10V_4
.1U/10V_4
DMI_TXN0_C
DMI_TXP0_C
C113
C104
R81
R80
C110
C122
R88
R86
C124
C132
.1U/10V_4
.1U/10V_4
*0/J_4
*0/J_4
*.1U/10V_4
*.1U/10V_4
*0/J_4
*0/J_4
*.1U/10V_4
*.1U/10V_4
DMI_TXN1_C
DMI_TXP1_C
DMI_RXN2_R
DMI_RXP2_R
DMI_TXN2_C
DMI_TXP2_C
DMI_RXN3_R
DMI_RXP3_R
DMI_TXN3_C
DMI_TXP3_C
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23
LAN
WLAN
Media Processor
PCIE_RXN0
PCIE_RXP0
PCIE_TXN0
PCIE_TXP0
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
C63
C71
C343
C344
C87
C80
C347
C346
K21
K22
PCIE_TXN0_CJ23
PCIE_TXP0_CJ24
M18
M19
.1U/10V_4 PCIE_TXN1_C K24
.1U/10V_4 PCIE_TXP1_C K25
L23
L24
.1U/10V_4 PCIE_TXN2_C L22
.1U/10V_4 PCIE_TXP2_C M21
P17
P18
*.1U/10V_4 PCIE_TXN3_C N25
*.1U/10V_4 PCIE_TXP3_C N24
.1U/10V_4
.1U/10V_4
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
D4
C5
D3
D2
E5
E6
C2
C3
USBRBIAS
USBRBIAS#
G2
G3
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBOC#R_1
USBOC#R_1
USBOC#
USBOC#L_1
USBOC#
USBOC#
USBOC#
USBOC#
CLK48
USBRBIAS
SYSTEM (Right Down)

SYSTEM (Right Up)
CCD
SYSTEM (Left/ USB Charger)
SIM
3G
BT
WLAN
R435
*0/short_4
USBOC#R [21,27] USBOC#R_1 R433

USBOC#L_1 R429
USBOC#
R432
R427
*0/short_4
USBOC#L [21,27]
R438
+3V_S5
8.2K/J_4
8.2K/J_4
1K/F_4
CRB ties unused OC pins together with 1k ohm
22.6/F_4
F4 CLKUSB_48
CLKUSB_48 [2]
EMI
<20110630> No support PCI-E in 3G card

R66
*10/F_4
<Layout note>
Close to pin within 500mil
+1.5V
[21]
[21]
[21]
[21]
[18]
[18]
[21]
[21]
[25]
[25]
[25]
[25]
[19]
[19]
[25]
[25]
<Layout note>
Close to pin within 200mil ; keep away from CLK/High speed signals
PCI-E
Card Reader
[22]
[22]
[22]
[22]
[25]
[25]
[25]
[25]
[26]
[26]
[26]
[26]
[25]
[25]
[25]
[25]
USB
<20110222> ES2 CPU DMI will change

from x4 to x2
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
R425
24.9/F_4 DMI_COMP H24

J22
[2] CLK_PCIE_ICH#
[2] CLK_PCIE_ICH
W23
W24
DMI_ZCOMP
DMI_IRCOMP
C81
*10P/50V_4
DMI_CLKN
DMI_CLKP
2
Tiger Point

PROJECT : ZE7
Size
Document Number
Rev
C3C
Tiger Point DMI/PCIE/USB

Date:
1
Sheet
10
of
42
11
Tiger Point (CLG)

<Layout note>
NOTE
1. CPUSLP# is supported only on nettop platforms.
Follow CRB
PCH_GPIO36
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
AC17
AB13
AC13
AB15
Y14
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
AB16
AE24
AE23
RSVD24
RSVD25
RSVD26
AA14
V14
RSVD27
RSVD28
AD16
AB11
AB10
AD23
RSVD29
RSVD30
RSVD31
GPIO36
SATA
R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12
[12,13,14] VCC3_VCC3
TGP
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9
SATA_RXN0 [24]
SATA_RXP0 [24]
SATA_TXN0 [24]
SATA_TXP0 [24]
AD4
AC4
SATARBIAS#
SATARBIAS
SATALED#
AD11
AC11
AD25
R466
SATALED#
R102
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#
<Layout note>
SATARBIAS#
U16 GA20
Y20 H_A20M#
Y21 CPUSLP#_R
Y18 H_IGNNE#
AD21
AC25 H_INIT#
AB24 H_INTR
Y22 H_FERR#
T17 H_NMI
AC21 KBRST#
AA16 SERIRQ
AA21 H_SMI#
V18 H_STPCLK#
AA20 PM_THRMTRIP#
4.7K/J_4
10K/J_4
GA20
PCH_GPIO36
R95
R103
8.2K/J_4
*10K/J_4
+3V
<20100811_Jerry>CDV doesn't support A20M,

please follow CRB to have a 1K pull up at the moment.
CLK_PCIE_SATA# [2]
CLK_PCIE_SATA [2]
R96
R117
<20100811_Jerry> Please follow CRB schematic (8.2K)
+1.05V
<20100813_Jerry> Update for the IGNNE#, please no

stuff the resister and follow CRB's circuit first.
SATA_CLKN
SATA_CLKP
SERIRQ
KBRST#
SATA HDD
<20110516>Reserve 1K PU to +1.05V for C6-state
HOST
U22C
<20110607_C-stage> Stuff 1K to follow CRB V1.5
H_A20M#
R109
1K/J_4
CPUSLP#_R
R532
*1K/J_4
H_IGNNE#
R105
1K/J_4
24.9/F_4
SATALED# [24]
10K/J_4
+3V
GA20
[27]
H_A20M# [6]
H_INIT# [6]
H_INTR [6]
R533
R110
0/J_4
CPUSLP# [6]
60.4/F_4
+1.05V
<Layout note>
Close to pin
<20100811_Jerry>you can follow PDG for the pull up

resistor value and tolerance requirement. CRB is more
strictly.
B
H_FERR# [6]
H_NMI [6]
KBRST# [27]
SERIRQ [27]
H_SMI# [6]
H_STPCLK# [6]
+1.05V
<20100811_Jerry>for Thermtrip#, please use 60 ohms+/-5% pull up.

R104
60.4/F_4 <Layout note>
Close to pin within 1"
PM_THRMTRIP# [6]
Tiger Point

PROJECT : ZE7
Size
Document Number
Rev
C3C
Tiger Point Sata/Host

Date:
5
Sheet
11
1
of
42
12
Tiger Point (CLG)

U22A
PCI CLK 33M-Hz

D
[2]
PCLK_ICH
EMI
R73
*33/J_4
A5
PCI_DEVSEL# B15
J12
T32
A23
PCI_IRDY#
B7
C22
PCI_SERR#
B11
PCI_STOP#
F14
PCI_LOCK#
A8
PCI_TRDY#
A10
PCI_PERR#
D10
PCI_FRAME# A16
C99
*10P/50V_4
[27]
EC_SCI#
Follow CRB
[11,13,14] VCC3_VCC3
+3V
T13
T4
A18
E16
GNT1#
GNT2#
PCI_REQ1#
PCI_REQ2#
G16
A20
REQ1#
REQ2#
PCH_GPIO48 G14
PCH_GPIO17
A2
PCH_GPIO22 C15
EC_SCI#
C9
T34
R70
R43
PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
TGP
PCI
GPIO48/ STRAP1#
GPIO17/ STRAP2#
GPIO22
GPIO1
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#
B2
D7
B3
H10
E8
D6
H8
F8
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCH_A16WP
10K/J_4
8.2K/J_4
D11
K9
M13
STRAP0#
RSVD01
RSVD02
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1
C/BE0#
C/BE1#
C/BE2#
C/BE3#
H16
M15
C13
L16
PCI_INTB#
PCI_IRDY#
PCI_INTG#
PCI_INTE#
RP3
1
3
5
7
2 8.2K_8P4R
4
6
8
PCI_LOCK#
PCI_INTD#
PCI_TRDY#
PCI_PERR#
RP2
1
3
5
7
2 8.2K_8P4R
4
6
8
PCI_DEVSEL#RP1
PCI_FRAME#
PCI_REQ1#
PCI_REQ2#
1
3
5
7
2 8.2K_8P4R
4
6
8
PCI_INTA#
PCI_INTC#
PCI_INTF#
PCI_INTH#
1
3
5
7
2 8.2K_8P4R
4
6
8
PCI_STOP#
PCI_SERR#
EC_SCI#
R30
R424
*1K/J_4
*1K/J_4
R389
RP4
R392
R391
R41
8.2K/J_4
8.2K/J_4
10K/J_4
PCH_GPIO48
PCH_GPIO17
R35
R421
*8.2K/J_4 PCH_GPIO22
R388
*1K/J_4
*1K/J_4
8.2K/J_4
+3V
D
+3V
+3V
+3V
+3V
C
+3V
+3V
<20101104> Reserve R389(PCH_GPIO22 PD) for 27MHz or 96MHz choosing, need vBIOS support
Pull up --> for 27MHz
Pull down --> for 96MHz
Tiger Point
B
<20090601(A1A)_Checklist Rev0.7>
Strap1#/strap2#: signals have weak
internal pull-ups
ICH Boot BIOS select

PCH_GPIO17
(INT PU)
PCH_GPIO48
(INT PU)
0
1
1
1
0
1
Boot BIOS Location

SPI
PCI
LPC (CURRENTLY USE)
Description
IRQ
PIRQA
USB UHCI Controller #1, #4
PIRQB
AC'97 Codec; option for SMBUS
PIRQC
USB UH Controller #3; SATA/IDE Native Mode
PIRQD
USB UHCI Controller #2
PIRQE
Internal LAN; Option for SCI, TCO, HPET#0,1,2
PIRQF
Option for SCI, TCO, HPET#0,1,2
PIRQG
Option for SCI, TCO, HPET#0,1,2
PIRQH
USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2
A16 SWAP Override strap

PCH_A16WP
(INT PU)
Low = A16 swap override enabled

High = Default

PCI_GNT#2
PROJECT : ZE7
Internal PU
Should not be PD
Size
4
Document Number
Rev
C3C
TigerPoint PCI
Date:
2
Sheet
12
1
of
42
13
Tiger Point (CLG)
+3V_S5
TGP
U22D
C136
*30P/50V_4
2011/4/28 For EMI Sam requestion
LAD0
LAD1
LAD2
LAD3
T21
[25,27] LFRAME#
AA5
V6
AA6
Y5
W8
Y8
Y4
P6
U2
W2
V2
P8
ACZ_SDOUT_AUDIO_R AA1
ACZ_SYNC_AUDIO_R
Y1
14M_ICH
AA3
[5] ACZ_SDINO
[20] ACZ_SDIN1
33/J_4 ACZ_RST#_AUDIO_R
90.9/F_4
[2]
33/J_4 ACZ_SDOUT_AUDIO_R
90.9/F_4
R451
R468
33/J_4 ACZ_SYNC_AUDIO_R
90.9/F_4
If integrated LAN is not used
LAN_RST# tie it to GND.
6P/50V_4
<20110516_DGv1.5>
Change ACZ BITCLK/RST/SDOUT/SYNC to CPU RES from 33ohm to 90.9ohm
32.768KHz,+-20PPM
Y4
6P/50V_4
R434
10M/J_4
RTC_X1 W4
RTC_X2 V5
RTCRST#
T5
R2
T1
M8
P9
R4
RTCX1
RTCX2
RTCRST#
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SMLALERT#
SMLINK0
SMLINK1
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB
THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRSTB
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
SPI
T36
T37
T14
T17
T16
E20
H18
E23
H21
F25
F24
CPUPWRGD/GPIO49
SMB
SMBALERT#
PCLK_SMB
PDAT_SMB
SMB_LINK_ALERT#
SMLINK0
SMLINK1
LAN_CLK
LANR_STSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
RTC
C349
T4
P7
B23
AA2
AD1
AC2
W3
T7
U4
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
LAN
C348
[20] ACZ_SYNC_CODEC
[5] ACZ_SYNC_CPU
R461
R472
U3
AE2
T6
V3
HDA_BIT_CLK
HDA_RST#
HDA_SDI0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14
EPROM
[20] ACZ_SDOUT_CODEC
[5] ACZ_SDOUT_CPU
14M_ICH
R452
R454
[20] ACZ_RST#_CODEC
[5] ACZ_RST#_CPU
BM_BUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39
AUDIO
ACZ_BITCLK_AUDIO_R
ACZ_RST#_AUDIO_R
LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#
LPC
[25,27]
[25,27]
[25,27]
[25,27]
MISC
T18
33/J_4 ACZ_BITCLK_AUDIO_R
90.9/F_4
R90
R93
[20] ACZ_BITCLK_CODEC
[5] ACZ_BITCLK_CPU
BATLOW#
DPRSTP#
DPSLP#
RSVD31
T15 BM_BUSY#
W16 PCH_GPIO6
W14 PCH_GPIO7
K18 PCH_GPIO8
H19 PCH_GPIO9
M17 EC_SMI#
A24 PCH_GPIO12
C23 PCH_GPIO13
PCH_GPIO14
P5
E24 PCH_GPIO15
AB20 PM_DPRSLPVR
Y16
AB19
R3 PCH_GPIO24
C24 DMI_AC_ENABLE
D19 PCH_GPIO26
D20 PCH_GPIO27
F22 PCH_GPIO28
AC19 CLKRUN#
U14 PCH_GPIO33
AC1 BOARDID0
AC23 BOARDID1
AC24 BOARDID2
T20
T19
<20101105> GPIO12 for A3-test CLKREQ setting

GPIO12 Command: For CLK Gen Byte5 CLKREQ# strap
Pull-high: 0x58 -> SRC2/4/6
Pull-low: 0x00 -> SRC1/3/5
EC_SMI# [27]
<20101108> GPIO13 for A3-test LAN chip selection

Pull-high -> for Atheros LAN AR8158
T38
Pull-down -> for Realtek LAN RTL8105TA-VC-CG
PM_STPPCI# [2]
<20110607> PU to +3V_S5 for GPIO12/13 no use to
PM_STPCPU# [2]
follow checklist v1.0
T35
PCLK_SMB
PDAT_SMB
PM_BATLOW#
DNBSWON#
EC_SMI#
SYS_RST#
SMBALERT#
SMB_LINK_ALERT#
PCIE_WAKE#
SMLINK1
SMLINK0
ICH_RI#
PCH_GPIO14
PCH_GPIO15
PCH_GPIO9
PCH_GPIO8
PCH_GPIO12
PCH_GPIO13
R378
R383
R402
R431
R49
R375
R379
R394
R404
R418
R420
R422
R28
R403
R380
R393
R407
R382
2.2K/J_4
2.2K/J_4
8.2K/J_4
*10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
T8
T10
T6
CLKRUN#
[27]
Follow CRB
T15
AB22 H_PWRGD
H_PWRGD [6,16]
AB17 THERM_ALERT#
V16 HWPG
AC18 MCH_SYNC#
E21 DNBSWON#
H23 ICH_RI#
G22
D22 SUSCLK
G18 SYS_RST#
G23 PLT_RST#
C25 PCIE_WAKE#
SM_INTRUDER#
T8
U10 TPT_PWROK
AC3 EC_RSMRST#
AD3 ICH_INTVRMEN
J16
<20110308> Unstuff R465 for adding

thermal sensor
Stuff -> Unuse thermal sensor
Unstuff -> Use thermal sensor
THERM_ALERT# [5,6,27]
HWPG [2,16,27]
DNBSWON# [16,27]
T5
SUSCLK [27]
PCIE_WAKE#
SPKR
VCC3_VCC3
R471
R464
R467
R465
1K/F_4
8.2K/J_4
10K/J_4
10K/J_4
DMI_AC_ENABLE
R401
1K/J_4
TPT_PWROK
R495
10K/J_4
EC_RSMRST#
R460
10K/J_4
[22,25]
VCCRTC
TPT_PWROK [16]
EC_RSMRST# [16,27]
H20 SUSB#
E25 SUSC#
F21
[11,12,14]
MCH_SYNC#
CLKRUN#
BM_BUSY#
THERM_ALERT#
[20]
SM_INTRUDER#
R473
1M/F_6
ICH_INTVRMEN
R458
332K/F_4
SUSB# [16,27]
SUSC# [16,27]
T12
B25 PM_BATLOW#
AB23 ICH_DPRSTP_R#
AA18 H_DPSLP#
F20
R107
R108
*56/F_4
+1.05V
*0/short_4
ICH_DPRSTP#
[6]
H_DPSLP# [6]
Tiger Point
TPT Power OK (CLG)
Platform Reset (CLG)

+3V
+3V
0.1U/10V_4
HWPG 2
[5,8,16,27]
TC7SH08FU
TPT_PWROK
4
<20110426 (G1A)>
Add 0.1uF CAP to prevent PWROK glitch issue
R395
C143
0.1U/10V_4
R101
0/J_4
*0/J_4
RTC (RTC)
Clock GEN I2C Level Shift
Mother Board ID (CLG)
VCCRTC
D16
C222
+3V
ACZ_SDOUT
(INT PD)
+3V
CH500H-40
1U/10V_6
R211
RTCRST#
CH500H-40
20K/F_6
C223
R254
1K/J_4
R513
VCCRTC_3
0/J_4
RTCRST#_EC [27]
PCH: +3V_S5
G1
[25]
PCLK_SMB
R374
2.2K/J_4
D15
R92
*10K/J_4
CLK GEN: +3V

1
R462
*10K/J_4
R457
*10K/J_4
20MIL
*SHORT_PAD
BOARDID0
BOARDID1
BOARDID2
2N7002K
Q38
2K/F_4 VCCRTC_2 R217
Description
* 4 x 1s
Reserved
1 x 4s(1 port/4 lanes)
Reserved
+5V_S5
20MIL
VCCRTC_1 R218
ACZ_SYNC
(INT PD)
SMBCK1 [2,4,25]
1U/10V_6
VCCRTC_4 1
100K_4
R417
+3VPCU
PLTRST# [6,16,22,25,26,27]
ECPWROK
*0.1U/10V_4
*TC7SH08FU
4
U4
PLT_RST#
C338
U21
C144
R87
10K/J_4
+3V
2K/F_4
R463
10K/J_4
R469
10K/J_4
INTVRMEN
A
Q27
METR3904-G
1
R376
2.2K/J_4
CLK GEN: +3V
<20110428 (G1A)>
Stuff 10K PD resistors for ZE7 A2-stage
Disable
PCH: +3V_S5
R216
68.1K/F_4
Enable internal VccSus1_5 VRM

(default)
[25]
CN5
RTC SOCKET
ML1220 Coin type

AHL03001406 Maxell
(HML) 18mAH
AHL03001424 FDK
(SAY) 15mAH
AHL03017100 Panasonic (MAT) 17mAH
R215
PDAT_SMB
SMBDT1 [2,4,25]
2N7002K
Q37
150K/F_4

PROJECT : ZE7
Size
Rev
C3C
TPT ACZ/GPIO/RTC
Date:
Document Number
Sheet

1
13
of
42
14
Tiger Point (CLG)

D36
<Layout note>
Place 0402 caps close to ball
Place 0603/0805 caps close to ICH
VCC5_VCC5REF
C333
RB500V-40
R390
100/F_4
D4
RB500V-40
R37
RVCC5_VCC5REF_SUS
6mA
10mA
VCC5REF
VCC5REF_SUS
45mA
VCCSATAPLL
6uA
24mA
10mA
C351
F12
C358
C355
Y6
VCCRTC
AE3
VCCDMIPLL
Y25
VCCUSBPLL
F6
.1U/10V_4
.01U/25V_4
*0/short_6
+1.5V
C147
10U/10V_8
L20
*0/short_6
+1.5V
C150
*4.7U/6.3V_6
VCCP_VCC1_05
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
AA8
M9
M20
N22
VCC1.5_VCC1.5
VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4
J10
K17
P15
V10
R120
C127
C84
C76
C72
C157
*0/short_6
.1U/10V_4
.1U/10V_4
1U/6.3V_4
1U/6.3V_4
4.7U/10V_8
+1.5V
A
POWER
+5V_S5
VCCRTC
W18
1.422A
NS3@10/F_4
L19
VCC1.5_VCCDMIPLL
C151
.01U/25V_4
V_CPU_IO
14mA
+3V_S5
.1U/10V_4
VCC1.5_SATAPLL
C133
.1U/10V_4
F5
+5V
1U/10V_4
TGP
U22E
+3V
0.955A
0.216A
0.092A
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCP_VCC1_05
R106
C119
C102
C137
H25
AD13
F10
G10
R10
T9
VCC3_VCC3
C135
C64
C74
C107
C121
F18
N4
K7
F1
RVCC3_VCCSUS3
C97
1U/6.3V_4
C70
1U/6.3V_4
C57
.1U/10V_4
C69
*10U/10V_8
*0/short_6
1U/6.3V_4
1U/6.3V_4
4.7U/10V_8
R503
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
.1U/10V_4
.1U/10V_4
+1.05V
*0/short_6
VCC3_VCC3
R430
*NS3@0/short_6
+3.3V_PRIME
[11,12,13]
+3V_S5
LAYOUT NOTE: place 10U CAP close to pin F18

5
Tiger Point
PROJECT : ZE7
Size
Rev
C3C
TigerPoint Power
Date:
Document Number
Sheet
14
of
42
15
Tiger Point (CLG)

U1LB
U22F
TGP
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25
VSS57
VSS58
VSS59
G24
AE13
F2
RSVD32
AE16
Tiger Point

PROJECT : ZE7
Size
Document Number
Rev
C3C
TigerPoint GND
Date:
1
Sheet
15
of
42
16
Power Sequence Connector 30pin (CPU)
CN17
D
[27,30,35] S5_ON
+3V_S5
[13,27] DNBSWON#
[13,27] SUSB#
+1.5VSUS
+5V
+1.05V
[27,31,34] +3.3V_PRIME_ON
+3.3V_PRIME
[2,13,27] HWPG
[13] TPT_PWROK
[6,13,22,25,26,27] PLTRST#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
S5_ON
DNBSWON#
SUSB#
+3.3V_PRIME_ON
HWPG
TPT_PWROK
PLTRST#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
NBSWON#
NBSWON# [24,27]
+5V_S5
EC_RSMRST# [13,27]
SUSC# [13,27]
SUSON [27,32,34]
MAINON [27,32,33,34]
+1.5V
HWPG_1.05V [31,33,34]
+VCC_CORE
+1.8V
ECPWROK [5,8,13,27]
H_PWRGD [6,13]
EC_RSMRST#
SUSC#
SUSON
MAINON
HWPG_1.05V
ECPWROK
H_PWRGD
*30pin POWER SEQ CONN
GND
11
+1.5VSUS
21
HWPG
NBSWON#
12
MAINON
22
ECPWROK
S5_ON
13
+5V
23
TPT_PWROK
+5V_S5
14
+1.5V
24
H_PWRGD
+3V_S5
15
+1.05V
25
PLTRST#
RSMRST#
16
HWPG_1.05V
26
RESERVE
DNBSWON#
17
VRON
27
RESERVE
SUSC#
18
+VCC_CORE
28
RESERVE
SUSB#
19
+3.3V_PRIME
29
RESERVE
10
SUSON
20
+1.8V
30
RESERVE

PROJECT : ZE7
Size
Document Number
Rev
C3C
Cedarview XDP
Date:
5
Sheet
1
16
of
42
17
HDMI (HDM)
Level Shifter motherboard topology for max data rate of 1.65Gb/s
<20101209> Change to DFHS19FR015 by ME design change
Close to HDMI connector
CN16
3
HDMITX2P_MOS
R200
620/F_4
R195
620/F_4
+3V
TX2_HDMI+
TX2_HDMI-
R189
620/F_4
TX1_HDMI+
R185
620/F_4
TX1_HDMI-
[5]
[5]
TX1_HDMITX0_HDMI+
[5]
[5]
TX0_HDMITX3_HDMI+
TX3_HDMI-
TX2_HDMITX1_HDMI+
TX1_HDMITX0_HDMI+
TX0_HDMITX3_HDMI+
TX3_HDMI-
+5V
+5V_HDMI
HDMI_HPD
1.1A 8V POLY(SMD1206P110TFT)
100K/J_4
+3V
C367
0.22U/6.3V_4
HDMITX3P_MOS
HDMITX1P_MOS
TX2_HDMITX1_HDMI+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HDMI_DDC_CLK
HDMI_DDC_DATA
R192
[5]
[5]
TX2_HDMI+
F2
Q19
2N7002K
100K/J_4
TX2_HDMI+
[5]
R174
620/F_4
TX3_HDMI+
R171
620/F_4
TX3_HDMI-
SHELL1
D2+
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0GND
CK+
CK Shield GND
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL2
20
D
23
22
21
HDMI connector
R142
1M/F_6
<20101001> Change from 100K to 1M ohm (follow DG0.7)
100K/J_4
R176
Q16
2N7002K
Q22
2N7002K
100K/J_4
+3V
HDMITX3N_MOS
HDMITX1N_MOS
R126
10K/J_4
R180
[5] HDMI_DDI0_HPD#
100K/J_4
100K/J_4
HDMI_DDI0_HPD#
Q17
2N7002K
Q23
2N7002K
R515
<20100115(B2A)>
Add fuse to meet IEC 60950-1
2nd certificationand.
HDMITX0N_MOS
HDMITX2N_MOS
[5]
TX0_HDMI-
100K/J_4
Q25
2N7002K
R209
620/F_4
R190
TX0_HDMI+
Q18
2N7002K
100K/J_4
+3V
620/F_4
2
Q24
2N7002K
R245
R181
R177
R233
HDMITX0P_MOS
+3V
HDMI_HPD
Q7
2N7002K
1
R138
*100K_4
SDVO I2C Control (HDM)
EMI reserve for HDMI (EMC)
<20100909_Jennifer> Change R500/ R502

from 1.5k to 2.2k to follow CRB.
ESD Protect (HDM)

B
Close to HDMI Connector
Close to HDMI Connector
+3V
U6
R500
2.2K/J_4
D39
RB500V-40
2.2K/J_4
+5V
[5] DDI0_HDMI_SCL
+3V
L22
BLM18AG601_6
HDMI_DDC_CLK
Q13
2N7002K
R502
2.2K/J_4
D41
RB500V-40
+5V
2.2K/J_4
C180
*0.1u/10V_4
The DDC signals are rated at 5V at connector. The

passgate can also be used to protect against
back-power
when computer is OFF but the display is ON and still
pulled up to 5 V.
[5] DDI0_HDMI_SDA
R196
*100/F_4
HDMI_HPD
HDMI_DDC_DATA_L
L23
BLM18AG601_6
10
9
7
6
7
6
HDMI_HPD
10
9
10
9
TX0_HDMI+
TX0_HDMI-
7
6
7
6
TX3_HDMI+
TX3_HDMI-
10
9
10
9
TX2_HDMI+
TX2_HDMI-
7
6
7
6
TX1_HDMI+
TX1_HDMI-
U7
R187
*100/F_4
HDMI_DDC_DATA
TX0_HDMI+
TX0_HDMITX3_HDMI+
TX3_HDMI-
1
2
3
4
5
R179
*100/F_4
C183
*0.1u/10V_4
HDMI_DDC_DATA
HDMI_DDC_CLK
10
9
*RClamp0524P
1
2
GND_3/8
4
5
*RClamp0524P
TX0_HDMI-
Q14
2N7002K
1
2
GND_3/8
4
5
TX1_HDMI+
TX0_HDMI+
3
1
2
3
4
5
TX2_HDMI-
TX1_HDMI-
R535
HDMI_DDC_CLK_L
HDMI_DDC_DATA
HDMI_DDC_CLK
TX2_HDMI+
R534
U9
TX2_HDMI+
TX2_HDMI-
TX3_HDMI+
R173
*100/F_4
TX1_HDMI+
TX1_HDMI-
TX3_HDMI-
1
2
3
4
5
1
2
GND_3/8
4
5
*RClamp0524P

PROJECT : ZE7
Size
Document Number
Date:
Rev
C3C
HDMI
5
Sheet
1
17
of
42
HALL IC (HSR)
LCD POWER SWITCH (LDS)

R91
+3VPCU
CAMERA POWER (CCD)

Irush=1.5A
AVG=0.24A
*100K_4
<EMI>
R536
47/F_6
D44 *VPORT_6
2
1
R349
R19
D7 *VPORT_6
1
2
LID#
C319
C324
*2.2U/6.3V_6
.1U/10V_4
C309
C310
.01U/16V_4
C312
*0.1U/10V_4
20mA*24pcs=480mA
D8
RB500V-40
LID#
R345
[27]
*EDP@0/J_8
U19
+3V
C328
4.7U/6.3V_6
DISPON
4
R350
[5] INT_LVDS_DIGON
R118
10K_4
0/J_4
IN
OUT
IN
GND
ON/OFF
GND
[5] TXLOUT1+
[5] TXLOUT1DDI1_AUX_DP
DDI1_AUX_DN
[5] DDI1_AUX_DP
[5] DDI1_AUX_DN
R359
R358
LVDS@0/J_4
LVDS@0/J_4
TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN
C326
C325
*EDP@.1U/16V_4
*EDP@.1U/16V_4
TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN
[5] TXLOUT2+
[5] TXLOUT2DDI1_TX0_DP
DDI1_TX0_DN
[5] DDI1_TX0_DP
[5] DDI1_TX0_DN
C18
4.7U/25V_1206
LVDS@0/J_4
LVDS@0/J_4
TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-
C314
C313
*EDP@.1U/16V_4
*EDP@.1U/16V_4
TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-
R26
+3V
CCD_POWER
0/J_6
C22
*IVO@4.7U/25V_8
INT_LVDS_BLON
TXLOUT2_R-_EDPTX0-_R1
TXLOUT2_R+_EDPTX0+_R1
TXLOUT1_R-_EDP_AUXN_R1
TXLOUT1_R+_EDP_AUXP_R1
100K_4
3
1
Reserve for IVO panel
[5]
[5] TXLOUT0+
[5] TXLOUT0-
USBP2-_R
USBP2+_R
C21
*IVO@0.1U/50V_6
R131
2N7002K
CCD_POWER
+5V_LCD
DISPON
LCD_VADJ
Refer to INTEL DG co-layout

2
Q6
CN1
V_BLIGHT
R348
R347
C19
0.1U/50V_6
LCDVCC
+5V
Q4
0/J_6
IVO panel : 21.W/5V=0.42A
IC(5P) G5243AT11U
R354
100K/J_4
BL#
R13
VIN
+3V
1000P/50V_4
LCD MODULE (LDS)
R113
10K_4
2N7002K
4.7U/10V_8
C308
*0/short_4
4.7u/10V_8
MR1
APX9132H AI-TRG
C138
1U/10V_6
CCD_POWER
*0/short_6
USBP2-_R
USBP2+_R
USBP2USBP2+
<G1A>
Change C138 from 4.7U to 1U
C318
*0/short_4
R20
.1U/10V_4
+3V
[10]
[10]
C327
CCD_POWER
R344
*0/short_8
18
0.15A
+3V
LCDVCC
LCDVCC_1
EC_FPBACK#
DDI1_TX1_DP
DDI1_TX1_DN
[5] DDI1_TX1_DP
[5] DDI1_TX1_DN
[27]
Q5
DTC144EUA
R352
R353
LVDS@0/J_4
LVDS@0/J_4
TXLOUT0_R+_EDPTX1+
TXLOUT0_R-_EDPTX1-
C315
C316
*EDP@.1U/16V_4
*EDP@.1U/16V_4
TXLOUT0_R+_EDPTX1+
TXLOUT0_R-_EDPTX1-
TXLCLKOUT-_R_EDPTX2-_R1
TXLCLKOUT+_R_EDPTX2+_R1
[5] TXLCLKOUT+
[5] TXLCLKOUTDDI1_TX2_DP
DDI1_TX2_DN
[5] DDI1_TX2_DP
[5] DDI1_TX2_DN
LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3+3V_EDP_HPD
R357
R356
LVDS@0/J_4
LVDS@0/J_4
TXLCLKOUT+_R_EDPTX2+
TXLCLKOUT-_R_EDPTX2-
C323
C322
*EDP@.1U/16V_4
*EDP@.1U/16V_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
31
32
33
34
LCD CONN
<C-test> Chang to DFHS30FR048 for SMT ME Peter request
Single-ended 50ohm
[5] LCD_CLK
[5] LCD_DATA
CRT(CRT)
DDI1_TX3_DP
DDI1_TX3_DN
[5] DDI1_TX3_DP
[5] DDI1_TX3_DN
Differential 90ohm
<20100115(B2A)>
Add F1(fuse) to meet IEC 60950-1 2nd certificationand.
R371
R370
LVDS@0/J_4
LVDS@0/J_4
LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3-
C332
C331
*EDP@.1U/16V_4
*EDP@.1U/16V_4
LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3-
Trace Impedance use

single-ended 50ohm and differential 90ohm
eDP (LDS)
C38
.1U/10V_4
+3V
+3V
F1
+5V
CRTVDD5
R365
*EDP@100K_4
1.1A 8V POLY(SMD1206P110TFT)
<Layout note>
PLACE inductances 90 DEGREE FROM EACH OTHER
R23
*EDP@1K/J_4
[5] DDI1_HPD#
CRT_R
[5]
CRT_G
[5]
CRT_B
R85
R84
R83
150/F_4 150/F_4 150/F_4
L14
PBY160808T-220Y-N
CRT_R1
L15
PBY160808T-220Y-N
CRT_G1
L13
PBY160808T-220Y-N
CRT_B1
C114
C109
C108
C77
C78
C79
*10P/50V_4
*10P/50V_4
*10P/50V_4
4.7P/50V_4
4.7P/50V_4
4.7P/50V_4
R366
*EDP@100K_4
CN10
11
CRT_11
12
CRT_SDA
13
CRTHSYNC
14
CRTVSYNC
15
CRT_SCL
DDI1_HPD R21
R22
17
R373
TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN
CRT_BYP
7
8
C47
0.22U/25V_6
+3V
C36
.1U/10V_4
CRT_R1
CRT_G1
CRT_B1
3
4
5
6
CRT_VSYNC1
CRT_HSYNC1
R76
R75
47/F_4 VSYNC_R
47/F_4 HSYNC_R
VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
16
14
15
13
CRT_VSYNC
CRT_HSYNC
VIDEO_1
VIDEO_2
VIDEO_3
DDC_IN1
DDC_IN2
10
11
CRT_DDC_SCL [5]
CRT_DDC_SDA [5]
DDC_OUT1
DDC_OUT2
9
12
GND
IP4772_Rout=10ohm
TXLOUT1_R+_EDP_AUXP_R1
TXLOUT1_R-_EDP_AUXN_R1
*0/short_4
R362
*0/short_4
TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-
U3
CRTVDD5
L17
L16
0/J_6
0/J_6
CRTVSYNC
CRTHSYNC
C37
*10P/50V_4
R79
2.2K/J_4
CRT_SCL
CRT_SDA
Pull up at CPU side
R78
2.2K/J_4
R59
0/J_4
R60
*0/J_4
C39
LCD_VADJ
*0.1U/10V_4
R361
*0/short_4
R364
*0/short_4
C131
*100P/50V_4
CRTVSYNC
C123
*100P/50V_4
CRTHSYNC
C85
*100P/50V_4
CRT_SCL
C86
*100P/50V_4
CRT_SDA
TXLOUT0_R-_EDPTX1TXLOUT0_R+_EDPTX1+
R363
*0/short_4
R368
*0/short_4

PROJECT : ZE7
TXLCLKOUT+_R_EDPTX2+_R1
TXLCLKOUT-_R_EDPTX2-_R1
R367
CONTRAST
CRTVDD5
CRTVDD5
[5]
[5]
[5] INT_LVDS_PWM
*0/short_4
R372
R25
*EDP@100K/J_4
+3V_EDP_HPD
+3V_EDP_HPD
[27]
<Layout note>
Close to CONN
C35
.1U/10V_4
*EDP@0/J_4
LVDS@0/J_4
CRT CONN
2nd source: 4.7P(+-0.25P) CH-4706TB01
+3V
T2
+3V
DDI1_HPD
Q3
*EDP@2N7002K
16
[5]
6
1
7
2
8
3
9
4
10
5
*EDP@0/J_4
TXLOUT1_R-_EDP_AUXN
TXLOUT1_R+_EDP_AUXP
R27
Size
Document Number
Date:
*0/short_4
Rev
C3C
CRT/LVDS/EDP
2
Sheet
18
of
42
<20110214(E1A)>
Change CP1~CP6 footprint from
8p4r-0402-smt to 8P4R, for SMT open issue.
KEYBOARD (KBC)
BLUETOOTH (BTM)
19
<EMI>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
CP4
*220P_8P4R
Q33
CP1
*220P_8P4R
+3V
CP3
*220P_8P4R
61mA BT_POWER
C283
BT@AO3413
[10]
[10]
CN2
*BT@0.1U/10V_4
USBP6+
USBP6-
+
R282
CP2
*220P_8P4R
5
4
3
2
1
BT_LED
T30
C246
BT@0.22u/25V_6
[25,27] BT_POWERON#
CN7
C248
BT@1000p/50V_4
6
7
BT@BT_CONN
BT@10K/J_4
C270
*BT@1000p/50V_4
CP6
*220P_8P4R
CP5
*220P_8P4R
0603 size
25
26
KB CONN
TOUCH PAD (TPD)

Left Button
+5V_TP
TP_R#
TP_L#
TPDATA_CN
TPCLK_CN
4.7K/J_4
+5V
+5V_TP
TP switch
<EMI>
D43
*14V/38V/100P_4
L9
<EMI>
L8
L7
+5V_TP
TP_CONN
R18
4.7K/J_4
3mA
TP_L#
0.4A/120ohm_6
0.4A/120ohm_6
TPDATA
TPCLK
[27]
[27]
10P/50V_4
C30
CX08T121000:0.4A/120ohm_6
CX121T04000:0.4A/120ohm_6
C34
3A/120ohm_8
CX121T30001:3A/120ohm_8
.1U/10V_4
C33
Right Button
10P/50V_4
SW3
1
2
TP_R#
TP switch
D42
*14V/38V/100P_4
2
3
4
5
6
7
8
1
2
3
4
5
6
R24
SW2
1
2
CN3
B
3
4
5
6

PROJECT : ZE7
Size
Document Number
Rev
C3C
KB/BT/TP/LED/Power Connector
Date:
5
Sheet
1
19
of
42
HPR
Codec ALC271X (ADO)
20
EARPHONE (AMP)
HPL
MIC1-VREFO-L
MIC2-VREFO
MIC1-VREFO-R
R244
2.2K/J_4
MIC2-VREFO
ADOGND
Place near codec

INT_AMIC-VREFO C208
10U/6.3V_6
ADOGND
2.2U/6.3V_6
C240
MIC2_L2
2.2U/6.3V_6
C244
1K/J_4
COMBO_MIC
R243
1
C206
MIC2_R2
Place next to pin 27
<20100917> Add 22k PD by FAE

suggestion for discharing
R236
22K/F_4
C209
2.2U/6.3V_6
C212
C210
0.1U/10V_4
*10U/6.3V_6
+5VA
ADOGND
C258
C243
4.7U/6.3V_6
.1U/10V_4
49
SPDIFO
PGND
R283
*0/short_6
SENSEB
MIC2_R2
16
MIC2_L2
1n/50V_4
1u/16V_6
1u/16V_6
HPL
R172
47/F_4
HPR
R497
47/F_4
HPL-1
L21
0_6
L39
0_6
HPL_SYS
HPR-1
HPR_SYS
R496
R152
C363
C174
*1K/J_4
*1K/J_4
2200P/50V_4
2200P/50V_4
D38
*14V/38V/100P_4
ADOGND
R249
39.2K/F_4
HP_JD#
R257
20K/F_4
MIC1_JD#
2
4
5
HP_JD#
<20110428> Add 1n PD to AGND for amic

noise depressing by FAE Vic suggestion
ADOGND
ADOGND
D40
*14V/38V/100P_4
6/*7&34"-+"$,
010030FR006G119ZR
ADOGND
D11
*14V/38V/100P_4
ADOGND
<20101103> Add EC PWM control

for beep sound volumn control
ANALOG
ALC271X-VB3-GR
PCBEEP dont coupling any signals if possible

8/17 separate PCBEEP to Digital from Realtek suggestion
1.6Vrms
PCBEEP_C C260
1U/10V_6 BEEP_1
C264
C263
4.7U/6.3V_6
100P/50V_4
R267
4.7K/J_4
R273
47K/J_4
R274
47K/J_4
PCBEEP
[27]
SPKR
[13]
MIC (AMP)
If either HDA device io power use +1.5V,

all device IO power change to +1.5V
MIC1-VREFO-R
MIC1-VREFO-L
Place next to pin 1

+AZA_VDD_R
T54
T55
3
6
1
MIC2-JD#
20K/F_4
C204
SENSEA
13
CN15
ADOGND
AMIC2_INT
LIN2_INT_L1 C239
14
LINE2-L
Sense A
R232
LIN2_INT_R1 C237
15
20K/F_4
18
17
Normal Open Jack
Audio Codec
R226
19
+AZA_VDD
C256
.1U/10V_4
ADOGND
Placement near
MIC1_L1
DIGITAL
+3V
AVDD1
27
25
26
VREF
AVSS1
29
28
LDO-CAP
MIC2-VREFO
MIC1-VREFO-R
30
31
32
HP-OUT-L
MIC1-VREFO-L
33
HP-OUT-R
35
SPDIFO2/EAPD
21
47
Spilt by DGND
C247
48
4.7U/6.3V_6.1U/10V_4
LINE2-R
MIC1_R1
PCBEEP
EAPD#
C234
PVDD2
RESET#
46
SYNC
+5VPVDD2
12
*0/short_6
11
R268
+5V
MIC2-L
22
20
MIC2-R
SPK-R+
R235
C231
*10U/6.3V_8
Sense-B
SPK-R-
10
Spilt by PGND
ALC271X-VB3-GR
PVSS2
DVDD-IO
45
SDATA-IN
44
R_SPK+
JDREF
DVSS2
R_SPK-
MONO-OUT
PVSS1
43
SPK-L-
42
22K/F_4
ADOGND
ADOGND
23
LINE1-L
MIC1-L
C219
10U/6.3V_6
24
LINE1-R
MIC1-R
BIT-CLK
.1U/10V_4
C227
.1U/10V_4
SPK-L+
SDATA-OUT
4.7U/6.3V_6
Q26
2SK3018
PVDD1
41
40
L_SPK-
4.7U/6.3V_6.1U/10V_4
L_SPK+
C226
PD#
C221
C220
AVDD2
GPIO1/DMIC-CLK
C230
AVSS2
+5V
39
GPIO0/DMIC-DATA
38
DVDD1
37
+5VPVDD1
*0/short_6
Spilt by AGND
R220
CPVEE
36
ADOGND
ANALOG
CBP
U11
ADOGND
CBN
C207
.1U/10V_4
34
2.2U/6.3V_6
C217
10U/6.3V_6
MIC2-JD#
ADOGND
C213
+5VA
D37
*14V/38V/100P_4
2.2U/6.3V_6
R266
*0/short_6
DMIC_DAT
DMIC_CLK
ACZ_RST#_CODEC [13]
PD#
0V : Power down Class D SPK amplifier

5V : Power up Class D SPK amplifier
ACZ_SYNC_CODEC
ACZ_SDIN1_R R265
33/J_4
C252
C265
.1U/10V_4
4.7U/6.3V_6
+AZA_VDD
R453
4.7K/F_4
R178
4.7K/F_4
Normal Open Jack
[13]
ACZ_SDIN1 [13]
CN13
Place next to pin 9
MIC1_L1
C356
4.7u/6.3V_6
MIC1_L2
R455
1K/F_4
MIC1_L3
R447
0_6
MIC1_L
MIC1_R1
C218
4.7u/6.3V_6
MIC1_R2
R202
1K/F_4
MIC1_R3
R183
0_6
MIC1_R
3
6
1
ACZ_SDOUT_CODEC [13]
MIC1_JD#
ACZ_BITCLK_CODEC [13]
*22P/50V_4
2
4
5
MIC1_JD#
6/*7&34"-+"$,
010030FR006G119ZR
C257
D12
*VPORT_6
Near CN13
C187
C353
C201
*470p/50V_4
*470p/50V_4
*0.1u/16V_6
ADOGND
Power (ADO)
GND
Internal Speaker (AMP)
ADOGND
Internal Analog MIC (AMP)
Demodulation Filter
Place close to Codec
+5VA
<20110811> For analog mic ESD protection using
ANALOG
L25
<20101115> Change to 10K by codec FAE suggestion
0/J_8
40mil for each signal
R520
R501
0/J_6
0/J_6
R439
R261
R188
R225
R175
R184
R441
R168
*0/J_6
*0/J_6
*0/J_6
*0/J_6
*0/J_6
*0/J_6
*0/J_6
*0/J_6
CN6
R_SPK+
R_SPKL_SPKL_SPK+
Mute (ADO)
R297
R290
R272
R242
*0/short_6
*0/short_6
*0/short_6
*0/short_6
R_SPK+_1
R_SPK-_1
L_SPK-_1
L_SPK+_1
4
3
2
1
R-L-SPEAKERS
C275
*68p/50V_6
C269
*68p/50V_6
C261
*68p/50V_6
C241
*68p/50V_6
+5V
<20101115> Change to 10K by codec FAE suggestion
*10K/J_4
C195
C251
D25
RB500V-40 ACZ_RST#_CODEC
D24
RB500V-40 EAPD#
D23
RB500V-40
10K/J_4
AMIC2_INT
1K/J_4
R140
CN4
AMIC2_INT_R
R130
1
2
INT_MIC
C158
*22P-50V_4
ADOGND
D9
TVS/6pF_4
ADOGND
ADOGND
<20110706> Stuff TVS BC040201Z00 for ESD solution

R511
R203
R444
R285
PD#
INT_AMIC-VREFO
DIGITAL
+5V
*Short_6
0/J_6
0/J_6
1000P/50V_4
1000P/50V_4
ADOGND
AMP_MUTE# [27]
PROJECT : ZE7
Size
Document Number
Rev
C3C
ALC271X / AMP / SPK

Date:
5

1
Sheet
20
of
42
USB Left (USB)
21
+5VPCU
D
4
1
2A
5VUSB_1
<Layout note>
Close to CONN
<Layout note>3528 type H=1.9mm

<2nd Source> CH71001M687
C377
+ C379
.1U/10V_4
USBOC#L [10,27]
Left
100U/6.3V_3528
R248
G547E2P81U: Enable: Low Active /2.5A

Follow ZH9
[10]
[10]
*0/short_4
CN21
USBP3-_CN
USBP3+_CN
USBP3USBP3+
R253
*0/short_4
1
2
3
4
VDD
DD+
GND1
2
3
USB_EN#
U25
IC(8P)G547E2P81U
8
IN1
OUT3
7
IN2
OUT2
6
OUT1
EN
GND
5
OC#
C380
1U/6.3V_4
D18
*5V/30V/0.2P_4
GND7
GND8
6
5
7
8
USB_CONN
D20
*5V/30V/0.2P_4
GND6
GND5
USB Right (USB)
+5VPCU
C111
4.7u/10V_6
2
3
[27] USB_EN#
2A
5VUSB_0
<Layout note>
Close to CONN
+ C26
USBOC#R
C24
220u/6.3V_7343
[10,27]
R15
[10]
[10]
G547E2P81U: Enable: Low Active /2.5A

Follow ZH9
CN9
1
2
3
4
*0/short_4
USBP1-_CN
USBP1+_CN
USBP1USBP1+
*0/short_4
GND7
GND8
6
5
7
8
D3
*5V/30V/0.2p_4
<Layout note>
Close to CONN
C73
+ C89
Right down
0.1u/10V_4
R50
*100u/6.3V_3528
*0/short_4
CN12
1
2
3
4
USBP0USBP0+
R44
*0/short_4
USBP0-_CN
USBP0+_CN
GND6
GND5
D2
*5V/30V/0.2p_4
[10]
[10]
VDD
DD+
GND1
USB_CONN
R14
Right up
0.1u/10V_4
U23
IC(8P)G547E2P81U
8
IN1
OUT3
7
IN2
OUT2
6
OUT1
USB_EN# 4
EN
1
GND
5
OC#
R82
*10K/J_4
+3VPCU
GND6
GND5
GND7
GND8
6
5
7
8
USB_CONN
D6
*5V/30V/0.2p_4
D5
*5V/30V/0.2p_4
VDD
DD+
GND1
PROJECT : ZE7
Size
Rev
C3C
USB Port/ MAX14566EETA

Date:
Document Number
Sheet
1
21
of
42
LAN (LAN)
22
+3V_LAN
VDD10
R1
Close To IC
C1
0.1U/16V_4
1
C304
0.1U/16V_4
C307
0.1U/16V_4
C320
0.1U/16V_4
Close to IC
EVDD10
*0/short_4
*0/short_6
C16
0.1U/16V_4
C2
0.1U/16V_4
R351
+3V_S5
C6
1U/10V_4
C5
0.1U/16V_4
Close To IC Pin 13.
C317
*4.7U/10V/8
D
R2
CTRL12
*0/short_4
C3
0.1U/16V_4
Close To IC Pin 31.
<20110510> Change from 27P to 33P by vendor's measure report.
C7
+3V_LAN
25MCLKX1
33P/50V_4
LAN_ACTLED#
R3
2.49K/F_4
25MCLKX2
CTRL12
RSET
GPO
R6
LAN_LINKLED#
1K/J_4
+3V_LAN
32
31
30
29
28
27
26
25
Y1
25MHz-LAN
TX0P
TX0N
TX1P
TX1N
Pull-Up at CLK Gen side
1
2
3
4
5
6
7
8
+3V_LAN
R343
[2] CLKREQ_LAN#
VDD10
CLKREQ_LAN#_R1
*0/short_4
HV
MDIP0
MDIN0
MDIP1
MDIN1
NC
VDD1
CLKREQBPIN
GND
GND
GND
EEDIPIN/TDI/SPISI/SDA
EEDOPIN/LED3/SPISO
EECSPIN/TCS/SCL
VDD1
LANWAKEBPIN
VDD3
ISOLATEBPIN
PERSTBPIN
EEDI/SDA
LED3/EEDO
EECS/SCL
VDD10
PCIE_WAKE#
24
23
22
21
20
19
18
17
ISOLATE#
R7
*10K/J_4
EEDI/SDA
R9
10K/J_4
EECS/SCL
R8
10K/J_4
T1
+3V_LAN
Int. PU in SB
PCIE_WAKE# [13,25]
R11
R10
1K/J_4
15K/J_4
+3V
RTL8105TA-VC-CG
R12
*0/short_4
PLTRST# [6,13,16,25,26,27]
C17
*4.7U/10V/8
40
41
42
9
10
11
12
13
14
15
16
37
38
39
GND
GND
GND
GND
*10K/J_4
PCIE_WAKE#
33
34
35
36
HSIP
HSIN
REFCLK_P
REFCLK_N
VDDTX
HSOP
HSON
GNDTX
33P/50V_4
GND
GND
GND
C4
RSET
CTRL12
CKXTAL2
CKXTAL1
LEDPIN/SPICSB
VDD3
GPOUTPIN
EESKPIN/LED1/TCLK/SPISCK
U1
CLKREQ_LAN#_R1 R342
[10] PCIE_TXP0
[10] PCIE_TXN0
[2] CLK_PCIE_LANP
[2] CLK_PCIE_LANN
C8
C14
[10] PCIE_RXP0
[10] PCIE_RXN0
.1U/10V_4
.1U/10V_4
EVDD10
PCIE_RXP0_LAN
PCIE_RXN0_LAN
For Rural
TRANSFORMER (LAN)
RJ45 Connector (LAN)
CN8
U17
R335
R336
R338
R337
0/J_4
0/J_4
0/J_4
0/J_4
TX0P_R
TX0N_R
TX1P_R
TX1N_R
1
2
3
4
1
2
3
4
LAN_LINKLED#
U15
8
7
6
5
X-TX0P
X-TX0N
X-TX1P
X-TX1N
8
7
6
5
1
2
3
4
*UCLAMP2512T.TCT
TX1N_R
TX1P_R
TX0N_R
TX0P_R
8
7
6
5
4
3
2
1
8
7
6
5
8
7
6
5
R346
C311
*510/J_6
+3V_LAN
11
12
TERM9
*0.1U/50V_8
*UCLAMP2512T.TCT
U16
For Rural, use 1/F_4 (CS-1002FB23)

For Normal, use 0/J_4 (CS00002JB38)
1
2
3
4
TDTD+
CT
NC
NC
CT
RDRD+
7
X-TX1N
TERM9
For Rural, stuff 0/J_4 (CS00002JB38)

For Normal, unstuff 0/J_4 (CS00002JB38)
TXTX+
CT
NC
NC
CT
RXRX+
9
10
11
12
13
14
15
16
X-TX1N
X-TX1P
TERM0
X-TX0N
X-TX0P
LAN_ACTLED#
R339
R334
*0/J_4
C299
NS0014 LF_Bothhand
R340
R341
75/F_8
75/F_8
TX0P
TX0N
TX1P
TX1N
X-TX1P
X-TX0N
X-TX0P
*510/J_6
+3V_LAN
9
10
GG+
GREEN
NC4/3NC/3+
RX-/1NC2/2NC1/2+
RX+/1+
TX-/0TX+/0+
GND
GND
AA+
14
13
AMBER
RJ45-CONN
*0.1U/50V_8
D35
C303
*10P/50V_4
C302
*10P/50V_4
C300
*10P/50V_4
C301
*10P/50V_4
C306
0.01U/25V_4
*P3100SBLRP
<20110105> Will add RJ45 connector without LED type by inner document
DFTJ08FR221 (FOX)
DFTJ08FR222 (AEC)
TERM9
The value should be

0.01uF-0.4uF
Reserve for EMI request
C305
1000P/3KV_1808
Size
Date:
5
PROJECT : ZE7
Document Number
Rev
C3C
LAN RTL8105TA-VC-CG
Sheet
1
22
of
42
23
Stitching Capacitor (CLG)

For RF Request
D
+1.05V
C145
1000P/50V_4
C27
1000P/50V_4
For CRT R/G/B Signals

VIN
C140
1U/25V_6
C

PROJECT : ZE7
Size
4
Rev
C3C
Stitching Cap
Date:
5
Document Number
23
Sheet
1
of
42
24
2.5" SATA HDD (HDD)
CN11
1
2
3
4
5
6
7
SATA_TXP0_C1
SATA_TXN0_C1
C340
C339
0.01u/16V_4
0.01u/16V_4
SATA_TXP0
SATA_TXN0
SATA_RXN0_C1
SATA_RXP0_C1
C342
C341
0.01u/16V_4
0.01u/16V_4
SATA_RXN0
SATA_RXP0
8
9
10
11
12
13
14
15
16
17
5V_SATA1
SATA_TXP0 [11]
SATA_TXN0 [11]
SATA_RXN0 [11]
SATA_RXP0 [11]
1A
R369
+
C25
C23
C20
0.1U/10V_4
*0.1U/10V_4
4.7U/10V_8
*0/short_8
+5V
C330
MAIN_SATA
*100U/6.3V_3528
LED/SW (UIF)
+3V_S5
D31
<20110223> In S5 and battery only mode,

EC will turn off PWRLED#/SUSLED# while EC is idle.
2 *5.5V/25V/410P_4
PWR indicator
+3V
LED1
2
LED3
PWR LED
SUS LED
R330
33/J_4
R331
220/F_4
PWRLED# [27]
R333
51/J_4
LED_BLUE_TOP
SUSLED# [27]
LED_AMBER/BLUE
D32
2 *5.5V/25V/410P_4
D33
2 *5.5V/25V/410P_4
PWR button
LED2
FULL LED
CHG LED
R327
33/J_4
BATLED0# [27]
R328
220/F_4
BATLED1# [27]
LED_AMBER/BLUE
NBSWON# [16,27]
D1
5.5V/25V/410P_4
Power Switch
2 *5.5V/25V/410P_4
NBSWON#
2
1
D34
SW1
3
4
5
6
+3VPCU
<20110530> Change from +3V to +5V Due to there is the

internal series resister in 3G/WLAN module, cause the forward voltage of LED4 is too small
D28
2 *3G@5.5V/25V/410P_4
+5V
LED4
3G LED
WLAN LED
R325
3G@150/F_4
R326
470/J_4
3G_MINI_LED# [25]
WLAN_LED# [25]
LED_AMBER/BLUE
D29
2 *5.5V/25V/410P_4
SATALED# [11]
+5V
LED5
3
HDD LED
R329
*330/J_4
*BSS84
Q36
Need the buffer for LED driving
capability since the IOL is 6mA only.
*LED_BULE_SIDE
D30
2 *5.5V/25V/410P_4
PROJECT : ZE7
Size
Document Number
Date:
<20101229> Unstuff HDD LED

5
Rev
C3C
SATA HDD/LED/SW
4
Sheet
1
24
of
42
Mini Card 1 (MPC)
Turn off WLAN LED when 3G module is on
25
+3V_Mini1_VDD
+1.5V_Mini1_VDD
+3V_Mini1_VDD
+3V_Mini1_VDD
RF_LED_ON
R308
*0/short_4
4
2
+3V_Mini1_VDD
3G_MINI_LED#
RN1
CN22
PCIE_TXP1
PCIE_TXN1
[10] PCIE_RXP1
[10] PCIE_RXN1
15
13
11
9
7
5
3
1
[2] CLK_PCIE_MPC_P
[2] CLK_PCIE_MPC_N
Q44
1
3
[13,22] PCIE_WAKE#
+3V_Mini1_VDD
53
[2] CLKREQ_MPC#
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
MINI1_WAKE#
*0/short_4
*4.7K_4P2R
WLAN_LED# [24]
[2,4,13] SMBDT1
[10]
[10]
WL_SMDATA
WL_SMCLK
PLTRST#_2
RF_EN
WL_SMDATA
R314
*0/J_4
+3V_Mini1_VDD
R521
*0/short_4
PLTRST# [6,13,16,22,26,27]
RF_EN [27]
[2,4,13] SMBCK1
R517
R518
R519
R522
R523
Q29
*2N7002E
*0/short_4
*0/short_4
*0/short_4
*0/short_4
*0/short_4
LFRAME#
LAD3
LAD2
LAD1
LAD0
[13,27]
[13,27]
[13,27]
[13,27]
[13,27]
R294
WL_SMCLK
1
*0/J_4
*10K/J_4
+1.5V
+3V_Mini1_VDD
+1.5V_Mini1_VDD
*0/short_8
R527
*0/J_8
*0/J_8
C385
+3VSUS
0.5A
0.75A
R260
R531
C390
C391
C382
C386
*1000P/50V_4
*10U/10V_8
.1U/10V_4
.1U/10V_4
C383
C250
*0.1U/10V_4
*10U/10V_8
C384
.1U/10V_4
Mini Card 2 (MNC)
.1U/10V_4
<2011/1/24(E1A)> Change from 10k to 100k to reduce leakage
no matter have 3G function or not,

need to stuff this PU.
+1.5V_Mini2_VDD
+3V_Mini2_VDD
+3VSUS
+3V_Mini2_VDD
+3V_Mini2_VDD
+3V_Mini2_VDD
R241
*0/short_8
R252
*0/short_6
+3V_Mini2_VDD
Peak:2.75A
Normal:1.1A
C233
C373
C371
C370
C366
C389
C378
+3V_Mini2_VDD
R210
CN19
PCIE_TXP3
PCIE_TXN3
[10] PCIE_RXP3
[10] PCIE_RXN3
B
15
13
11
9
7
5
3
1
[2] CLK_PCIE_MNC_P
[2] CLK_PCIE_MNC_N
CLKREQ_3G#
T42
53
T41
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
R508
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
GND
[10]
[10]
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
100K/J_4
3G_MINI_LED# [24]
R224
*3G@0/J_8
R222
*3G@0/J_6
3G@10P/50V_4
Q21
*3G@2N7002E
[13]
PDAT_SMB
PDAT_SMB 3
R194
*3G@10K_4
*3G@10K_4
3G_SMDATA
USBP5+_R
USBP5-_R
R207
+1.5V
3G_SMDATA
3G_SMCLK
+1.5V_Mini2_VDD
R228
*3G@0_4
0.5A
*3G@0/J_8
+3V_Mini2_VDD
PLTRST#_1
R516
3G_EN
*3G@0/J_4 PLTRST#
[27]
C235
C369
*3G@1000P/50V_4
*3G@0.1U/10V_4
Q15
*3G@2N7002E
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
16
14
12
10
8
6
4
2
[13]
PCLK_SMB
PCLK_SMB 3
3G_SMCLK
R201
*3G@0_4
3G@3G CONN
3G@0_4
USBP5+_R
USBP5-_R
USBP5+
USBP5R510
+3V
R262
WLAN_LED1#
3G_MINI_LED#
3G@10U/10V_8 3G@0.1U/10V_4 3G@0.1U/10V_4 3G@0.1U/10V_4 3G@0.1U/10V_4 3G@0.47U/6.3V_4
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
GND
T39
Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
54
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
R530
*2N7002K
+3V
C
R525
USBP7+
USBP7-
16
14
12
10
8
6
4
2
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
WLAN CONN
3
1
WLAN_LED1#
WIMAX_LED#
Q32
*2N7002E
[10]
[10]
4.7K/J_4
Q30
2N7002K
R302
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
0/J_4
0/J_4
Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
GND
[2] PCLK_DEBUG
R529
R526
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
GND
PLTRST#
*0/J_4
54
R528
[19,27] BT_POWERON#
[10]
[10]
3G@0_4
MultiMedia SIM (MNC)

<Layout Notes> Keep USIM signals max length within 8000mils.
JSIM1
R5
*3G@0/short_4
CLK(C3)
D-(C8)
D+(C4)
CT
CD
3G@SIM-CONN
GND(C5)
VCC(C1)
VPP(C6)
RST(C2)
DATA(C7)
1
2
3
4
5
UIM_PWR
UIM_VPP
UIM_RST
UIM_DATA
GND
GND
USB_SIM_P4-_R
USB_SIM_P4+_R
USBP4USBP4+
13
11
[10]
[10]
6
7
8
9
10
GND
GND
UIM_CLK
UIM_PWR C13
<20090604(A1A)_Qualcomm design guide>

Place 0.1uF near connector's VCC pin
3G@27P/50V_4
+3V
Max: 7.5mA (Option)

UIM_DATA C11
3G@10P/50V_4
UIM_CLK
3G@10P/50V_4
UIM_PWR
U18
UIM_RST
C12
1
2
UIM_RST
C10
3G@27P/50V_4
UIM_CLK
CH1
VN
CH2
CH4
VP
CH3
UIM_VPP
C321
*3G@0/short_4
C15
5
3G@1U/10V_6
UIM_DATA
3G@0.1U/10V_4
*3G@CM1293-04SO
12
14
R4
UIM_VPP
C9
*3G@33P/50V_4
PROJECT : ZE7
Size
3
Rev
C3C
Mini-Card/WL/3G/SIM
<20110609> Un-stuff C9 since EM820W doesn't use Vpp

5
Document Number
Date:
2

1
Sheet
25
of
42
5 IN 1 Card Reader CONN (MMC)
Card reader controller (MMC)
26
+3V3_IN
D
VCC_XD
[6,13,16,22,25,27]
CN20
13
1
2
3
4
10
19
23
25
5
8
17
21
SD_CD#
SD_WP/XD_D7
SD_D1_R
SD_D0_R
SD_CLK_R
SD_CMD_R
SD_D3_R
SD_D2_R
SD_D7/XD_RDY
SD_D6/XD_RE#
SD_D5/XD_CE#
SD_D4/XD_WE#
PLTRST#
C286
*1U/6.3V_4
[2] CLKREQ_MMC#
7
15
26
27
TP1
0.1U/10V_4
TP2
TP3
+3V3_IN
C289
<Layout Note> Place Close to Chip Pin
PCIE_TXP2
PCIE_TXN2
[2] CLK_PCIE_MMC_P
[2] CLK_PCIE_MMC_N
4
AV12
[10]
PCIE_RXP2
C292
0.1U/10V_4
PCIE_RXP2_C 6
[10]
PCIE_RXN2
C293
0.1U/10V_4
PCIE_RXN2_C 7
C294
0.1U/10V_4
*0/short_6
DV12
VCC_XD
10
+3V3_IN
11
TP4
SD_CD#
SD_WP/XD_D7
XD_D6
38
37
SP14
SP15
40
39
SD_CD#
MS_INS#
MS_INS#
EESK
42
41
GPIO/EEDI
EECS
EESK
EEDO
43
EECS
PLTRST#
44
EEDO
46
SP10
AV12
SP9
HSOP
SP8
RTS5209-GR
SP7
GND
SP6
DV12
SP5
Card1_3V3
DV12_S
3V3_IN
GND
Card2_3V3
SD_D2
C290
0.1U/10V_4
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
SD-GND1
SD-GND2
SD-WP-GND
SD-CD-GND
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
MS-VCC
MS-BS
MS-DATA1
MS-DATA0
MS-DATA2
MS-INS
MS-DATA3
MS-SCLK
XD-GND1
XD-GND2
XD-GND3
MS-GND1
MS-GND2
45
28
29
30
31
32
33
34
35
XD_CD#
SD_D7/XD_RDY
SD_D6/XD_RE#
SD_D5/XD_CE#
MS_BS/XD_CLE
MS_D5/XD_ALE
SD_D4/XD_WE#
MS_D1/XD_WP#
37
38
39
40
41
42
43
44
MS_D4/XD_D0
MS_D0/XD_D1
MS_D2/XD_D2
MS_D6/XD_D3
MS_D3/XD_D4
MS_D7/XD_D5
XD_D6
SD_WP/XD_D7
36
46
47
36
MS_D7/XD_D5
35
MS_D3/XD_D4
34
MS_D6/XD_D3
33
MS_D2/XD_D2
32
MS_D0/XD_D1
31
MS_D4/XD_D0
30
MS_D1/XD_WP#
29
MS_D5/XD_ALE
28
MS_BS/XD_CLE
27
VCC_XD
DV12_S
26
GND
25
SD_D2
R269
C376
0.1u/10V_4
C255
4.7U/6.3V_6
C262
0.1U/10V_4
C381
0.1u/10V_4
C297
0.1u/10V_4
C387
4.7U/10V_8
33/J_4
SD_D2_R
SD_D3
24

SD_D3
SD_D0
SD_CMD
23
SD_CLK
22
21
SD_CMD
SP4
SP3
SD_D1
20
SD_CLK
SD_D0
SD_D1
15
GND
SD_D4/XD_WE# 19
14
SD_D5/XD_CE# 18
13
*PBY160808T-601Y-N_1A DV12
SP2
XD_CD#
L33
PERST#
REFCLKN
DV33_18
AV12
CLK_REQ#
SP11
XD_CD#
C298
4.7U/10V_8
12
22
9
11
12
14
16
18
20
MS_BS/XD_CLE
MS_D1/XD_WP#
MS_D0/XD_D1
MS_D2/XD_D2
MS_INS#
MS_D3/XD_D4
MS_CLK
10P/50V_4
XD-VCC
Card Reader CONN
REFCLKP
HSON
C276
SD-VCC
SD-CD-SW
SD-WP-SW
SD-DAT1
SD-DAT0
SD-CLK
SD-CMD
SD-DATA3
SD-DAT2
MMC-DATA7
MMC-DATA6
MMC-DATA5
MMC-DATA4
<20101206> Change to DFHS44FR015 by ME design change
SP12
SD_D6/XD_RE# 17
R332
GND
MS_CLK
6
24
SP13
SP1
+3V
4.7U/6.3V_6
33/J_4
HSIN
GND
Zdiff = 80 ohm
C295
R305
HSIP
SD_D7/XD_RDY 16
Zdiff = 95 ohm
[10]
[10]
DV33_18
Zdiff = 80 ohm
47
48
RREF
U14
3V3_IN
45
6.2K/F_4
CARDREF
R323
VCC_XD
R319
*100K_4
C288
*4.7U/6.3V_6
R286
33/J_4
SD_D3_R
SD_D3_R
C282
*10P/50V_4
R292
33/J_4
SD_CMD_R
SD_CMD_R
C284
*10P/50V_4
R303
33/J_4
SD_CLK_R
SD_CLK_R
C291
*10P/50V_4
R307
33/J_4
SD_D0_R
SD_D0_R
C296
*10P/50V_4
R315
33/J_4
SD_D1_R
SD_D1_R
C392
*10P/50V_4
SD_D2_R
C393
*10P/50V_4
C287
0.1U/10V_4
SD_CLK_R
<EMI>
C274
10P/50V_4

PROJECT : ZE7
Size
Document Number
Rev
C3C
RTS5209-GR (Card Reader)

Date:
5

1
Sheet
26
of
42
C181
C374
C267
C232
4.7U/6.3V_6
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
U10
3
126
127
128
1
2
LCLK_EC
CLKRUN#
[11]
GA20
121
[11]
KBRST#
122
EC_SCI#
[18] EC_FPBACK#
[6,13,16,22,25,26]
KBRST/GPIO86
29
ECSCI/GPIO54
GPIO24/LDRQ
LPC
GPIO10/LPCPD
LREST
[25]
RF_EN
123
GPIO67/PWUREQ
SERIRQ
125
SERIRQ
EC_SMI#
FOR VGA
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
[19]
[19]
54
55
56
57
58
59
60
61
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
GPIO56/TA1
KBSOUT7
GPIO20/TA2/IOX_DIN_DIO
KBSOUT8
GPIO14/TB1
KBSOUT9/SDP_VIS
TIMER
KBSOUT10/P80_CLK
GPIO15/A_PWM
KBSOUT11/P80_DAT
GPIO21/B_PWM
KBSOUT12/GPIO64
GPIO13/C_PWM
KBSOUT13/GPIO63
GPIO32/D_PWM
KBSOUT14/GPIO62
GPIO45/E_PWM
KBSOUT15/GPIO61/XOR_OUT
GPIO40/F_PWM/RI1
GPIO60/KBSOUT16
GPIO66/G_PWM
GPIO57/KBSOUT17
GPIO33/H_PWM/SOUT1
MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
[29] MBCLK
[29] MBDATA
[5] 2ND_MBCLK
[5] 2ND_MBDATA
T23
T24
TPCLK
TPDATA
TPCLK
TPDATA
[19,25] BT_POWERON#
[13] SUSCLK
GPIO01/TB2
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06/IOX_DOUT/RTS1
GPIO07
GPIO16
GPIO30
GPIO36/CTS1
GPIO41
GPIO42/SCL3B/TCK
GPIO43/SDA3B/TMS
GPIO44/TDI
GPIO
GPO47/SCL4
GPIO50/PSCLK3/TDO
GPIO51
GPIO52/PSDAT3/RDY
GPIO53/SDA4
GPIO70
GPIO71
GPIO72
GPIO75/SPI_SCK
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST
GPO84/IOX_SCLK/XORTR
GPIO97
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
72
71
10
11
R161
*0/short_4 E775_32KX1 77
R275
*0/short_4
97
98
99
100
C186
.01U/16V_4
ICMNT_EC
R182
E791AGND
*0/short_4
C188
ICMNT
R160
64
79
95
96
108
93
94
114
109
15
80
17
20
21
24
25
26
27
28
73
74
75
82
83
84
91
110
112
107
R155
R214
CHARGE_IC_ON
[29]
3300P/50V_4
SM BUS PU(KBC)
ACIN
USBOC#R2_R
USBOC#R1_R
10K/J_4
1/13 Comfirm by vendor mail :

Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
TEMP_MBAT [29]
101
105
106
3G_EN
SHBM
[29]
NBSWON# [16,24]
USBOC#R [10,21]
USBOC#L [10,21]
LID#
[18]
*0/J_4
*0/J_4
MBCLK
MBDATA
R164
R165
2ND_MBCLK
2ND_MBDATA
R154
R169
+3VPCU
+3V
4.7K/J_4
4.7K/J_4
*4.7K/J_4
*4.7K/J_4
<20110308> Change from +3V_S5 to

+3V for thermal sensor
T56
T25
+3.3V_PRIME_ON
HWPG
THERM_ALERT#_R R276
+3.3V_PRIME_ON
*0/J_4
USB_CHARGE_ON
T28
S5_ON
HDMI_IN
T27
PWROK_EC_uR
RSMRST#_uR
R163
R162
D/C#
S5_ON
T22
DNBSWON#_1
D10
[16,31,34]
1ST: Battery
2ND: CPU Thermal Sensor / DTS
3RD: VGA Thermal Sensor
THERM_ALERT# [5,6,13]
SUSB# [13,16]
[29]
[16,30,35]
SUSC# [13,16]
ECPWROK [5,8,13,16]
EC_RSMRST# [13,16]
MAINON [16,32,33,34]
3G_EN [25]
*0/short_4
*0/short_4
RB500V-40
DNBSWON#
[13,16]
BATLED0#
BATLED1#
T40
USB_EN# [21]
31
117
63
RTCRST#_EC [13]
SUSON [16,32,34]
FANSIG [6]
32
118
62
65
22
16
81
66
CONTRAST [18]
PCBEEP [20]
PWRLED# [24]
BATLED0# [24]
CPUFAN# [6]
SUSLED# [24]
+3VPCU
R167
R166
100K/J_4
100K/J_4
<20090831(A1A)_EC team suggest>

1.change R166/R167 to 1M or 100K ohm
2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
can reduce pull-high resistor of SUSLED#/PWRLED#
SPI FLASH(KBC)
1/13 Comfirm by vendor mail :
If the Southbridge enables 'Long Wait Abort' by default, the
flash device should be 50MHz (or faster)
BATLED1# [24]
+3VPCU
70
69
67
68
119
120
SMB
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
VTT
PECI
If PECI 3.0 access functionality is not used,

NPCE791L
connect VTT pin to GND.
F_SDI/F_SDIO1
F_SDO/F_SDIO0
F_CS0
F_SCK
PS/2 FIU
GPIO00/32KCLKIN
12
13
GPIO87/CIRRXM/SIN_CR
GPIO34/SIN1/CIRRXL
GPIO46/CIRRXM/TRST
GPO83/SOUT_CR/TRIST
IR
GPIO55/CLKOUT/IOX_DIN_DIO
GND1
GND2
GND3
GND4
GND5
GND6
FOR CPU Thermal Sensor
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
GPIO65/SMI
5
18
45
78
89
116
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
GPIO94/DA0
GPI95/DA1
GPI96/DA2
D/A
[11]
[13]
C281
4.7U/6.3V_6
GPIO85/GA20
PLTRST#
A/D
GPIO11/CLKRUN
124
[20] AMP_MUTE#
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
L24
PBY160808T-250Y-N/3A/25ohm_6
VCC_POR
VCORF
[12]
C272
.1U/10V_4
E791AGND
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
AGND
[13]
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK_EC
SHBM=0: Enable shared memory with host BIOS

<20090602(A1A)_Vendor suggest>
Place 10nF-0.1uF capacitors for
every AD input. And close to the AD
input.
VREF
<20090721_FAE suggestion>
Stuff 100K and close to EC side
for improving power consumption
113
14
23
111
86
87
90
92
SPI_SDI_uR
SPI_SDO_uR
SPI_CS0#_uR
SPI_SCK_uR
30
ECDB_CLOCK
85
VCC_POR#
R506
47K/J_4
104
VREF_uR
R206
*0/short_4
22/J_4 SPI_SDO_uR_R
R153
22/J_4 SPI_SCK_uR_R
+3VPCU
R159
22/J_4
SPI_SDI_uR_R
SPI_SDO_uR_R
SPI_SCK_uR_R
R158
10K/J_4
SPI_CS0#_uR
SO
VDD
SI
HOLD
C364
WP
0.1U/16V_4
VSS
SCK
CE
W25Q16BVSSIG
R157
T26
100K/J_4
+3VPCU
+A3VPCU
C375
ZS9 A1~A3-test
W25Q16BVSSIG
AKE38FP0N01
16M bit
ZS9 A4-test
W25Q16CVSSIG
AKE38ZP0N02
16M bit
ZS9 A5-test
MX25L1606EM2I-12G
AKE38FP0Z01
16M bit
ZS9 A6-test
MX25L1606EM2I-12G
AKE38FP0Z01
16M bit
ZS9 A7-test
W25Q16BVSSIG
AKE38FP0N01
16M bit
Winbond W25Q16BVSSIG
EON
EN25F16-75HCP
MXIC
MX25L1606EM2I-12G
1U/6.3V_4
E791AGND
E791AGND
U8
SPI_SDI_uR
SPI_SDI_uR
R156
VCORF_uR 44
[13,25]
[13,25]
[13,25]
[13,25]
[13,25]
[2]
*RB500V-40
C182
D22
VDD
C177
+3V
+3V_EC
<Layout note>
Place every 0.1uF
close to every
power pin
E791AGND
103
E791AGND
0.03A (30mils)
+3VPCU_EC
19
46
76
88
115
2.2/J_6
2
27
*0/short_6
10mA
4.7U/6.3V_6
VCC1
VCC2
VCC3
VCC4
VCC5
R504
1
I/O ADDRESS SETTING(KBC)

R281
C202
.1U/10V_4
+3VPCU
+A3VPCU
C211
102
PBY160808T-250Y-N/3A/25ohm_6
AVCC
L26
EC (KBC)
30mil
AKE38FP0N01
AKE38ZA0Q00
AKE38FP0Z01 (ZE6 MAC ID fail)
<EMI>
INTERNAL KEYBOARD STRIP SET (KBC)
HWPG (KBC)
<20110829> DDRAM_PWROK no need connecting to EC side

+3V
LCLK_EC
[31] HWPG_VCCGFX
+3VPCU
RP5
10
9
8
7
6
10K/J_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5
10/26 UnStuff
MY0
R193
*10K/J_4
[8,32] DDRAM_PWROK
+3VPCU
[34] HWPG_1.8V
[30] SYS_HWPG
[6,31] IMVP_PWRGD
*RB500V-40
D14
*RB500V-40
D19
RB500V-40
D21
*RB500V-40
D13
*RB500V-40
R278
R280
HWPG_R
R277
10K/J_4
HWPG
*0/short_4
HWPG
[2,13,16]
*22/J_4
[34] MAINON_ON_G
C271
*10P/50V_4
+3VPCU
Q28
2N7002K
PROJECT : ZE7
Size
MX4
MX5
MX6
MX7
D17
Document Number
Rev
C3C
NPCE791L & FLASH

Date:
5
Sheet

1
27
of
42
28
HOLE (OTH)
HOLE13
2
3
4
HOLE18
HOLE17
HOLE19
2
3
4
2
3
4
2
3
4
h-c197d63p2
5
6
7
*HG-TC276BC315D98P2
HOLE1
5
6
7
h-c197d63p2
8
1
9
*HG-C276D98P2
HOLE3
5
6
7
8
1
9
8
1
9
2
3
4
h-c197d63p2
HOLE10
5
6
7
8
1
9
* ZE7-P2
HOLE2
5
6
7
2
3
4
PAD2
*HG-C276D98P2
HOLE4
5
6
7
8
1
9
*HG-C276D98P2
HOLE7
2
3
4
2
3
4
PAD1
HOLE6
5
6
7
1
*HG-TC276BC256D98P2
*ZE7-P1
HOLE16
5
6
7
8
1
9
2
3
4
8
1
9
HOLE14
5
6
7
8
1
9
HOLE9
2
3
4
*HG-C276D98P2
8
1
9
*HG-C276D98P2
HOLE21
TP ESD PAD
5
6
7
h-tc177bc295d120p2 h-tc177bc295d120p2
*HG-C276D98P2
HOLE20
LED ESD PAD
5
6
7
2
3
4
BOT(Mini-PCIe Hole)
HOLE15
5
6
7
2
3
4
8
1
9
HOLE12
5
6
7
8
1
9
8
1
9
2
3
4
8
1
9
HOLE8
5
6
7
8
1
9
HOLE5
2
3
4
BOT(Thermal Hole)
TOP(HDD Hole)
*HG-TC276BC315D98P2 *HG-TC276BC315D98P2 *HG-TC276BC315D98P2 *ZE7-P3
*O-ZE6-2
HOLE11
*O-ZE6-3

PROJECT : ZE7
Size
Document Number
Rev
C3C
EMI/Hole
Date:
5
Sheet
1
28
of
42
VA1
PJ1
VA
1
2
3
VA2
PR133
.01_3216
8
7
6
5
1
2
3
CSIP_1
PR132
220K/F_6
VIN
PC87
0.1U/50V_6
8
7
6
5
PR157
33K/J_6
2200P/50V_4
PC84
2200P/50V_6
29
PQ41
AO4427
VIN
PC88
PC83
0.1U/50V_6
PC86
0.1U/50V_6
7
6
5
4
PQ38
AO4427
PD7
SBR1045SP5-13
1
PL6
FBMA-11-201209-800A50T
PD8
SMAJ20A
PC85
0.1U/50V_6
PD6
1SS355
PR131
220K/F_6
PR156
10K/J_6
D/C#
[27]
PR134
*0/short_4
1
2
POWER_JACK
dcjk-2dc2003-000111-3p-v
PQ39
IMD2AT108
VIN
2
PQ40
2N7002K
CSIP_1
VIN
PC100
1U/10V_4
PR42
10/F_6
PR43
10/F_6
PC20
2200P/50V_4
PR173
4.7/J_6
PC22
0.1U/25V_4
PC25
1U/10V_4
ISL88731_VDDP
PC19
0.1U/50V_6
21
MBDATA
[27]
ACIN
VDDP
VCC
BOOT
PR47
2.7/J_6
88731B_2
25
PC17
0.1U/50V_6
88731B_1
4
PQ1
AON7410
SDA
UGATE
24
ISL88731_UGATE
10
SCL
PHASE
23
ISL88731_PHASE
13
ACOK
LGATE
20
ISL88731_LGATE
PR59
100K/F_4
MBCLK
VDDSMB
.01_3216
PR155
PL7
6.8uH/4.5A_7X7X3
3
2
1
11
CSSN
NC
GND
GND
GND
GND
CSSP
PC34
1U/10V_4
+3VPCU
PC99
4.7U/25V_8
PD1
*RB500V-40
+3VPCU
BAT-V
27
26
CSIN
1
33
32
31
30
28
CSIP
C
PR54
2.2/F_4
PC9
.01U/25V_4
PR170
49.9/F_4
PC21
0.1U/25V_4
DCIN
22
19
CSOP
18 CSOP
PU2
ISL88731C
DCIN
PR55
10/F_6
PR48
82.5K/F_4
88731ACSET
PGND
PR51
22K/F_4
VREF
ICOMP
NC
PC6
47P/50V_4
PC8
0.1U/25V_4
PC5
BAT-V
CSOP_1
PR56
10/F_6
15
GND
29
BAT-V
Close battery side
GND
NC
BAT-V
PC4
100P/50V_4
PC24
*1U/10V_4
PC33
.01U/25V_4
ICMNT
47P/50V_4
PR23
*0/short_4
PR27
100/J_4
PC90
10U/25V_1206
12
PR57
2.21K/F_4
Batt_Conn
bat-btj-08tc0b-8p-l-v
VBF
VCOMP
TEMP_MBAT [27]
PC91
PR148
100/J_4
14
100/J_4
17 CSON
PR58
*0/short_4
16
NC
NC
PR24
TEMP_MBAT_C
BAT-V
MBAT+
ICM
FBMA-11-201209-800A50T
PL1
10 1
2
3
4
5
6
7
9 8
5
PJ2
PC10
2200P/50V_4
PC31
0.1U/25V_4
CSON
FBMA-11-201209-800A50T
PL2
PR25
100K_4
PQ50
AON7410
PC26
2200P/50V_4
CSOP_1
10U/25V_1206
ACIN
+3VPCU
B
3
2
1
PR26
100/J_4
ISL88731 thermal pad

tie to Pin12
ICMNT
[27]
PC28
PC30
0.01U/25V_4 *0.01U/25V_4
PU1
*CM1293A-04SO
1
MBCLK
MBDATA
[27]
[27]
TEMP_MBAT
CH1
VN
CH2
CH4
VP
CH3
MBDATA
+3VPCU
MBCLK
Add ESD diode base on EC FAE suggestion
PROJECT : ZE7
Size
Document Number
Rev
C3C
CHARGER (ISL88731)
Date:
5
Sheet

1
29
of
42
MAIND
SUSD
MAIND
[32,34]
SUSD
[34]
SYS_SHDN#
SYS_SHDN#
30
[6,35]
[27] SYS_HWPG
VIN
+3VPCU
VIN
VL
8223REF
+3VPCU
VIN
EN
+3V_PG
23
PGOOD
+5V_DH
21
UGATE1
22
BOOT1
1
2
3
PC42
0.1u/50V_6
PR76
1/F_6
+5V_B
+5V_LX
20
PHASE1
+5V_DL
19
LGATE1
24
VOUT1
17
TONSEL
+3V_TON
UGATE2
10
+3V_DH
BOOT2
+3V_B
PHASE2
11
+3V_LX
12
+3V_DL
5
PC43
0.1u/50V_6
PR78
1/F_6
PL4
2.2uH_7X7X3
+3VPCU
3 Volt +/- 5%
TDC : 2.368A
PEAK : 3.16A
OCP : 4A
Width : 100mil
GND
OUT2
FB2
PR187
4.7_6
+3V_FB
4
PC118
0.1u/50V_6
PC58
220uF/6.3V_6X4.2
PC112
680p/50V_6
PC111
680p/50V_6
3
2
1
PQ17
AON7702
8223_EN
PR185
10K/F_4
PR183
6.81K/F_4
15
GND
ENTRIP2
6
25
PR81
*0/short_4
1
2
3
PC113
0.1u/50V_6
FB1
ENTRIP1
ENC
+5V_FB
PQ21
AON7702
PR188
4.7_6
PC46
220uF/6.3V_6X4.2
+3V_SKIP
LGATE2
18
PR182
15.4K/F_4
PU3
RT8223M
14
PC39
4.7u/25V_8
+3VPCU
PQ13
AON7410
SKIPSEL
PL3
2.2uH_7X7X3
PC40
2200p/50V_6
3
2
1
13
PR67
*0/short_4
PR186
*0/short_4
REF
SYS_SHDN#
VREG3
VIN
5
PQ14
AON7410
PR189
*0_4
PR72
*0_4
PR83
330K/F_4
VREG5
PR73
100K/F_4
+5VPCU
5 Volt +/- 5%
TDC : 4.858A
PEAK : 6.5A
OCP : 8A
Width : 200mil
16
+5VPCU
PC37
1u/6.3V_4
PC49
PR75
*0/short_4
PC38
PC47
0.1u/25V_4
8223_EN
PC45
2200p/50V_6
PC44
4.7u/25V_8
8223_VIN
PR82
665K/F_4
4.7u/6.3V_6
PR190
10_8
4.7u/6.3V_6
VIN
PR184
10K/F_4
PC48
0.1u/10V_4
PR84
100K/F_4
PR70
97.6K/F_4
PR69
48.7K/F_4
+5V_DL
OCP:8A
PD3
1PS302
L(ripple current)
=(9-5)*5/(2.2u*0.4M*9)
=2.525A
Iocp=8-(2.525/2)=6.74A
Vth=6.74A*14mOhm=94.32mV
R(Ilim)=(94.32mV*10)/10uA
~94.32K
PC52
0.1u/50V_6
OCP:4A
PR68
*0/short_6
L(ripple current)
=(9-3.3)*3.3/(2.2u*0.5M*9)
~1.9A
Iocp=4-(1.9/2)=3.05A
Vth=3.05A*14mOhm=42.7mV
R(Ilim)=(42.7mV*10)/10uA
=42.7K
+3V_DL
3
PR86
*0/short_6
1
PC51
0.1u/50V_6
PR71
*0/short_6
PR85
*0_6
2
PD2
1PS302
3
PC50
0.1u/50V_6
+15V_ALWP
+15V
PR191
22_8
PC115
0.1u/50V_6
+3VPCU
S5D
MAIND
PQ12
AO3404
PQ22
AO3404
PQ35
AO3404
PQ33
2N7002K
SUSD
PQ15
AO3404
PQ34
2N7002K
+5V_S5
TDC : 0.008A
PEAK : 0.01A
Width : 10mil
+5V
+3V
PQ24
AO3404
TDC : 1.03A
TDC : 1.858A
PEAK : 1.38A
PEAK : 2.477A
Width : 50mil
Width : 80mil
3
TDC : 0.94A
PEAK : 1.25A
Width : 40mil
+3VSUS
PROJECT : ZE7
Size
Document Number
Rev
C3C
SYSTEM 5V/3V (RT8206)

Date:
+3V_S5
PQ16
2N7002K
PR126
1M_6
PQ32
DTC144EU
TDC : 0.15A
PEAK : 0.2A
Width : 10mil
S5_ON
[16,27,35]
MAIND 2
S5D
+3VPCU
PR125
1M_6
+3VPCU
PR74
22/J_8
+5VPCU
PR124
22/J_8
+5VPCU
PR123
1M_6
+15V
+5V_S5
+3V_S5
VIN
Sheet

1
30
of
42
31
8165_VCC
VIN
+5V_S5
PC123
*22U/25V_1210
PC124
*22U/25V_1210
PC125
*22U/25V_1210
PC126
*22U/25V_1210
PC127
*22U/25V_1210
8165_VCC
PR37
2_6
PC89
4.7u/6.3V_6
PC98
4.7u/6.3V_6
PR46
130K/F_4
<20110428> For EMI request
PR53
4.7_6
PR29
*0/short_4
PR39
*0/short_4
27
FBA
TONSETA
PC12
33P/50V_4
UGATEA
VCCGFX
PR35
750/F_4
PR34
11K/F_4
31
8165_TONSETA
34
8165_DH2
33
8165_BOOTA
PR41
88.7K/F_4
COMPA
BOOTA
8165_RGNDA 26
[7] GTVSS_SENSE
RGNDA
PHASEA
8165_LX2
36
8165_DL2
PR12
100/J_4
[6] VR_SVID_ALERT#
8165_ALERT#
[27] HWPG_VCCGFX
8165_VRHOT#
[6,27] IMVP_PWRGD
[6] H_PROCHOT#
[16,33,34]
+3V
10K/F_4
PR13
10K/F_4
PR50
HWPG_1.05V
25
8165_VDIO
24
PR146
*0/short_4
8165_ALERT# 23
PR144
*0/short_4
8165_VRA
22
PR143
*0/short_4
8165_VR
21
PR142
*0/short_4
[16,27,34]
8165_VR
0_4
PR49
+3.3V_PRIME_ON
8165_VRHOT# 20
8165_EN
PR44
*0/short_4
For HW Debug
8165_VRA
PR14
8165_VCLK
*0/short_4
PR40
100K_4
PR28
100/F_4
32
8165_TEMPMAX 12
*0_4
PC3
470p/50V_4
PR22
*0/short_4
PR36
*0/short_4
8165_ICCMAX
13
8165_ICCMAXA
14
8165_OCSET
16
8165_OCSETA
18
8165_SETINI
11
8165_SETINIA
10
8165_TSEN
15
8165_TSENA
17
8165_FB
PC11
36p/50V_4
VCLK
ISENAP
ALERT
VRA_READY
ISENAN
VRHOT
PR45
130K/F_4
EN
2
8165_TONSET
40
8165_DH1
PR52
4.7_6
<20110428> For EMI request

VIN
ICCMAX
ICCMAXA
UGATE1
PC18
0.1u/25V_6
OCSET
PR169
2.2_6
OCSETA
BOOT1
8165_BOOT1
39
8165_LX1
SETINI
PC29
2200P/50V_4
PC104
0.1u/50V_6
PC106
4.7u/25V_8
PC105
4.7u/25V_8
SETINIA
PHASE1
PC97
0.22U/25V_6
TSEN
TSENA
LGATE1
FB
ISEN1P
COMP
GND
38
+VCC_CORE
PQ5
AON7410
L=1.5uH, typ.DCR=14m-ohm
8165_DL1
PL9
1.5uH_7X7X3
3
+
4
PR174
*2.2/F_6
PR162
3.57K/F_4
PC109
0.1u/50V_6
PR160
*0/short_4
PC107
330U/2V_7343
PC32
*330u/2V_7343
assume
ESR=9m-ohm
41
PQ3
AON7702
PC92
+VCC_CORE
TDC : 3.18A
PEAK : 4.23A
OCP : 10.4A
Width : 160mil
0.1u/25V_4
PR171
1K_6_NTC(B=3650)
8165_ISEN1P
8165_IBIAS
8
8165_GFXPS2
PC101
*1000P/50V_6
IBIAS
RGND
19
PR152
*0/short_4
GFXPS2
8165_RGND
TEMPMAX
for droop fine tune

PR151
100/F_4
PR159
1K/F_4
4
8165_COMP
[7] CPUVSS_SENSE
PR165
1.15K/F_4
Rsense=12.63m-ohm
PR38
88.7K/F_4
[7] CPUVCC_SENSE
3
2
1
PC15
*0.1u/50V_6
PU8
RT8165BGQW
TONSET
PC14
330u/2V_7343
VCCGFX
TDC : 2.58A
PEAK : 3.44A
OCP : 9A
Width : 120mil
PR167
1K_6_NTC(B=3650)
8165_ISENAN
VR_READY
ISEN1N
PR31
10K/F_4
29
PC95
0.1u/25V_4
8165_ISENAP
PC94
*0.1u/10V_4
+VCC_CORE
PR30
2.55K/F_4
30
VDIO
*90.9/F_4
*0/short_4
PR149
110/F_4
PR1
PR150
assume
ESR=9m-ohm
PR161
*0/short_4
PC16
0.1u/50V_6
3
2
1
[6] VR_SVID_DATA
8165_VDIO
PR163
6.98K/F_4
PC108
*1000P/50V_6
3
2
1
[6] VR_SVID_CLK
54.9/F_4
PR15
PR175
*2.2/F_6
4
PQ4
AON7702
8165_VCLK
35
PC96
0.22U/25V_6
Place close to VR
PR19
VCCGFX
L=2.2uH, typ.DCR=18m-ohm
PR153
*0/short_4
LGATEA
PC103
4.7u/25V_8
PL8
2.2uH_7X7X3
for compensation fine

tune
+1.05V
PC102
0.1u/50V_6
PR166
2.2_6
8165_COMPA 28
[7] GTVCC_SENSE
PR158
100/F_4
PC27
2200P/50V_4
4
PQ2
AON7410
PC7
100p/50V_4
3
2
1
8165_FBA
PR32
100/F_4
PVCC
VCC
37
VIN
PC23
0.1u/25V_6
8165_ISEN1N
PC93
*0.1u/10V_4
Rsense=4.24m-ohm
PR164
1K/F_4
PR154
1K/F_4
Load-line = -5.9mv/A
for Cedar trial-M
8165_VCC
8165_VCC
Temp max=100C
8165_ICCMAX
VICCMAX=164mV, /19.2mV=8.563
8165_ICCMAXA
VICCMAXA=68mV, /19.2mV=3.532
8165_OCSETA
OCSETA=2.619V
8165_OCSET
OCSET=2.56V
8165_SETINIA
VBOOTA=1V
8165_SETINI
*0_4
VBOOT=1V
8165_GFXPS2
GFX Not force PS2
PC13
*0.1u/50V_6
PR11
53.6K/F_4
for noise filtering,

place close to
RT8165B
33K/F_4
PR145
2.21K/F_4
16.9K/F_4
5.1K/F_4
PR136
PR21
*0/short_8
PR33
*0/short_8
PR4
PR5
PC1
1u/10V_4
PR6
PR7
1K/F_4
16.9K/F_4
10K/F_4
8165_TSEN
PR9
1K/F_4
PR135
PR147
PC2
1u/10V_4
11.8K/F_4
PR10
8165_TSENA
PR17
750/F_4
21K/F_4
PR140
10K/F_4
PR16
750/F_4
PR141
10K/F_4
place close to
Vcore inductor
182K/F_4
10K/F_4
place close to
GFX inductor
274K/F_4
PR139
PR8
PR20
10K/F_4
PR138
PR2
PR18
10K/F_4
PR172
10K_6_NTC
PR3
PR168
10K_6_NTC
8165_TEMPMAX
51K/F_4
10K/F_4
PR137
PROJECT : ZE7
Size
Rev
C3C
CPU CORE (RT8165B)

Date:
Document Number
Sheet

1
31
of
42
32
[PWM]
PC67
10U/10V_8
20mil
0.375A
PR111
*0/short_6
PC73
0.1U/50V_6
8207A_VBST
+0.75V_DDR_VTT
D
VIN
8207A_DH
PC59
10U/10V_8
VTTSNS
19
DRVL
LL
DRVH
20
21
22
VBST
23
GND
MODE
VTTREF
COMP
PC66
4.7U/25V_8
4
PQ25
AON7410
PGND
18
CS_GND
17
PU5
RT8207L
PC65
4.7U/25V_8
CS
16
V5IN
15
V5FILT
14
PGOOD
13
PC63
2200P/50V_6
PL5
2.2uH
+1.5VSUS
+1.5VSUS
1.5 Volt +/- 5%
TDC : 4.32A
PEAK : 5.76A
OCP : 10A
Width : 200mil
VTTGND
VLDOIN
24
3
+1.5VSUS
VTT
GND
25
8207A_DL
10mil
0.188A
PR119
13K/F_4
PR115
*4.7/J_6
+5V_S5
PR121
*100K/F_4
PR198
0/J_4
*0/short_4
S3_1.8V
PR113
PR100
*0/J_4
PC68
*33P/50V_6
PR103
10K/F_4
3
2
1
PQ28
AON7702
PC76
1U/10V_4
PC72
*680p/50V_6
PC61
330U/2V_7343
PC64
10U/10V_8
NC
S5_1.8V
PR118
PR96
*0/short_6
PC77
1U/10V_4
PR120
620K/F_4
PR97
*0/short_6
PR122
5.1/F_6
+3V_S5 <20110728> Change DDRAM_PWROK PU from +3V_S5 to +1.5VSUS (no connect at EC side )
12
S5
11
S3
VDDQSET
9
10
VDDQSNS
PC56
0.033U/50V_6
+5V_S5
NC
+SMDDR_VREF
8207A_LX
3
2
1
PC60
10U/10V_8
*0/short_4
VIN
DDRAM_PWROK
(For RT8207A
SUSON
[16,27,34]
MAINON
[16,27,33,34]
[8,27]
400KHZ) close to PC2016
+5V_S5
Vout = (PR150/PR149) X 0.75 + 0.75

AON7702 Rdson=11~14mOhm
L(ripple current)
=(19-1.5)*1.5/(2.2u*400k*19)
~1.57A
Vtrip= (10-1.57/2)*14mohm=0.12901V
RILIM=Vtrip/10uA~12.901Kohm
8207A_SET
S5_1.8V
S3_1.8V
PR117
*0/J_4
+1.5VSUS
PR110
10K/F_4
MAIND
MAIND
[30,34]
PQ11
AO3404
+1.5V
TDC : 1.24A
PEAK : 1.65A
Width : 60mil
S3
S5
+1.5VSUS
REF
VTT
S0
ON
ON
ON
S3
S4/S5
ON
ON
OFF
OFF
OFF
OFF
A

PROJECT : ZE7
Size
Rev
C3C
DDR 1.5V(TPS51116)
Date:
Document Number
Sheet
1
32
of
42
33
[PWM]
VIN
+5V_S5
PR89
10/J_6
PC121
2.2n/50V_4
PD4
RB500V-40
PR114
2.2/F_6
+3V
PR90
10K/J_4
PC57
0.1U/50V_6
HWPG_1.05V
EN/DEM
16
TON
VOUT
VDD
FB
PGOOD
GND
PR104
*0/short_6
PC69
0.1U/50V_6
13
UGATE
12
UGATE-1.05V
PHASE
11
PHASE-1.05V
OC
PR108
3K/F_4
10
VDDP
LGATE
PGND
TPAD
17
5
4
BOOT
NC
14
NC
PQ45
AON7410
PC70
1U/10V_4
LGATE-1.05V
PL10
2.2uH_7X7X3
PR192
*4.7/J_6
3
2
1
[16,31,34]
G5602
15
PU4
MAINON
PC117
.1U/10V_4
[16,27,32,34]
PR99
33K/J_4
+1.05V
PC74
4.7U/10V_6
3
2
1
PR92
1M/F_4
PC122
4.7U/25V_8
PQ51
AON7702
PC119
*680p/50V_6
PC114
330U/2.5V
PC54
1U/10V_4
PC116
*10U/10V_8
PC55
*1000P/50V_6
R1
PR88
4.02K/F_4
PC53
*33P/50V_6
+1.05V
1.05 Volt +/- 5%
TDC : 1.36A
PEAK : 1.82A
OCP : 5A
Width : 60mil
VOUT=(1+R1/R2)*0.75
1.05V_FB
R2
PR93
10K/F_4
PR94
*0/short_6
TON=3.85p*RTON*Vout/(Vin-0.5)
TON=3.85p*1M*1/(Vin-0.5)
AON7702 Rdson=11~14mOhm
L(ripple current)
=(19-1.05)*1.05/(2.2u*272k*19)
~1.658A
Frequency=1/(0.0036767)=272K
Rth=14m*(5-0.829)/20uA
RILIM=2.92Kohm
Frequency=Vout/(Vin*TON)
A
PR95
*0/short_6

PROJECT : ZE7
Size
Document Number
Rev
C3C
+1.05V(UP6111AQDD)
Date:
5
Sheet
1
33
of
42
VIN
+1.5VSUS
PR194
1M/J_4
+3VSUS
PR195
*22/J_8
34
+15V
PR197
22/J_8
PR196
1M/J_4
SUSD
[30]
SUSD
SUS_ON_G
3
PQ46
DTC144EU
PQ47
*DMN601K-7
1
VIN
+3V
PR91
1M/J_4
+5V
PR101
22/J_8
PQ48
2N7002K
+1.5V
+1.05V
PR98
22/J_8
PC120
*2200P/50V_4
PQ49
2N7002K
SUSON
[16,27,32]
PR193
1M/J_4
PR80
*22/J_8
+15V
PR79
22/J_8
PR77
1M/J_4
[30,32]
MAIND
MAIND
3
MAINON_ON_G
1
MAINON_ON_G
MAINON_ON_G
PQ27
2N7002K
PQ20
*DMN601K-7
PQ18
2N7002K
PQ19
2N7002K
PC41
*2200P/50V_4
2
PQ26
2N7002K
PQ23
DTC144EU
MAINON
[16,27,32,33]
PR87
1M/J_4
[27]
+1.8V
1.8Volt +/- 5%
TDC : 0.113A
PEAK : 0.151A
Width : 20mil
PC81
10U/10V_8
PQ29
AO4468
PC82
10U/10V_8
PR102
100K_4
8
7
6
5
PU7
G9334 ADJ
5
PR129
261/F_4
PC79
10U/10V_8
Rg
3
DRV
PGD
EN
FB
HWPG_1.8V
[27]
1
+5V
6
PC110
*0.1U/10V_4
PR181
0/J_4
PR180
*0/J_4
+3.3V_PRIME_ON
PC71
.1U/10V_4
PR107
47/F_4
<20100902> reserve for H/W debug
Rh
VCC
PR130
100/F_4
+3V
1
2
3
PC80
.1U/10V_4
+1.8V
+3VSUS
GND
Reserve For VCCGFX
PC62
33N/25V_4
Vout1 = (1+Rg/Rh)*0.5
PR105
*30K/F_4
<20101217> Reserve 30K for Duncan suggestion
VCCGFX
For +3V_PRIME
VIN
PR178
*22/J_8
+3.3V_PRIME
PR62
1M/J_4
+1.8V
PR179
22/J_8
+3V
+15V
PR61
22/J_8
PR64
1M/J_4
PR176
*1M/J_4
VIN
3
*0/short_4
PQ7
DTC144EU
1
2
PR66
*0/short_4
PR63
*100K_4
PC35
*1U/10V_4
PQ8
2N7002K
PQ6
2N7002K
TDC : 0.17A
PEAK : 0.22A
Width : 10mil
PQ9
2N7002K
+3.3V_PRIME
PC36
*2.2n/50V_4
MAINON_ON_G
PQ10
AO3404
PQ44
2N7002K
PR60
1M/J_4
PR65
+3.3V_PRIME_ON
[16,27,31]
PQ43
*DMN601K-7
HWPG_1.05V
[16,31,33]
PR177
*1M/J_4
2
PQ42
*DTC144EU
PROJECT : ZE7
Size
Rev
C3C
Discharge/1.8V
Date:
Document Number
Sheet

1
34
of
42
35
Thermal Protection (DCD)

VIN
PD5
1SS355
PQ30
AO3409
2
TSNS_ON
PR127
1M/F_4
S5_ON
<20110421>
Change PR112 from CS21742FB00 to CS22212FB11,
for change M/B from 67 to 60 and bottom fin to
88 thermal protection. (Follow ZE6)
VL
VL
SYS_SHDN# [6,30]
PR112
2.21K/F_4
PR106
200K/F_4
PC75
0.1U/25V_4
PR116
10K/J(NTC) _6
2.469V
[16,27,30] S5_ON
PR128
200K/F_4
2.52V
Thermal protection temperature = 60C
PU6A
AS393MTR-E1
PQ36
2N7002K
PC78
0.1U/25V_4
PQ37
DTC144EU
2
PR109
200K/F_4
PQ31
2N7002K
7
PU6B
AS393MTR-E1

PROJECT : ZE7
Size
Document Number
Rev
C3C
Thermal protect
Date:
1
Sheet
5
35
of
42
(100MHz)
SRC_P/N
WLAN(Mini Card 1)
36
(33MHz)
PCI_33
Debug Card
Page 25
CPU_ITPP/N
(100MHz)
SATAP/N
SATACLKP/N
(100MHz)
To CPU
Tigerpoint
SRC_P/N
DMICLK100P/N
(24MHz)
Audio
ALC271X
Page 20
BIT_CLK
(48MHz)
CLK48
USB_48
LVDS_CLKP/N
(14.318MHz)
REF
DDR_CLK0P/N
CLK14
PCICLK
DDR_CLK1P/N
(32.768KHz)
(400/533MHz)
DDR3 SO-DIMM0
Page 4
SUSCLK
Cedarview-M
CLOCK GEN CK505
SLG8LV631V
DDR_CLK2P/N
Page 10~15
(400/533MHz)
DDR_CLK3P/N
(100/133MHz)
HPLLREFCLK_P/N
CPU_0P/N
Y4(32.768K KHz)
(100/133MHz)
DDR3REF_P/N
CPU_1P/N
(100MHz)
DPL_REFSSCLKIN_P/N
LCD_CLKP/N
(100MHz)
DMICLKIN_P/N
SRC_P/N
(96MHz)
DPLREFCLK_P/N
DOT_96P/N
(Max. 112MHz)
LVDS_CLKP/N
10.1" LED Panel

Page 18
(33MHz)
PCI_33
Page 5~9
HDMI
Page 17
SPI Flash
Page 27
DDI0_TXP/N3
AZIL_BCLK
(33MHz)
SPICLK
Page 27
Page 2
(Max. 340MHz)
EC
WPCE791L
(100MHz)
SRC_P/N
Card Reader
RTS5209-GR
Page 26
Y3(27 MHz)
(100MHz)
SRC_P/N
(24MHz)
LAN
RTL8105TA-VC-CG
Y5(25 MHz)
Page 22
From TPT
(100MHz)
WLAN(Mini Card 2)
SRC_P/N
Page 25
A
Y2(14.318 MHz)

PROJECT : ZE7
Size
Document Number
Rev
C3C
Clock Distribution Diagram

Date:
5
Sheet
1
36
of
42
37
+VCC_CORE(0.75V-1.18V,4.234A)
<HWPG_1.05V>
CPU core
(RT8165)
PU8
VIN
VCCGFX(0.76V~1.05V,3.438A)
<HWPG_1.05V>
+1.05V
(G5602)
PU4
BOM Structure
Function
3G
+1.05V(1.8164A)
<MAINON+RC>
BT
PU3
+5V_S5(10mA)
<S5D>
AO3404
PQ12
+5V(2.477A)
<MAIND>
stuff 3G@
w/o 3G module
unstuff 3G@
w/ BT module
stuff BT@
w/o BT module
unstuff BT@
LVDS@
w/ LVDS (default)
stuff LVDS@
L38: CV+1003JN01 (0.1UH)
C334: CH5102K9B06 (1UF)
EDP@
w/ EDP
stuff EDP@
L38: CS00003J951 (0ohm)
C334:CS00002JB38 (0ohm)
DS3@
w/ deep standby (default)
stuff DS3@
NS3@
w/ normal standby
stuff NS3@
1.5VPLL@
w/ 1.5VPLL (default)
stuff 1.5VPLL@
BT@
+3V_S5(197mA)
<S5D>
AO3404
PQ24
+3VSUS(1.1A)
<SUSD>
PLL Power
1.05VPLL@ w/ 1.05VPLL
ADAPTER
CHARGER
Description
w/ 3G module
LVDS/EDP
Deep Standby
AO3404
PQ15
+3VSUS
(1.182A)
AO3404
PQ35
+3VPCU(55mA)
<AC/DC Insert>
SYSTEM
5V/3V
(RT8223)
+3VPCU
(3.034A)
VIN
+5VPCU
(6.517A)
+5VPCU(4.03A)
<AC/DC Insert>
3G@
VIN
(5.48A)
G9334
AO4468
PU7/PQ29
stuff 1.05VPLL@
+1.8V(151mA)
<+3.3V_PRIME_ON>
(ISL88731)
PU9001
AO3404
PQ22
+3V
(1.6A)
BATTERY
+3V(1.38A)
<MAIND>
B
AO3404
PQ10
+3.3V_PRIME(220mA)
<+3.3V_PRIME_ON>
DDR PWR
1.5V
(RT8207)
+1.5VSUS
(5.008A)
VIN
+1.5VSUS(3.362A)
<SUSON>
AO3404
PQ11
+1.5V(1.646A)
<MAIND>
PU5
+SMDDR_VREF(0.25A)
<SUSON>
A
+0.75V_DDR_VTT(0.5A)
<MAINON>
PROJECT : ZE7
Size
Document Number
Date:
Rev
C3C
Power Tree
5
Sheet
37
of
42
JE01_CT(Cedar Trail) Power On Sequence
From AC,BATT
38
VIN
+5VPCU +3VPCU VCCRTC
From PWM to EC
HWPG_SYS(PCU)
>=18ms (VCCRTC to RTCRST#)(t200)
From Button to EC
From EC to PWM
From EC to SB
From EC to SB
RTCRST#
NBSWON#
S5_ON
+5V_S5
>=0ms (VCCRTC to S5 well)(t203)

+5V_S5 power up before +3V_S5, or
after +3V_S5 within 0.7V (t201)
+3V_S5
EC_RSMRST#
+3V_S5 power down before +5V_S5,

or after +5V_S5 within 0.7V
>=5ms (S5 well to EC_RSMRST#)(t205)

100ms (EC define)
DNBSWON#(PWRBTN#)
1~2 RTCCLK (SUSC# to SUSB#)(t234) (1RTC: 28.992 s to 32.044 s)
From SB to EC
From EC to PWM
SUSB#(SLP_S3#),SUSC#(SLP_S4#)
SUSON
+3VSUS +SMDDR_VREF +1.5VSUS(to DDR3_DRAM_PWROK)
From PWM to EC
HWPG_1.5V (SUS)
From EC to PWM
MAINON
+5V power up before +3V, or

after +3V within 0.7V (t209)
+3V power down before +5V,

or after +5V within 0.7V
+5V +3V +1.5V +0.75V_DDR_VTT
V_CPU_IO power down before +1.5V,

or after +1.5V within 0.7V
CPU: +1.5V power up before +1.05V ; PCH: +1.5V power up
before V_CPU_IO, or after V_CPU_IO within 0.7V (t211)
+1.05V (also for V_CPU_IO of PCH)

From PWM to CPU VR HWPG_1.05V
+VCC_CORE VCCGFX
From PWM to EC IMVP_PWRGD/HWPG_VCCGFX
From EC
+3.3V_PRIME_ON
CPU:+3V_PRIME and +1.8V needs to be <700mV
+3V_PRIME +1.8V
From PWM to EC
B
HWPG_1.8V
From PWM HWPG(to EC,VRMPWRGD,CK505)

From EC to CPU,SB ECPWROK(AND with HWPG to PWROK,to DDR3_VCCA_PWROK)
100ms(EC define)
B
BCLK
From CLK Gen
99ms(S0 well of TPT to TPT_PWROK)(t214)
From EC to SB
From SB to CPU
TPT_PWROK
H_PWRGD
From SB to All
PLTRST#
NOTE:PWROK assertion indicates that PCICLK has been stable for at least 1 ms.
*Note: EC will sampling SUSB# & SUSC# every 5ms.
EC SMBUS Table
ICH SMBUS Table

A
(SMB_DATA)/(SMB_CLK) (+3V_S5)
Power Plane
MOS CKT (Level shift)
CLK GEN
RAM
*Mini Card (WLAN)
*XDP
+3V
+3V
+3V
+3V
Stuff
Stuff
Stuff
Stuff
Battery
EC791 SDA1 / SCL1 (+3VPCU)
EC791 SDA2 / SCL2

EC791 SDA3 / SCL3
Power Plane
MOS CKT (Level shift)
*=Reserve
CPU Thermal Sensor GFX Thermal Sensor
+3VPCU
PROJECT : ZE7
5
Size
Document Number
Rev
C3C
Power Sequence
Date:
2

1
Sheet
38
of
42
SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.
SLP_S4#(SUSC#):
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components
when system transitions to S4 or S5 state.
1
AC Adapter
VIN
BATT Charger
PU2
39
NBSWON#
5
+5VPCU
S5_ON
(S5D)
PQ33
+5V_S5
MOS
2
+3VPCU
+3V_S5
MOS
+3VPCU
PQ12
Always System power
Regulator
Battery
+5VPCU
EC_RSMRST#
PU2
10
RSMRST#
8
DNBSWON#
3
SUSON(SUSD)
13
SUSC#
PWRBTN#
9
SLP_S4#
MAINON(MAIND)
EC
SUSB#
14
MAIND
+3VPCU/+5VPCU
+3V
MOS
+5V
SLP_S3#
22
PCH
23
ECPWROK
TPT_PWROK
PWRGD
+1.5VSUS
MAIND
+1.5V
MOS
100ms
MAINON
+RC
VIN
+1.05V
VR
15
HWPG_1.05V
VRM_PWRGOOD
16
CPU_PG
+VCC_CORE
VIN
Regulator
PU8
PLTRST#
17
VCCGFX
HWPG_SYS
+3.3V_PRIME_ON
IMVP_PWRGD/ HWPG_VCCGFX
18
(From EC)
21
19a
+3V
MOS
PQ9
+3V_PRIME
HWPG
19b
24
25
H_PWRGD
PLTRST_N
B
20
HWPG_1.8V
+3VSUS
MOS
PU7
CK505
EN
MAINON_ON_G
HWPG_1.5V
+1.8V
NMOS
G
S
D
GND
NMOS MAINON_ON_G
12
For Power Down Sequence
PWRGD
RESET_L
For Power Down Sequence

DDR3_VCCA_PWROK
GND
+0.75V_DDR_VTT
MAINON
CPU
VIN
SUSON
Regulator
PU5
SUSD
+3VPCU
MOS
PQ22
+SMDDR_VREF
+1.5VSUS
DDR3_DRAM_PWROK
11
+3VSUS
PROJECT : ZE7
Size
Rev
C3C
power sequence block diagram

Date:
Document Number
W ednesday, August 31, 2011

1
Sheet
39
of
42
MODEL
Model
REV
D1A
CHANGE LIST
20101124: <Page 27> Del net USB_EN#_1 / USB_EN#_2 / USBOC#R2
ZE7
FROM
To
C1A
D1A
D1A
E1A
/ USBOC#R1 / 5VUSB_3
<Page 27> Add USB_EN# / USBOC#R
ZE7 MB
<Page 10> Del USBOC0#/ USBOC3#/ USBOC1# ; Add USBOC#R_1/ USBOC#L_1

<Page 26> Add net SD_D2_R
20101125: <Page 26> Del net MS_CLK_R / PCIE_CLK_REQ1#
<Page 26> Delete R628; Reserve C510 for EMI (follow vendor CRB)
20101126: <Page 5> Add net name TX1_HDMI+ / TX1_HDMI- / TX2_HDMI+ / TX2_HDMI- / TX3_HDMI+ / TX3_HDMI<Page 5> Add net name TXLOUT0_R+_EDPTX1+ / TXLOUT0_R-_EDPTX1- / TXLCLKOUT+_R_EDPTX2+ / TXLCLKOUT-_R_EDPTX2<Page 5> Add net name LCD_CLK_R_EDPTX3+ / LCD_DATA_R_EDPTX320101129: <Page 27> Change U14 from AKE38FP0N01 to AKE38ZP0N02 for EC request
<Page 20> Modify Headphone Jack schematic to follow ZE6
<Page 24> Add LED5 for power indicator
20101130: <Page 16> Delete SIO board connector
<Page 5> Stuff C432 to follow checklist0.7
<Page 7> Stuff C422; Unstuff C210/C111; Change C408 to 22U/6.3V_8/ C409 to 1U/6.3V_4 to follow checklist0.7
20101206: <Page 26> Change card reader connector P/N footprint due to ME request
<Page 29> Update battery connector to follow ZE6
20101209: <Page 17> Change HDMI connector to DFHS19FR015 by PDC suggestion
20101213: <Page 31> Delete PC120 at +VCC_CORE (Power team Duncan will use A3 M/B to verify again)
<Page 18> Reserve L21/ L22 /L40 /L41/ R253/ R255/ R258/ R259/ R262/ R263/ R265/ R269 for LVDS signals (RF suggestion)
20101216: <Page31> Reserve PC53/PC120 for EMI suggestion
<Page12> Reserve R356/ C290 for EMI suggestion
20101217: <Page20> Change CN10(internal speaker CONN) from DFHD04MR981 to DFHD04MRA75 (follow ZE6)
<Page28> Add NUT part number (follow ZE6)
20101220: <Page5> Swap DDI0_TX2_DP /DDI0_TX0_DP ; Swap DDI0_TX2_DN /DDI0_TX0_DN to correct HDMI channel
<Page22> Change RJ45 connector to DFTJ12FR221 to follow ZE6
20101221: <Page13> Change RTC battery from pin type to holder(DFHS02FS561)

20101228: <Page29-35> Update power budget description
<Page1-40> Update test pad size to TP2650
<Page29> Update battery connector P/N to DFAD08MR013 (follow ZE6)
20101229: <Page24> Unstuff HDD LED related circuit for cost down requirement
<Page31> Change PR71 to 5.72K_F cause VCCGFX power-budget has changed to 2.58A (Power budget V0.3)
<Page20> Modify speaker connector pin definition to follow PDC design
20101231: <Page20> Modify earphone and mic connector pin definition
20110103: <Page22> Modify CLKREQ_LAN#_R to
CLKREQ_LAN#_R1 because netname duplicate
20110104: <Page13> Change EC_SMI# to GPIO10; Delete net PCH_GPIO10; Add net PCH_GPIO8
<Page20> Modify speaker connector pin definition back to original design
<Page19> Modify TP connector pin define to correct TP doesn't work issue
--Gerber out for A4-test--
E1A
20110105: <Page 25> Add net WLAN_LED1#

20110106: <Page 7> Change L8/ L12/ L13 from CV01001MN16 to CV01001MN08 for shortage issue
20110107: <Page 5> Add NCT7717U thermal sensor circuit (Reserve)
20110110: <Page 2> Add R515/ R516 for USB_48M CFG input hardware strapping to allocate PLL assignment. (Reserve)
<Page 10> Exchange USB port1 with port3 for S3 auto resume issue
20110111: <Page 21> Add USBP3-_L1/ USBP3+_L1/ USBP3-_L2/ USBP3+_L2/ USBP3-_L/ USBP3+_L/ CHARGE_IC_ON for USB charger reserve
<Page 20> Add net AMIC2_INT; Delete net LIN2_INT_R/ LIN2_INT_L for A-MIC (follow ZE6)
20110113: <Page 27> Add DNBSWON#_1 and D41 to solve +3V_S5 current leakage
20110117: <Page 20> Reverse CN4 connector routing for A-MIC cable design (follow ZE6)
20110119: <Page 2> Change R515 from 10K ohm to 20K ohm for vendor's suggestion. (Reserve)
20110124: <Page 25> Change net name from CLKREQ_MMC# to CLKREQ_3G#
<Page 25> Change R257 from 10K to 100K to solve leakage (follow ZE6)
20110127: <Page 18> Delete netname VCC_DDC
20110214: <Page 19> Change CP1~CP6 footprint from 8p4r-0402-smt to 8P4R for SMT open issue
20110221: <Page 2> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes will change to 25MHz after flash BIOS and restart in first time issue.
<Page 2> Exchange PCLK_DEBUG and LCLK_EC for PCICLK issue.
20110224: <Page 18> Change C300 from 2.2U to 10U to solve LCDVCC fall time issue.
<Page 18> Add net +5V_LCD for IVO panel using
<Page 20> Reserve DMIC signals to co-layout with DMIC connector, reserve R526/ R527 add net AMICINT_DMICDAT / AMICGND_DMICCLK
<Page 10> Unstuff C111/ C123/ C125/ C133/ R78/ R79/ R84/ R86 to change DMI from x4 to x2
20110301: <Page 07> Change C326 from 10U to 47U; Add C386 47U for CRT flickr issue.
<Page 18> Change L15/ L16/ L17 from 47ohm to 22ohm; Remove C109/ C110/ C114 for CRT issue
<Page 18> Change C79/ C80/ C81 from 22pF to 4.7pF for CRT issue.
20110302: <Page 35> Reserve PR129 for no use
20110303: <Page 5> Reserve DDI1 PU resistors R529 to follow CRB(eDP); Add net DDI1_DDC_SCL/ DDI1_DDC_SDA
<Page 20> Reserve L42/ L43/ L44/ L45 for ESD solution
20110304: <Page 20> Change R525 from 0603 short pad to 0603 0ohm
<Page 25> Unstuff PD8/ PR106/ PR133 for no use
<Page 5> Stuff R512/ R513/ U26/ C381/ C382/ R514/ R509/ C384/ C383 for thermal sensor
<Page 27> Stuff R175/ R160 for thermal sensor
<Page 24> Unstuff C320 for cost down
20110307: <Page 18> Reserve R530 for eDP function hardware short term solution
20110308: <Page 23> Reserve stitching cap for RF suggestion
<Page 24> Unstuff C320 for cost down
<Page 35> Delete PR106/ PR113/ PD8/ PR129 (thermal protection) for unused circuit (follow ZYG)
<Page 28> Change Hole16/ Hole17 footprint to h-tc177bc295d120p2
<Page 5> Delete R510/ R511 for thermal sensor SMBUS PU (PU at EC side)
<Page 5> Unstuff C384/ C383; Change C382 from 10U_8 to 4.7U_6
<Page 6> Reserve R531 for thermal sensor test

PROJECT MODEL :
DOC NO.
ZE7
APPROVED BY:
PART NUMBER:
5
DATE:
PROJECT : ZE7
http://hobi-elektronika.netChange List1
REVISON:
DRAWING BY:
3
Size
Document Number
Date:
Rev
C3C
Sheet
1
40
of
42
MODEL
Model
REV
E1A
CHANGE LIST
ZE7
FROM
To
C1A
D1A
<Page 27> Change thermal sensor SMBUS PU from +3V_S5 to +3V
D1A
E1A
<Page 28> Change Hole18/ Hole19/ Hole20 footprint to h-c197d63p2
E1A
<Page 18> Add R510 for eDP function verifying
F1A
G1A
G1A
A3A
20110308: <Page 13> Unstuff R451 for using thermal sensor (Need stuff when no use thermal sensor)
ZE7 MB
20110309: <Page 28> Add hole23
F1A
<Page 20> Change R525 from 0603 short pad to 0402 0ohm
--Gerber out for A5-test--
F1A
20110309: <Page 20> Change R525 from 0603 short pad to 0402 0ohm
20110314: <Page 27> Change U7(BIOS) to AKE38FP0Z01 (follow ZE6)
20110315: <Page 20> Change L27 from CS00004JA40 to CX121T30001
<Page 20> Delete R208/ R261/ R433/ R475 for CS00003J951
20110318: <Page 29> Change DC jack to DFPJ03MR043 (follow ZE6)
20110328: <Page 28> Change Thermal nut to MBZH5002012 (follow ZE6)
20110330: <Page 2> Change R236 PU connect from PM_STPCPU# to PM_STPCPU#_R
20110406: <Page 24> Change R329 from CS11202JB21(120ohm) to CS05102JB35(51ohm) PWR light
<Page 24> ChangeR326/ R323/ R321 from CS12702JB14(270ohm) to CS12002FB25(200ohm) Blue light
<Page 24> ChangeR327/ R324/ R322 from CS14702JB28(470ohm) to CS13302FB11(330ohm) Amber light
<Page 22> Unstuff R341/ R330 for W/O LED RJ45 CONN (follow ZE6)
<Page 27> Del T44 for no use of CIR uart function, will place T34 for ICT programming
20110407: <Page 28> Add GND PAD1 for LED ESD using
<Page 16> Unstuff R100/ R142/ R143/ R132/ R96/ R97 for height limit
20110412: Change Q1/ Q27/ Q34/ Q35/ Q39/ Q42/ Q43 from BA0390400H0 to BA039040020 for EOL issue
Change PL1/ PL2/ PL6 from CX0R800R014 to CX12T800000 for EOL issue (EMI Sam provide)
<Page 18> Change MR1 from AL003661003 to AL002618001 for EOL issue (ZE6 2nd source)
G1A
20110413: <Page 30> Change PU3 from AL008206002 to AL008206000

<Page 23> Add C388/ C389 stitching caps for monitor flickr issue
<Page 11> Add net CPUSLP# / CPUSLP#_R and add R511/ R532 to reserve CPUSLP function
20110414: <Page 22> Change D35 from CY640P31Z08 to CY003100Z06 for cost down
<Page 13> Stuff R451 to reserve thermal sensor function
<Page 9> Unstuff C381/ C382/ R509/ R512/ R513/ R514/ U26 to reserve thermal sensor function
<Page 27> Unstuff R175/ R160 to reserve thermal sensor function
<Page4> Modify DDR DQ/ DQS/ DM signals to no swap type
20110418: <Page29~35> Change Power solution for ZE7 project

<Page 23> Delete C389 for CRT DAC stitching cap
<Page 30> Change JP1007 footprint to RC3720-SMT
20110420: <Page 11> Delete net CPUSLP# / CPUSLP#_R and delete R511/ R532 to remove CPUSLP function (nettop platforms only)
<Page 20> Change R178/ R477 from 75ohm to 47ohm for earphone gain fine tune (follow ZE6)
20110422: <Page 18> Change MR1 from AL002618001 to AL003661006(PT3661G-BB) for Lid switch issue
<Page 30> Delete PC1032 for power request
<Page 31> Delete PC1019; Add PR1104; Change PQ1001 (Dual MOS) to PQ1001 & PQ1008 (3X3 QFN)
<Page 9> Un-stuff R149/ R151/ R478/ R479 to solve leakage issue
<Page 18> Change C138 from 0.1U_6 to 4.7U_8 to solve hall sensor issue
20110425: <Page 25> Change U7 from AKE38FP0Z01 to AKE38FP0N01 for ICT MAC ID issue
<Page 18> Change C138/ C318 from 4.7u_8 to 4.7u_6 (CH5471K9E07)
20110426: <Page 13> Add C389 0.1U_4 for TPT_PWROK glitch issue
<Page 2> Change Y2 from BG614318242 to BG614318F33 for new part
20110427: <Page 26> Change C267/ C268 from 22P/50V_4 to 10P/50V_4 for EMI request
<Page 26> Add R511 and net MS_CLK_R for EMI request
<Page 26> Change R271/ R285/ R290/ R299/ R305/ R313 from 0ohm to 33ohm for EMI request
20110428: <Page 26> Del R511 and net MS_CLK_R, change R303 from 0ohm to 33ohm for EMI request
<Page 13> Reserve C390 30P_4 for EMI request
<Page 20> Add C391 1n_4 for amic noise depressing (Realtek Vic suggest)
<Page 31> Add PC1019/PC1032 2200p_4 for EMI request
<Page 30> Change PC1043/ PC1046 from 330uF to 220uF; Change PL4 from 3.3uH to 2.2uH
<Page 30> Change PR1098 from 4.7K ohm to 48.7K ohm
20110429: <Page 13> Stuff R85,R449,R455 for ZE7 A2 stage (Board ID PD)
<Page 20> Change R178/ R477 from 47ohm to 56ohm to meet acer Full Scale Output Voltage (FSOV) spec
<Page 13> Reserve R511 0ohm and RTCRST#_EC for RTC reset workaround solution
<Page 19> Stuff CP1~CP6 for EMI Sam request
A3A
20110506: Rename
<Page 17> Unstuff R138 to follow CRB
20110510: <Page 18> Change MR1 from AL003661006(PT3661G-BB) to AL009132001 (CMOS type)
<Page 18> Change C138 from 4.7U_6 to 1U_6; Unstuff R91 because MR1 is CMOS type
<Page 22> Change C4/C7 from 27P to 33P(CH03306JB04) by vendor fine tune result
20110516: <Page 11> Add R532/ R533 and net CPUSLP#_R / CPUSLP# (enable C6-state)
<Page 17> Add R534/ R535 PU 2K for HDMI I2C to follow CRB
<Page 24> Del SW4 for no use
<Page 5> Change C334/ C335 from 18P_6 to 33P_4 for crystal vendor's report
<Page 18> Add R536/ D44 for MR1 EOS protection
<Page 10> Modify USBOC pin
<Page 13> Change CN5 to DFHS02FS032 for SMT issue
<Page 13> Change R93/ R454/ R472/ R468 from CS03302JB29 to CS09092FB15 (RES CHIP 90.9 1/16W +-1%(0402)) to follow CRBv1.5
Remove Deeper Standby/ XDP/ DMIC/ USB charger function
20110520: <Page 8> Change R99 from 12.1K to 121ohm to follow CRBv1.5
<Page 8> Change R98 from 10K to 100ohm to follow CRBv1.5
20110525: <Page 30> Modify JP9 footprint to RC3720-SMT for SMT open issue
20110530: <Page 24> Modify LED4 from +3V to +5V Due to there is the internal series resister in 3G/WLAN module, cause the
forward voltage of LED4 is too small
20110531: <Page 29~35> Update power portion
20110601: <Page 26> Modify CN20 (Card
<Page 23> Change C140 from
<Page 29> Change PU9001 to
<Page 31> Add Power Jumper
reader CONN) footprint to 7in1-cm7r-052-h-d-44p-smt by SMT ME Peter request

0402 to 0603; Del C141
PU2; Change PU2 footprint from QFN28-5X5-5-33P to QFN28-5X5-5-33P-SMT
for power consumption measurement

PROJECT MODEL :
DOC NO.
ZE7
APPROVED BY:
PART NUMBER:
5
DATE:
PROJECT : ZE7
REVISON:
DRAWING BY:
3
Size
Document Number
Date:
Rev
C3C
Sheet
1
41
of
42
MODEL
Model
CHANGE LIST
REV
ZE7 MB
D
ZE7
FROM
To
20110602: <Page 7> Del R490 and short for VCCCKDDR_VSM
C1A
D1A
20110603: <Page 23> Del C215 for no use(DMIC stitching cap for RF)
D1A
E1A
20110607: <Page 2> Delete R287/ R288/ T28 /T29 since SIO board was canceled
<Page 2> Delete R238/R239/ CLK_PCIE_MNC_XDP_N/ CLK_PCIE_MNC_XDP_P and short directly since XDP was canceled
<Page 25> Un-stuff R314,R294 since all of WLAN modules dont use SMBUS
<Page 21> Change USB_CHARGE_ON to USB_EN#, delete R524/ USB_BC_EN and short , change U25 to
AL000547005 since charge IC was canceled
<Page 31> Add PC123(100u/25V_6X5.8) to suppress VIN noise
<Page 11> Stuff R105_1K for IGNNE to follow CRB design
<Page 13> Del R396/ R387, stuff R407/ R382 for PCH_GPIO12/ PCH_GPIO13 (PU for no use)
<Page 4> Unstuff C200 /C190 for +0.75V_DDR_VTT
<Page 4> Unstuff C203 for +1.5VSUS
<Page 7> Change R31/ R45/ R32 from 10uF_8 to 4.7uF_6
<Page 7> Change C362 from 22uF_8 to 10uF_8
E1A
F1A
F1A
G1A
G1A
A3A
A3A
B3B
D
20110608: <Page 27> Reserve D22. stuff R281 for +3V_EC; Change D22 from BC000316Z07 to BCRB500VZ29
<Page 31> Add PC123~PC127 to supress Vin noise
<Page 27> Reserve D13/D14/ D17/D21 for HWPG
20110609: <Page 25> Un-stuff C9 since EM820W doesnt use Vpp
<Page 13> Change Y4 from BG332768A01(20PPM/12.5PF) to BG332768542(20PPM/7PF), and change C348,C349 from 15pF_4 to 6pF_4
Change D8,D10,D19,D23,D24,D25,D39,D41 from BC000316Z07 to BCRB500VZ29
20110610: <Page 24> Change R330/ R327/ R325 to 51ohm_4 for Blue LED; Change R331 to 220ohm_4; Change R328 to 270ohm_4 for Orange LED
--Gerber out for C-test--
B3B
20110614: <Page 6> Stuff R33 PU 1k ohm(CS21002JB34) to +3V for DBR# by Intel Nick confirming
<Page 31> Change PR138 from CS41602FB00 to CS42742FB00 by Duncan request
20110622: <Page 24> Change R330 from CS05102JB35(51ohm) to CS03302JB29(33ohm) to meet LED brightness spec.
<Page 24> Change R327 from CS05102JB35(51ohm) to CS03302JB29(33ohm) to meet LED brightness spec.
<Page 24> Add R328 for CS12202FB14(220ohm) to meet LED brightness spec.
<Page 24> Change R325 from CS05102JB35(51ohm) to CS11502FB21(150ohm) to meet LED brightness spec.
<Page 24> Change R326 from CS13302FB11(330ohm) to CS14702JB28(470ohm) to meet LED brightness spec.
20110627: Change 0ohm resistors to short PAD
20110628: Remove common choke footprint

Remove power short jumper
<Page 2> Unstuff R229 CS00002JB38 for CPU_STOP# to follow checklist rev1.5
<Page 5> Remove R411 / R412 CS00002JB38 and short for CRT_HSYNC / CRT_VSYNC
<Page 13> Stuff R513 CS00002JB38 (0/J_4) for RTCRST#_EC ; Stuff R417 for PLT_RST#
<Page 18> Stuff R26 CS00003J951 (0/J_6) for +5V_LCD (IVO panel)
<Page 20> Stuff R203/R444 CS00003J951 (0/J_6) for audio ESD solution
20110630: <Page 20> Change CN15/CN13(Audio Jack CONN) footprint from phjk-2sj2326-002111-6p to phjk-2sj2326-002111-6p-smt
for SMT open issue
Change PR65/PR66/PR39/PR29/PR153/PR22/PR36/PR152/PR160/PR161 footprint from RC0402 to short0402 by power Duncan request
<Page 31> Stuff PC7 CH14706KB18 (470p_4) for GFX issue
<Page 10> Un-stuff C346/ C347 for no support PCI-E in 3G card
<Page 18> Remove C324 for LCDVCC power
<Page 20> Change C230,C221,C234,C247,C263,C265 from CH6101M9905 (10uF_6) to CH5471M9907 (4.7uF_6) for Audio power
<Page 5> Un-stuff R62 to reserve eDP function
Unstuff C69; Change C20/C137/C157/C298/C310/C309/C387 from (10uF_8) to CH5472K9A02 (4.7uF_8)
<Page 5> Change R38/R39 from 4.7K to 2.2K for EDID(follow CRB).
<Page 29> Unstuff PU1 (battery connector ESD solution)
Ramp
20110705: <Page 25> Swap USBP7+/USBP7- to correct Wimax function.

<Page 20> Stuff BC040201Z00(TVS/6pF_4) at D9 for analog mic ESD solution
20110707: <Page 8> Stuff CS41002JB20(100K_4) at R474 for DDR3_DRAMRST#_R by Intel Nick confirming
by Richtek's feedback
20110708: <Page 31> Change PC7 from CH14706KB18(470p/50V_4) to CH13306JB14(330p/50V_4) for GFX compensation.
20110711: <Page 18> Change R536 from CS00003J951(0_6) to CS04703F912(47_6) to increase hall IC ESD protection level
20110719: <Page 20> Change R172/R497 from CS05602JB17(56_4) to CS04702FB16(47_4) for FAE Vic suggestion to meet acer FSOV spec
20110721: <Page 21> Change U23/U25 footprint from MSOP8-4_9-65-9p to MSOP8-4_9-65 to cancel GND pad for SMT open issue
20110725: <Page 8> Add CH4103K1B08(0.1U/16V_4) cap footprint at C159 for Elpida DDR 2A issue debugging (to suppress glitch)
20110727: <Page 8> Reserve 1U/10V_6 cap footprint at C388 for DDRAM_PWROK RC delay
<Page 32> Un-stuff PR121 CS41002FB28(100K/F_4) PU for DDRAM_PWROK because D14 is un-stuff at EC side
<Page 32> Add PR198 0/J_4 for DDRAM_PWROK
<Page 32> Del netname HWPG_1.5V and change to DDRAM_PWROK
20110804: <Page 20> Change L25 from CX121T30001 (120ohm bead) to CS00004JA40 (0_8) by EMI confirmed
<Page19> Un-stuff CA122084N98 at CP1 - CP6 by EMI confirmed
<Page26> Reserve C282/C284/C291/C296/C392/C393 CH01006JB08 (10p_4) by EMI confirmed
20110805: <Page 20> Reserve R520 0_6 footprint for analog mic ESD protection
<Page 20> Stuff R501 0_6 for analog mic ESD protection
20110811: Change PC7 from 330p_4 (CH13306JB14) to 100p_4 (CH11006JB00) for power GFX issue
20110819: <Page 18> Change R75/R76 from CS01802JB13(18/J_4) to CS04702FB16(47/F_4)
<Page 18> Change L16/L17 from CX8BA220007(0.5A/22ohm_6) to CS00003J951(0/J_6)
20110830: <Page 8> Change R537/R539 from CS00002JB38(0_4) resistors back to 0402 short pad for Elpida DDR 2A issue debugging
20110831: <Page 26> Connect CN20(Card reader CONN) pin27 to GND by EMI Sam suggestion
<Page 20> Add R520 CS00003J951(0_6) for analog mic ESD protection
<Page 28> Modify Hole1 footprint from hg-c276do94x106p2 to ZE7-P3 for power button ESD solution
<Page 28> Modify Hole15 footprint from HG-C276D98P2 to ZE7-P1 for touch pad ESD solution
<Page 28> Modify Hole16 footprint from HG-C276D98P2 to ZE7-P2 for touch pad ESD solution
<Page 28> Add GND PAD2 for touch pad ESD solution

PROJECT MODEL :
DOC NO.
ZE7
APPROVED BY:
PART NUMBER:
5
DATE:
PROJECT : ZE7
REVISON:
DRAWING BY:
3
Size
Document Number
Date:
Rev
C3C
Sheet
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Netbook Acer Aod270

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1

ZE7 Block Diagram (Intel Cedar Trail-M Platform)

DC(3.5W) & DC(6.5W)

DDR III,800/1066 MT/s

Mobile 2.5" HDD

SD3.0, MS, MS PRO,

DDR 1.5VSUS P32

Quanta Computer Inc.

CLK GEN (CLK)

Place close to L32

<20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress

Place close to L27

0.1uF near every power pin

0.1uF near every power pin

VDD_IO can be ranging from 1.05V to 3.3V.

Place close to L28

To CPU (Host CLK)

To CPU (DDR3 IO CLK)

To Mini Card 1 (WLAN)

To CPU (DMI CLK)

To Card Reader (MMC)

0.1uF near every power pin

<20110110> CFG input hardware strapping to allocate PLL assignment.

<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.

To CPU (PLL CLK)

To CPU (DPLSS CLK)

<20110110> DPL_REFSSCCLK is used to drive internal

<20100819> Add 475ohm resistors to prevent current leakage

Control SRC_1 Register B5b6 for CLKREQ_A#

1 = Pin 43/44 as CPU_ITP

0 = Pin 43/44 as SRC_1

Quanta Computer Inc.

Wednesday, August 31, 2011

Quanta Computer Inc.

Wednesday, August 31, 2011

Populate rules: populate

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

<20100827> Add by DG request

Place these Caps near DIMM0

LAYOUT NOTE: PLACE CAPS

Quanta Computer Inc.

1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4

Wednesday, August 31, 2011

Cedar View (CPU)

Level Shifter For HDMI

eDP: 7", 3 via, 2.7Gbps

<20100818_Jerry> If you implement XDP, you need the PU 2.2K

<20110610> Remove PU resistor for Intel update.

<20110110> DPL_REFSSCCLK is used to drive internal

LAYOUT NOTE: PLACE THESE 3 RESISTORS

<20101125_Colt> Please follow PDG, we will

HDMI: 7.5", 4 via, 1.65 Gbps

LCD Panel Power (LDS)

<20101109> Add DMI_REF1.5V to follow CRB v0.7

<20101109> Add C354 to follow CRB v0.7

For HDMI deep color mode support

LCD Panel Backlight (LDS)

<20100727_Sam> Customer must to use 27MHz due to

<20110414> Pull up at EC side

LAYOUT NOTE: PLACE CLOSE TO PIN

<20110414> Unstuff Thermal Sensor and related circuit.

THERMAL SENSOR (THM)