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Colour Television

Chassis

Q551.2E
LA

19050_000_110505.eps
110809

Contents

Page

1.
2.
3.
4.
5.
6.
7.
8.
9.

Revision List
2
Technical Specifications, Diversity, and Connections2
Precautions, Notes, and Abbreviation List
7
Mechanical Instructions
11
Service Modes, Error Codes, and Fault Finding 22
Alignments
44
Circuit Descriptions
49
IC Data Sheets
63
Block Diagrams
Wiring diagram Oscar 32"
77
Wiring diagram Oscar 37"
78
Wiring diagram Oscar 46"
79
Wiring diagram Oscar Platinum 58"
81
Wiring diagram Cannes 40 - 46"
82
Wiring diagram Sundance 50"
83
Block Diagram Video
84
Block Diagram Audio
85
Block Diagram Control & Clock Signals
86
Block Diagram I2C
87
Supply Lines Overview
88
10. Circuit Diagrams and PWB Layouts
Drawing
92
B01 310431365381
B02 310431365381
103
B03 310431365381
112
B04 310431365381
120
B05 310431365381
125
B06 310431365381
126
B07 310431365381
130
B08 310431365381
131
B09 310431365381
133
B10 310431365381
134
B11 310431365381
135
B01 310431365392
139

Contents

Page

B02 310431365392
B03 310431365392
B04 310431365392
B05 310431365392
B06 310431365392
B07 310431365392
B08 310431365392
B09 310431365392
B10 310431365392
B12 310431365392
FB01 820400091952
FB01 820400091992
FB01 820400092112
BB 310431364723
E 272217190427 IR/LED/Key Board
E 272217190459 Leading Edge
E 272217190447 Leading Edge
UD 310431365083
W 310431363282 WiFi Antenna
ALD 310431365212
ALD 310431365473
AL1 820400091574
AL3 820400091263
11. Styling Sheets
Oscar 32"
Oscar 37"
Oscar 46"
Oscar 52"
Oscar 58"
Cannes 40 - 46"
Sundance 50"

150
159
167
172
173
177
178
180
181
182
185
208
238
255
274
276
278
280
281
282
284
300
302
320
321
323
324
325
326
327

Copyright 2011 Koninklijke Philips Electronics N.V.


All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by ER/EL 1169 BU TV Consumer Care, the Netherlands

Subject to modification

EN 3122 785 19052


2011-Sep-09

EN 2

1.

Revision List

Q551.2E LA

1. Revision List
Manual xxxx xxx xxxx.2
Chapter 2: removed 37PFL9606T/12 from the table, see
Table 2-1.
Chapter 4: added mechanical information Cannes, see
section 4.5 Assy/Panel Removal Cannes Styling
(xxPFL8xxx/xx series).
Chapter 7: power supply connector overview, see section
7.2 Power Supply.

Manual xxxx xxx xxxx.0


First release.
Manual xxxx xxx xxxx.1
Chapter 2: added CTNs to the table, see Table 2-1.
Chapter 5: modified SSB replacement procedure; see
section 5.8.12.
Chapter 7: added section 7.8 Back-End Processing.

2. Technical Specifications, Diversity, and Connections


2.1

Index of this chapter:


2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
2.4 Chassis Overview

Technical Specifications
For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
started, user manuals, frequently asked questions and
software & drivers.

Notes:
Figures can deviate due to the different set executions.
Specifications are indicative (subject to change).
Table 2-1 Described Model Numbers and Diversity
10

FBxx (Bolt-on)

ALD (DC/DC Board)

B12 (DVBS DC/DC)

B11 (FPGA)

B10 (DVBT2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

ALxx (Ambilight) LiteOn

Block diagram Bolt-on

Schematics

Wiring Diagram

AmbiLight

PSU

Mechanics

LCD Removal

7
Descriptions

Assembly Removal

Wire Dressing

Connection Overview

3104 313 xxxxx

SSB

CTN

Styling

32PFL9606H/12

Oscar
11-1

65381 2.3

4-1 4.3

4.3.8 7.2

7.9

9-1 -

10-49 10-1 10-2


10-52

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10 10-11 -

32PFL9606K/02

Oscar
11-1

65381 2.3

4-1 4.3

4.3.8 7.2

7.9

9-1 -

10-49 10-1 10-2


10-52

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10 10-11 -

32PFL9606M/08

Oscar
11-1

65381 2.3

4-1 4.3

4.3.8 7.2

7.9

9-1 -

10-49 10-1 10-2


10-52

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10 10-11 -

37PFL9606H/12

Oscar
11-2

65392 2.3

4-2 4.3

4.3.8 7.2

7.9

9-2 -

10-49 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-53 13

10-23 -

10-28
10-29
10-30

37PFL9606K/02

Oscar
11-2

65392 2.3

4-2 4.3

4.3.8 7.2

7.9

9-2 -

10-49 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-53 13

10-23 -

10-28
10-29
10-30

37PFL9606M/08

Oscar
11-2

65392 2.3

4-2 4.3

4.3.8 7.2

7.9

9-2 -

10-49 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-53 13

10-23 -

10-28
10-29
10-30

40PFL8606H/12

Cannes
11-7

65392 2.3

4-3 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-25
10-26

40PFL8606H/60

Cannes
11-7

65392 2.3

4-3 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-25
10-26

40PFL8606K/02

Cannes
11-7

65392 2.3

4-3 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-25
10-26

40PFL8606M/08

Cannes
11-7

65392 2.3

4-3 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-25
10-26

40PFL8606T/12

Cannes
11-7

65392 2.3

4-3 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-25
10-26

46PFL8606H/12

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8606H/60

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8606K/02

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8606M/08

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8606T/12

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8686H/12

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

46PFL8686K/02

Cannes
11-7

65392 2.3

4-4 4.5

4.5.2 7.2

7.9

9-6 9-14 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-51 13

10-23 -

10-25
10-26

2011-Sep-09

back to
div. table

Technical Specifications, Diversity, and Connections

2.2

2.

EN 3

10

FBxx (Bolt-on)

ALD (DC/DC Board)

B12 (DVBS DC/DC)

B11 (FPGA)

B10 (DVBT2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

ALxx (Ambilight) LiteOn

Block diagram Bolt-on

Schematics

Wiring Diagram

AmbiLight

PSU

Mechanics

Descriptions

LCD Removal

Assembly Removal

Wire Dressing

Connection Overview

3104 313 xxxxx

SSB

Q551.2E LA

CTN

Styling

46PFL9706H/12

Oscar
11-4

65392 2.3

4-5 4.3

4.3.8 7.2

7.9

9-3 9-13 10-46 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

46PFL9706K/02

Oscar
11-4

65392 2.3

4-5 4.3

4.3.8 7.2

7.9

9-3 9-13 10-46 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

46PFL9706M/08

Oscar
11-4

65392 2.3

4-5 4.3

4.3.8 7.2

7.9

9-3 9-13 10-46 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

46PFL9706T/12

Oscar
11-4

65392 2.3

4-5 4.3

4.3.8 7.2

7.9

9-3 9-13 10-46 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

50PFL7956H/12

Sundance 65392 2.3


11-8

4-6 4.4

4.4.8 7.2

7.9

9-7 9-15 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-32
10-33

50PFL7956K/02

Sundance 65392 2.3


11-8

4-6 4.4

4.4.8 7.2

7.9

9-7 9-15 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-32
10-33

50PFL7956T/12

Sundance 65392 2.3


11-8

4-6 4.4

4.4.8 7.2

7.9

9-7 9-15 10-48 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-50 13

10-23 -

10-32
10-33

52PFL9606H/12

Oscar
11-5

65392 2.3

4-7 4.3

4.3.8 7.2

7.9

9-4 9-13 10-47 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

52PFL9606K/02

Oscar
11-5

65392 2.3

4-7 4.3

4.3.8 7.2

7.9

9-4 9-13 10-47 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

52PFL9606M/08

Oscar
11-5

65392 2.3

4-7 4.3

4.3.8 7.2

7.9

9-4 9-13 10-47 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

52PFL9606T/12

Oscar
11-5

65392 2.3

4-7 4.3

4.3.8 7.2

7.9

9-4 9-13 10-47 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 13

10-23 10-42 10-25


10-26

58PFL9956H/12

Oscar
11-6

65392 2.3

4-8 4.3

4.3.8 7.2

7.9

9-5 9-13 10-49 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-53 13

10-23 10-44 10-25


10-26

58PFL9956T/12

Oscar
11-6

65392 2.3

4-8 4.3

4.3.8 7.2

7.9

9-5 9-13 10-49 10- 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-53 13

10-23 10-44 10-25


10-26

Directions for Use


You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

back to
div. table

2011-Sep-09

EN 4
2.3

2.

Technical Specifications, Diversity, and Connections

Q551.2E LA

Connections

Connections
Side

H D MI Side

U SB

U SB

SD CARD

C O MMO N IN T ER FAC E

Back

SCART (RGB / CVBS)

AUDIO IN

Y Pb Pr - L R

DVI / VGA

Bottom

NETWORK

6
AUDIO OUT

HDMI 2

HDMI 1

OPTICAL

ARC

10

7
HDMI 3

11

ANTENNA

11

12

VGA

13

14
19050_067_110505.eps
110505

Figure 2-1 Connection overview

Connections
Side

Back

USB

USB

SD CARD

ARC

HDMI Side

HDMI 1

HDMI 2

HDMI 3

SCART

NETWORK

10

11

11

SATELLITE

Y Pb Pr - L R

AUDIO OUT

VGA

OPTICAL

15

AUDIO IN

12
ANTENNA

DVI / VGA

14

13

COMMON INTERFACE

4
19052_007_110909.eps
110909

Figure 2-2 Connection overview


Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.

2011-Sep-09

back to
div. table

Technical Specifications, Diversity, and Connections


2.3.1

Q551.2E LA

EN 5

10 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/


Out

Back Connections
5 - Video RGB - In, CVBS - In/Out, Audio - In/Out
20

2.

19
18

1
2

10000_017_090121.eps
090428
21

Figure 2-5 HDMI (type A) connector

10000_001_090121.eps
090121

Figure 2-3 SCART connector


1
2
3
4
5
6
7
8

- Audio R
- Audio R
- Audio L
- Ground Audio
- Ground Blue
- Audio L
- Video Blue
- Function Select

9
10
11
12
13
14
15
16

- Ground Green
- n.c.
- Video Green
- n.c.
- Ground Red
- Ground P50
- Video Red
- Status/FBL

17
18
19
20
21

- Ground Video
- Ground FBL
- Video CVBS/Y
- Video CVBS
- Shield

0.5 VRMS / 1 kohm


0.5 VRMS / 10 kohm
0.5 VRMS / 1 kohm
Gnd
Gnd
0.5 VRMS / 10 kohm
0.7 VPP / 75 ohm
0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3
Gnd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

k
j
k
H
H
j
jk
j
H

0.7 VPP / 75 ohm

Gnd
Gnd
0.7 VPP / 75 ohm
0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm
Gnd
Gnd
1 VPP / 75 ohm
1 VPP / 75 ohm
Gnd

H
H
j
j
H
H
k
j
H

jq
jq
jq
jq
jq

7 - Cinch: Audio - In (VGA/DVI)


Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm

jq
jq

19
18

1
2

10000_017_090121.eps
090428

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

12345678

10000_025_090121.eps
090121

Figure 2-4 Ethernet connector


Transmit signal
Transmit signal
Receive signal
Centre Tap: DC level fixation
Centre Tap: DC level fixation
Receive signal
Gnd
Gnd

Hot Plug Detect


Gnd

j
H
j
j
H
j
j
H
j
j
H
j
jk
k
j
jk
H
j
j
H

11 - HDMI 2 & 3: Digital Video, Digital Audio - In

8 - RJ45: Ethernet

- TD+
- TD- RD+
- CT
- CT
- RD- GND
- GND

Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel
Audio Return Channel
DDC clock
DDC data
Gnd

Figure 2-6 HDMI (type A) connector

6 - Cinch: Video YPbPr - In, Audio - In


Gn - Video Y
1 VPP / 75 ohm
Bu - Video Pb
0.7 VPP / 75 ohm
Rd - Video Pr
0.7 VPP / 75 ohm
Rd - Audio - R
0.5 VRMS / 10 kohm
Wh - Audio - L
0.5 VRMS / 10 kohm

1
2
3
4
5
6
7
8

- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- ARC
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

k
k
j

- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- n.c.
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel

j
H
j
j
H
j
j
H
j
j
H
j
jk

DDC clock
DDC data
Gnd

j
jk
H
j
j
H

Hot Plug Detect


Gnd

12 - Head phone (Output)


Bk - Head phone
32 - 600 ohm / 10 mW

j
H
H

13 - Aerial - In
- - IEC-type (EU)

Coax, 75 ohm

ot

14 - VGA: Video RGB - In


9 - Cinch: S/PDIF - Out
Bk - Coaxial
0.4 - 0.6VPP / 75 ohm

kq

6
11

5
10
15

10000_002_090121.eps
090127

Figure 2-7 VGA Connector


1
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div. table

- Video Red

0.7 VPP / 75 ohm

j
2011-Sep-09

EN 6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2.3.2

2.

Q551.2E LA

- Video Green
- Video Blue
- n.c.
- Ground
- Ground Red
- Ground Green
- Ground Blue
- +5VDC
- Ground Sync
- n.c.
- DDC_SDA
- H-sync
- V-sync
- DDC_SCL

Technical Specifications, Diversity, and Connections

0.7 VPP / 75 ohm


0.7 VPP / 75 ohm

j
j

Gnd
Gnd
Gnd
Gnd
+5 V
Gnd

H
H
H
H
j
H

3 - SD-Card: Secure Digital Card - In/Out (optional)


14
GND

j
j
j
j

DDC data
0-5V
0-5V
DDC clock

Side Connections

WP

12

GND

11

CD

10

DAT1/IRQ

DAT0/D0

GND2

CLOCK

VDD

GND1

CMD/DI

DAT3/CS

DAT2/NC

GND
13

10000_049_100210.eps
100210

1 - HDMI : Digital Video, Digital Audio - In


See 11 - HDMI 2 & 3: Digital Video, Digital Audio - In

Figure 2-9 SD-Card connector


2 - USB2.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14

10000_022_090121.eps
090121

Figure 2-8 USB (type A)


1
2
3
4

- +5V
- Data (-)
- Data (+)
- Ground

Gnd

k
jk
jk
H

- DAT3/CS
- CMD/DI
- GND1
- Vdd
- CLOCK
- GND2
- DAT0/D0
- DAT1/IRQ
- DAT2/NC
- CD
- GND
- WP
- GND
- GND

Signal
Signal
Gnd
Supply
Signal
Gnd
Signal
Signal
Signal
Signal
Gnd
Signal
Gnd
Gnd

4 - Common Interface
68p - See diagram B01A Common Interface
15 - SAT - In (optional)
- - F-type
Coax, 75 ohm

2.4

Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.

2011-Sep-09

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jk
k
H
k
k
H
jk
jk
jk
j
H
j
H
H

jk

Precautions, Notes, and Abbreviation List

Q551.2E LA

3.

EN 7

3. Precautions, Notes, and Abbreviation List


Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List

3.1

3.3.2

Safety Instructions

Safety regulations require that after a repair, the set must be


returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.

3.3.3

All resistor values are in ohms, and the value multiplier is


often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( = 10-6),
nano-farads (n = 10-9), or pico-farads (p = 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.

Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.

3.3.4

BGA (Ball Grid Array) ICs


Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.

3.3.5

3.2

Schematic Notes

Safety regulations require the following during a repair:


Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.

Where necessary, measure the waveforms and voltages


with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.

Lead-free Soldering

Warnings

3.3

Notes

3.3.1

General

Due to lead-free technology some rules have to be respected


by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.

All ICs and many other semiconductors are susceptible to


electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.

Measure the voltages and waveforms with regard to the


chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).

3.3.6

Alternative BOM identification


It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.

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2011-Sep-09

EN 8

3.

Q551.2E LA

Precautions, Notes, and Abbreviation List


3.4

The third digit in the serial number (example:


AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number 1
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a 2 (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.

Abbreviation List
0/6/12

AARA

ACI

ADC
AFC

AGC

Identification: The bottom line of a type plate gives a 14-digit


serial number. Digits 1 and 2 refer to the production centre (e.g.
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M.
code, digit 4 refers to the Service version change code, digits 5
and 6 refer to the production year, and digits 7 and 8 refer to
production week (in example below it is 2010 week 10 / 2010
week 17). The 6 last digits contain the serial number.

AM
AP
AR
ASF

ATSC

ATV
Auto TV

AV
AVC
AVIP
B/G
BDS
BLR
BTSC

B-TXT
C
CEC

10000_053_110228.eps
110228

Figure 3-1 Serial number (example)


3.3.7

CL

Board Level Repair (BLR) or Component Level Repair


(CLR)

CLR
ComPair
CP
CSM
CTI

If a board is defective, consult your repair procedure to decide


if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8

CVBS

Practical Service Precautions

2011-Sep-09

DAC
DBE

It makes sense to avoid exposure to electrical shock.


While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.

DCM

DDC
D/K
DFI
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SCART switch control signal on A/V


board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
Analogue to Digital Converter
Automatic Frequency Control: control
signal used to tune to the correct
frequency
Automatic Gain Control: algorithm that
controls the video input of the feature
box
Amplitude Modulation
Asia Pacific
Aspect Ratio: 4 by 3 or 16 by 9
Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
Advanced Television Systems
Committee, the digital TV standard in
the USA
See Auto TV
A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
External Audio Video
Audio Video Controller
Audio Video Input Processor
Monochrome TV system. Sound
carrier distance is 5.5 MHz
Business Display Solutions (iTV)
Board-Level Repair
Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
Blue TeleteXT
Centre channel (audio)
Consumer Electronics Control bus:
remote control bus on HDMI
connections
Constant Level: audio output to
connect with an external amplifier
Component Level Repair
Computer aided rePair
Connected Planet / Copy Protection
Customer Service Mode
Color Transient Improvement:
manipulates steepness of chroma
transients
Composite Video Blanking and
Synchronization
Digital to Analogue Converter
Dynamic Bass Enhancement: extra
low frequency amplification
Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
See E-DDC
Monochrome TV system. Sound
carrier distance is 6.5 MHz
Dynamic Frame Insertion

Precautions, Notes, and Abbreviation List


DFU
DMR
DMSD
DNM
DNR
DRAM
DRM
DSP
DST

DTCP

DVB-C
DVB-T
DVD
DVI(-d)
E-DDC

EDID
EEPROM
EMI
EPG
EPLD
EU
EXT
FDS
FDW
FLASH
FM
FPGA
FTV
Gb/s
G-TXT
H
HD
HDD
HDCP

HDMI
HP
I
I 2C
I2D
I2S
IF
IR
IRQ
ITU-656

Directions For Use: owner's manual


Digital Media Reader: card reader
Digital Multi Standard Decoding
Digital Natural Motion
Digital Noise Reduction: noise
reduction feature of the set
Dynamic RAM
Digital Rights Management
Digital Signal Processing
Dealer Service Tool: special remote
control designed for service
technicians
Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
Digital Video Broadcast - Cable
Digital Video Broadcast - Terrestrial
Digital Versatile Disc
Digital Visual Interface (d= digital only)
Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
Extended Display Identification Data
(VESA standard)
Electrically Erasable and
Programmable Read Only Memory
Electro Magnetic Interference
Electronic Program Guide
Erasable Programmable Logic Device
Europe
EXTernal (source), entering the set by
SCART or by cinches (jacks)
Full Dual Screen (same as FDW)
Full Dual Window (same as FDS)
FLASH memory
Field Memory or Frequency
Modulation
Field-Programmable Gate Array
Flat TeleVision
Giga bits per second
Green TeleteXT
H_sync to the module
High Definition
Hard Disk Drive
High-bandwidth Digital Content
Protection: A key encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a snow vision mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP software key
decoding.
High Definition Multimedia Interface
HeadPhone
Monochrome TV system. Sound
carrier distance is 6.0 MHz
Inter IC bus
Inter IC Data bus
Inter IC Sound bus
Intermediate Frequency
Infra Red
Interrupt Request
The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.

iTV
LS

LATAM
LCD
LED
L/L'

LPL
LS
LVDS
Mbps
M/N
MHEG

MIPS

MOP
MOSFET
MPEG
MPIF
MUTE
MTV
NC
NICAM

NTC
NTSC

NVM
O/C
OSD
OAD

OTC
P50
PAL

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Q551.2E LA

3.

EN 9

SDI), is a digitized video format used


for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
Institutional TeleVision; TV sets for
hotels, hospitals etc.
Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
Latin America
Liquid Crystal Display
Light Emitting Diode
Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LG.Philips LCD (supplier)
Loudspeaker
Low Voltage Differential Signalling
Mega bits per second
Monochrome TV system. Sound
carrier distance is 4.5 MHz
Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
Matrix Output Processor
Metal Oxide Silicon Field Effect
Transistor, switching device
Motion Pictures Experts Group
Multi Platform InterFace
MUTE Line
Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)
Not Connected
Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
Negative Temperature Coefficient,
non-linear resistor
National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
Non-Volatile Memory: IC containing
TV related data such as alignments
Open Circuit
On Screen Display
Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels.
On screen display Teletext and
Control; also called Artistic (SAA5800)
Project 50: communication protocol
between TV and peripherals
Phase Alternating Line. Color system
mainly used in West Europe (colour
carrier = 4.433619 MHz) and South
America (colour carrier
2011-Sep-09

EN 10

3.

PCB
PCM
PDP
PFC
PIP
PLL

POD

POR
PSDL
PSL
PSLS

PTC
PWB
PWM
QRC
QTNR
QVCP
RAM
RGB

RC
RC5 / RC6
RESET
ROM
RSDS
R-TXT
SAM
S/C
SCART

SCL
SCL-F
SD
SDA
SDA-F
SDI
SDRAM
SECAM

SIF
SMPS
SoC
SOG
SOPS
SPI

S/PDIF
SRAM
SRP
SSB
SSC
STB
STBY
2011-Sep-09

Q551.2E LA

Precautions, Notes, and Abbreviation List

PAL M = 3.575612 MHz and


PAL N = 3.582056 MHz)
Printed Circuit Board (same as PWB)
Pulse Code Modulation
Plasma Display Panel
Power Factor Corrector (or Preconditioner)
Picture In Picture
Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Power On Reset, signal to reset the uP
Power Supply for Direct view LED
backlight with 2D-dimming
Power Supply with integrated LED
drivers
Power Supply with integrated LED
drivers with added Scanning
functionality
Positive Temperature Coefficient,
non-linear resistor
Printed Wiring Board (same as PCB)
Pulse Width Modulation
Quasi Resonant Converter
Quality Temporal Noise Reduction
Quality Video Composition Processor
Random Access Memory
Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
Remote Control
Signal protocol from the remote
control receiver
RESET signal
Read Only Memory
Reduced Swing Differential Signalling
data interface
Red TeleteXT
Service Alignment Mode
Short Circuit
Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
Serial Clock I2C
CLock Signal on Fast I2C bus
Standard Definition
Serial Data I2C
DAta Signal on Fast I2C bus
Serial Digital Interface, see ITU-656
Synchronous DRAM
SEequence Couleur Avec Mmoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
Sound Intermediate Frequency
Switched Mode Power Supply
System on Chip
Sync On Green
Self Oscillating Power Supply
Serial Peripheral Interface bus; a 4wire synchronous serial data link
standard
Sony Philips Digital InterFace
Static RAM
Service Reference Protocol
Small Signal Board
Spread Spectrum Clocking, used to
reduce the effects of EMI
Set Top Box
STand-BY

SVGA
SVHS
SW
SWAN
SXGA
TFT
THD
TMDS
TS
TXT
TXT-DW
UI
uP
UXGA
V
VESA
VGA
VL
VSB
WYSIWYR

WXGA
XTAL
XGA
Y
Y/C
YPbPr

YUV

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800 600 (4:3)


Super Video Home System
Software
Spatial temporal Weighted Averaging
Noise reduction
1280 1024
Thin Film Transistor
Total Harmonic Distortion
Transmission Minimized Differential
Signalling
Transport Stream
TeleteXT
Dual Window with TeleteXT
User Interface
Microprocessor
1600 1200 (4:3)
V-sync to the module
Video Electronics Standards
Association
640 480 (4:3)
Variable Level out: processed audio
output toward external amplifier
Vestigial Side Band; modulation
method
What You See Is What You Record:
record selection that follows main
picture and sound
1280 768 (15:9)
Quartz crystal
1024 768 (4:3)
Luminance signal
Luminance (Y) and Chrominance (C)
signal
Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
Component video

Mechanical Instructions

Q551.2E LA

4.

EN 11

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal Oscar Styling (xxPFL96xx/xx series)
4.4 Assy/Panel Removal Sundance Styling (xxPFL7xxx/xx
series)
4.5 Assy/Panel Removal Cannes Styling (xxPFL8xxx/xx
series)
4.6 Set Re-assembly
Notes:

4.1

Figures below can deviate slightly from the actual situation,


due to the different set executions.

Cable Dressing

19050_071_110506.eps
110506

Figure 4-1 Cable dressing 32PFL9606x/xx (Oscar 32")

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2011-Sep-09

EN 12

4.

Q551.2E LA

Mechanical Instructions

19051_161_110809.eps
110809

Figure 4-2 Cable dressing 37PFL9606x/xx (Oscar 37")

19051_162_110809.eps
110809

Figure 4-3 Cable dressing 40PFL8606x/xx (Cannes 40")


2011-Sep-09

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Mechanical Instructions

Q551.2E LA

4.

EN 13

19051_163_110809.eps
110809

Figure 4-4 Cable dressing 46PFL8606x/xx (Cannes 46")

19051_164_110810.eps
110810

Figure 4-5 Cable dressing 46PFL9706x/xx (Oscar 46")

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2011-Sep-09

EN 14

4.

Q551.2E LA

Mechanical Instructions

19051_165_110810.eps
110810

Figure 4-6 Cable dressing 50PFL7956x/xx (Sundance 50")

19051_166_110810.eps
110810

Figure 4-7 Cable dressing 52PFL9606x/xx (Oscar 52")

2011-Sep-09

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Mechanical Instructions

Q551.2E LA

4.

EN 15

19051_167_110810.eps
110810

Figure 4-8 Cable dressing 58PFL9956x/xx (Oscar 58")

4.2

Service Positions
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.

4.3

Assy/Panel Removal Oscar Styling


(xxPFL96xx/xx series)
The instructions apply to the 32PFL9606H/12.
Caution
When removing the SSB, the board should not be handled by
touching the heatsink of the PNX85500.
Refer to section 5.8.11 Additional information for replacing the
ceramic heatsink application on the PNX85500.

4.3.1

Rear Cover
Warning: Disconnect the mains power cord before you remove
the rear cover.
Refer to Figure 4-9 for details.

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2011-Sep-09

EN 16

4.

Mechanical Instructions

Q551.2E LA

3
3

3
2

2
2

3
3

3
2
3

19050_072_110506.eps
110506

Figure 4-9 Rear cover removal


4.3.7

1. Remove the stand [1].


2. Remove all screws of the rear cover [2] and [3].
3. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.3.2

Ambilight Units
Refer to Figure 4-10 and Figure 4-11 for details.

Speakers
The speakers are located in the stand.
When defective, replace the whole unit.

4.3.3

Mains Switch

2
The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
When defective, replace the whole unit.
4.3.4

1
3

Keyboard Control, IR & LED Board


Release the catches and take the board out.
When defective, replace the whole unit.

4.3.5

19050_073_110506.eps
110506

IR Blaster
Figure 4-10 Ambilight units -1-

Release the catches and take the board out.


When defective, replace the whole unit.
4.3.6

1. Locate the separator [1].


2. Gently lift the diffusor [2] near the separator [1], slide the
diffusor [3] and take the diffusor out.
3. Lift the catches gently [4] while sliding the Ambilight PWB
out. Use a dedicated tool such as a screwdriver.

WiFi antennas
Release the catches and take the board out.
When defective, replace the whole unit.

2011-Sep-09

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Mechanical Instructions

Q551.2E LA

4.

EN 17

When defective, replace the whole unit.


4.3.8

LCD Panel
Refer to Figure 4-12 and Figure 4-13 for details.

19050_074_110506.eps
110506

Figure 4-11 Ambilight units -2-

5
5

2
3

6
19050_076_110506.eps
110506

Figure 4-12 LCD panel


1. Remove the AL units as earlier described.
2. Remove the power switch with the power inlet subframe
[1].
3. Remove the SSB [2].
4. Remove the PSU [3].
5. Remove the WiFi module [4].
6. Remove the AL subframes [5].
7. Remove the stand and -support as described earlier.
8. Remove all remaining cables and subframes.
9. Remove the clamps [6].

4
19100_056_110217.eps
110217

Figure 4-13 LCD panel -2-

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2011-Sep-09

EN 18

4.

Mechanical Instructions

Q551.2E LA

19100_047_110216.eps
110216
19050_075_110506.eps
110506

Figure 4-15 Mains switch


The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.

Figure 4-14 LCD panel -3-

4.4

Assy/Panel Removal Sundance Styling


(xxPFL7xxx/xx series)
4.4.4

The instructions apply to the 32PFL7406K/02.


4.4.1

Main Power Supply


Refer to Figure 4-16 for details.

Rear Cover
Warning: Disconnect the mains power cord before you remove
the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.

1. Remove all screws of the rear cover.


2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.4.2

Speakers
Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.

2
1

Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.
4.4.3

19100_050_110216.eps
110216

Figure 4-16 Main Power Supply

Mains Switch

1. Unplug all connectors [1].


2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.

Refer to Figure 4-15 for details.

2011-Sep-09

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Mechanical Instructions
4.4.5

Q551.2E LA

4.

EN 19

Small Signal Board (SSB)


Refer to Figure 4-17 for details.

2
2

19100_053_110216.eps
110216

Figure 4-19 Keyboard control, IR & LED board [2/2]

2
1. Remove the stand and the plastic support [1].
2. Unplug the connector [2].
3. Remove the screws [3] and take the board out.
When defective, replace the whole unit.
4.4.7

Ambilight Units
The Ambilight units can be lifted from the subframes without
the use of tools.
Refer to Figure 4-20 for details.

19100_051_110216.eps
110216

Figure 4-17 SSB


1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.
4.4.6

Keyboard Control, IR & LED Board

Refer to Figure 4-18 and Figure 4-19 for details.

1
1

19100_054_110216.eps
110216

Figure 4-20 Ambilight units


1. Unplug the connector [1].
2. Carefully lift the board [2] and take the board out.
When defective, replace the whole unit.

1
1

19100_052_110216.eps
110216

Figure 4-18 Keyboard control, IR & LED board [1/2]

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2011-Sep-09

EN 20
4.4.8

4.

Q551.2E LA

Mechanical Instructions

LCD Panel
Refer to Figure 4-21 and Figure 4-22 for details.

2
2

1
4

19100_055_110216.eps
110216

Figure 4-21 LCD panel [1/2]


1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -support as described earlier.
5. Remove the cables [1].
6. Remove the stand subframe [2].
7. Remove the mains switch subframe [3].
8. Remove the Ambilight units together with their subframes
as described earlier.
9. Unplug the connector from the keyboard control-, and IR &
LED board as described earlier.
10. Remove all remaining cables and subframes.
11. Use a screwdriver to release the clamps [4] that secure the
panel and take the panel out.
Remove the clamps from the panel before sending the panel in
for Service.

4
19100_056_110217.eps
110217

Figure 4-22 LCD panel [2/2]

4.5

Assy/Panel Removal Cannes Styling


(xxPFL8xxx/xx series)
The Cannes styling is similar to the Sundance, except for the
removal of the rear cover.
Special attention is required to avoid pollution of the glass plate
when mounting a new LCD panel.

2011-Sep-09

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Mechanical Instructions
4.5.1

4.6

Rear Cover

Q551.2E LA

4.

EN 21

Set Re-assembly

Warning: Disconnect the mains power cord before you remove


the rear cover.

To re-assemble the whole set, execute all processes in reverse


order.

Refer to Figure 4-23 for details.

Notes:
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

19052_005_110908.eps
110908

Figure 4-23 Rear cover


1. Remove all screws of the rear cover.
2. Release the catches from the rear cover using a
screwdriver as indicated in Figure 4-23.
3. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.5.2

LCD Panel
When mounting a new LCD panel, pay attention to clean the
inside of the glass plate before mounting a new panel.

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2011-Sep-09

EN 22

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:


5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading

5.1

How to Activate SDM


For this chassis there are two kinds of SDM: an analogue SDM
and a digital SDM. Tuning will happen according Table 5-1.
Analogue SDM: use the standard RC-transmitter and key
in the code 062596, directly followed by the MENU (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
"HOME") button again.
Analogue SDM can also be activated by grounding for a
moment the solder path on the SSB, with the indication
SDM (see Service mode pad).
Digital SDM: use the standard RC-transmitter and key in
the code 062593, directly followed by the MENU (or
"HOME") button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
"HOME") button again.

Test Points
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.

5.2

All service-unfriendly modes (if present) are disabled, like:


(Sleep) timer.
Child/parental lock.
Picture mute (blue mute or black mute).
Automatic volume levelling (AVL).
Skip/blank of non-favourite pre-sets.

Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.

SDM
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section 5.4.1 ComPair).
19100_057_110217.eps
110217

Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old MENU
button is now called HOME (or is indicated by a house icon).
5.2.1

Figure 5-1 Service mode pad


After activating this mode, SDM will appear in the upper right
corner of the screen (when a picture is available).

Service Default Mode (SDM)

How to Navigate
When the MENU (or HOME) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.

Purpose
To create a pre-defined setting, to get the same
measurement results as given in this manual.
To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section 5.3 Stepwise Start-up.
To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section 5.5 Error Codes).

How to Exit SDM


Use one of the following methods:
Switch the set to STAND-BY via the RC-transmitter.
Via a standard customer RC-transmitter: key in 00sequence.

Specifications
5.2.2

Service Alignment Mode (SAM)

Table 5-1 SDM default settings

Freq. (MHz)

Default
system

Europe, AP(PAL/Multi)

475.25

PAL B/G

Europe, AP DVB-T

546.00 PID
DVB-T
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07

Region

2011-Sep-09

Purpose
To perform (software) alignments.
To change option settings.
To easily identify the used software version.
To view operation hours.
To display (or clear) the error code buffer.
How to Activate SAM
Via a standard RC transmitter: Key in the code 062596
directly followed by the INFO or OK button. After activating
SAM with this method a service warning will appear on the
screen, continue by pressing the OK button on the RC.

All picture settings at 50% (brightness, colour, contrast).


Sound volume at 25%.
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Service Modes, Error Codes, and Fault Finding


Contents of SAM
Hardware Info.
A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
AAAA= the chassis name.
B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
the software is now multi-region).
X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
B. STBY PROC Version. Displays the software
version of the stand-by processor.
C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or OK button)
pressed here, followed by the OK button, the error buffer
is reset.
Alignments. This will activate the ALIGNMENTS submenu. See Chapter 6. Alignments.
Dealer Options. Extra features for the dealers.
Options numbers. Extra features for Service. For more
info regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored, otherwise changes will be lost.
Initialize NVM. The moment the processor recognizes a
corrupted NVM, the initialize NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialize the NVM.

Q551.2E LA

5.

EN 23

Display Option
Code

39mm

27mm

PHILIPS

040

MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001

(CTN Sticker)

10000_038_090121.eps
090819

Figure 5-2 Location of Display Option Code sticker

Note: When the NVM is corrupted, or replaced, there is a high


possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or "HOME")
button and XXX (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zeros. If the above action is
successful, the front LED will go out as an indication that the
RC sequence was correct. After the display option is changed
in the NVM, the TV will go to the Stand-by mode. If the NVM
was corrupted or empty before this action, it will be initialized
first (loaded with default values). This initializing can take up to
20 seconds.

Store - go right. All options and alignments are stored


when pressing cursor right (or the OK button) and then
the OK-button.
Operation hours display. Displays the accumulated total
of operation hours of the screen itself. In case of a display
replacement, reset to 0 or to the consumed operation
hours of the spare display.
SW Maintenance.
SW Events. In case of specific software problems, the
development department can ask for this info.
HW Events. In case of specific software problems, the
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Personal settings, Option codes, Alignments,
Identification data (includes the set type and prod code +
all 12NC like SSB, display, boards), History list. The All
item supports to upload all several
items at once.
A directory repair\ will be created in the root of the
USB stick.
To upload the settings, select each item separately, press
cursor right (or the OK button), confirm with OK and
wait until the message Done appears. In case the
download to the USB stick was not successful, Failure will
be displayed. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customers
TV settings and to store them into another SSB.
Important remark : to upload the channel list, select
Home => Setup => TV settings => Preferences
=> Channel list copy => Copy to USB.The procedure of
channel map cloning is clearly described in the
(electronic) user manual.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in Upload to USB. The All item
supports to download all several items at once.
Important remark : to download the channel list, select
Home => Setup => TV settings => Preferences
=> Channel list copy => Copy to TV. The procedure of
channel map cloning is clearly described in the
(electronic) user manual.

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2011-Sep-09

EN 24

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

NVM editor. For NET TV the set type number must be


entered correctly.
Also the production code (factory location code) can be
entered here via the RC-transmitter.
Correct data can be found on the side/rear sticker.

How to Activate CSM


Key in the code 123654 via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!

How to Navigate
In SAM, the menu items can be selected with the
CURSOR UP/DOWN key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the CURSOR UP/DOWN key to
display the next/previous menu items.
With the CURSOR LEFT/RIGHT keys, it is possible to:
(De) activate the selected menu item.
(De) activate the selected sub menu.
With the OK key, it is possible to activate the selected
action.

How to Navigate
By means of the CURSOR-DOWN/UP knob on the RCtransmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this. The update
can also be done via the NVM editor available in SAM.
Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee in a possibility to
do this. The update can also be done via the NVM editor
available in SAM.
Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
Options 1. Gives the option codes numbers of option
group 1 as set in SAM (Service Alignment Mode).
Options 2. Gives the option codes numbers of option
group 2 as set in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
12NC display. Shows the 12NC of the display.
12NC supply. Shows the 12NC of the power supply.
12NC 200Hz board. Shows the 12NC of the 200Hz Panel
(when present).
12NC AV PIP. Shows the 12NC of the AV PIP board
(when present).

How to Exit SAM


Use one of the following methods:
Switch the TV set to STAND-BY via the RC-transmitter.
Via a standard RC-transmitter, key in 00 sequence, or
select the BACK key.
5.2.3

Customer Service Mode (CSM)


Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
Provided CSM is activated, a test pattern can be displayed
during 5 seconds (1 second Blue, 1 second Green and 1
second Red, then again 1 second Blue and 1 second Green).
This test pattern is generated by the PNX51X0 (part of the
display). So if this test pattern is shown, it could be determined
that the back end video chain (PNX51X0 and display) is
working.For TV sets without the PNX51X0 inside, every menu
from CSM will be used as check for the back end chain video.
When CSM is activated and there is a USB stick connected to
the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.

Software versions
Current main SW. Displays the build-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
Standby SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_83.84.0.0.
e-UM version. Displays the electronic user manual SWversion (12NC version number). Most significant number
here is the last digit.
FPGA dimming software.Displays the backlight FPGA
software version.Device processes the dimming +
scanning and 3D LED.
AV PIP software. not applicable.
3D dongle software version. not applicable.
FRC-V software.Represence software version for the
Frame Rate Convertor(Vx1 - or LVDS version).
FPGA HDR software.
FPGA lattice backlight software.
FPGA C-balancer software.
FPGA PQ software. Displays the picture quality FPGA
software version.Device supports contrast/sharpness
improvement, 2D-3D conversion and 3D-3D depth

Additional in CSM mode (with USB stick connected), pressing


OK will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
The normal CSM dump information,
All items (from SAM load to USB, but in readable format),
Operating hours,
Error codes,
SW/HW event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the red
button and key in serial digits 2679 (same keys to form the
word COPY with a cellphone). A file Dump_model
number_serial number.bin will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed (see also
section 5.5 Error Codes).

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Service Modes, Error Codes, and Fault Finding


5.3

adaptation + 3D IR LED in case of no backlight FPGA


present.

Q551.2E LA

5.

EN 25

Stepwise Start-up
When the TV is in a protection state due to an error detected by
standby software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
in this mode with a faulty FET 7U0X is done, you can destroy
all ICs supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET
7U0X or others FETs on shortcircuit before activating SDM via
the service pads.

Quality items
Signal quality. Bad / average /good (not for DVB-S).
Ethernet MAC address. Displays the MAC address
present in the SSB.
Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
BDS key. Indicates if the set is in the BDS status.
CI module. Displays status if the common interface
module is detected.
CI + protected service. Yes/No.
Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW EVENTLOG #(events)
H : 000X 0000(number of hardware errors)
H : 0000 000X (number of hardware events : SW EVENTLOG #(events).

The abbreviations SP and MP in the figures stand for:


SP: protection or error detected by the Stand-by
Processor.
MP: protection or error detected by the MIPS Main
Processor.

How to Exit CSM


Press MENU (or "HOME") / Back key on the RC-transmitter.

Mains
off

Mains
on

- WakeUp requested
- Acquisition needed
- Tact switch pushed

St by

WakeUp
requested

Semi
St by

- stby requested and


no data Acquisition
required

Active
- St by requested
- tact SW pushed

Tact switch
pushed

Hibernate

WakeUp
requested
(SDM)

- Tact switch pushed


- last status is hibernate
after mains ON

GoToProtection
GoToProtection

Protection

18770_250_100216.eps
100402

Figure 5-3 Transition diagram


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2011-Sep-09

EN 26

5.

Service Modes, Error Codes, and Fault Finding

Q551.2E LA

Off
Stand by or
Protection

Mains is applied

Standby Supply starts running.


All standby supply voltages become available.

st-by P resets

If the protection state was left by short circuiting the


SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.

Initialise I/O pins of the st-by P:


- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH

- Switch Audio-Reset high.


It is low in the standby mode if the standby
mode lasted longer than 10s.

start keyboard scanning, RC detection. Wake up reasons are


off.

Switch ON Platform and display supply by switching


LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power


is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval.

Detect2 high received


within 2 seconds?

Yes

12V error:
Layer1: 3
Layer2: 16

No

Enter protection

Enable the DCDC converters


(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address


of Standby P to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to
ground by inserting EJTAG probe)

An EJTAG probe (e.g. WindPower ICE probe) can be


connected for Linux Kernel debugging purposes.

EJTAG probe
connected ?

Yes

No
No

No

Cold boot?

Yes
Release AVC system reset
Feed warm boot script

Release AVC system reset


Feed cold boot script

Release AVC system reset


Feed initializing boot script
disable alive mechanism

18770_251_100216.eps
100216

Figure 5-4 Off to Semi Stand-by flowchart (part 1)

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Service Modes, Error Codes, and Fault Finding

Q551.2E LA

5.

Reset-system is switched HIGH by the


AVC at the end of the bootscript

Reset-system is switched HIGH by the


AVC at the end of the bootscript

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

EN 27

No

This cannot be done through the bootscript,


the I/O is on the standby P

Timing need to be updated if


more mature info is available.

Bootscript ready
in 1250 ms?

No

Yes
Set IC slave address
of Standby P to (60h)

RPC start (comm. protocol)


Timing needs to
be updated if more
mature info is
available.

Flash to Ram
image transfer succeeded
within 30s?

No
Code =
Layer1: 2
Layer2: 15

Yes

Switch AVC PNX85500 in


reset (active low)

Code =
Layer1: 2
Layer2: 53

No

SW initialization
succeeded
within 20s?

Wait 10ms

Timing needs to be
updated if more
mature info is
available.

Yes

Enable Alive check mechanism


Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
MIPS reads the wake up reason
from standby P.

Wait until AVC starts to


communicate

Wait 5ms

switch off the remaining DC/DC


converters

3-th try?

Startup screen shall only be visible when there is a coldboot to


an active state end situation. The startup screen shall not be
visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode..

Wake up reason
coldboot & not semistandby?
yes

Switch Standby I/O line high


and wait 4 seconds

The first time after the option turn on of the startup screen or
when the set is virgin, the cfg file is not present and hence
the startup screen will not be shown.

Startup screen cfg file


present?

Yes

yes

Blink Code as
error code

200Hz set?

yes

No

Enter protection

85500 sends out startup screen

85500 sends out startup screen

85500 starts up the display.

200Hz Tcon has started up the


display.

Startup screen visible

85500 requests Lamp on

No

No
To keep this flowchart readable, the exact
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid.

Startup screen visible

Initialize audio
initialize tuner and channel decoders
Initialize source selection
Initialize video processing ICs

initialize AutoTV by triggering CHS AutoTV Init interface


Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps
100216

Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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2011-Sep-09

EN 28

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.

Semi Standby

The assumption here is that a fast toggle (<2s) can


only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s.

Wait until previous on-state is left more than 2


seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

CPipe already generates a valid output


clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?


(splash screen)
No

Switch on the display power by


switching LCD-PWR-ON low

The exact timings to


switch on the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Yes
Wait x ms
Initialize audio and video
processing IC's and functions
according needed use case.

Switch on LVDS output in the 85500


Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set


the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line


detection algorithm

Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.

return

Switch Audio-Reset low and wait 5ms


A LED set does not normally need a
preheat time. The preheat remains present
but is set to zero in the display file.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

Restore dimming backlight feature, PWM and BOOST output


and unblank the video.

The higher level requirement is that audio and video


should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_253_100216.eps
100216

Figure 5-6 Semi Stand-by to Active flowchart (EEFL or LED backlight 50/100 Hz only)

2011-Sep-09

back to
div. table

Service Modes, Error Codes, and Fault Finding

The assumption here is that a fast toggle (<2s)


can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s,
we have to delay the semi -> stby transition until
the requirement is met.

Q551.2E LA

5.

EN 29

Semi Standby
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

There is no need to define the


display timings since the timing
implementation is part of the Tcon.

Backlight already on?


(splash screen)
Yes
Initialize audio and video
processing IC's and functions
according needed use case.

No
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED

Start POK line


detection algorithm
Wait until valid and stable audio and video, corresponding to
the requested output is delivered by the AVC.
return
Switch Audio-Reset low and wait 5ms

The higher level requirement is that audio and


video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

unblank the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_254_100216.eps
100216

Figure 5-7 Semi Stand-by to Active flowchart (LED backlight 200 Hz)

back to
div. table

2011-Sep-09

EN 30

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

Active
Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground


(I/O: audio reset)
And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power


Observer should be zero

Switch off POK line


detection algorithm

switch off LCD backlight


(I/O or IC)

Mute all video outputs

Yes

200Hz set?

No

Wait x ms (display file)


Instruct 200Hz
Tcon to turn off
the display

Switch off LVDS output in 85500

Wait x ms

The exact timings to


switch off the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Switch off the display power by


switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps
100216

Figure 5-8 Active to Semi Stand-by flowchart

2011-Sep-09

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div. table

Service Modes, Error Codes, and Fault Finding

Q551.2E LA

5.

EN 31

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is


finished. *)

*) If this is not performed and the set is


switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more


stable condition when switching off the power).

Switch AVC system in reset state (reset-system and


reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:
release reset audio 10 sec after entering
standby to save power
Also here, the standby state has to be
maintained for at least 4s before starting
another state transition.

Stand by
18770_256_100216.eps
100216

Figure 5-9 Semi Stand-by to Stand-by flowchart

back to
div. table

2011-Sep-09

EN 32

5.

Service Modes, Error Codes, and Fault Finding

Q551.2E LA

5.4

Service Tools

5.5

Error Codes

5.4.1

ComPair

5.5.1

Introduction

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the P
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.

The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.

Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.

New in this chassis is the way errors can be displayed:

How to Connect
This is described in the chassis fault finding database in
ComPair.

TO TV
TO
UART SERVICE
CONNECTOR

ComPair II
RC in

RC out

TO
I2C SERVICE
CONNECTOR

TO
UART SERVICE
CONNECTOR

Multi
function

Optional Power Link/ Mode


Switch
Activity

I2C

RS232 /UART

If no errors are there, the LED should not blink at all in


CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
LAYER 1 errors are one digit errors.
LAYER 2 errors are 2 digit errors.
In protection mode.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
In CSM mode.
When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode.
When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Error display on screen.
In CSM no error codes are displayed on screen.
In SAM the complete error list is shown.

PC

Basically there are three kinds of errors:


Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section 5.5 Error Codes, 5.5.4
Error Buffer. Note that it can take up several minutes
before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.

ComPair II Developed by Philips Brugge

HDMI
I2C only

Optional power
5V DC

10000_036_090121.eps
091118

Figure 5-10 ComPair II interface connection


Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!

5.5.2

Use one of the following methods:


On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.

How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
Software is available via the Philips Service web portal.
ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: When you encounter problems, contact your local
support desk.
2011-Sep-09

How to Read the Error Buffer

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div. table

Service Modes, Error Codes, and Fault Finding

5.5.3

Via the blinking LED procedure. See section 5.5.3 How to


Clear the Error Buffer.
Via ComPair.

5.

EN 33

content, as this history can give significant information). This to


ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Via error bits in the status registers of ICs.
Via polling on I/O pins going to the stand-by processor.
Via sensing of analog values on the stand-by processor or
the PNX8550.
Via a not acknowledge of an I2C communication.

How to Clear the Error Buffer


Use one of the following methods:
By activation of the RESET ERROR BUFFER command
in the SAM menu.
If the content of the error buffer has not changed for 50+
hours, it resets automatically.

5.5.4

Q551.2E LA

Error Buffer

Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.

In case of non-intermittent faults, clear the error buffer before


starting to repair (before clearing the buffer, write down the
Table 5-2 Error code overview

Description

Monitored Error/ Error Buffer/


Layer 1 Layer 2 by
Prot Blinking LED Device

Defective Board

I2C3

SSB

SSB

I2C2

SSB

13

MIPS

BL / EB

14

MIPS

BL / EB

SSB

PNX doesnt boot (HW cause) 2

15

Stby P

BL

PNX8550

SSB

12V

16

Stby P

BL

Supply

Inverter or display supply

17

MIPS

EB

Supply

I2C4

18

MIPS

BL / EB

SSB

SSB

HDMI mux

23

MIPS

EB

Sil9x87

SSB

I2C switch

24

MIPS

EB

PCA9540

SSB

Channel dec DVB-T2

27

MIPS

EB

CXD2820

SSB

Channel dec DVB-S

28

MIPS

EB

STV0903

SSB

Lnb controller

31

MIPS

EB

LNBH23

SSB

FPGA 21/9 Scaler

33

MIPS

EB

Backend board

Tuner

34

MIPS

EB

TH 26x3

SSB

Main nvm

35

MIPS

EB

STM24C64

SSB

Tuner DVB-S

36

MIPS

EB

STV6110

SSB

I2C switch

37

MIPS

EB

PCA9540

Backend board

FPGA Dimming

38

MIPS

EB

Backend board

T sensor SSB/set

42

MIPS

EB

LM 75

T sensor

T sensor LED driver/Tcon

42

MIPS

EB

LM 75

T sensor

FRC-V

44

MIPS

EB

Backend board

FPGA PQ

45

MIPS

EB

6SLX25

Backend board

FPGA C-balancer

47

MIPS

EB

FPGA/

Backend board

PNX doesnt boot (SW cause) 2

53

Stby P

BL

PNX8550

SSB

TCON Display

7/9

54

MIPS

EB

Display

FPGA HDR

61

MIPS

EB

Display

FPGA lattice backlight

62

MIPS

EB

Display

Display

64

MIPS

EB

Display

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.6
Logging). Its shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
Error 13 (I2C bus 3, SSB bus blocked). Current situation:
when this error occurs, the TV will constantly reboot due to
the blocked bus. The best way for further diagnosis here, is
to use ComPair.
Error 14 (I2C bus 2, TV set bus blocked). Current
situation: when this error occurs, the TV will constantly
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.

back to
div. table

Error 18 (I2C bus 4, Tuner bus blocked). In case this bus


is blocked, short the SDM solder paths on the SSB during
startup, LAYER error 2 = 18 will be blinked.
Error 15 (PNX8550 doesnt boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C1 bus is
blocked (NVM). I2C1 can be indicated in the schematics as
follows: SCL-UP-MIPS, SDA-UP-MIPS.
Other root causes for this error can be due to hardware
problems regarding the DDRs and the bootscript reading
from the PNX8550.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
2011-Sep-09

EN 34

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

Error 17 (Invertor or Display Supply). Here the status of


the Power OK is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark: this only
works for TV sets with an I2C controlled screen included.
Error 28 (Channel dec DVB-S). When there is no I2C
communication towards the DVB-S channel decoder,
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched on. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched on.
Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
Error 53. This error will indicate that the PNX8550 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
Error 64. Only applicable for TV sets with an I2C controlled
screen.

5.6

The Blinking LED Procedure

5.6.1

Introduction

When one of the blinking LED procedures is activated, the front


LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. n long blinks (where n = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. n short blinks (where n= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2

Use one of the following methods:


Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in normal operation
mode or automatically when the error/protection is
monitored by the Stand-by processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.6 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.

5.7

Protections

5.7.1

Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.

The blinking LED procedure can be split up into two situations:


Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table 5-2 Error code overview) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the root cause of the defective board.
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.
2011-Sep-09

How to Activate

Remark on the Supply Errors


The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Stepwise Start-up).

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Service Modes, Error Codes, and Fault Finding


5.7.2

5.8

Hardware Protections

+3V3-STANDY (3V3 nominal) is the permanent voltage,


supplying the Stand-by microprocessor inside PNX855xx.

Fault Finding and Repair Tips

+12V is considered OK (=> DETECT2 signal becomes "high",


+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesnt drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.

Supply voltage +1V1 is started immediately when +12V voltage


becomes available (+12V is enabled by STANDBY signal when
"low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched "on" by signal ENABLE-3V3 when "low", provided
that +12V (detected via 7U40 and 7U41) is present.

Ambilight

Description DVB-S2:
LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
supply voltage that feeds the outdoor satellite reception
equipment.
+3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilized at the
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilizers from +5V-DVBS that by
itself is generated via the first conversion channel of 7T03.

Audio Amplifier

At start-up, +24V becomes available when STANDBY signal is


"low" (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
inside 7T03 are activated. Initially only the 24V to 5V converter
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6T55.
After 7T03 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.

CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)

5.8.4

SSB diversities the stabilizer is 7UD2 while for the other


diversities 7UC0 is used.
+3V3 supply voltage (3V3 nominal) for 5000 series SSB
diversities, provided by 7UD3; in this case the 12V to 3V3
DC-DC converter is not present.
+5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.

Repair Tip
There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
also behaves similar.

The Class D-IC 7D10 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.
5.8.3

EN 35

Due to degeneration process of the LEDs fitted on the ambi


module, there can be a difference in the colour and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted.
5.8.2

5.

The only real hardware protection in this chassis appears in


case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
7D10; see diagram B03A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).

Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info.
5.8.1

Q551.2E LA

DC/DC Converter
Description basic board

If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present.

The basic board power supply consists of 4 DC/DC converters


and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
+1V1 supply voltage (1.15V nominal), for the core voltage
of PNX855xx, stabilized close to the point of load;
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
+1V8 supply voltage, for the DDR memories and DDR
interface of PNX855xx.
+3V3 supply voltage (3.30V nominal), overall 3.3 V for
onboard ICs, for non-5000 series SSB diversities only.
+5V (5.15V nominal) for USB, WIFI and Conditional
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer.

Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power on via the mains cord,
presuming that the stand-by microprocessor and the external
supply are operational. Take STANDBY signal "high"-to-"low"
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes "low") then +1V1 is started immediately.
After ENABLE-3V3 goes "low", all the other supply voltages
should rise within a few milliseconds.
Tips
Behaviour comparison with a reference TV550 platform
can be a fast way to locate failures.
If +12V stays "low", check the integrity of fuse 1U40.
Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits

The linear stabilizers are providing:


+1V2 supply voltage (1.2V nominal), stabilized close to
PNX855xx device, for various other internal blocks of
PNX855xx; SENSE+1V2 signal provides the needed
feedback to achieve this.
+2V5 supply voltage (2.5V nominal) for LVDS interface and
various other internal blocks of PNX855xx; for 5000 series

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2011-Sep-09

EN 36

5.8.5

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

between any power rail and ground or between +12V and


any other power rail.
Short circuit at the output of an integrated linear stabilizer
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.

Uart loggings reporting fault conditions, error messages, error


codes, fatal errors:
Some failures are indicated by error codes in the logging,
check with error codes table (see Table 5-2 Error code
overview).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).

I2C bus error mentioned as e.g.: I2C bus 4 blocked.


Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
codes settings => e.g. DVBS2Suppoprted : False/True.
In the Uart log startup script we can observe and check the
enabled loaded option codes.

Exit Factory Mode


When an F is displayed in the screens right corner, this
means the set is in Factory mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the VOLUME minus button on the TVs local keyboard for 10
seconds (this disables the continuous mode).
Then push the SOURCE button for 10 seconds until the F
disappears from the screen.

5.8.6

No startup will end up in a blinking LED status : error


LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM
solder paths short).
Error LAYER 2 = 15 (hardware cause) is more related to
a supply issue while error LAYER 2 = 53 (software cause)
refers more to boot issues.

Defective sectors (bad blocks) in the Nand Flash can also be


reported in the logging.

Logging

Startup in the SW upgrade application and observe the Uart


logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM.Progress is shown in the logging as follows:
cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
40505344 of 40607744 bytes programmed.

When something is wrong with the TV set (f.i. the set is


rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UARTcable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file Q55X.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the Display Option Code (useful when there is no picture),
look for item DisplayRawNumber in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.

Startup in Jett Mode:


Check Uart logging in Jet mode mentioned as : JETT UART
READY.
Uart logging changing preset:
=> COMMAND: calling DFB source = RC6, system=0, key = 4.

5.8.8

Loudspeakers
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!

5.8.9

Power Supply
In case of no picture when CSM (test pattern) is activated and
backlight doesnt light up, its recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).

5.8.10 Display option code


5.8.7

Guidelines Uart logging


Attention: In case the SSB is replaced, always check the
display option code number (group 2, first number e.g. 44855)
in SAM, even when picture is available. Performance with the
incorrect display option code can lead to unwanted side-effects
for certain conditions.

Description possible cases:


Uart loggings are displayed:
When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The PNX855xx is able to read and write in the DRAMs.
We can not yet conclude : Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM erros, read/write speed and timing
control.

Also supported in this chassis:


While in the download application (start up in TV mode + OK
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).
5.8.11 Additional information for replacing the ceramic heatsink
application on the PNX85500

No Uart logging at all:


In case there is no Uart logging coming out, check if the
startup script can be send over the I2C bus (3 trials to
startup) + power supplies are switched on and stable.

2011-Sep-09

When replacing the PNX85500, ensure that the ceramic


heatsink is replaced as follows:

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Service Modes, Error Codes, and Fault Finding

Q551.2E LA

5.

EN 37

Clean the PNX85500 top side with dust-free and


Isopropanol or similar cleaning agent.
Remove liner from double sided tape (inner pad and outer
ring).
Position heatsink on the IC by means of a jig. Tolerances
+/- 1 mm in all directions; angle +/- 2 degrees. Orientation
and location according to figure 5-11 Heatsink application.
Dimensions measured from the centre of the heatsink.
Press the heatsink with a pressure of 4kg during a minimal
duration of 5 seconds. Sufficient board support should be
present during mounting and pressing.
- Apply force gradually
- Use full heatsink area to apply force.
- Equipment should fulfil strain gage measurement
requirements.
Mount spring and press pushpins through the board.
Double check correct mounting of pushpins (touch-up,
package operator).
Attention points:
A removed or touched heatsink should be replaced by a
new heatsink or by a cleaned one with new thermal pad.
The top side of the IC needs to be cleaned and free of any
old glue residues before replacing the heatsink.
Handling boards by means of the heatsink is never allowed
and should be avoided during the entire process.

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2011-Sep-09

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

119.850 mm

EN 38

105.345 mm
19050_077_110506.eps
110810

Figure 5-11 Heatsink application

2011-Sep-09

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Service Modes, Error Codes, and Fault Finding


5.8.12 SSB Replacement

Q551.2E LA

5.

EN 39

For a more general overview of steps to follow, refer to figure


5-14 SSB replacement flowchart.

Follow the instructions in the flowchart in case a SSB has to be


exchanged. See table 5-3 SSB replacement instructions.

Table 5-3 SSB replacement instructions

Step #

Action to do

Advise / Attention points / Remarks

Ensure ESD protection by using a wristband

If SSB is still functional: Go via SAM to upload to USB and copy Personal
settings - Option codes - Alignments (Presets) - Set Identification.
Advice: because of differences in memory allocation, it is advised to upgrade
main SW before copying data from existing SSB. Copy of Preset list is
possible from normal user interface.

Upload to USB: A directory repair will be created on the USB, and all data will be copied in this
directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the
program map table, so it is advised to reinstall the programs from Virgin mode instead of using
copy via USB.

Disconnect set from mains and from antenna.

Safety and ESD!

Open the set and disconnect LVDS flat cable. Disconnect other cables /
connections.

Always take care for ESD! Be extra careful when removing connectors!

Dismount the (defective) SSB from the set.

Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-12 and Figure 5-13.

Place new SSB in the set, and fixate/mount carefully.

Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-12 and Figure 5-13.

Connect PSU and other connectors. Insert the optional WiFi module.

Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the
optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this
case do a trial without WiFi module.

Connect LVDS connector(s).

Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage
the LCD display. Check if flat cables are fitted correctly before closing the connector lock.

Connect set to mains and switch TV On.

Check start-up of the set, backlight switch On

10

If the set does not start (or reboots) check:


- The connectors from the power supply,
- The power supply cable and connection pins,
- LVDS cable connection.

Power supply connector must snap into the socket.

11

Before programming the new SSB, upgrade to latest software. If set is starting Some SSBs will start-up in software upgrade mode, and software needs to be installed before you
up in software upgrade mode, then first install new software via software
can program the Display Option codes. Its adviced to use an autorun.upg file for software
Upgrade Menu or via the autorun.upg file.
upgrade, this in case you have no OSD on the screen.

12

If set is starting up without picture or menu (OSD), first program the correct
Display Option codes.

13

Go to SAM and program Set type and Serial number. This is possible via Programming Set type and Serial number is mandatory to have all functionality of the set, like
the NVM editor and virtual keyboard. In case personal settings were
DLNA, Net TV For certain sets you may need to use ComPair for this.
recovered from the defective SSB, you can use an Upload from USB.

14

Check if option codes are correct, and keys are present. SSBs with integrated Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.
TCON needs TCON alignment in SAM.

15

Update to latest software (Standby and main software). This step is necessary Even when the SSB already has the latest software, it is mandatory to upgrade again the software
to make sure that the (optional) 200 Hz T-CON board has the latest software. to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated
software is loaded, from the main processor via the LVDS connection, to upgrade the
200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is
available. See General Service info GSC_85590.

16

Once the set is playing, check cable connection between PSU and SSB, by
moving the cable if there are no bad connections.

17

Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the At Your Service web portal).
and TV serial number.

18

Install presets or check if all presets are OK. Check in CSM if Type number,
Serial number, Main and Standby software are correct.

19

Check connectivity to Net TV and DLNA. Check AmbiLight functionality.

Only for sets having these functionalities.

20

Inform customer about Memory Card, USB, or Hard drive PVR (Personal
Video Recording) recordings.

Inform customer that previous recordings made on Memory Card (movie download), USB, or Hard
drive will be lost. USB or Hard drive needs to be re-formatted and matched with new SSB (WDRM
Keys!).

Use blind service mode 062598 + Home button, directly followed by the
Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.

Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give
reboots.

Special attention for Standby software: check if Standby software ID is matching with the D-RAMs
mounted on the SSB (2 Elpida = 73, 4 Elpida = 64, 2 Hynix = 72, 4 Hynix = 63).

SSB fixation points

Significant risk of damaging the board


by the fixation point
Blue arrows: traces of friction
Red arrows: damaged components

19070_201_110728.eps
110804

19070_202_110728.eps
110804

Figure 5-12 Mounting attention points [1/2]

Figure 5-13 Mounting attention points [2/2]

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2011-Sep-09

EN 40

5.

Service Modes, Error Codes, and Fault Finding

Q551.2E LA

In st ru ct io n n o t e SSB rep lacem en t Q55x.x

ST AR T

Before starting:
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in
case there are more than one "autorun.upg" files on the USB stick.

Set is still oper ating?


No
Yes

C onnect the U SB stick to the set,


go to SAM and save the current TV settings via Upload to USB

1. D ismount the defective SSB.


2. Replace the SSB by a Service SSB.

Start-up the set


Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback).
No pictur e displayed

1) Start up the TV set, equiped with the Service SSB,


and enable the UART logging on the PC.

Set behaviour?

Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen

2) The TV set will start-up automatically in the


download application if main TV software is not loaded.

3) Plug the prepared USB stick into the TV set. Follow the
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.

1) Plug the USB stick into the TV set and select


the autorun .upg file in the displayed browser.

2) Now the main software will be loaded automatically,


supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.

5) Wait until the message Operation successful ! is logged in


the UART log and remove all inserted media. Restart the TV set.

3) Wait until the message Operation successful ! is displayed


and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to


Standby
(= validation of code)

No

Connect PC via the ComPair interface to Service connector.

Restart the set

Saved settings
on USB stick?

Yes

Start TV in Jett mode (DVD I + (OSD))


Open ComPair browser Q54x

Go to SAM and reload settings


via Download from USB function.

In case of settings reloaded from USB, the set type,


serial number, display 12 NC, are automatically stored
when entering display options.

Program set type number, serial number, and display 12 NC


Program E - DFU if needed.
If not already done:
Check latest software on Service website.
Update main and Stand-by software via USB.

Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.

- Check if correct display option code is programmed.


- Verify option codes according to sticker inside the set.
- Default settings for white drive > see Service Manual.

Check and perform alignments in SAM according to the


Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.


Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End

Q55x.E SSB Board swap ER on behalf of VDS


Updated 28-07-2011

19070_200_110728.eps
110728

Figure 5-14 SSB replacement flowchart

2011-Sep-09

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Service Modes, Error Codes, and Fault Finding

Q551.2E LA

5.

EN 41

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the


RED LED is continuous on.

An F is displayed (and the HDMI 1


input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds
- Press the SOURCE button for 10 seconds until the F disappears
from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced


with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct


disabling of the Factory mode.

Program display option code


via 062598 MENU, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering display option code, the set is


going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-15 SSB replacement flowchart - Factory mode

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2011-Sep-09

EN 42

5.

Q551.2E LA

Service Modes, Error Codes, and Fault Finding

18753_211_100811.eps
110810

Figure 5-16 SSB start-up

5.9

Software Upgrading

For the correct order number of a new SSB, always refer to the
Spare Parts list!

Attention!
Software version numbers for 2011 sets are all defined below
number 0.40.x.x. This might confuse servicers who store
software versions for more than one set and/or platform on the
same storage device (USB stick).

5.9.2

Introduction
The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.

2011-Sep-09

The UpgradeAll.upg file is only used in the factory.

Automatic Software Upgrade


In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the AUTORUN.UPG
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The autorun.upg file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy AUTORUN.UPG to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.

Always check the latest software version on the servicer


website in relation to the correct CTN!!!
5.9.1

Main Software Upgrade

Manual Software Upgrade


In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the OK button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use

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Service Modes, Error Codes, and Fault Finding


a TV remote in DVD mode). Keep the OK button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.

Q551.2E LA

5.

EN 43

http://www.p4c.philips.com
(Software for servicers only)
FPGA dimming software.
FPGA 21/9 Scaler software (no software version
supported in CSM!).
FRC-V software.
FPGA HDR software.
FPGA Lattice backlight software.
FPGA C-balancer software.
FPGA PQ software.

Attention!
In case the download application has been started manually,
the autorun.upg will maybe not be recognized.
What to do in this case:
1. Create a directory UPGRADES on the USB stick.
2. Rename the autorun.upg to something else, e.g. to
software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.

5.9.6

UART logging 2K10 (see section 5.8 Fault Finding and


Repair Tips, 5.8.6 Logging)

Back-up Software Upgrade Application


If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.
5.9.3

Stand-by Software Upgrade via USB


In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbyFactory_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

5.9.4

Content and Usage of the One-Zip Software File


Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
BLCtrlFPGA_Q55X_x.x.x.x_prod.zip. (Only applicable
for 32PFL9606X/XX). Contains the BLCtrlFPGA software
(sw version nummer can not be retrieved from the set) in
upg format.Attention : no mains interruption allowed
during the upgrade process (upgrade not full proof).
FUS_Q555X_x.x.x.x_prod.zip. Contains the
autorun.upg which is needed to upgrade the TV main
software and the software download application.
StandbySW_Q555X_x.x.x.x_prod.zip. Contains the
StandbyFactory software in upg format.
ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
NVM are overwritten here.

5.9.5

FPGA software releases.


You can download all available FPGA software releases
according latest updates from the Servicer Network support
located on website:
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2011-Sep-09

EN 44

6.

Q551.2E LA

Alignments

6. Alignments
Index of this chapter:
6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes

6.1

General Alignment Conditions

6.3.1

Perform all electrical adjustments under the following


conditions:
Power supply voltage (depends on region):
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
EU: 230 VAC / 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
US: 120 VAC / 60 Hz ( 10%).
Connect the set to the mains via an isolation transformer
with low internal resistance.
Allow the set to warm up for approximately 15 minutes.
Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heat sinks as ground.
Test probe: Ri > 10 M, Ci < 20 pF.
Use an isolated trimmer/screwdriver to perform
alignments.

White Point

Contrast

100

Brightness

50

Colour

Light Sensor

Off

Picture format

Unscaled

Picture Setting
Dynamic Contrast

Off

Dynamic Backlight

Off

Colour Enhancement

Off

Gamma

Go to the SAM and select Alignments-> White point.

White point alignment LCD screens:


Use a 100% white screen (format: 720p50) to the HDMI
input and set the following values:
Colour temperature: Cool.
All White point values to: 127.

First, set the correct options:


In SAM, select Option numbers.
Fill in the option settings for Group 1 and Group 2
according to the set sticker (see also paragraph 6.4
Option Settings).
Press OK on the remote control before the cursor is
moved to the left.
In submenu Option numbers select Store and press
OK on the RC.
OR:
In main menu, select Store again and press OK on
the RC.
Switch the set to Stand-by.
Warming up (>15 minutes).

In case you have a colour analyser:


Measure, in a dark environment, with a calibrated
contactless colour analyser (Minolta CA-210 or Minolta
CS-200) in the centre of the screen and note the x, y value.
Change the pattern to 90% white screen. If a Quantum
Data generator is used, select the GreyAll test pattern at
level = 230.
Adjust the correct x, y coordinates (while holding one of the
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
values - LED - Minolta CA-210, or 6-2 White D alignment
values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy:
0.002.
Repeat this step for the other colour temperatures that
need to be aligned.
When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
NVM.
Restore the initial picture settings after the alignments.

Hardware Alignments
Not applicable.

6.3

In menu Picture, choose Pixel Precise HD and set


picture settings as follows:

Alignment Sequence

6.2

Choose TV menu, Setup, More TV Settings and then


Picture and set picture settings as follows:

Picture Setting

6.1.1

EU/AP-PAL models: a PAL B/G TV-signal with a signal


strength of at least 1 mV and a frequency of 475.25 MHz
US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).
LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).

Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
White point
Ambilight.

Table 6-1 White D alignment values - LED - Minolta CA-210

To store the data:


Press OK on the RC before the cursor is moved to the
left
In main menu select Store and press OK on the RC
Switch the set to stand-by mode.

Cool (9800K)

Normal (8250K)

Warm (6190K)

0.280

0.291

0.318

0.293

0.308

0.341

Table 6-2 White D alignment values - LED - Minolta CS-200

For the next alignments, supply the following test signals via a
video generator to the RF input:

2011-Sep-09

Value

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Value

Cool (11000K)

Normal (9000K)

Warm (6500K)

0.276

0.287

0.313

0.282

0.296

0.329

Alignments

6.3.2

e.g. 32PFL9606x
R

Normal

127

116

113

Cool

124.

115.

126

Warm

127

105

72

Table 6-4 White tone default setting 37" (Oscar)


White Tone

e.g. 37PFL9606x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

Table 6-5 White tone default setting 46" (Oscar)


White Tone

e.g. 46PFL9706x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

EN 45

White Tone

e.g. 50PFL7956x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

Ambilight
Every ambient light module is aligned by a matrix and by the
brightness. After replacement of a module, the brightness/color
can be adjusted with the neighbouring modules. (attention! :
this alignment is only supported for modules stuffed with the
storage device).
1. Go to SAM.
2. Select Alignments.
3. Select Ambilight. A white test pattern shall be displayed
by the ambilight modules.
4. Select the number of the module that have to be aligned.
Module 1 is the first one which will come across according
the wiring path, starting at the small signal panel,
proceeding towards the ambient light modules.The first
module will be attached to the next module 2. Module
number 2 to number 3 etc.Herewith the way to define the
ambilight module numbering.
5. Align the brightness compaired with the neighbouring
modules. The brightness is automatically stored.
6. Select one of 10 matrixes which color matches most with
the neighbouring modules, matrix 0 is the factory
alignment and can always be retrieved. (see table 6-11
Overview matrix correction table
7. The alignment is stored automatically (tip : dont switch off
the set immediately after the alignment is done, automatic
storage can require a time frame of 10 seconds).

Table 6-3 White tone default setting 32" (Oscar)

Colour Temp

6.

Table 6-10 White tone default setting 50" (Sundance)

If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
Set the RED, GREEN and BLUE default values according
to the values in Table 6-3.
When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments.

White Tone

Q551.2E LA

Table 6-6 White tone default setting 52" (Oscar)

Table 6-11 Overview matrix correction table

White Tone

e.g. 52PFL9606x

Matrix #

fR

fG

Colour Temp

Matrix 0

fB
1

Normal

t.b.d.

t.b.d.

t.b.d.

Matrix 1

0.95

0.95
0.95

Cool

t.b.d.

t.b.d.

t.b.d.

Matrix 2

0.95

Warm

t.b.d.

t.b.d.

t.b.d.

Matrix 3

0.95

0.95

Matrix 4

0.95

Matrix 5

0.95

Matrix 6

0.95

Matrix 7

0.97

0.95

Matrix 8

0.97

0.95

Matrix 9

0.95

0.97

Table 6-7 White tone default setting 58" (Oscar)


White Tone

e.g. 58PFL9956x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

Table 6-8 White tone default setting 40" (Cannes)


White Tone

e.g. 40PFL8606x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

6.3.3

TCON alignment (not applicable)

6.4

Option Settings

6.4.1

Introduction
The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address.

Table 6-9 White tone default setting 46" (Cannes)


White Tone

e.g. 46PFL86x6x

Colour Temp

Normal

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

Notes:
After changing the option number(s), save them by
pressing the OK button on the RC before the cursor is
moved to the left, select STORE in the SAM root menu and
press OK on the RC.
The new option setting is only active after the TV is
switched off / stand-by and on again with the mains
switch (the NVM is then read again).

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2011-Sep-09

EN 46
6.4.2

6.

Q551.2E LA

Alignments

Dealer Options

After a SSB repair, the original channel map can be restored,


provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
result of the defect. The procedure of channel map cloning is
clearly described in the (electronic) user manual.

For dealer options, in SAM select Dealer options.


See Table 6-12 SAM mode overview.
6.4.3

(Service) Options

In case of a display replacement, reset the Operation hours


display to 0, or to the operation hours of the replacement
display.

From 2011 onwards, it is not longer possible to change


individual option settings in SAM. Options can only be changed
all at once by using the option codes as described in section
6.4.4.
6.4.4

Opt. No. (Option numbers)


Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or option byte) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
Example: The options sticker gives the following option
numbers:
08192 00133 01387 45160
12232 04256 00164 00000
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specifications, Diversity, and
Connections.

6.4.5

Option Code Overview


Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!

6.5

Reset of Repaired SSB


A very important issue towards a repaired SSB from a Service
repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
00PF0000000000 and Production code 00000000000000.
Also the virgin bit needs to be set. To set all this, you can use
the ComPair tool or use the NVM editor and Dealer options
items in SAM (do not forget to store).
After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the Net TV feature and
access to the Net TV portals. The loading of the CTN and
production code can also be done via ComPair (Model number
programming).

2011-Sep-09

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Alignments
6.5.1

Q551.2E LA

6.

EN 47

SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of the correct Service SSB is the one
preceded by the letter S in case 2 or more ordering numbers
are present on the bar code sticker.

18310_221_090318.eps
090319

Figure 6-1 SSB identification

6.6

Total Overview SAM modes


Table 6-12 SAM mode overview
Main Menu

Sub-menu 1

Sub-menu 2

Hardware Info

A. SW version

e.g. Q5551_0.9.1.0

Sub-menu 3

B. Stand-by processor version e.g. STDBY_83.84.0.0


C. Production code

Description
Display TV & Stand-by SW version and CTN serial
number

e.g. see type plate

Operation hours

Displays the accumulated total of operation hours.TV


switched on/off & every 0.5 hours is increase one

Errors

Displayed the most recent errors

Reset error buffer


Alignment

Clears all content in the error buffer


White point

Colour temperature

Normal
Warn

3 different modes of colour temperature can be


selected

Cool
White point red

LCD White Point Alignment. For values,


see Table 6-3 White tone default setting 32" (Oscar)

White point green


White point blue
Ambilight

Select module
Brightness
Select matrix

Dealer options

Virgin mode

Off/On

Select Virgin mode On/Off. TV starts up / does not


start up (once) with a language selection menu after
the mains switch is turned on for the first time (virgin
mode)

E-sticker

Off/On

Select E-sticker On/Off (USPs on-screen)

Auto store mode

None
PDC/VPS
TXT page
PDC/VPS/TXT

Option numbers

Group 1

e.g. 00008.00001.15421.02239

The first line (group 1) indicates hardware options 1


to 4

Group 2

e.g. 44816.34311.33024.00000

The second line (group 2) indicates software options


5 to 8

Store

Store after changing

Initialise NVM

N.A.

Store

Select Store in the SAM root menu after making any


changes

Operation hours display

Software maintenance

Software events

0003

In case the display must be swapped for repair, you


can reset the Display operation hours to 0. So,
this one does keeps up the lifetime of the display
itself (mainly to compensate the degeneration
behaviour)

Display

Display information is for development purposes

Clear
Test reboot
Test cold reboot
Test application crash
Hardware events

Display

Display information is for development purposes

Clear

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2011-Sep-09

EN 48

6.

Q551.2E LA

Alignments

Main Menu

Sub-menu 1

Sub-menu 2

Test setting

Digital info

Current frequency: 538

Sub-menu 3

QAM modulation: 64-qam

Description
Display information is for development purposes

Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency

000

Install start frequency from 0 MHz

Install end frequency

999

Install end frequency as 999 MHz

Digital only
Digital + Analogue

Select Digital only or Digital + Analogue before


installation

Display parameters DISPT5.0.9.29

Display information is for development purposes

Default install frequency


Installation
Development file
versions

Development 1 file version

Acoustics parameters ACSTS


5.0.6.20
PQ - TV550 1.0.27.22
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.5.2
Development 2 file version

12NC one zip software

Display information is for development purposes

Initial main software


NVM version Q55x1_0.4.5.0
Flash units software
Temp com file version none
Upload to USB

Channel list

Item Channel list removed from the user interface

Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB

Channel list

Item Channel list removed from the user interface

Personal settings
Option codes
Alignments
Identification data
All (options included)
NVM editor

2011-Sep-09

Type number

see type plate

Production code

see type plate

NVM editor; re key-in type number and production


code after SSB replacement

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Circuit Descriptions

Q551.2E LA

7.

EN 49

7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 DC/DC Converters
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.5 Front-End DVB-S(2) reception
7.6 HDMI
7.7 Video and Audio Processing - PNX855xx
7.8 Back-End Processing

7.1

The Q551.2E LA chassis comes with the following stylings:


Cinema 21:9 Gold (series 50PFL8956 & 50PFL7956),
Cannes (series 4xPFL86x6),
Design Line Contour (series 46PFL8906),
Oscar (series xxPFL9606),
Cinema 21:9 Platinum (58PFL9956).

Notes:
Only new circuits (circuits that are not published recently)
are described.
Figures can deviate slightly from the actual situation, due
to different set executions.
For a good understanding of the following circuit
descriptions, please use the wiring-, block- (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.

7.1.1

TV550 2011 Architecture Overview


For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 2011 architecture
can be found in Figure 7-1 and Figure 7-2.

FLASH
512MB

DDR2
4x 128MB-533

Introduction

DVB-T (EU)
DVB-C (EU+HK)

DVB-T2

Hybrid
Tuner
DVB-S2
Tuner

NXP
PNX85500
SOC

DVB-S2

PWM

Back
light

Backlight dimming
Goggle drive

LR

Active 3D

9287
mux

AL

CPLD

USB

CLASS-D
Int-USB

LCD

I2C Enable FRED

32

SPI

Wifi

3D
Dongle

8x PWM

HUB

buffer
CI

USB
USB

SD-CARD

Ethernet
PHY
19050_078_110506.eps
110506

Figure 7-1 Architecture of TV550 platform 2011 (32" Oscar)

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2011-Sep-09

EN 50

7.

Q551.2E LA

Circuit Descriptions

19070_102_110720.eps
110720

Figure 7-2 Architecture of TV550 platform 2011 (remaining sets)

2011-Sep-09

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Circuit Descriptions
7.1.2

Q551.2E LA

7.

EN 51

SSB Cell Layout

19050_079_110506.eps
110506

Figure 7-3 SSB layout cells (top view) (32" Oscar)

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2011-Sep-09

EN 52

7.

Q551.2E LA

Circuit Descriptions

19051_168_110810.eps
110810

Figure 7-4 SSB layout cells (top view) (remaining sets)

2011-Sep-09

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Circuit Descriptions
7.2

Power Supply

7.2.1

Power Supply Unit

EN 53

Connector

In this manual, no detailed information is available because of


design protection issues.
Connector overview
Table 7-1 Connector overview 32" sets
Connector
no.

1308

1316

Descr.

Mains

to display

to SSB

Pin

CN1

CN2

CN4

A2

+3V3SB

n.c.

Standby

pin 5

GND1

no.

1308

1316

1M95

Descr.

Mains

to display

to SSB

Pin

CN1

CN2

CN4

Anode 1+

+3V3stdby

n.c.

Standby

Cathode 1-

GND1

n.c.

GND1

Anode 2+

+12V

n.c.

+12V

Cathode 2-

+Vsnd (+24V)
GND_SND

n.c.

Anode 3+

BL-ON-OFF

10

n.c.

BL-DIM1 (Vsync)
BL-I-CTRL

11

Cathode 3-

12

n.c.

POK

13

Anode 4+

+24V (AL2_DVBS)

14

n.c.

GND1

15

Cathode 4-

1M95

n.c.

GND1

pin 3

+12V3

n.c.

+12V3

OCD

+Vsnd

n.c.

GND1

A1

BL-ON-OFF

10

n.c.

BL-DIM1

11

pin 13

BL-I-CTRL

12

n.c.

POK

13

pin 11

+24V

14

n.c.

GND1

15

GND1

Table 7-4 Connector overview 50" Sundance sets


Connector

Table 7-2 Connector overview 37" sets


Connector
no.

7.

Table 7-3 Connector overview 40 - 46" sets

All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Philips Service web portal for the order codes of the
boards.

7.2.2

Q551.2E LA

1308

1316

Descr.

Mains

to display

to SSB

Pin

CN1

CN2

CN4

Anode_R

+3V3stdby

n.c.

Standby

R5 Cathode

GND1

R4 Cathode

GND1

R3 Cathode

+12V

R2 Cathode

+12V

R1 Cathode

+Vsnd (+24V)

L1 Cathode

GND_SND

L2 Cathode

BL-ON-OFF

10

L3 Cathode

BL-DIM1 (Vsync)

11

L4 Cathode

BL-I-CTRL

12

L5 Cathode

POK

13

n.c.

+24V (AL2_DVBS)

14

Anode_L

GND1

15

no.

1308

1319

1M95

Descr.

Mains

to display

to SSB

Pin

CN1

CN3

CN4

24Vled

+3V3stdby

24Vled

Standby

24Vled

GND1

24Vled

GND1

24Vled

+12V

GND1

+12V

GND1

+Vsnd

GND1

GND_SND

GND1

BL-ON-OFF

10

GND1

BL-DIM1 (Vsync)

11

n.c.

BL-I-CTRL

12

BL-ON-OFF

POK

13

n.c.

+24V (AL2_DVBS)

14

BL-DIM1

GND1

15

1M95

Table 7-5 Connector overview 52" sets


Connector

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no.

1308

1316

1319

Descr.

Mains

to display

to display

1M95
to SSB

Pin

CN1

CN2

CN3

CN4

24V

24V

+3V3stdby

24V

24V

Standby

24V

24V

SGND

24V

24V

SGND

24V

24V

+12V

SGND

SGND

+12V

SGND

SGND

+24V

SGND

SGND

SGND

SGND

SGND

BL-ON

10

SGND

SGND

BL-DIM

11

n.c.

n.c.

BL-I-CTRL

12

BL-ON

n.c.

POK

13

n.c.

+24V)

14

n.c.

SGND

15

2011-Sep-09

EN 54

7.

Q551.2E LA

Circuit Descriptions

Table 7-6 Connector overview 58" sets

Connector
no.

1308

1316

1319

1M95

Descr.

Mains

to display

to display

to SSB

Pin

CN1

CN4

CN3

CN5

V01

V02

+3V3stdby

V01

V02

PS-ON

V01

V02

SGND

V01

V02

SGND

V01

V02

SGND

V01

V02

+12V3

V01

V02

+12V3

V01

V02

+12V3

V01

V02

24VA

10

V01

V02

SGND

11

V01

V02

n.c.

12

V01

V02

13

V01

V02

14

V01

V02

15

the switching frequency of the +5V-DVBS to +1-DVBS


switched mode converter is 900 kHz (item no. 7T00)
a delay line for the +2V5-DVBS and +1V-DVBS lines is
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
a 3.3V to 2.5V linear stabiliser is built around item no. 7T01
a 5V to 3.3V linear stabiliser is built around item no. 7T02.

Diagram B08B contains the DVB-S2 LNB supply:


the +V-LNB signal comes from item no. 7T03
the V0-CTRL signal goes to item no. 7T03
the LNB-RF1 goes to the LNB.
Figures gives a graphical representation of the DC/DC
converters with its current consumptions:
+ 5V 5-TUN
196 m A
+ 5V
dc -dc

+ 12V
2919 m A

7.3

+ 3V 3
dc -dc

+ 5V 5-TUN

+ 5V
2179 m A

+ 3V 3

+ 3V 3
2371 m A

+ 5V -TUN
s tabiliz er

+ 2V 5
s tabiliz er

+ 5V -TUN
196 m A

+ 2V 5
450 m A

DC/DC Converters
+ 1V 8
dc -dc

The on-board DC/DC converters deliver the following voltages


(depending on set execution):
+3V3-STANDBY, permanent voltage for the Stand-by
controller, LED/IR receiver and controls; connector 1M95
pin 1
+12V, input from the power supply for TV550 common
(active mode); connector 1M95 pins 6, 7 and 8
+24V, input from the power supply for DVB-S2 (in active
mode); connector 1M09 pins 1 and 2
+1V1, core voltage supply for PNX855xx; has to be started
up first and switched "off" last (diagram B03B)
+1V2, supply voltage for analogue blocks inside PNX855xx
+1V8, supply voltage for DDR2 (diagram B03B)
+2V5, supply voltage for analogue blocks inside PNX855xx
(see diagram B03E)
+3V3, general supply voltage (diagram B03E)
+5V, supply voltage for USB and CAM (diagram B03E)
+5V-TUN, supply voltage for tuner (diagram B03E)
+V-LNB, input voltage for LNB supply IC (item no. 7T50)
+5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
+3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder
+2V5-DVBS, clean voltage for DVB-S2 channel decoder
+1V-DVBS, core voltage for DVB-S2 channel decoder.

+ 1V 1
dc -dc

+ 1V 8

+ 1V 8
2450 m A

+ 1V 2
s tabiliz er

+ 1V 2
550 m A

+ 1V 1
5100 m A

18770_226_100127.eps
100426

Figure 7-5 DC/DC converters

7.4

Front-End Analogue and DVB-T, DVB-C;


ISDB-T reception

7.4.1

European/China region
The Front-End for the European/China region consist of the
following key components:

A +12 V under-voltage detector (see diagram B03C) enables


the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
Stand-by microcontroller and ENABLE-3V3n is the signal
coming from the Stand-by microcontroller.

Hybrid Tuner
Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)
Bandpass filter
Amplifier
PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this


region.

Diagram B03D contains the following linear stabilisers:


+2V5 stabiliser, built around item no. 7UCO
+5V-TUN stabiliser, built around items no. 7UA6 and 7UA7
+1V2 stabiliser, built around items no. 7UA3 and 7UA4.
Diagram B08A contains the DVB-S2-related DC/DC
converters and -stabilisers:
a +24V under-voltage detection circuitry is built around
item no. 7T04
the switching frequency of the 24 to 14...20V switched
mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
the output signal on the +V-LNB line goes to the LNBH23Q
(item no. 7T50)
the LNBH23Q (item no. 7T50) sends a feedback signal via
the V0-CNTRL line
2011-Sep-09

18770_235_100127.eps
100219

Figure 7-6 Front-End block diagram European/China region

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Circuit Descriptions
7.5

Q551.2E LA

7.

EN 55

Front-End DVB-S(2) reception


The Front-End for the DVB-S(2) application consist of the
following key components:

Satellite Tuner; I2C address 0xC6 (bridged via channel


decoder)
Channel decoder; I2C address 0xD0
LNB switching regulator; I2C address 0x14
Amplifier
PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for


DVB-S(2) reception.

18770_243_100203.eps
100203

Figure 7-8 HDMI input configuration


The following multiplexers can be used:
Sil9187A (does not support Instaport technology for fast
switching between input signals)
Sil9287B (supports Instaport technology for fast
switching between input signals).
The hardware default I2C addresses are:
Sil9187A: 0xB0/0xB2 (random: software workaround)
Sil9287B: 0xB2 (fixed).

18770_237_100127.eps
100219

Figure 7-7 Front-End block diagram DVB-S(2) reception


This application supports the following protocols:
Polarization selection via supply voltage (18V = horizontal,
13V = vertical)
Band selection via toneburst (22 kHz): tone on = high
band, tone off = low band
Satellite (LNB) selection via DiSEqC 1.0 protocol
Reception of DVB-S (supporting QPSK encoded signals)
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
32APSK encoded signals), introducing LDPC low-density
parity check techniques.

7.6

The Sil9x87 has the following specifications:


+5V detection mechanism
Stable clock detection mechanism
Integrated EDID
RT control
HPD control
Sync detection
TMDS output control
CEC control
EDID stored in Sil9x87, therefore there are no EDID pins
on the SSB.

HDMI
7.7

In this platform, the Silicon Image Sil9x87 HDMI multiplexer is


implemented. Refer to figure 7-8 HDMI input configuration for
the application.

Video and Audio Processing - PNX855xx


The PNX855xx is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:

Multi-standard digital video decoder (MPEG-2, H.264,


MPEG-4)
Integrated DVB-T/DVB-C channel decoder
Integrated CI+
Integrated motion accurate picture processing (MAPP2)
High definition ME/MC
2D LED backlight dimming option
Embedded HDMI HDCP keys
Extended colour gamut and colour booster
Integrated USB2.0 host controller
Improved MPEG artefact reduction compared with
PNX8543
Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions,


such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
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2011-Sep-09

EN 56

7.

Circuit Descriptions

Q551.2E LA

and vivid colour management. High flat panel screen


resolutions and refresh rates are supported with formats
including 1366 768 @ 100Hz/120Hz and 1920 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
that, optional support is available for 2D dimming in

PNX85500x

DVB

For a functional diagram of the PNX855xx, refer


to Figure 7-9.

MEMORY
CONTROLLER

TS input

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

combination with LED backlights for optimum contrast and


power savings up to 50%.

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

SSIF, LR

DIGITAL IF

MPEG/H.264
VIDEO
DECODER

VIDEO
ENCODER

analog CVBS

AUDIO DACS

analog audio

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

AUDIO IN

SPDIF

AUDIO DSP
AUDIO OUT
HDMI
RECEIVER

HDMI

450 MHz
AV-DSP
560 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I 2S
SPDIF

DRAWING
ENGINE

DMA BLOCK

I2C

PWM GPIO

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x8
Card

18770_241_100201.eps
100219

Figure 7-9 PNX855xx functional diagram

7.8

Back-End Processing
All sets except the 32" Oscar have a back-end board. For the
configuration, refer to Figure 7-10 to Figure 7-13.

2011-Sep-09

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Circuit Descriptions

DDR2
1 64MB-800

Q551.2E LA

7.

EN 57

DDR3
LR

I2C
Mux

I2C -Set
ENABLE-DCDC
SPLASH-ON
BL-ON
SPI/Vsync
Sound in stand
detection

Back -end
Board
FPGA + FRC-V

LCD
FPGA
BL

Backlight

Trident
FRC-V

Vx1/LVDS Connector

Vsync, LR

8 Vx1

1F53

3D-LED

LVDS Connector

Dual LVDS

FPGA LX25
2D/3D or 3D/3D
Local Contrast
Int Dongle

2 128MB-1333

1W35
19051_169_110810.eps
110810

Figure 7-10 Back-end board Oscar except 37"

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2011-Sep-09

7.

Q551.2E LA

Circuit Descriptions

DDR2
1 64MB-800

DDR3

BL-PWM

3D-LED

LVDS Connector

Dual LVDS

FPGA LX25
2D/3D or 3D/3D
Local Contrast
Int Dongle
Backlight

2 128MB-1333

8 LVDS

LR

Vsync, LR

8 mini LVDS

TCON
IC

Trident
FRC-V

FPGA
Backlight

LCD

EN 58

I2C
Mux

Sound in stand
detection

Backlight

5 BL PWM

1M54

Back -end
Board
FPGA + FRC-V

PSU

I2C -Set
ENABLE-DCDC
SPLASH-ON
BL-ON

1W35
19051_170_110810.eps
110810

Figure 7-11 Back-end board Oscar 37"

DDR2
1 64MB-800

DDR3

3D-LED

LR

Trident
FRC-V

FPGA
Backlight

I2C
Mux

LCD

Vsync, LR

8 Vx1

Vx1/LVDS Connector

BL-PWM

LVDS Connector

Dual LVDS

FPGA LX25
2D/3D or 3D/3D
Local Contrast
Int Dongle
Backlight

2 128MB-1333

Sound in stand
detection

Backlight

8 BL PWM

PSU

Back -end
Board
FPGA + FRC-V

1M54

I2C -Set
ENABLE-DCDC
SPLASH-ON
BL-ON

1W35
19051_171_110810.eps
110810

Figure 7-12 Back-end board Cannes


2011-Sep-09

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Circuit Descriptions

DDR2
1 64MB-800

Q551.2E LA

LVDS Connector

DDR3
LR

EN 59

4 HS LVDS

I2C
Mux

LCD

Trident
FRC-V+
LVDS Connector

LVDS Connector

FPGA LX25
2D/3D or 3D/3D
Local Contrast

2 128MB-1333

Dual LVDS

7.

Enable LGD
2D Dimming

Backlight

Sound in stand
detection

Back -end
Board
FPGA + FRC-V

PSU

BL-PWM

1M95

I2C -Set
ENABLE-DCDC
SPLASH-ON
BL-ON

1W35
19051_172_110810.eps
110810

Figure 7-13 Back-end board Sundance

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2011-Sep-09

7.

Circuit Descriptions

Q551.2E LA

1M54

1F53

I/O

1M09
(4p)

(9p TH)

1M99
(10p)

1T03

1M85

DC/DC

1M84

EN 60

1M83

BL
FPGA

DDR 2
512M

DDR

DDR
DDR

DC/DC
RB4+
LVDS
REC

GPIO

RA0WX0-

WX2+

GPIO

PQ
FPGA

LVDS
TRANS
W

LVDS
TRANS
W

Trident
FRC-V
27x27
1.0

1T20

1T02

1SG2

1T51: 51pin

1T25

I/O

1G51: 51pin

1W35

1T01

19051_173_110810.eps
110810

Figure 7-14 Back-end layout cells (top view) Oscar except 37" & Cannes

2011-Sep-09

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Circuit Descriptions

1M99
(10p)

1W35

1M54

1T25

I/O

(9p TH)

1T03

Q551.2E LA

1T02

7.

EN 61

1G51: 51pin

1M09

1F53

BL
FPGA

DDR

DDR

DDR 2
512M

DDR

Trident
FRC-V
27x27
1.0

RB4+
LVDS
REC

DC/DC

RA0GPIO

WX2+

GPIO

PQ
FPGA

LVDS
TRANS
W

LVDS
TRANS
W

WX0-

DC/DC +
DC/DC
TCON

1SG2

1T01

TCON IC LG

I/O

1L02: 80pin

1L01: 80pin

19051_174_110810.eps
110810

Figure 7-15 Back-end layout cells (top view) Oscar 37"

1W35

DC/DC

1T25

DDR

LVDS
TRANS
W

WX2+

1S
G2
1T51

1G51

1T50

DDR

1T02

Trident
FRC-V
27x27
1.0

DDR

WX0LVDS
TRANS
W

DC/DC

GPIO

1M99
(10p TH) (VDISP)

KEEPOUT

LVDS
REC

RA0-

RB4+

DDR

PQ
FPGA

GPIO

1M09

19051_175_110810.eps
110810

Figure 7-16 Back-end layout cells (top view) Sundance


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2011-Sep-09

EN 62
7.9

7.

Circuit Descriptions

Q551.2E LA

AmbiLight
For the configuration, refer to Figure 7-17 to Figure 7-18.

Microprocessor

Glue
logic

1
M
5
9

1
M
8
3

AmbiLight

1
M
8
4

1
M
8
3

AmbiLight

1
M
8
4

1
M
8
3

SSB

AmbiLight

1
M
8
4

optional

19052_003_110907.eps
110907

Figure 7-17 High-level architecture AmbiLight 2-/3-sided (12-V implementation)

19052_004_110907.eps
110907

Figure 7-18 Low-level architecture AmbiLight 2-/3-sided (12-V implementation)

2011-Sep-09

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IC Data Sheets

Q551.2E LA

8.

EN 63

8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as black boxes in the

Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To Upstream
VBUS

Upstream
USB Data

To EEPROM or
SMBus Master

24 MHz
Crystal

SDA SCL

3.3 V

BusPower
Detect/
Vbus Pulse

Upstream
PHY

Regulator

Serial
Interface

PLL

Serial
Interface
Engine

Repeater

3.3 V

...

TT
#1

Regulator

Controller

TT
#x

Port
Controller

CRFILT

Routing & Port Re-Ordering Logic

Port #1
PHY#1

OC Sense
Switch Driver/
LED Drivers

...

Port #x
OC Sense
Switch Driver/
LED Drivers

PHY#x

USB Data
OC
Port
Downstream Sense Power
Switch/
LED
Drivers

OC
USB Data
Port
Downstream Sense Power
Switch/
LED
Drivers

The x indicates the number of available downstream ports: 2, 3, 4, or 7.

NC

NC

NC

21

19

SCL / SMBCLK / CFG_SEL[0]

24

20

HS_IND / CFG_SEL[1]

25

VDD33

RESET_N

26

SDA / SMBDATA / NON_REM[1]

VBUS_DET

27

Pinning information

22

The LED port indicators only apply to USB2513i.

23

SUSP_IND / LOCAL_PWR / NON_REM[0]

28

18

NC

VDD33

29

17

OCS_N[2]

USBDM_UP

30

16

PRTPWR[2] / BC_EN[2]*

USBDP_UP

31

15

VDD33

XTALOUT

32

14

CRFILT

XTALIN / CLKIN

33

13

OCS_N[1]

PLLFILT

34

12

PRTPWR[1] / BC_EN[1]*

11

TEST

10

VDD33

9
NC

6
NC

5
VDD33

4
USBDP_DN[2]

NC

3
USBDM_DN[2]

36

VDD33

35

Ground Pad
(must be connected to VSS)

USBDP_DN[1]

RBIAS

SMSC
USB2512/12A/12B
USB2512i/12Ai/12Bi
(Top View QFN-36)

NC

Note :

USBDM_DN[1]

8.1

electrical diagrams (with the exception of memory and logic


ICs).

Indicates pins on the bottom of the device.

18770_301_100217.eps
100217

Figure 8-1 Internal block diagram and pin configuration


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2011-Sep-09

EN 64
8.2

8.

IC Data Sheets

Q551.2E LA

Diagram Temperature sensor & AmbiLight B01J, LM75BDP (IC 7FD1)

Block diagram
VCC

LM75B
BIAS
REFERENCE

POINTER
REGISTER

CONFIGURATION
REGISTER

BAND GAP
TEMP SENSOR

COUNTER

TEMPERATURE
REGISTER

TIMER

TOS
REGISTER

COMPARATOR/
INTERRUPT

THYST
REGISTER

11-BIT
SIGMA-DELTA
A-to-D
CONVERTER

OSCILLATOR

POWER-ON
RESET

OS

LOGIC CONTROL AND INTERFACE

A2

A1

A0

SCL SDA

GND

Pinning information

SDA

VCC

SCL

A0

A1

A2

OS

GND

LM75BDP

18770_300_100217.eps
100217

Figure 8-2 Pin configuration

2011-Sep-09

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IC Data Sheets
8.3

Q551.2E LA

8.

EN 65

Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)

Block diagram
PNX8550x

MEMORY
CONTROLLER

TS input

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder

DVB

AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

MULTISTANDARD
VIDEO
DECODER

DIGITAL IF

Direct-IF

SPDIF

AUDIO IN

HDMI

HDMI
RECEIVER

analog CVBS

AUDIO DACS

analog audio

analog Y/C

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

SSIF, LR

VIDEO
ENCODER

AUDIO DSP
AUDIO OUT
450 MHz
AV-DSP
500 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I2S
SPDIF

DRAWING
ENGINE
Scatter/Gather
TS Demux

I2C

PWM Px_x

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x 10
Card

Pinning information
ball A1
index area

PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Transparent top view
18770_308_100217.eps
100217

Figure 8-3 Internal block diagram and pin configuration

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2011-Sep-09

EN 66
8.4

8.

IC Data Sheets

Q551.2E LA

Diagram Audio B03A, TPA312xD2PWP (IC7D10)

Block diagram
TPA3120D2
1 F

0.22 F
LIN

BSR

RIN

ROUT

1 F

22 H

0.68 F

PGNDR

0.68 F

PGNDL

1 F
BYPASS
AGND

470 F

LOUT
22 H

BSL

470 F

0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
Control

SD

1 F

MUTE

GAIN0
GAIN1

Control

Pinning information
PWP (TSSOP) PACKAGE
(TOP VIEW)

PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
I_18020_142.eps
100402

Figure 8-4 Internal block diagram and pin configuration

2011-Sep-09

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IC Data Sheets
8.5

Q551.2E LA

8.

EN 67

Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1

28

NC

27

LL1

EN1

26

DRVL1
PGND1

DRVH1

25

24

TRIP1

NC

23

VIN

22

VREG5

GND

TEST1

NC

TPS53124

VO1
VFB1

21

V5FILT

20

TEST2
TRIP2

VFB2

10

19

VO2

11

18

PGND2

17

DRVL2

EN2

12

NC

13

16

LL2

VBST2

14

15

DRVH2

18310_300_090319.eps
100416

Figure 8-5 Internal block diagram and pin configuration

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2011-Sep-09

EN 68
8.6

8.

IC Data Sheets

Q551.2E LA

Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Block diagram

ST1S10PH

Pinning information

DFN8 (4 4)

PowerSO-8
I_18010_083.eps
110601

Figure 8-6 Internal block diagram and pin configuration

2011-Sep-09

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IC Data Sheets
8.7

Q551.2E LA

8.

EN 69

Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-7 Internal block diagram and pin configuration

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2011-Sep-09

EN 70
8.8

8.

IC Data Sheets

Q551.2E LA

Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

Block diagram
MODE0
MODE1
MODE2
nRST

MODE Control

AutoNegotiation

10M Tx
Logic

Reset
Control

SMI

RMIISEL

HP Auto-MDIX

10M
Transmitter

TXP / TXN

Transmit Section
100M Tx
Logic

Management
Control

RXP / RXN

100M
Transmitter
MDIX
Control

TXD[0:3]
TXEN
TXER
TXCLK

CRS
COL/CRS_DV

RMII / MII Logic

RXD[0:3]
RXDV
RXER
RXCLK

100M Rx
Logic

DSP System:
Clock
Data Recovery
Equalizer

PLL

Analog-toDigital

XTAL2

Interrupt
Generator

nINT

100M PLL

Receive Section

LED Circuitry
10M Rx
Logic

Squelch &
Filters
10M PLL

MDC
MDIO

XTAL1/CLKIN

LED1
LED2

Central
Bias

RBIAS

PHY
Address
Latches

PHYAD[0:2]

RBIAS

RXP

RXN

TXP

TXN

VDD1A

RXDV

TXD3

32

31

30

29

28

27

26

25

Pinning information

VDD2A

24

TXD2

LED2/nINTSEL

23

TXD1

LED1/REGOFF

22

TXD0

21

TXEN

20

TXCLK

19

nRST

18

nINT/TXER/TXD4

17

MDC

13

14

15

16

RXER/RXD4/PHYAD0

CRS

COL/CRS_DV/MODE2

MDIO

VSS
12

VDDIO

RXD3/PHYAD2

10

11

RXD0/MDE0

VDDCR
RXCLK/PHYAD1

RXD1/MODE1

RXD2/RMIISEL

XTAL2
XTAL1/CLKIN

SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)

18770_302_100217.eps
100217

Figure 8-8 Internal block diagram and pin configuration

2011-Sep-09

back to
div. table

IC Data Sheets
8.9

Q551.2E LA

8.

EN 71

Diagram HDMI B04D, SII9x87B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps
100217

Figure 8-9 Internal block diagram and pin configuration

back to
div. table

2011-Sep-09

EN 72

8.

IC Data Sheets

Q551.2E LA

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Block diagram
VDD 8

VDD/2
2

IN 1

BYPASS

VO1 1

TPA6111A2
6

IN 2

SHUTDOWN

VO2 7

Bias
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1
IN1
BYPASS
GND

VDD
VO2
IN2
SHUTDOWN
18770_309_100217.eps
110602

Figure 8-10 Internal block diagram and pin configuration

2011-Sep-09

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div. table

IC Data Sheets

Q551.2E LA

8.

EN 73

8.11 Diagram DVBS-FE B07A, STV6110AT (IC 7R02)

Block diagram
STV6110AT

RF_OUT
IP

RF_IN

IN
QP
AGC
QN
PLL, dividers
XTAL_IN
XTAL_INN

DC offset compensation
SCL
I2C bus interface

Amplifier

SDA

XTAL_OUT

18770_304_100217.eps
110601

Figure 8-11 Internal block diagram and pin configuration

back to
div. table

2011-Sep-09

EN 74

8.

IC Data Sheets

Q551.2E LA

8.12 Diagram DVBS supply B08A, TPS54283PWP (IC 7T03)

Block diagram
TPS54283PWP
CLK1

Level
Shift

+
4
+
FB1

BOOT1

PVDD1

SW1

Current
Comparator

f(IDRAIN1) + DC(ofst)
GND

2
BP

R
R

f(IDRAIN1)

Overcurrent Comp

0.8 VREF

RCOMP
Soft Start
1

SD1

f(ISLOPE1)

BP

f(IMAX1)
CLK1

CCOMP

Anti-Cross
Conduction

VDD2

Weak
Pull-Down
MOSFET

f(ISLOPE1)
Ramp
Gen 1
TSD

6 A
EN1

EN2

1.2 MHz
Oscilator

6 A

CLK1

Divide
by 2/4

f(ISLOPE2)
Ramp
Gen 2

SD1
Internal
Control

SD2

CLK2

UVLO
150 k
SEQ 10

BP
150 k

FB1
FB2

CLK2

Output
Undervoltage
Detect

13 BOOT2
BP

Level
Shift

14 PVDD2

f(IDRAIN2) + DC(ofst)

Current
Comparator
+

GND

4
+

FB2

R
R

FET
Switch

f(IDRAIN2)

Overcurrent Comp

0.8 VREF

RCOMP
Soft Start
2

SD2

f(ISLOPE2)

CLK2

CCOMP

5.25-V
Regulator

BP 11
150 k

12 SW2
BP

f(IMAX2)

Anti-Cross
Conduction

Weak
Pull-Down
MOSFET

PVDD2

BP
ILIM2

Level
Select

9
150 k

0.8 VREF
References
IMAX2 (Set to one of two limits)
UDG-07007

18770_305_100217.eps
110601

Figure 8-12 Internal block diagram and pin configuration

2011-Sep-09

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div. table

IC Data Sheets

Q551.2E LA

8.

EN 75

8.13 Diagram DVBS supply B08B, LNBH23Q (IC 7T50)

Block diagram
ISEL

TTX

ADDR

SDA SCL

Vcc

LX
PWM
Controller

Rsense

Byp

Vcc- L

Preregulator
+U.V.lockout
+P.ON reset
EN
VSEL

P-GND

VSEL
EN

TTX
ITEST

Vup

I2C interface

VOUT Control
TEN

Linear Post-reg
+Modulator
+Protections
+Diagnostics

VoRX

I2C Diagnostics

VoTX
TTX

22KHz
Oscill.

22KHz Tone
Amp. Diagn.

EXTM

22KHz Tone
Freq. Detector

DETIN

DSQOUT

DSQIN

LNBH23

V CTRL

A-GND

Pinning information
1 n.c .
2 n.c .
3 n.c .
4 LX
5 P -G ND
6 S DA
7 n.c .
8 n.c .
9 S CL
10 A D D R
11 D S Q out
12 D S Q IN
13 E XTM
14 TTX
15 B Y P
16 n.c .
17 n.c .
18 V c c -L
19 V c c
20 A -G N D
21 V oR X
22 V oTX
23 n.c .
24 n.c .
25 n.c .
26 n.c .
27 V up
28 IS E L
29 D E TIN
30 V CTRL
31 n.c .
32 n.c .

Epad

Connected with power grounds and to


the ground layer through vias
to dissipate the heat.

18770_306_100217.eps
100217

Figure 8-13 Internal block diagram and pin configuration

back to
div. table

2011-Sep-09

EN 76

8.

Q551.2E LA

IC Data Sheets

Personal Notes:

10000_012_090121
110

2011-Sep-09

back to
div. table

Block Diagrams

Q551.2E LA

9.

EN 77

9. Block Diagrams
9-1 Wiring diagram Oscar 32"
WIRING DIAGRAM 32" OSCAR
1M84
26P

AL

1M83
26P

AMBILIGHT MODULE

1M84
26P

AL

(1070)

1M83
26P

AMBILIGHT MODULE
(1072)

8684

8683
8395
1M84
26P

1M84
26P

8354
8324

8584

8309
1M54
9P

1M54
9P

1W35
3P

1319
12P

1M95
14P

4P
1M09

1316
10P

LCD DISPLAY
(1004)

1H95
14P

1H99
4P

1H59
26P

1H24
4P

SSB
3104 313 6538.x
(1011)

MAIN POWER SUPPLY

AL
8583

8121

WIFI-MODULE

8801

(1042)

8408

INLET

(8408)

8802
8120
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND

IR/LED/KEYBOARD

W WIFI
(1040)

1H95 (B11B)

(1010)

1M20
11P

MAINS
SWITCH

2P3
1308

8735
1M83
26P

1M83
926

TO STAND

1M21
18P

8151

(1075)

1735
4P
1G51
51P

(1073)

AL

AMBILIGHT MODULE

8150

AMBILIGHT MODULE

1G50
41P

32" PSLC-P019A
(1050)

1M22
11P
1M21
18P

UD

3D TRANSMITTER
(1002)

1M54 (B11B)
1.
2.
3.
4.
5.
6.
7.
8.
9.

GND
BL-DIM5
BL-DIM6
BL-DIM7
BL-DIM8
BL-DIM9
BL-DIM10
BL-DIM11
BL-DIM12

W WIFI
(1041)
1M21 (B09A)

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.

1H24 (B11B)
1.
2.
3.
4.
5.
6.

+3V3-1
USB-WIFI-DDn
USB-WIFI-DDp
GND
GND
GND

1H99 (B11B)
1.
2.
3.
4.

GND_AL_BRG
+12V_AL_BRG
GND_AL_BRG
+12V_AL_BRG

2011-Sep-09 back to

div. table

1W35 (B11B)
1. GND
2. N.C.
3. AUDIO-SPEAKERn

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1.
2.
3.
4.
5.
6.
7.
8.
9.

LIGHT-SENSOR
LED-1
LED-2
GND
KEYBOARD
+3V3-STANDBY
RC
+5V
N.C.

10. GND
11. N.C.
12. N.C.
13. N.C.
14. GND
15. N.C.
16. 3D-LED
17. N.C.
18. N.C.

1H59 (B11B)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP-1

15. GND_AL_BRG
16. GND_AL_BRG
17. GND_AL_BRG
18. GND_AL_BRG
19. GND_AL_BRG
20. N.C.
21. +12V_AL_BRG
22. +12V_AL_BRG
23. +12V_AL_BRG
24. +12V_AL_BRG
25. +12V_AL_BRG
26. +12V_AL_BRG

19050_036_110421.eps
110801

Block Diagrams

Q551.2E LA

9.

EN 78

9-2 Wiring diagram Oscar 37"

WIRING DIAGRAM 37" OSCAR


1M83

1M84
26p

AMBILIGHT MODULE
(1072)

26p

AL

8683

26p

AMBILIGHT MODULE
(1073)

26p

1M83

8584

8M09

1M84

LCD DISPLAY
(1004)

8684

26p

1M83

26p

AL

1M83

1M84

26p

8316
8395
8324

1M54
9p

1316
14 p

1M99
10p

1M95
14 p

1M95
14 p

0
104

1M09
4p

8395

1M99
4p

1M59
26p

fi (
Wi

1F24
5p

AL

1735
4p

8583

(1)

8M99

SSB
3104 313 6539.x
(1011)

1M54
9p

1M99
10p

1G51
51p

1G51
51p

1W35
3p

AMBILIGHT MODULE
(1075)

Main Power Supply


(1050)

AL

AMBILIGHT MODULE
(1070)

8M54

Bolt On
(1030)

1M21
18p

FB

2p3
1308

MAINS
SWITCH

INLET

TO
STAND

8735

8408

80p
1L02

80p
1L01

1M84

8121

8801

8152

8154
8802
18p
1M20

Led & Control (1010)


15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

11p

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

1M21

8120

W
1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

Wifi
(1040)

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

2011-Sep-09 back to

div. table

3D Transmitter (1002)

1M20

1735 (B03]A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

11p

W
1M21 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET

Wifi
(1041)

10. GND
11. SDA-SET
12. NC
13. NC
14. GND
15. NC
16. 3D-LED
17. NC
18. NC

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

19050_082_110727.eps
110728

Block Diagrams

Q551.2E LA

9.

EN 79

9-3 Wiring diagram Oscar 46"

WIRING DIAGRAM 46" OSCAR


1M84

26p

AMBILIGHT MODULE

AL (1070)

1M83

1M84

26p

26p

1M83

26p

AMBILIGHT MODULE

AL (1072)

8683

CN3
50p

CN4
50p

CN5
50p

CN6
50p

1M09

LCD DISPLAY
(1004)

12p
1316

26p

14p
1319

CN7
50p

1M85
26p
4p

CN2
50p

1M84

8584
CN1
50p

26p

1M83

8582
8684

26p
1M83

15p

ALD

DC/DC
(1051)
26p
1M84

8580

8319
8316

1M95
14p

8F53

1M59
26p

1F24
5p

8309
8399

AMBILIGHT MODULE
(1073)

1M09

8581
10p
1M99

AL

Bolt On
(1030)

FB
8395

1735
4p

14 p
1M95

3p
1W35

1M21

8152

8151

1G51
51p

51p
1G51

18p

Main Power Supply


(1050)

51p
1T51

26p

26p

8735

2p3

Wifi (1042)

8801

1G51
51p

1308

1M83

INLET

TO
STAND

LCD DISPLAY
(1004)

MAINS
SWITCH

1M84

SSB
3104 313 6539.x
(1011)

4p

AMBILIGHT MODULE

14p

1316
12p

AL (1075)

1M99
10p

1F53
15p
1319

8408

8802

8121

3D Transmitter

Wifi
(1040)

Led & Control (1010)

1M20
11p

1M21 18p
1M20

8120

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

1735 (B03]A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

UD (1002)

11p

Wifi
(1041)

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

1M21 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET

10. GND
11. SDA-SET
12. NC
13. NC
14. GND
15. NC
16. 3D-LED
17. NC
18. NC

19050_080_110725.eps
110728

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 80

9-4 Wiring diagram Oscar 52"


WIRING DIAGRAM 52" OSCAR
1M84

26p

AL

1M83

1M84

1M83

26p

26p

26p

8684

AMBILIGHT MODULE
(1072)

AL

AMBILIGHT MODULE
(1071)

1M84

8683

1M83

26p

26p

AL

AMBILIGHT MODULE
(1070

1M84

26p

1M83

26p

1M84

26p

1M83

26p

1M83

26p

8584
8685

CN1

CN2

CN3

CN4

CN5

CN6

CN7

CN8

50p

50p

50p

50p

50p

50p

50p

50p

LCD DISPLAY
(1004)

8582

AL

1M85

8316
8309

26p
4p

8319

1M09

AMBILIGHT MODULE
(1075)

15p
I 2S

12p
1316

ALD

AL

26p
1M83
1319
12p

1316

1M09

14p

4p

AMBILIGHT MODULE
(1073)

14p
1319

DC/DC
(1051)
26p
1M84

26p

1M84

8580
8F53
10p

1M99

8324

8M99

8581
8395

8687

14p

1M95

1M95

10p

1M59
26p

14p

1F24

8686

1M99

1F53
15p

5p

FB

26p

1M83

Main Power Supply


(1050)
Bolt On
(1030)

51p
1T51

51p
1G51

3p
1W35

1735

51p

AMBILIGHT MODULE
(1074)

AMBILIGHT MODULE
(1076)

AL

1G51

8G51

AL

1M21

18p

8T51

2p3

26p

LCD DISPLAY
(1004)

Wifi (1042)

8735

1308

1G51
G
51p

TO
STAND

8802

0
I

INLET

8408
MAINS
SWITCH

1M84

SSB
3104 313 6539.x
(1011)

4p

8801

8121

Led & Control (1010)

18p

1M20

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

Wifi
(1040)

11p

3D Transmitter (1002)

1M21

1M20

11p

Wifi
(1041)

8120
15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

1M21 (B09A)
1. LIGHT-SENSOR 10. GND
2. LED-1
11. SDA-SET
3. LED-2
12. NC
4. GND
13. NC
5. KEYBOARD
14. GND
6. +3V3-STANDBY 15. NC
7. RC
16. 3D-LED
8. +5V
17. NC
9. SCL-SET
18. NC

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

2011-Sep-09 back to

div. table

1735 (B03]A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

19050_092_110825.eps
110907

Block Diagrams

Q551.2E LA

9.

EN 81

9-5 Wiring diagram Oscar Platinum 58"


WIRING DIAGRAM 58" OSCAR PLATINUM
1M84
26p

AMBILIGHT MODULE
(1072)

AL

1M83

1M84

26p

26p

1M84

1M83

AL

26p

AMBILIGHT MODULE
(1071)

26p

8584

CN5

CN1

50p

1319

1316

8323

25p

14p

14p
1319

1319
14p

3p

50p

50p

LCD DISPLAY
(1004)

14p
1316

8320

8322
1322

CN4

CN3

50p

8321

8316
8319

CN2

50p

14p

AMBILIGHT MODULE
(1073)

14p
1316

CN4
50p

LCD DISPLAY
(1004)

1L11

AMBILIGHT MODULE
(1075)

CN3
50p
15p
I 2S

AL

50p

25p

14p
1319

CN2

50p

1L12

3p
1322

CN1

1316
14p

1MP1
8p

AL

8N99

ALD

1M99
10p

1F53
15p

8N09
DC/DC
(1051)

1M84

26p

8N95

26p

9p

1M95
14p

11p

1N95
1N09

8687

51p
1T51

Main Power Supply


(1050)

8M09

51p
1G51

1M84

26p

8G51

8301
1M99
9p

26p

8M95

8686

1M99
10p

8M99

4p

26p

Bolt On
(1030)

1M83

1N99

4p

1M09

FB

Wifi (1042)

1M83

26p

AMBILIGHT MODULE
(1070)

8685

1M09
4p

1M84

AL

8683

8684

1M83

1M83

26p

8T51
1M95
14 p

1M99
4p

1M59
26p

1F24
5p

1M95
11p
1MP1

1G51

8P

SSB
3104 313 6539.x
(1011)

1735

51p

13

08

1M84

26p

1M83

2p3

18p

8735

(5212)

1G51

(5211)

1M21

LCD DISPLAY
(1004)

4p

AL

8801

AMBILIGHT MODULE
(1074)

AMBILIGHT MODULE
(1076)

AL

8802

8581

Woofer L

Woofer R

8408

8121

MAINS
SWITCH

Tweeter

Tweeter

INLET
11p

1M20

Led & Control (1010)

1M21
1M20

18p
11p

3D Transmitter (1002)

8120

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

Wifi
(1040)

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

1735 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

2011-Sep-09 back to

div. table

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

Wifi
(1041)

1M21 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET

10. GND
11. SDA-SET
12. NC
13. NC
14. GND
15. NC
16. 3D-LED
17. NC
18. NC

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

19050_088_110727.eps
110728

Block Diagrams

Q551.2E LA

9.

EN 82

9-6 Wiring diagram Cannes 40 - 46"

WIRING DIAGRAM 40- 46" CANNES

LCD DISPLAY
(1004)

1319
10p

1316
12p

1M54
9p

1M83

26p

1M84

26p

1M99
10p

8395
1M95
14p

1M95
14p

8M54

26p

4p

8584

1M09

1M83

8309

1M99
4p

1M59
26p

1F24
5p

8M99
Main Power Supply
(1050)

1M54
9p

1M99
10p

1735

4p

1G51

51p

8735

From SSB
51p
1G51

1M21

2p3
To TCon
51p
1T51

18p

Bolt On
(1030)

AMBILIGHT MODULE
(1075)

AL

FB

SSB
3104 313 6539.x
(1011)

AL

AMBILIGHT MODULE
(1073)

3p
1W35

1308

8G51

8T51

8735

8408

8583

1G51

LCD DISPLAY
(1004)
TO
STAND

INLET

8121

51p

Wifi (1042)

MAINS
SWITCH

8735
0

1M84

8802

8801

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

1M21 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET

10. GND
11. SDA-SET
12. NC
13. NC
14. GND
15. NC
16. 3D-LED
17. NC
18. NC

11p

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

Led & Control (1010)

18p
1M21
1
M2
1M20
1
M2
11p

1M20

Wifi
(1040)

3D Transmitter (1002)

8120

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

2011-Sep-09 back to

div. table

1735 (B03]A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

Wifi
(1041)

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

19050_090_110728.eps
110728

Block Diagrams

Q551.2E LA

9.

EN 83

9-7 Wiring diagram Sundance 50"

WIRING DIAGRAM 50" SUNDANCE

1319
14p

14p

26p

30 p

1M83

30 p

1M84

8399

8319

26p

1M83

26p

8584

8324
8395

8M99
1M99
10p

LCD DISPLAY
(1004)

1M95
14p

1M99
10p

1M59
26p

1F24
5p

1M95
14p

Main Power Supply


(1050)

1M99
4p

FB
Bolt On
(1030)

SSB
3104 313 6539.x
(1011)

8583

1735 1D38
3p
4p

1T50
41p

1M21
18p

8149

1G51
51p

1G51

2p3

8150

1308

AL

AMBILIGHT MODULE
(1074)

AMBILIGHT MODULE
(1076)

AL

1M09
4p

Woofer (5211)

1T51
51p

8151

1G51
51p

Wifi (1042)

INLET

1M21
18p

1G50
41p

8408

8120

11p
1M20

1M84

8801

Tweeter R (5221)

LCD DISPLAY
(1004)

Tweeter L (5221)
8121

8802

MAINS
SWITCH

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. NC
21. AMBI-POWER
22. AMBI-POWER
23. AMBI-POWER
24. AMBI-POWER
26. AMBI-POWER
26. AMBI-POWER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

1F24 (B01C)
1. +3V3-1
2. USB-WIFI-DDn
3. USB-WIFI-DDp
4. GND
5. GND
6. GND

1M20

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT_G1
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

11p

Led & Control (1010)

Wifi
(1041)

Wifi
(1040)

1D38 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1735 (B03]A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

2011-Sep-09 back to

div. table

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
|
51. N.C.

1M21 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET

10. GND
11. SDA-SET
12. NC
13. NC
14. GND
15. NC
16. 3D-LED
17. NC
18. NC

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY-1
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND-AUDIO
9. LAMP-ON-1
10. BACKLIGHT-PWM_BL-VS-1
11. BACKLIGHT-BOOST-1
12. POWER-OK-1
13. +24V
14. GND_AL

19050_081_110726.eps
110728

Block Diagrams

Q551.2E LA

9.

EN 84

9-8 Block Diagram Video


VIDEO
B01A

COMMON INTERFACE

B02

1P00
17
51
52

7F01
74LVC245APW
20

VIDEO OUT - LVDS

N.C.

7S00
PNX85537EB
+3V3

68P

PCMCIA

B06B

PNX85500

+5VCA

18

50
I2C

B02A VIDEO STREAM

MDO(0-7)

CA-MDO(0-7)

BUFFER

MD0

CA-MDI(0-7)

49

LAMP-ON
B03C
BACKLIGHT-PWM_BL-VS
B03C
CTRL-DISP
B02G
3D-LED
B09A
SPLASH-ON
B02G

B02F LVDS
CONDITIONAL
ACCESS

1G51
51

MDI

48
47
46
45
42

TO DISPLAY
OR
BOLT-ON MODULE

40

19

QM

11

AGC

16

DVB-S
CHANNEL
DECODER

9R03-1

78
75
74

TS-DVBS-VALID
TS-DVBS-SOP
TS-DVBS-CLOCK

9R03-2

73

TS-DVBS-DATA

9R03-4

9R04

B10A

ONLY FOR TV-SETS WITH DVB-S


1T01
TH2627

RF_AGC
IF-OUT1
IF-OUT2

RF-AGC

10

TUN-IF-P

4 5F73

11

TUN-IF-N

1
2

2F90

1F75

B04D

IF-P-DVBT2

2F78

IF-P-DVBT2

3F79-4

26

DRX2DRX1+

25
24

AVI-B

20

AV1-CVBS

DRX1DRX0+

23
RXD
22

DRXC+

20

12

DRXC-

19

19

20

72

ARX2ARX1+

71
70

ARX1ARX0+

69
RXA
68

AV1-STATUS
7E09-1

16

66

ARXC-

65

B02G
CONTROL
B02G
CONTROL

BRX2+

BRX2BRX1+

7
6

BRX1BRX0+

5
RXB
4

9
10

BRX0-

BRXC+

12

BRXC-

B04B

R-VGA

G-VGA
B-VGA
H-SYNC-VGA

3
13
14

AF16 VGA_R
AD16
VGA_G
AE16
VGA_B
AB18
HSYNC_IN
AC18
VSYNC_IN

V-SYNC-VGA

B01C

USB HUB

+5V-USB1
1P08
1

B02E CONROL

USB_DN
USB_DP

9F26

USB-DM
USB-DP

R26
R25

B01B

B02A FLASH

FLASH

7FL5
CY7C65631

7F20
H27U4G8F2DTR

NAND_CE1
NAND_RDY1
NAND_WP_

USB
HUB

17

E21 NAND-CE1n
F21 NAND-RDY1n
NAND-WPn
A21

+5V-USB2
1P07
1

9
10
5

SIDE USB
CONNECTOR

21

9
7
19

B11C

EXT 3

AC15

AV3-PR

1E03
2

AV3-Y

AE15

AV3-PB

AD15

TO WIFI MODULE
PR_R_C1

RESET-USBn

PB_B1
DDR2-D(0-31)

15
14

9
10

CRX0-

13

CRXC+

12

12

CRXC-

11

+3V3-HDMI

9,27,64

RXC

VCC33

62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N

HDMIA-RXC+
HDMIA-RXCHDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX23S0W
+3V3

W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N
W24
RREF

SDRAM
128Mx8

A1 E2
A

7B01
H5PS1G83E

SDRAM
128Mx8

A1 E2

7B02
H5PS1G83E

SDRAM
128Mx8

A1 E2

7B03
H5PS1G83E

SDRAM
128Mx8
VDDL
VREF

CRX1CRX0+

7B00
H5PS1G83E

D(24-31)

17
16

B02C HDMI_DV

VDDL
VREF

CRX2CRX1+

TO WIFI MODULE

DDR

D(16-23)

2
3
4
5

SSB 3104 313 6538.x

B05A

VDDL
VREF

18

1H24
1

B02G

Y_G1

D(8-15)

CRX2+

+3V3-1

2
3
4
5

DQ

1F24
1

13 USB-WIFI-DDn
14 USB-WIFI-DDP

+3V3

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

42

1E08

CONNECTORS

22

1E04
PR

2
3

USB2-DM
USB2-DP

+5V

A2
V1

SIDE USB
CONNECTOR

NAND
FLASH

XIO-D(00-07)

VCC
12,37
VREF_1
VREF_2

2
3

USB1-DM
USB1-DP

9F25

VDDL
VREF

1
2
19
18

ONLY FOR SSB 3104 313 6538.x

B02B MEMORY

1P02

HDMI 1
CONNECTOR

3
1

XIO_D

ANALOGUE EXTERNALS B

PB

4
6
7

PX4

1E05

VGA
CONNECTOR

1
4
6
7

CVBS1_OUT

LOUT4

VGA

10

67

B01I

15

ARX0ARXC+

IF_AGC

TO DISPLAY

18

1P03

1
2

12

AF11

CVBS-MON-OUT1

21

11

19
18

9
10

HDMI 3
CONNECTOR

19
18

7E06
EF

HDMI
SWITCH

ARX2+

TUNER_N

AC13
AV1_R
AE13
AV1_G
AD13
AV1_B
AB15
CVBS_Y1

15

SCART1

3
4
6
7

HDMI 2
CONNECTOR

7E05
EF

11

1
2

EXT 1
16

AF12

AV1-R
AV1-G

AV1-BLK

1P04

PNX-IF-N

PX3

LOUT3
TUNER_P

1E01

1
2
19
18

HDMI SIDE
CONNECTOR

BANDPASS
FILTER

AE12

ANALOGUE EXTERNALS A

DRX2+

21

1G50
41

N.C.

32

PNX-IF-P

AD12

DRX0-

B02I ANALOG VIDEO

OUT
4 IN
AGC CONTROL

9
10

TS-FE-DATA

ONLY FOR TV-SETS WITH DVB-T2

15
11

4
6
7

+VDISP

VCC

7EC1
SII9287BC

11

4 TS-FE-VALID
TS-FE-SOP
3
5 TS-FE-CLOCK
7

7F75
UPC3221GV
3F79-1

1P05

PX2

3
2

PNX-IF-AGC

B04A

HDMI

64

AGC AMPLIFIER 7

7F70

HDMI

49
50

IF-AGC

SELECT-SAW
B02E
CONTROL

B01H

DVBT2-IFN
DVBT2-IFP

DVBT2
CHANNEL
DECODER

2F74

SAW 36MHZ17

LOUT2

D(0-7)

RF IN

+5V-TUN-PIN
3

5F70

MAIN HYBRID
TUNER

TS-FE-DATA

7FJ0
CXD2820R

53

TUNER

R23 TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21 TNR_SER1_DATA

DVBT2
7FJ1

B01F

TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK

8
122
12

3 2

IM
XTAL
QP

31

IP

20
32
18

16M

1R10

30

21

PX1

3 2

DVB-S
TUNER

4
SAT IN

LOUT1

24M

1R01

7R01
STV0903BAC

7R02
STV6110A

1FL5

DVBS-FE

PNX85537

B07A

A1 E2
DDR2-A(0-14)
+1V8
DDR2-VREF-DDR
19050_006_110415.eps
110805

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 85

9-9 Block Diagram Audio


AUDIO

7F01
74LVC245APW
20

68P

B02A VIDEO STREAM

ADAC_1

19

QM

11

AGC

16

ADAC_2

DVB-S
CHANNEL
DECODER

9R03-1

78
75
74

TS-DVBS-VALID
TS-DVBS-SOP
TS-DVBS-CLOCK

9R03-2

73

TS-DVBS-DATA

9R03-4

9R04

+5V-TUN-PIN

MAIN HYBRID
TUNER
IF-OUT1
IF-OUT2

10

TUN-IF-P

4 5F73

11

TUN-IF-N

2F90

5F70

RF IN

1
1F75

2F74

2F78

DVBT2-IFN

49

DVBT2-IFP

50

DVBT2
CHANNEL
DECODER

1
2
19
18

HDMI SIDE
CONNECTOR

26

6 3F79-4

IF-P-DVBT2

BANDPASS
FILTER

PNX-IF-P

AE12

AP-SCART-OUT-L

3EA7-1

AUDIO-OUT-L

AP-SCART-OUT-R

3EA7-4

AUDIO-OUT-R

DRX2DRX1+

25
24

DRX1DRX0+

23
RXD
22

4
6
7
9
10

DRX0-

21

DRXC+

20

12

DRXC-

19

PNX-IF-N

AF12

PO_6

1
2

16
20

IF_AGC

7S05

ADAC(5)

AE6

ADAC(6)

AF6 ADAC_6

72

ARX2ARX1+

71
70

ARX1ARX0+

69
68 RXA
67

ARXC+

66

12

ARXC-

65

ARX0-

AE10 AIN1_L

AUDIO-IN1-R

AF10

15

AIN1_R

21

7E01

ARX2+

9
10

ADAC_5

AUDIO-IN1-L

A-PLOP

B04E

B04B ANALOGUE EXTERNALS B


1E08
6
AUDIO IN
L+R

AUDIO-IN3-L

AE9

AUDIO-IN3-R

AF9

AIN3_L

AUDIO-IN4-L

AD9

AUDIO-IN4-R

AC9

AB19

HEADPHONE
AMPLIFIER

ADAC3

ADAC(3)

AD6

ADAC(4)

IN-1

VO_2

AMP1

AMP2

3
1

ADAC4

IN-2

VDD

B01C USB HUB


+5V-USB1
1P08
1

USB_DN
USB_DP

R26

9F26

USB-DM
USB-DP

R25

7FL5
CY7C65631

B01B FLASH
B02A FLASH

7F20
H27U4G8F2DTR-BC

17

+5V-USB2
1P07
1

USB
HUB

10
5

18

7
6

BRX1BRX0+

5
RXB
4

NAND_CE1
NAND_RDY1
NAND_WP_

E21 NAND-CE1n
F21 NAND-RDY1n
NAND-WPn
A21

9
7
19

NAND
FLASH

B11B CONNECTORS

22
VCC

AIN4_R

BRX0-

BRXC+

21,37

+5V

+3V3

19
18

HDMI 1
CONNECTOR

CRX2CRX1+

17
16

CRX1CRX0+

15
RXC
14
13
12

12

CRXC-

11

14

AF18

P0_4

ARC-eHDMI+

5EC2

B02C HDMI_DV
W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N

HDMIA-RXC+
HDMIA-RXC-

62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N

HDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX2-

eHDMI+

2
3
4
5

3S0W
+3V3

B02G

TO WIFI MODULE

SSB 3104 313 6538.x

DDR2-D(0-31)
7B00
H5PS1G83EFR

SDRAM
128Mx8

A1 E2

7B01
H5PS1G83EFR

SDRAM
128Mx8

A1 E2

7B02
H5PS1G83EFR

SDRAM
128Mx8

A1 E2

D(24-31)

CRX0-

SEL-HDMI-ARC

DQ

VCC33

18

CRXC+

1H24
1

B05A DDR

SPDIF_OUT

D(16-23)

CRX2+

9
10

AF5

B02G STANDBY

1
4
6
7

SPDIF-OUT-PNX

1
9,27,64

TO WIFI MODULE
RESET-USBn

VDDL
VREF

1
2

+3V3-HDMI
1P02

SPDIF-OPT

7S09
2
3 &
1

VDDL
VREF

BRXC-

+3V3

+5V

42

D(8-15)

12

2
1
3

1F24
1
2
3
4
5

13 USB-WIFI-DDn
14 USB-WIFI-DDP

B02B MEMORY

VDDL
VREF

9
10

1E10

USB 2 SIDE
CONNECTOR

21

+3V3
DIGITAL
AUDIO
OUT

2
3

USB2-DM
USB2-DP

4
XIO-D(00-07)

USB 1 SIDE
CONNECTOR

7B03
H5PS1G83EFR

SDRAM
128Mx8
VDDL
VREF

BRX2BRX1+

2
3

USB1-DM
USB1-DP

9F25
RES

D(0-7)

1
2
19
18

HDMI 2
CONNECTOR

BRX2+

4
6
7

HEADPHONE
OUT 3.5mm

+3V3

B02E CONROL

XIO_D

AIN4_L

1328

SHUTDOWN
VO_1

AF7

1P03
3

TO WOOFER

B04A

1
1

B03A

A-PLOP

RESET-AUDIO

AIN3_R

1E09
VGA (OR DVI)
AUDIO

5D03

7EE0-2

TUNER_N

A-PLOP

1D38
1

7D03
STANDBY &
PROTECTION

A-STBY

7EE1
TPA6111A2DGN

SCART1

1
4
6
7
19
18

11

HDMI
SWITCH

1P04

HDMI 3
CONNECTOR

SD

TUNER_P

B02D PNX85500: AUDIO

1E01-1
3

TO SPEAKERS
(IN STAND)

B01J TEMP SENSOR + HEADPHONE


7EE0-1

AD12

B04A ANALOGUE EXTERNALS A

7D11
MAINS SWITCH
DETECT

DETECT2

RIGHT-SPEAKER

15

B04E HEADPHONE

VCC
IF-P-DVBT2

4 MUTE
OUT-R

B02I ANALOG VIDEO

AGC AMPLIFIER 7 3F79-1

1P05
DRX2+

AUDIO-MUTE-UP

ONLY FOR TV-SETS WITH DVB-T2

IN-R

B04E

RES

B02D AUDIO

AC19

B03C

PNX-IF-AGC

7EC1
SII9287BCNU

PO_7

A-PLOP

TS-FE-DATA

7F75
UPC3221GV

SELECT-SAW
B02E
CONTROL

B04D HDMI

B02G STANDBY

4 TS-FE-VALID
TS-FE-SOP
3
5 TS-FE-CLOCK

OUT
4 IN
AGC CONTROL

SAW 36MHZ17
7F70

B01H HDMI

TS-FE-DATA

A-PLOP

7FJ0
CXD2820R

ONLY FOR TV-SETS WITH DVB-S

1T01
TH2627

7D15

R23
TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21
TNR_SER1_DATA

A-STBY

B10A DVBT2

B01F TUNER

TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK

1735
1

LEFT-SPEAKER

22

8
122
12

3 2

31

IM
XTAL
QP

OUT-L

-AUDIO-R

10

16M

1R10

30

IP

20
32
18

ADAC(2)

AE7

+24V-AUDIO-POWER

SAT IN

21

5D07
10,12 5D08
1,3

PVCC_L

IN-L

PVCC_R

7R01
STV0903BAC

DVB-S
TUNER

+AUDIO-L

1FL5

1R01

14

12

ADAC(1)

AD7

MDI

PNX85537

7R02
STV6110A

CLASS D
POWER
AMPLIFIER

7S05
LM324P

MD0

CA-MDO(0-7)

BUFFER

B02D AUDIO

3 2

MDO(0-7)

CA-MDI(0-7)

B07A DVBS-FE

7D10
TPA3123D2PWP

7S00
PNX85537EB

+3V3

51
52

CONDITIONAL
ACCESS

B03A AUDIO

+5VCA

18

PCMCIA

B02D PNX85500: AUDIO

B02 PNX85500

1P00
17

24M

B01A COMMON INTERFACE

A1 E2
DDR2-A(0-14)

+1V8
W24

RREF
VREF_1
VREF_2

A2
V1

DDR2-VREF-DDR
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

19050_007_110415.eps
110728

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 86

9-10 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS

SDRAM
128Mx8

SDRAM
128Mx8

ETHERNET + SERVICE

ETH-RXD
ETH-TXD

ETHERNET

RXD
TXD

ETH-RXCLK

AA3

20

ETH-TXCLK

AA2

RXCLK

B02H POWER
AF1
VDD_1V1
AA15
VDDA_1V2

TXCLK

RESET-ETHERNETn

PNX-SPI-CLK
PNX-SPI-SDI

41

PNX-SPI-SDO

39

B02E CONTROL
B02G

CPLD

18
19
21

QP

12

QM
IP
IM

20

SENSE+1V0-DVBS

TS-DVBS-DATA

74
MULTI
11
75
STANDARD
7 DEMODULATOR 78
8 FOR SAT DIG TV 62

TS-DVBS-CLOCK

9R03-4
9R04

TS-FE-CLOCK

T22

B01F

DVBT2
49

TS-FE-VALID

DVBT2-IFP

50

TS-FE-SOP
3
DVBT2
CHANNEL 5 TS-FE-CLOCK
DECODER 7
TS-FE-DATA

RESET-SYSTEMn

COMMON INTERFACE
7F00

1P00
1
20

MOCLK

CA-MOCLK

K24

62
63

MOVAL
MOSTRT

CA-MOVAL
CA-MOSTRT

L23
L22

VS_2
MOVAL
MOSTRT
MDI

CA-MDI(0-7)
7F01

NAND
FLASH
VCC

12,37

PCMCIA

+3V3

MDO(0-7)

COMMON INTERFACE

7F20
H27U4G8F2DTR

23
29
30

AMBI-SPI-SDI-OUT_G1
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2

4
6
8

4
6
8

31

AMBI-LATCH1_G2

CONDITIONAL
ACCESS

MDO

CA-MDO(0-7)
7F02
7F03

B02A FLASH

CA-A(00-14)

XIO-A(0-15)

XIO_A

7F04
7F05

CA-D(0-7)

AD5

VCCIO

20
19
28

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS

11
12
13

11
12
13

AMBI-TEMP-1

14

3D-VS-DISP

VIO

B01C

USB HUB

R25

3D-VS

20

CH01

BL-DIM

PR3D-LED

57

4
RESET-SYSTEMn
SELECT-SAW

CONNECTORS

1M54
2

89

BL-DIM5

88

BL-DIM6

86
85
84

BL-DIM7
BL-DIM8
BL-DIM9

4
5
6

73
78

BL-DIM10
BL-DIM11

7
8

77

BL-DIM12

10

AUDIO-SPEAKERn

TO
POWER
SUPPLY

1W35
3

TO
STAND

B01F

7FL5
CY7C65631

ETHERNET + SERVICE
17

+5V-USB2
1P07
1

USB
HUB

10
5

18

Y23

RXD1-MIPS

Y24

TXD1-MIPS

SIDE USB
CONNECTOR

RES

B01K B02G

2
3

USB-DM2
USB-DP2

1E06
2

SIDE USB
CONNECTOR

21
UART
SERVICE
CONNECTOR

3
1

B11B
+5V

22

1F24
1

CONNECTORS

+3V3-1 1H24
1

2
3
4
5

13 USB-DM3
14 USB-DP3

2
3
4
5

TO WIFI MODULE

SSB 3104 313 6538.x

68

B02G

XIO-D(00-07)
B02G STANDBY

CH02

2
3

USB-DM1
USB-DP1

9F25

XIO_D

XIO-D(00-15)

B11B

+5V-USB1
1P08
1

9F26

USB-DM
USB-DP

R26

B04C

GPI0_3

TO
DISPLAY

45
42

BACKLIGHT-PWM_BL-VS

PNX85500: MIPS

AE4
RESET_SYS
U23
GPI0_11

GPI0_2

46

ONLY FOR SSB 3104 313 6538.x

B02E

USB_DN
USB_DP

48
47

3D-LR-DISP

13

14

9GA0

BACKLIGHT-PWM

27
46
51

FOR SSB 3104 313 6538.x

43
3
26

BL_PWM

53

SP3A-CSO-B
SP3A-MOSI
SP3A-MISO

TO
AMBILIGHT
MODULE

B09A

7FJ0
CXD2820R

DVBT2-IFN

B02E

B01A

FLASH

3C70

SP3A-CCLK

1
5

1H59
1

B02G

4
B01F

1M59
1

AMBI-SPI-CLK-OUT
AMBI-SPI-SDO-OUT

32
PXCLK54
PNX-SPI-CS-BLn

AC5
CLK_54_OUT
V22
GPI0_7

TNR_SER1_DATA

TNR_SER1_MICLK
R22
TNR_SER1_SOP
R23
TNR_SER1_MIVAL

TS-FE-SOP
TS-TS-VALID

9R03-1

RESET-DVBS

B10A

T21

9R03-2

TS-DVBS-SOP
TS-DVBS-VALID

52

TS-FE-DATA

27

B02G
73

LAMP-ON
B03C
BACKLIGHT-PWM_BL-VS
B03C
CTRL-DISP
B02G
3D-LED
B09A
SPLASH-ON
B02G

FPGA

CONNECTORS

22

24M

122

FLASH

B11B

CONNECTORS COMP

1FL5

XTAL

PNX85537

32

40

B02A VIDEO STREAM

7R01
STV0903BAC

SATELLITE
TUNER

B01B

B03D

PNX-SPI-CSBn

DVBS-FE

7R02
STV6110A

B08A

B03B

SENSE+1V2

25M

1E70

SENSE+1V1

B09A

7GA0
XC9572XL

100

F8 E8

512K

AMBILIGHT CPLD

B07A

F8 E8
DDR2-A(0-13)

B06C

ETHERNET
CONNECTOR
RJ45

19

F8 E8
DDR-CLK_N
DDR-CLK_P

N5
N4

PROG-B

1G51

7H08
XC3S200A
A

83

7H06
RT9818C

SDRAM
128Mx8

SDCD
SDWP

CLK_N
CLK_P

FPGA-SYS-CLK
27M

DAT_2

7E10
LAN8710A-EZK

1N00

SDRAM
128Mx8

7B03
H5PS1G83EFR

INP OUTP
3
GND

F8 E8

B04C

7B02
H5PS1G83EFR

W3
U6
V6

7B01
H5PS1G83EFR

3 2

SDIO-DAT2
SDIO-CDn
SDIO-WP

7B00
H5PS1G83EFR

W1
W5
W4

DDR2-D(0-31)

DQ

CMD
CLK
DAT_0
DAT_1

9
10
12

SDIO-DAT1

B02B MEMORY

CC_DAT3

3 2

Pin8 Pin7

Pin6 Pin5

Pin4 Pin3 Pin2

5
7
8

W2
W6

VIDEO OUR - LVDS

7GA0
XC9572XL

SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0

B06B

FPGA-BACKLIGHT DIMMING
7H05
3225

+3V3

D(24-31)

Pin1

Pin9

1
2

B11A

DDR

D(16-23)

1P09

SD-CARD
CONNECTOR

B05A

PNX85500

7S00
PNX85537EB
B02E ETHERNET

D(8-15)

B02A

SD-CARD

D(0-7)

B01D

GPIO_10

PNX85500: STANDBY CONTROLLER

B01E

9CH0

BOOST-PWM

V23

PNX85500-CONTROL
BACKLIGHT-BOOST

B06C

DC / DC
AE26

9U41

LED-2

P5_1

6
7
8
16

PWM_0

RC

SPI_CLK
P6_5

AD23

P5_0

SPI_CSB
SPI_SDO
SPI_SDI

AD23

P5_0

P3_0

AC25

KEYBOARD
+3V3-STANDBY
+5V

AD26

LED2

4
5

TO IR / LED BOARD AND


KEYBOARD CONTROL

B02G

LED1

LED-1

PWM_1

P3_1
3D-LED

P1_7
RESET_IN
P6_4

B11A
B06B

B03C
B02E
B04A
B03H
B04A

DETECT2
RESET-SYSTEMn
AV1-BLK

AB22
AD22

LCD-PWR-ONn
AV1-STATUS

AC20
AE25

AA22

P3_2
P3_3

XTAL_IN

P3_5
P2_0
CADC_2

XTAL_OUT
P1_1
P2_7
P0_6

19
18

1
2

B04D HDMI

4x HDMI
CONNECTOR

AE22
AF23
AE23
AF25

P0_7
7EC0
EF

PCEC-HDMI

ARX-HOTPLUG
1P02-19
BRX-HOTPLUG
1P03-19
CRX-HOTPLUG
1P04-19
DRX-HOTPLUG
1P05-19

41
45

HDMI
SWITCH

6
3
1
5
2

AF19

RX

HDMIA-RX

W24

RREF

+3V3-STANDBY

1F51
3
1
2
4
5

FF04

AF22

SDM
FF29

AF17

2
3

INP OUTP
GND

RESET-USBn

AD18
AD21

ENABLE-3V3n

AB19
AC19

RESET-AUDIO
AUDIO-MUTE-UP

LEVEL SHIFTED
FOR
DEBUG USE
ONLY

SPI-PROG

7S20
NCP303LSN28G

AE17

SPLASH-ON

RESET-STBYn

B01C

B03C

RES

DC / DC

+12V
+3V3-STANDBY

ENABLE-3V3-5V
ENABLE-1V8
DETECT2

B03E
B03B B03D
B02G B03A

B04E
B03A

B06B

DC/DC

1H95

1M95
10
11
9

BACKLIGHT-PWM_BL-VS-1

10
11
9

P0_4
P2_2

AF18
AE20

SEL-HDMI-ARC

P2_6

AC21

POWER-OK

12

POWER-OK

12

AF20

STANDBY

STANDBY

AA18
AE18

RESET-DVBS
RESET-ETHERNETn

P2_3
3S0W
+3V3

VCC

512K

SDM
RESET-STBYn
SPI-PROG

P1_2

B02C HDMI_DV

FLASH

TXD-UP

B03C
CEC-HDMI

7EC1
SII9187ACNU
SII9287BCNU
31
35

PNX-SPI-CLK
PNX-SPI-WPn
PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

RXD-UP

AE21
AF21
AB20
AA26

+3V3-STANDBY

PNX85500: STANDBY CONTROLLER

TO PIN:
1P02-13
1P03-13
1P04-13
1P05-13

AF24

3U42

3U43

LIGHT-SENSOR
7U43

CONTROL

B03C

1M21
1

54M

CONNECTORS COMP

1S02

B09A

7F52
M25P05-AVMN6P

P0_1
P0_3

LAMP-ON

B02D

BACKLIGHT-BOOST-1
LAMP-ON

TO
POWER
SUPPLY

B07A
B04C

ONLY FOR SSB 3104 313 6538.x


19050_019_110419.eps
110805

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 87

9-11 Block Diagram I2C


IC
B01E

PNX85500: MIPS

B01J

PNX85500-CONTROL

MAIN NVM
SW

3F64

Y24

B02I

44

DRX-DDC-SCL

RXD1-MIPS

3E53-4

3E53-3

TXD1-MIPS

3E53-2

3E53-1

1E06
3

PNX85500: ANALOG VIDEO

47

UART
SERVICE
CONNECTOR

2
1

EDID
SW

48

9FC1

VGA-SCL-EDID-HDMI

9FC3

VGA-SDA-EDID

9FC2

VGA-SCL-EDID

9FC4

RES

B06B

B26

3S58

A25

3S5W

2_SCL

3R14

3FJH

3FJJ

3T51

3T61

3R01

3R00
1P05
16

HDMI
CONNECTOR
SIDE

OPTIONAL

OPTIONAL

1E05
12
15

VGA
CONNECTOR

1G51
9S12

SDA-DISP

3G2W

50

SCL-SET

9S11

SCL-DISP

3G2Y

49

+3V3

3S81

D(24-31)

W21
GPIO_2
W22

7S01
PCA9540B

RXD2-MIPS
TXD2-MIPS

2 CHAN.
MULTIPLEX.

4
5

B11A

FPGA-BACKLIGHT DIMMING

B09A

3C83

1M71
3

9S10

SCL-BL

3C81

AC1

22
23
24
25

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)

AA1
AA4
AB1
AB2

20

ETH-TXCLK

AA2

AA3

RXD_2
RXD_3
RXCLK
TXD_0
TXD_1
TXD_2
TXD_3
TXCLK

B24

3S60

A23

3S61

4_SDA
4_SCL

ERR
18

3S6F

ETH-RXD(3)
ETH-RXCLK

RXD_0
RXD_1

3S6G

ETH-RXD(2)

Y5
Y6
AB4

B01F

TUNER

16

3H13

SDA-BL

7E10
LAN8710A-EZK
ETH-RXD(0)
ETH-RXD(1)

FPGA - I/O BANKS

FB02x

FPGA

FB02G

FPGA - BACKLIGHT DIMMING

PQ-FPGA
SW

for component 7T00

FRCV
SW

for component 7T20

BL-FPGA
SW

for component 7T08

DVBS CONNECTOR BOARD

9S13

3H14

ETHERNET + SERVICE

11
10
9

FB02A

RES

+3V3

LVDS
CONNECTOR
TO DISPLAY
OR BOLT-ON

ERR
64

3S66

ERR
14

3S68

+3V3
3S80

DQ

7B03
H5PS1G83EFR

D(16-23)

ERR
36

VIDEO OUT - LVDS

SDA-SET

ERR
24

ETHERNET
CONNECTOR
RJ45

ERR
31

RES

3S65

D(0-7)

MEMORY

DDR2-D(0-31)

1
2

VGA-SDA-EDID-HDMI

3S5V-3

B02B

ETHERNET

DVBT
CHANNEL
DECODER

+5V-VGA

3S5V-1

+3V3

GPIO_3

B04C

LNB
CONTROLLER

ANALOGUE
VIDEO

DDR2-A(0-13)

SDRAM
128Mx8

7FJ0
CXD2820R

VGA

AD24

2_SDA

7B02
H5PS1G83EFR

HDMI

15

+5V-EDID

ETHERNET + SERVICE

3S67

SDRAM
128Mx8

3R15

3EC1-3

3EC1-1

+3V3
DRX-DDC-SDA

7T50
LNBH23QT

DIN-5V

AD25

3S6B

SDRAM
128Mx8

B01H

HDMI
CONNECTOR 1
43

12

OPTIONAL

3S6C

7B01
H5PS1G83EFR

D(8-15)

7B00
H5PS1G83EFR

3FE8

3FE9
15

VGA_EDID_SDA
VGA_EDID_SCL

1
2
19
18

CRX-DDC-SCL

B01I
B04C

B02I

SDRAM
128Mx8

uP
LEVEL SHIFTED
FOR DEBUG
1
USE ONLY

DDCA-SCL

Y23

DDR

TXD-UP

HDMI_DV

GPIO_3

B05A

3F65

+3V3

GPIO_2

1P02
16

13

30

SATELITE
TUNER

RES

10

Y26

HDMI
CONNECTOR 2
CRX-DDC-SDA

RES

29

15

MAIN
SW

RXD-UP

DDCA-SDA

DDC_A_SDA
DDC_A_SCL

40

SCLT

7R02
STV6110A

XIO_D
FLASH
E21
NAND_CE1
F21
NAND_RDY1
A21
NAND_WP_

Y25

15

1F51
3

RES

3S84

XIO-D(00-07)

B02C

3S83

B02A

AF21

39

DEBUG
ONLY

BRX-DDC-SCL

SDAT

19

11

P3_1

NAND-CE1n
NAND-RDY1n
NAND-WPn

DVBT2

P3_0
7F20
H27U4G8F2DTR

9
7
19

B10A

3S1H

3S1G

AE21

3F62

16

18

ERR
28

1P03
BRX-DDC-SDA

CIN-5V

1F52
3

+3V3RF
97

CHANEL DEC
DVBS

19
18

+3V3-STANDBY

3F63

DEMODULATOR

HDMI
CONNECTOR 3

1
2

ERR
35

98

7R01
STV903BAC

3FBF-1

3S2G

FLASH

3EC3

34

RES

7FE0
TC90517FG

3FBF-2

AC24

33

EEPROM
(NVM)

15

3FC2

3S2F

MC_SDA

16

ARX-DDC-SCL

3FC1

AC23

ERR
23

45

19
18

ERR
53

MC_SCL

FLASH
(4Gx16)

DVBS-SUPPLY

1
2

ERR
15

RES

B01B

ERR
42

ARX-DDC-SDA

19
18

STANDBY
SW

7F58
M24C64

3ECA-2

PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

+3V3-STANDBY
STANDBY

46

1P04

BIN-5V

HDMI
MUX

3ECA-4

1
5
2

AF24
SPI_CLK
AE22
P6_5
AF23
SPI_CSB
AE23
SPI_SDO
AF25 SPI_SDI

30

3ECP-1

PNX-SPI-WPn

TEMP
SENSOR

29

3ECA-1

PNX-SPI-CLK

PNX85500: STANDBY
CONTROLER

3S6V

512K

SCL-UP-MIPS

AIN-5V
54

7EC1
SII9287B
SII9187A

7FD1
LM75BDP

SDA-UP-MIPS

3S6W

FLASH

B02G

B02G

53

3ECA-3

3S57

3ECP-3

1_SCL

3F59

C26

1_SDA

3F60

C25

3S56

3S69

CONTROL

3S6A

ERR
13

PNX85537

VCC

B08B

DVBS-FE

SCL-SSB
+3V3

B07A

TUNER BRAZIL

SDA-SSB

3EC5

3S5Z

3FD3

3_SCL

+3V3-STANDBY

B01K

HDMI

3ECU-4

3S5Y

A24

3_SDA

3ECU-2

B25

3S6D

B02E

7F52
M25P05-AVMN6P

B04D

TEMP SENSOR +
HEADPHONE

+3V3

7S00
PNX85537EB

3FD4

B02E

PNX85500: CONTROL

3S6E

B01E

RES
15

TCON
SW

supported via main software

7H08
XC3S200A

SDA-TUNER

3F75

TUN-P7

SCL-TUNER

3F76

TUN-P6

FPGA
(SPARTAN)

1T01
TH2627
MAIN
TUNER
ERR
34

ONLY FOR
SSB 3104 313 6538.x

2011-Sep-09 back to

div. table

SW

Programmable via USB

19050_005_110415.eps
110810

Block Diagrams

Q551.2E LA

9.

EN 88

9-12 Supply Lines Overview


SUPPLY LINES OVERVIEW

+24V

GND1

1M95
1
2
3
4
5

CONNECTORS

1H95
1
2
3
4
5

B01I
+3V3-STANDBY

STANDBY-1

B02G

VGA
1E05
9

VGA
CONNECTOR

B01e,B02e,
g,h,B03a,b,c,h,
B04d,e,B09a

+5V-VGA

B01J

B03c,h

7
8

7
8

9
10

9
10

11
12

11
12

+24V-AUDIO-POWER

B04d

TEMP SENSOR + HEADPHONE

+3V3

B03e

LAMP-ON-1
B02G
BACKLIGHT-PWM_BL-VS-1
B06C
BACKLIGHT-BOOST-1
B01E
POWER-OK-1
B02G

13

14

14

1M99
1

1H99
1

2
3
4

2
3
4

B01K

+3V3

+3V3

+5V

+5V

B04B

B02b,h,B03d,
B05a
+5V

+12V_AL
B09a

+5V

B03e

+5V
+2V5-BRA

IN OUT
COM

+5V

+3V3-STANDBY

+12VIN

+12VD

PNX85500: NANDFLASH
CONDITIONAL ACCESS

+5V

+3V3

B03e

+3V3

B08B

+12V

T 3.0A

+5V

+3V3
5EC0

+3V3-STANDBY

+3V3-HDMI
+3V3-STANDBY

B03c (B11b)
B03h

1U40

+5V-VGA

B08a

+3V3-DVBS

+12V

B03c

+12V

+V-LNB

+V-LNB

B08a

+5V-VGA

B03b,d,e,g,
B08b,B09a

B09A

+5V-EDID
+5V

DVBS-SUPPLY

+3V3-DVBS

B01I

B03e

B07a
+V-LNB
B08b

HDMI

B03e

+12VIN

IN OUT
COM

+2V5-DVBS

+3V3-ET-ANA

+3V3
+3V3-STANDBY

B07a,B08b

7T01

12 5T04

DC / DC

B04D

+3V3-DVBS

IN OUT
COM

+3V3
5E08

+3V3

B07a

ETHERNET + SERVICE

+3V3

ONLY FOR SSB 3104 313 6538.x

B02A

IN OUT
COM

5T01 +1V-DVBS

7T02

+3V3

B04C

+3V3

B03e

5T00

B02h,g,B03e

B03e
B03c (B11b)

7FE3
5FE9

B03C

+5V-DVBS

7T00

Dual
N-Synchr
Converter

ANALOGUE EXTERNALS B

B03e

+3V3-BRA-FLT

7T03
1 TPS54283PWP
3 5T03

B03e

23

+3V3-BRA
5FE4

B11b

+24V

B03c (B11b)

+1V1

5U01

+3V3
5FE7

+12V_AL_BRG

12V/1V1
COVERSION

7U04

+1V2-BRA-DR1

+3V3

+3V3

+24V

B03e

1
+1V2-BRA-VDDC

B01g
B03e

DVBS-SUPPLY

+3V3

B03e

+1V8

5U00

7U01

B01g
+1V2-BRA-DR1

GND_AL

12V/1V8
COVERSION

7U02-1

TUNER BRAZIL

+1V2-BRA-VDDC
B08a,B09a

GND_AL

B03e

+3V3

+24V

13

14

B03e

12
Dual
Synchronous
7U02-2
Step-Down
Controller
14

+3V3

B04A

ANALOGUE EXTERNALS A

+12V

+12V

B03c

B02d,B03a

13

1M09
1
GND1
2
+12V3
3
GND1
4
+12V3

+3V3-STANDBY

7U03
TPS53126PW
+12VIN

B08A

DC / DC

+3V3-STANDBY

B03c (B11b)

5T02

1M95
1
3V3SB
2
STANDBY
3
GND1
4
GND1
5
GND1
6
+12V3
7
+VSND
8
GND1
9
BL-ON-OFF
10
BL-DIM1
11
BL-I-CTRL
12
POK

B11B

CONNECTORS COMP

+3V3

B03e

6EC1

PSU

B03B

CONNECTORS
COMP

5U02

B03C

+3V3
1M71
4

+5V

B03e

B03D
B01A

B02B

COMMON INTERFACE

+3V3

+3V3

+5V

3S20

DDR2-VREF-CTRL3

3S06

DDR2-VREF-CTRL2

B02C
+3V3

3U16

+3V3

1P04
18

AIN-5V

+3V3-STANDBY

B03c (B11b)

1P03
18

BIN-5V

3U15

CIN-5V

+12V_AL

B03c (B11b)

B02D

+3V3

+3V3

+5V

+5V

B03e
B03e

B03d
B03e

+3V3

T 2.0A

B02d,h
B02h

B04E

B10A

HEADPHONE

+3V3

+3V3

+3V3

+3V3

+3V3

B03e

3F32

+5V-USB2

+24V-AUDIO-POWER

B03c (B11b)

3S0Z

+T

B01D

SD-CARD

B02E

+3V3

3UA0
+2V5-AUDIO

B02h

3F40

+3V3-SD

3B20

+2V5-REF

B06A
B03E

+24V-AUDIO-VDD
B03b
B03c

+1V1

+12V

+12V

+3V3-STANDBY

IN OUT
COM

5UD2

+3V3

B01,a,b,c,d,e,
g,j,k,
B02a,c,d,e,h,
B03c,f,g,h,
B04a,c,d,e,
B06b,c,d,
B08a,B09a,
B10a,B11a

5UD1

+5V5-TUN

7UD0
IN OUT
COM

PNX85500: STANDBY CONTROLLER

6UD0

+5V

B03e
+3V3-STANDBY

+3V3-STANDBY

+5V

+1V1

B03b

+1V1
B03e

+5V

B03F

B03e
+3V3-STANDBY

B03d
B01,a,c,e,k,
B03c,d,e,
B04a,b,d,
B09a

TEMPSENSOR + AMBILIGHT

+3V3

1G03

+VDISP

B06b
B01f

T 3.0A

B06B

5UM1

B03d

9F71

B02H

+5V-TUN-PIN

B10a
B03b
B03d
B03b

B01G

TOSHIBA SUPPLY

+3V3
B03e

+3V3

IN OUT
COM

5FA3

+1V2-BRA-VDDC

5FA4

+1V2-BRA-DR1

+1V1

+1V1

+1V2

+1V2

+1V8

+1V8

+2V5

+2V5

B03G

+2V5-AUDIO

B02d
B03d
B01k
B03e
B01k

+3V3

+3V3

+3V3

+12V

+12V

+3V3-STANDBY
B03c

B03A

HDMI
1P05
18

B03c (B11b)
B03c (B11b)

B04d

+24V-AUDIO-POWER
3D09

+5V-TUN-PIN

FPGA-BACKLIGHT DIMMING

+3V3

+3V3
VCCA-O
VCCINT

+VDISP

SSB 3104 313 6538.x

B06C

B11B

AMBILIGHT CPLD

+3V3

+3V3
5GA0

VINT

5GA1

VIO

B03e
B01c
B03e

B06D

CONNECTORS

+3V3

+3V3

+3V3-1

+3V3-1

+5V

+5V

+12V_AL_BRG

+12V_AL_BRG

T 2.0A

+3V3
B03f

TO
26
AMBILIGHT
5 MODULE
10

V-AMBI

+3V3

+3V3-STANDBY
+12VD

B07A

+3V3-STANDBY
+12VD
+VDISP-INT

DVBS-FE

+1V-DVBS

B08a

SSB 3104 313 6538.x


+1V-DVBS

B12A
B06a

B09a

1H59
21

1H87

SPI-BUFFER

B03e

VDISP - SWITCH

+2V5-DVBS

+2V5-DVBS

+3V3-DVBS

+3V3-DVBS

B08a

AUDIO

+3V3-STANDBY
DIN-5V

+1V2-DVBT2-P

IN OUT
COM

B11b

+3V3
B03e

5FJ7

+3V3

+3V3

B03c (B11b)
+3V3-STANDBY

+3V3

B03H

+2V5-LVDS

+1V2-DVBT2-M

5H01

B03e

+2V5-AUDIO

+2V5-LVDS

+1V2-DVBT2-C

5FJ6

7H03
+3V3

FAN - CONTROL

7UU0

HDMI SIDE
CONNECTOR

B09a
B03e

B03c (B11b)

B01H

V-AMBI

PNX85500: POWER

B03c

B03d

7FA3

1UM0
T 1.0A

+5V-TUN

5FJ5

+3V3

TUNER

+5V-TUN

+2V5-DVBT2-X

+1V2-FE

VIDEO OUT - LVDS

B03b

B01F

5FJ4

+5V-TUN-PIN

B11A
B03e

+VDISP

B06a

+3V3-STANDBY

B03c (B11b)

+VDISP-INT

B03h

7UD1
5UD3

5UD0

B02G

+2V5-DVBT2-A

+1V2

DISPLAY INTERFACING-VDISP

+VDISP-INT

B03c (B11b)

+3V3

5FJ3

+1V2

DC / DC

+1V1

PNX85500: CONTROL

+3V3

DDR2-VREF-DDR
B03d

+24V-AUDIO-POWER

+3V3

+3V3-STANDBY

+T

+2V5-DVB
IN OUT
COM

+1V8

9FK6

PNX85500: MIPS

+3V3

B03e

DDR

+1V8

B03b

7UA0
VOLT.
REG.

+3V3-DVBT2-R

7FK1
5FK1

B05A
+12V

+3V3

B03e

B01E

+3V3-ARC

IN OUT
COM

+5V-USB1

+T
3FL2

5FJ2

+5V-TUN

ENABLE-1V8

+12V

+3V3
+3V3-DVBT2-D

+3V3-STANDBY

B01f

7S08

B11b

+3V3-STANDBY
B03c (B11b)

B03c

DVBT2

5FJ1

+5V5-TUN
7UA6

+2V5

+3V3-1

TO
IR/LED
BOARD

1M59
TO
AMBI-POWER 4
AMBILIGHT
MODULE

1C87

B01h

+2V5-LVDS

CUA0

B03e

PNX85500: AUDIO

+2V5

3S11

9FL2

1M21
6

+12V_AL

DIN-5V

B03e

USB HUB

+5V

1P02
18

DIN-5V

+2V5

IN OUT
COM

+5V5-TUN

B01C

+3V3-STANDBY

+5V

B03e

TEMP
SENSOR
(OPTIONAL)

7UC0

B03e

B03c (B11b)

HDMI 2
CONNECTOR
HDMI 1
CONNECTOR

+5V

PNX85500: DIGITAL VIDEO IN

+3V3

B03e

B02g,h,
B03e,B10a

+12V
B03e

FLASH

+3V3

+1V2

+5V

+5VCA

+T

B01B

+1V8

B03b
7UA3

+5V
3F01

HDMI 3
CONNECTOR

+1V8

B03e
B03e

+1V8

PNX85500: SDRAM

+1V8

B03b

DC / DC

B03e

DVBS DCDC TPA54231

+24V

+24V

7K00
+3V3-STANDBY

7UU2
LCD-PWR-ONn

+24V-AUDIO-POWER

5K00

B08a
5R00
5R01

IN OUT
COM

+3V3-DEMOD
+3V3RF

+5V-DVBS

B03e

+3V3

+3V3

SSB 3104 313 6539.x

+AVCC

19050_004_110415.eps
110729

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 89

9-13 Block Diagram Bolt-On 1, 3104 313 65372, xxPFL9xx6 series except 37"
BLOCK DIAGRAM Bolt-On 1, 3104 313 65372, xxPFL9xx6 series except 37"
SUPPLY LINES OVERVIEW

BLOCK DIAGRAM VIDEO, AUDIO


FB02C FPGA-DDR FB02x FRC-V
7T20
TFRCV-B1A03

7T04
H5PS5162

1G51

1M99
1

7T50
H5TQ1G63

DDR3
128MB

TRIDENT
FRC-V

MD(0-15)

DQ(0-15)

FROM SSB

41
FPGA-RX2

FB01A DC-DC CONVERTERS

FB01A DC-DC CONVERTERS

1T51
MA(0-13)

DDR2
1x64MB

A(0-12)

7T00
XC6SLX9

FB02P FRC-V-BY-ONE

FB02Q FCR-DDR3

FROM PSU

FB02x FPGA

FB02N INPUT-LVDS

5U54

2
3
4
5

FB01a
+12V
FB02n

5U55

7U76

+12VD

MOSI
CCLK

TPS53114
9S05

FB01a

FB02L FRC - SUPPLY ANA


+2V5

3U15

54
...
61

+1V2-FPGA

FB02b

FB02b
FB02b

FB01a
FB01a

+1V8-FPGA

+1V8-FPGA
3T18

FB01a

+12VD 7T06

+1V05

+3V3
FB01a

+3V3

FB02P FRC V-BY-ONE OUTPUT


+3V3

FB01a

FB02p

+3V3

+1V8-FPGA

FB02b

+VDSIP

+1V8-FPGA

+VDISP

+VDISP

FB02e

T 3.0A

FB02Q FRC - DDR3


+1V5

VCCO0

VCCO1

VCCO1

VCCO2

VCCO2

FB02n

VAUX

FB01a

FB01a

FPGA-DDR2-VREF

+1V5

+1V05

FB02O I2C-MUX & TEMPSENS.


FB02a

FPGA-DDR2-VREF

1T10

+3V3

+1V5

FB01a

VCCO0

VAUX

FB02b

TO
STAND

AUDIO-SPEAKERn

+3V3

+1V8-FPGA

+1V8-FPGA

1W53
3

FB02a

FB02E OUTPUT-VDISP

+1V2-FPGA

FB02b

FB02M FRC - SUPPLY DIG

FPGA-DDR2-VREF

FB02b

FB02H AUDIO + WiHD

+1V2-FPGA

+5V

+2V5

FB01a

+1V2-FPGA

FB02b

+1V5

FB01a

FB02a,
FB02c

FB02C FPGA-DDR

13

+12V

SFB-WPn
SFB-Hldn

FRCV
SW

PQ-FPGA
SW

FB02K FRC - DDR IO

+1V8-FPGA

5U51 +1V05

15
7U06

+3V3
+3V3-SFB

5TDA

+1V5

6U15

FROM SSB

48
...
51

SFB-CS

CSO-B

FB02a

+5V

FB02A FPGA I/O BANKS

V1-TX7

SFB-SI
SFB-SCK

FB02a

VCCO0

FB01a

SF-SO

FLASH
16Mbit

VCCO1

5T07

+1V8-FPGA

7U05

1G51
TO DISPLAY PANEL

7T30
M25P16
MISO

+3V3
FB01a

7T15...7T17

7U51

SUPPLY & CTL


FLASH
16Mbit

FB02a
FB02a

5T05

IN OUT
COM

FB02N INPUT - LVDS

V1-TX0

FB02J FRC-CONTROL

7T02
M25P40

VAUX
VCCO2

5U53

40

FB02B FPGA

5T00

+3V3

FB02J FRC - CONTROL

7T09

+2V5

7U10

FB02e

FPGA-TX1

FB01a

GND_AL

9
10

PQ FPGA

FPGA-RX1

5U76 +3V3

+2V5

+3V3 5T03

6
7
8

+3V3
FB01a

5U75 +1V5

7U75

FPGA-TX2
12

FB02H AUDIO - WiHD


FB02B FPGA-SUPPLY & CRTL

+2V5

LCD-PWR-ONn

+1V5

FB01a

+2V5

FB02R POWER SEQUENCING

FB01a

FPGA-DDR2-VREF

+12V

+12V

+3V3

+3V3

+2V5

+2V5

FB02S CONNECTORS BACKL.

FB02c

+3V3

+3V3

FB01a

BLOCK DIAGRAM IC

RES

SCL-DISP

FB02J

FB02E

FB02S CONNECTORS

9GS7

3SEG

SDA-BL

RES
9GS6

3SC6

SCL-BL

LCD-PWR-ONn

FLASH
16Mbit

3D-LR-FPGA-FRC
3D-LR-DISP
BL-SPI-SDO

CCLK
CSO-B

FB02J FRC-CONTROL

FRC-V

3D-LR
RESET-FRCn

SF-WPn
SF-Hldn

SFB-WPn
SFB-Hldn

FRCV
SW

CTRL-DISP
3D-LR-FPGA-FRC
BL-SPI-SDO

BL-SPI-CSn
BL-SPI-CLK

BL-ON
VSYNC-FRC

BL-SPI-CSn
BL-SPI-CLK

+3V3 7T25
NCP303LSN28G
INP
OUTP
GND

FB02P FRC-V-BY-ONE
1T51
CTRL-DISP

FB02S CONNECTORS
BACKLIGHT

3TDG

B24
SDA-FRC
3TDF
C24

3TDV

W1
3TDW

3TDC

RES
3TDB

3TDD

7T20
TFRCV-B1A03

FLASH
16Mbit

TRIDENT
FRC-V

+3V3

1T22
3
1

VSYNC-FRC
DEBUG

PQ FPGA

RES
3TDA

3T29

3T30

7T00
XC6SLX9

V3

SFB-SO
SFB-SI
SFB-SCK
SFB-CS

3D-LR-DISP

27M

R12

SF-SO
SF-SI
SF-SCK
SF-CS

3D-LR
3D-VS

MOSI

FPGA-SYS-CLK

T12

PQ FPGA

MISO

PQ-FPGA
SW

7T30
M25P16

7T60, 7T61

RESET-FRCn
CTRL-DISP

7T03

FB02A FPGA-I/O BANKS

FB02J FRC-CONTROL

LCD-PWR-ON-FRCn

7T02
M25P40

BACKLIGHT
1F53
2

CONTROL

SUPPLY & CTL

RES

FB02B LCD-PWR-ON-FRCn

9T14

TO DISPLAY PANEL

3SH1

3TN6

CONTROL

FB02B FPGA

TO DISPLAY PANEL

2 CHAN.
MULTIPLEX.

TEMP
SENSOR

1T51
1

3TN7

3GS7

7GS1
PCA9540B

7GS2
LM75BDP

FROM SSB

3HS0

3GS6

+3V3

3TS5

FB02P FRC V-BY-ONE OUTPUT

TO DISPLAY
PANEL

9GS4
3TS4

3S42

DDR3
128MB

SCL-FRC

1F53
13
7
5

BL-SPI-SDO
BL-SPI-CLK

BL-SPI-SDO-OUT
BL-SPI-CLK-OUT

BL-SPI-CSn

BL-SPI-CSn-OUT 11

TO DISPLAY
PANEL

SCL_SSB

FB02J
3

7T50
H5TQ1G63

3TG4

SDA-DISP

FB02N

BL-ON-OUT

9GS5

DDR2
1x64MB

SPLASH-ON

FB02Q FCR-DDR3

RESET-FRCn
3TG3, 9T19
3D-VS

SDA_SSB

7T04
H5PS5162

7T20
TFRCV-B1A03

BL-ON-OUT
SPLASH-ON

MA(0-13)

49

FB02J FRC - CONTROL

MD(0-15)

3T62

CTRL-DISPIN
BL-ON-OUT
BL-DIM
3D-LED-S6

FB02C FPGA-DDR

24M

3T61

7T00
XC6SLX9

1T21

3SH2

1G51
6
4
5
7
4
10

1T61
50

A(0-12)

3SG2

3SG9

3SH3

FB02N INPUT-LVDS

DQ(0-15)

1SG2

+3V3

3S40

FB02D OUTPUT-LVDS FPGA

FROM SSB

1G51

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

FB02O IC-MUX & IC TEMP SENSOR


PROGRAMMING
ENGINEERING

FB02N INPUT-LVDS

9T23..25

19050_094_110902.eps
110908

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 90

9-14 Block Diagram Bolt-On 1, 3104 313 65372, xxPFL8xx6 series


BLOCK DIAGRAM Bolt-On 1, 3104 313 65372, xxPFL8xx6 series
SUPPLY LINES OVERVIEW

BLOCK DIAGRAM VIDEO, AUDIO


FB02C FPGA-DDR FB02x FRC-V
7T20
TFRCV-B1A03

7T04
H5PS5162

1G51

7T50
H5TQ1G63

1M99
1

7T51
H5TQ1G63

DDR3
128MB

TRIDENT
FRC-V

DDR3
128MB

5U54

2
3
4
5

5U55

7
8

GND_AL
+12VD

7U10

FB02e

MISO

TPS53114
9S05

FB01a
54
...
61

CCLK

FB02b

FB02b
1W53
3

AUDIO-SPEAKERn

+12VD 7T06

VCCO1

VCCO1
VCCO2

+2V5

+VDISP

FB02Q FRC - DDR3

LCD-PWR-ONn

FB02R POWER SEQUENCING


FB02n

+3V3

+3V3

FB01a

7TC3
IN OUT
COM

FPGA-DDR2-VREF

+1V5

FB01a

+2V5

FB01a

+12V

+12V

+3V3

+3V3

+2V5

+2V5

FB02S CONNECTORS BACKL.


+3V3

+3V3

FB01a

VCCA-O

RES

DDR2
1x64MB

FB02J

FB02E

FB02S CONNECTORS

LCD-PWR-ONn

SDA-BL

9GS6

SCL-BL

1F53
2

3SEG

PQ FPGA

MISO

3D-LR-FPGA-FRC

MOSI

3D-LR-DISP
BL-SPI-SDO

CCLK

RES
PQ-FPGA
SW

3D-LR
RESET-FRCn

SF-WPn
SF-Hldn

SFB-WPn
SFB-Hldn

FRCV
SW

CTRL-DISP
3D-LR-FPGA-FRC
BL-SPI-SDO

BL-ON
VSYNC-FRC
+3V3 7T25
NCP303LSN28G

3D-LR-DISP

7T03

FB02J FRC-CONTROL

1T21

FB02G FPGA-BACKLIGHT DIMMING

FLASH
16Mbit

BL-SPI-CSn
BL-SPI-CLK

RES

FB02A FPGA-I/O BANKS

SFB-SO
SFB-SI
SFB-SCK
SFB-CS

TRIDENT
FRC-V

BL-SPI-CSn
BL-SPI-CLK

CSO-B
3SC6

SF-SO
SF-SI
SF-SCK
SF-CS

3D-LR
3D-VS
RESET-FRCn
CTRL-DISP

FLASH
16Mbit

FPGA-SYS-CLK
CPLD-SYS-CLK

7T20
TFRCV-B1A03

PQ FPGA

BL FPGA

FRC-V

3TDG

B24
SDA-FRC
3TDF
C24

1T22
3
1

FLASH
512kbit

DEBUG

7T08
XCS3S50A

BL-FPGA
SW

BL-SPI-CSn
BL-SPI-CLK

3D-LR-DISP
BL-SPI-SDO

CTRL-DISP

1T51
CTRL-DISP

FB02S CONNECTORS
CTRL-DISPIN

SP3A-MOSI
SP3A-CSO-B

INP
OUTP
GND

FB02P FRC-V-BY-ONE

BACKLIGHT

SP3A-MISO
SP3A-CCLK

SCL-FRC

3D-LR

7T08
XC3S50A

7TC2
M25P05
3TDV

7T00
XC6SLX9

+3V3
W1
3TDW

3TDD
V3

3TDC

15

RES
3TDB

16

RES
3TDA

3TCH

3TCK

3T30

3T29
R12

FB02G FPGA-BACKLIGHT DIMMING

3D-VS
RESET-FRCn

BL-DIM(5-12)

27M

T12

7T30
M25P16

7T60, 7T61

7T02
M25P40

BACKLIGHT
9GS7

FB02J FRC-CONTROL

LCD-PWR-ON-FRCn

RES

CONTROL

TO DISPLAY
PANEL

FB02B LCD-PWR-ON-FRCn

CONTROL

9T14

3SH1

3TN6

FB02J

DDR3
128MB

FB02B FPGA
SUPPLY & CTL

TO DISPLAY PANEL

2 CHAN.
MULTIPLEX.

TEMP
SENSOR

1T51
1

3TN7

3GS7

7GS1
PCA9540B

7GS2
LM75BDP

FROM SSB

3HS0

3GS6

3TS5

3TS4

FB02P FRC V-BY-ONE OUTPUT

7T51
H5TQ1G63

DDR3
128MB

BL-DIM

BL FPGA

3D-LED-S3A
SPLASH-ON

1M54
BL-DIM(5-12)
FB02N

2
:
9

TO PSU

SCL-DISP

+3V3

FB02N

3TG4

SCL_SSB

MA(0-13)
7T50
H5TQ1G63

BL-ON-OUT

SDA-DISP

9GS4

BL-ON-OUT
SPLASH-ON

7T04
H5PS5162

3D-VS

9GS5

FB02Q FCR-DDR3

3TG3,
9T19

SDA_SSB

7T20
TFRCV-B1A03

MD(0-15)

49

FB02J FRC - CONTROL

RESET-FRCn

3T62

CTRL-DISPIN
BL-ON-OUT
BL-DIM
3D-LED-S6
3D-LED-S3A
SPLASH-ON

FB02C FPGA-DDR

MD(16-31)

3SG2

1T61
50

3T61

7T00
XC6SLX9

A(0-12)

3SH2

1G51
6
4
5
7
4
10

FROM SSB

PROGRAMMING
ENGINEERING

3SH3

FB02N INPUT-LVDS

FB02G
3

3S42

+VDISP

FB02e

VCCINT

DQ(0-15)

3S40

FB02D OUTPUT-LVDS FPGA


1SG2

+3V3

3SG9
2

FB02b

+VDSIP

+3V3
+1V8-FPGA

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

FB02O IC-MUX & IC TEMP SENSOR

1G51

+3V3
+1V8-FPGA

FB02c

BLOCK DIAGRAM IC

+3V3

FB02P FRC V-BY-ONE OUTPUT

FB01a

FB02p

5T06

FB02N INPUT-LVDS

+3V3
FB01a

FB02G FPGA BACKLIGHT DIM


FB01a

VAUX

FPGA-DDR2-VREF

+1V05

+1V5
FB01a

VCCO2

+1V5

+1V05

FB02O I2C-MUX & TEMPSENS.


FB02a

FPGA-DDR2-VREF

1T10

+3V3

+1V5

FB01a

T 3.0A

VCCO0

VAUX

FB02b

TO
STAND

FB02H AUDIO + WiHD

FB01a

+1V8-FPGA

VCCO0

FB02b

FB01a

FB02E OUTPUT-VDISP

+1V8-FPGA

FB02b

FB01a

FPGA-DDR2-VREF

+1V2-FPGA

+2V5

FB02M FRC - SUPPLY DIG

FB02a

+1V8-FPGA
3T18

+5V

FB02b

SFB-WPn
SFB-Hldn

FRCV
SW

PQ-FPGA
SW

+1V2-FPGA

+1V8-FPGA

FB02b

+1V2-FPGA

SFB-CS

CSO-B

FB02L FRC - SUPPLY ANA


+2V5

FB02C FPGA-DDR

+1V5

FB01a

+3V3

FB02A FPGA I/O BANKS

V1-TX7

SFB-SI
SFB-SCK

FB02a,
FB02c

FB01a

5U51 +1V05

3U15

FB02K FRC - DDR IO

FB02a

+1V2-FPGA

13

+12V

+3V3-SFB

5TDA

FB02a

+1V8-FPGA

+5V

15
7U06

+3V3

FB01a

+1V5

6U15

FROM SSB

TO DISPLAY PANEL

48
...
51

SF-SO

FLASH
16Mbit

MOSI

VCCO0

FB01a

1G51

SUPPLY & CTL


FLASH
4Mbit

VCCO1

5T07

+1V8-FPGA

7U05

+3V3

FB02J FRC - CONTROL


+3V3

7T15...7T17

7U51

FB02J FRC-CONTROL

7T02
M25P40

FB02a

5T05

IN OUT
COM

FB02N INPUT - LVDS

V1-TX0

7T30
M25P16

FB02a

VCCO2

5U53

40

FB02B FPGA

VAUX

7T09

+2V5

FPGA-TX1

FB01a

5U76 +3V3

7U76

5T00

+3V3 5T03

9
10

PQ FPGA

FPGA-RX1

+2V5

FB01a
+12V
FB02n

+3V3
FB01a

5U75 +1V5

7U75

FPGA-TX2
12

FB02H AUDIO - WiHD


FB02B FPGA-SUPPLY & CRTL

24M

FROM SSB

FPGA-RX2

MD(0-15)

MD(16-31)

DQ(0-15)
41

FB01A DC-DC CONVERTERS

FB01A DC-DC CONVERTERS

1T51
MA(0-13)

DDR2
1x64MB

A(0-12)

7T00
XC6SLX9

FB02P FRC-V-BY-ONE

FB02Q FCR-DDR3

FROM PSU

FB02x FPGA

FB02N INPUT-LVDS

19050_093_110902.eps
110908

2011-Sep-09 back to

div. table

Block Diagrams

Q551.2E LA

9.

EN 91

9-15 Block Diagram Bolt-On 3, 3104 313 65462, xxPFL7xx6 series


BLOCK DIAGRAM Bolt-On 3, 3104 313 65462, xxPFL7xx6 series
SUPPLY LINES OVERVIEW

BLOCK DIAGRAM VIDEO, AUDIO


FB02C FPGA-DDR FB02x FRC-V

A(0-12)

7T00
XC6SLX9

1M99
1

MA(0-13)

DDR2
1x64MB

7T50
H5TQ1G63

7T51
H5TQ1G63

DDR3
128MB

TRIDENT
FRC-V

DDR3
128MB
MD(0-15)

MD(16-31)

FROM SSB

FPGA-RX2

FB01a
+12V
FB02n

5U55

+12VD

SUPPLY & CTL


7T30
M25P16

SFB-SI
SFB-SCK

CCLK

TX3

SFB-WPn
SFB-Hldn

FRCV
SW

+1V5

FB02L FRC - SUPPLY ANA


+2V5

TPS53114
9S05

TX4

+1V2-FPGA

FB01a

FB02a

+3V3
+1V2-FPGA

FB02b

3U15

54
...
61

FB02b
FB02b
FB02b
FB02b

FB01a
FB01a

3T18

+1V8-FPGA

+1V8-FPGA

FB01a

+12VD 7T06

1T10

+VDISP

FB02Q FRC - DDR3


+1V5

VCCO0

VCCO1

VCCO1

VCCO2

VCCO2

FB02n

VAUX

VAUX

FB01a

+2V5

+VDISP

FB02p
T 3.0A

FB01a

+3V3

FB02P FRC LVDS OUT

FB02e

+VDSIP

VCCO0

FPGA-DDR2-VREF

+1V05

+3V3
FB01a

FB02E OUTPUT-VDISP
+1V2-FPGA

+1V5

+1V05

FB02O I2C-MUX & TEMPSENS.


FB02a

FPGA-DDR2-VREF
FPGA-DDR2-VREF

+1V2-FPGA

+3V3

+1V5

FB01a

+1V8-FPGA

+1V8-FPGA

+5V

FB02b
FB02b

FB02M FRC - SUPPLY DIG

FB02C FPGA-DDR

13

+12V

+2V5

FB01a

5U51 +1V05

15
7U06

+1V5

FB01a

+1V8-FPGA

+5V

FB02A FPGA I/O BANKS

32

SFB-CS

CSO-B
PQ-FPGA
SW

48
...
51

SF-SO

FLASH
16Mbit

MOSI

FB02K FRC - DDR IO

FB02a,
FB02c

FB01a

TO DISPLAY PANEL

FLASH
16Mbit

FB02a

+1V8-FPGA

7U05

1G51

1T50

MISO

VCCO0

7T09

6U15

11

FB02J FRC-CONTROL

7T02
M25P40

5T07

7T15...7T17

7U51

FROM SSB

TX2

FB02B FPGA

FB02a
FB02a

IN OUT
COM

FB02N INPUT - LVDS

TO DISPLAY PANEL

40
TX1

FPGA-TX1

VCCO2
VCCO1

5U53
9

+3V3
+3V3-SFB

5TDA

FB02a

5T05

+2V5

7U10

FB02e

VAUX

5T00

+3V3 5T03

GND_AL

9
10

1T51

PQ FPGA

FPGA-RX1

5U76 +3V3

7U76

FB01a

+2V5

6
7
8

+3V3
FB01a

5U75 +1V5

7U75

FPGA-TX2
12

FB02J FRC - CONTROL


FB02B FPGA-SUPPLY & CRTL

5U54

2
3
4
5

DQ(0-15)
41

FB01A DC-DC CONVERTERS

FB01A DC-DC CONVERTERS

7T20
TFRCV-B1A05

7T04
H5PS5162

1G51

FB02P FRC LVDS OUT

FB02Q FRC-DDR3

FROM PSU

FB02x FPGA

FB02N INPUT-LVDS

LCD-PWR-ONn

+1V5

FB01a

+2V5

FB02R POWER SEQUENCING


+12V

+12V

+3V3

+3V3

+2V5

+2V5

FB01a

FPGA-DDR2-VREF

FB02c

BLOCK DIAGRAM IC

SCL_SSB

SCL-DISP

2 CHAN.
MULTIPLEX.

10

SCL-CRP

SDA-CRP

11

LCD-PWR-ONn

FB02E

FLASH
16Mbit

3D-LR-FPGA-FRC
3D-LR-DISP
BL-SPI-SDO

PQ-FPGA
SW

FB02J FRC-CONTROL
FPGA-SYS-CLK

MA(0-13)
SF-WPn
SF-Hldn

SFB-WPn
SFB-Hldn

FRCV
SW

CTRL-DISP
3D-LR-FPGA-FRC
BL-SPI-SDO

BL-SPI-CSn
BL-SPI-CLK

BL-ON
VSYNC-FRC

BL-SPI-CSn
BL-SPI-CLK

+3V3 7T25
NCP303LSN28G
INP
OUTP
GND

B24
SDA-FRC
3TDF
C24

SCL-FRC

1M21

1T22
3
1

1M20
1

18

LIGHT-SENSOR

17

LED1-OUT

16
14

3
5

12

LED2-OUT
KEYBOARD
IR_IRQ_RF4CE

10
8

SCL-CRP
SDA-CRP

7
9
11

TO LED & CONTROL

FRC-V

3TDG

FROM SSB

PQ FPGA

3D-LR
RESET-FRCn

FB01C LEADING EDGE CONN.

W1

DEBUG

7T20
TFRCV-B1A05

3TDV

7T00
XC6SLX9

FLASH
16Mbit

TRIDENT
FRC-V

+3V3

3TDW

3TDC

3TDD
V3

RES
3TDB

R12

RES
3TDA

3T29

3T30

27M

T12

SFB-SO
SFB-SI
SFB-SCK
SFB-CS

3D-LR-DISP

7T03

FB02A FPGA-I/O BANKS

SF-SO
SF-SI
SF-SCK
SF-CS

3D-LR
3D-VS

MOSI
CCLK

SDA-BL
SCL-BL

PQ FPGA

MISO

CSO-B
9GS6

7T30
M25P16

7T60, 7T61

RESET-FRCn
CTRL-DISP

7T02
M25P40

9GS7

CONTROL

FB02J FRC-CONTROL

LCD-PWR-ON-FRCn

FB02J

9T14

3SH1

FB02B LCD-PWR-ON-FRCn

SUPPLY & CTL

1M20

3GS7

7GS1
PCA9540B

CONTROL

DDR3
128MB

FB02B FPGA

TO LED & CONTROL

FROM SSB

TEMP
SENSOR

FROM SSB

7GS2
LM75BDP

3HS0

1M21
2

3GS6

FB01C LEADING EDGE CONN.

+3V3

3TS5

3TS4

3S42

7T50
H5TQ1G63

3TG4

9GS4

FB02J
3

FB02N

BL-ON-OUT

SDA-DISP

DDR2
1x64MB

SPLASH-ON

FB02Q FRC-DDR3

RESET-FRCn
3TG3, 9T19
3D-VS

9GS5

10

7T20
TFRCV-B1A05

BL-ON-OUT
SPLASH-ON

MD(0-15)

RES

SDA_SSB

49
RES

7T04
H5PS5162

FB02J FRC - CONTROL

24M

3TN2

CTRL-DISPIN
BL-ON-OUT
BL-DIM

FB02C FPGA-DDR

1T21

3SH2

3TN1

7T00
XC6SLX9

A(0-12)

3SG2

3SG9
3S40

3SH3

1G51
6
4
5

1T51
50

DQ(0-15)

1SG2

+3V3

FB02N INPUT-LVDS

FB02P FRC LVDS OUT

FROM SSB

1G51

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

FB02O IC-MUX & IC TEMP SENSOR


PROGRAMMING
ENGINEERING

FB02N INPUT-LVDS

19050_095_110906.eps
110907

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 92

10. Circuit Diagrams and PWB Layouts


10-1 B01 310431365381
Common Interface

19

100R
3F03-2 2

0R4

3F03-1

IF02
3
4
5
6
7
8
9

8
100R

7
100R

CA-DATAENn

IF03

1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn
MOCLK
MOVAL

10

MOSTRT

2F02

19

RES
MDO2

100n

20

7F01
74LVC245A
1

MDO1

MDO3

3EN1
3EN2
G3

IF05
CA-MDO0

3F04-1 1

8 100R
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

MDO5

8
10K
7
10K
3 3F10-3 6
10K
4 3F10-4 5
10K

MDO6
MDO7

3F10-2

3F12

10

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3
18

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

CA-WP

100n

20

7F02
74LVC245A

RES

10K
2 3F11-2 7
10K
3F11-3
3
6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K

20

100n

3EN1
3EN2
G3

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

17
16
15
14
13
12
11

1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

18

+3V3
2F05

8-BIT DATA
7F04
74LVC245A

18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D00

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

+3V3
2F06

CONTROL
7F05
74LVC245A

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

18

1
2

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D11

IF08

+5VCA

+3V3

1P00

+5VCA
2F04 RES

XIO-A08

+3V3

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY

+3V3

7F03
74LVC245A

IF04

3F10-1

CA-RDY

IF07

+3V3

1 3F08-1 8
10K
2 3F08-2 7
10K
3 3F08-3 6
10K
3F08-4
4
5
10K

MDO4
MDO0

17
16
15
14
13
12
11

B01A

100K

4 3F07-4 5
10K
2 3F07-2 7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

1 3F09-1 8
10K
2 3F09-2 7
10K
3F09-3
3
6
10K
4 3F09-4 5
10K

MDO0
+3V3

10

22u 16V

RES 2F01

CA-MOVAL
CA-MOSTRT

CA-CD2n

20

+5VCA
+T

CA-CD1n

3EN1
3EN2
G3

20

3F01
+5V

3F06

CA-RST
RES

100n

IF01

3F02

CA-MOCLK

2F00
20

7F00
74LVC245A
1

+3V3

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n
71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X07
REF EMC HOLE

1X04
EMC HOLE

1X08
REF EMC HOLE

1X01
REF EMC HOLE

1X10
HOOK1

1X11
HOOK1

92789-055LF

SPB SSB
TV550 2K11 4DDR EU SD

10

B01A

Common Interface TRANSPORT STREAM FROM CAM

2011-03-07

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 93

Flash

Flash

B01B

12

7F20
NAND04GW3B2DN6F

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

0
1
2
3
IO
4
5
6
7

NC

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

7
100R
3F22-3 3
10K
3F22-1 1
5 100R

100R

100R

16
17
9
8
18
19
7

IF22
3F24

+3V3
2K2
NAND-RDY1n

CLE
ALE
CE
RE
WE
WP
R
B

VSS
13

3F19

10K

IF23

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

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div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 94

USB Hub

B01C

USB Hub

B01C

+3V3

USB-OVR1
3FL2

100K
3FLE-2
100K
3FLE-4
100K
3FLE-3

45

26
IFLA

7
9F26
9F25

IFL1 17
IFL2 18

9FLC
9FLD

13
14

6
9
10

100K
3FLF

+3V3

9FLF
9FLG

10K

RESET-USBn
USB1-DM
USB1-DP
USB-DM
USB-DP
USB2-DM
USB2-DP
USB-WIFI-DDn
USB-WIFI-DDp

46

IFL3

9FLK
9FLL

USB2-DM
USB2-DP

53
51
5
6
42
41
54
1
2
44
43
52

3FLG

+3V3

10K
USB-OVR1
3FLH
+3V3
10K

SELFPWR

RESET
PWR2
OVR2

DD+

SPI_CS
SPI_SCK
SPI_SD

DD1DD1+
DD2DD2+

VIA

RES

NC

1P08
Y
Y
Y
Y

1F24
N
Y
N
Y

3FLG
N
Y
Y
N

3FL2
N
N
Y
Y

3FL4
N
N
Y
Y

3FL7
N
Y
N
Y

3F32
Y
Y
Y
Y

3F34
N
Y
Y
Y

7FL5
CY7C65621
CY7C65621
CY7C65631

9FLE 9FLC/D 9F25/6 9FL2


N
Y
N
N
N
Y
N
N
Y
N
N
Y
N
Y
N
N

2FLB 1n0

10n
2FL3

2FLC 1n0

10n
2FLD

2FLA 1n0

10n
2FL5

100n

2FL2 100n

2FL1
IFLB

1P08
+5V-USB1

FL36
FL37

USB1-DM
USB1-DP

FL32

3
10K
15K
10K

58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

IFLF

USB-16-PBT-B-30-CU1-BRF

+5V
4

9FLE

3FLA
3FLB
3FLC

+T

3F34-4

0R4

FL43

USB2 (BOT)
1P07

+5V-USB1
+5V-USB2

100K

IFLC
IFLD
IFLE

1
2
3
4
5

3F32

31
32
25
48
49

USB1 (TOP)
6

100K

37
38
29
30

100K
3FL4-1

+5V-USB2

3F34-3

FL40
FL41

USB2-DM
USB2-DP

100K
+3V3
+3V3

3F34-2

FL42

3F34-1

7
USB-16-PBT-B-30-CU1-BRF

100K
1

1
2
3
4
5

100K
+3V3

+5V

RES
RES
RES
RES

1
2
3
4

9FL1-1
9FL1-2
9FL1-3
9FL1-4

8
7
6
5

1
2
3
4

9FL2-1
9FL2-2
9FL2-3
9FL2-4

8
7
6
5

(WIFI)

RES 3FLJ
+T

0R4

RES
1F24
+3V3-1

FL38
FL39
FL30

USB-WIFI-DDn
USB-WIFI-DDp

1
2
3
4
5
6

502386-0570

GND
HS

4
8
12
16
20
24
28
34
40
47
50
56
1P07
N
N
Y
Y

+3V3
PWR1
OVR1

VBUSPOWER

GND

SCENARIO
1x USB
1x USB + WIFI
2x USB
2x USB + WIFI

100n

100n

GREEN2
AMBER2

10K

10K

XOUT

35
36

100K
3FL4-2

FL33

9FL3

3FLE-1

100K
3FL4-3

FL31

3FL4-4

0R4

9FL3
N
N
N
Y

57

GREEN1
AMBER1

9FLH
9FLJ

+5V

3FLD

22

VCC
XIN

3FL7

IFLG

21

3
7
11
15
19
23
27
33
39
55

12p

2FL7

7FL5
CY7C65621-56LTXCT
IFL4

+3V3

2FL9

1u0
2FL8

24M

12p

2FL6

4
2

1FL5

2FL4

+5V
+T

9FLF/G 9FLH/J 9FLK/L


N
N
N
Y
N
N
N
N
Y
Y
N
Y

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 95

SD Card

SD-Card

B01D

3F40
+3V3
2F40

+T
22u 16V

B01D

FF45

+3V3-SD

0R4

+3V3

3F41-1

IF47

SDIO-DAT3

47K

3F41-2

SDIO-CMD

SDIO-DAT3

3F44-1
100R

SDIO-CMD

FF47

8
2

47K
SDIO-CLK

3F42-3

47K

FF48

+3V3-SD

SDIO-DAT0

3 3F43-3 6

FF49

100R
SDIO-DAT0

3F44-4

SDIO-CLK

10K
3 3F41-3 6
3F41-4

1P09-1
7

100R

3F45 RES

47K

3F43-2

SDIO-DAT1

SDIO-DAT1

SDIO-DAT2

SDIO-DAT2

47K

100R
2

3F44-2

FF41
4

3F43-4
100R

FF42
FF43

3F42-2

FF46

1P09-2
SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
2

14
16

SCDA7A0200

100R

1 3F42-1 8

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 96

PNX85500 Control

PNX85500-Control

+3V3-STANDBY

B01E

+3V3-STANDBY

IF50

512K
FLASH

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO
IF52

10K
RES

10K

3F67

3F66

IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

47K

+3V3

+3V3

3F68 RES

IF51

3F52

7F52
M25P05-AVMN6

VCC
PNX-SPI-SDI

+3V3

100n
RES

2F52

100p

2F49

+3V3-STANDBY

10K

B01E

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

2
1

FF04

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

DEBUG ONLY
IF58

2F58 RES

SCL-SSB

1
2
3

0
1
2

3F62

100R

SDA-SSB
3F63

FF63

WC
SCL

ADR
SDA

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

IF59

(8K 8)
EEPROM

10K

3F58

RES
1F52
FF62

100n
7F58

FF61

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 97

Tuner

B01F

Tuner

B01F
IF10
IF11

AF73

15p

2F65 RES
1p0

2F73

220R

2F70 RES

3F79-4

820R

AGC CONTROL

VAGC

IF16
330n
3F82 RES

10n

RES 5F76

10n

2F62

220R
IF80

5F74

2F79

2F72

9F03

9F02

IF78

*
AF72

3F79-1

2F82

10n

IF79

10n

1K0
2F92

3F72

BA591

6F72

3F81
220R

2F91 RES

IF13
IF-

10n
IF14

2F64

IF15

15p

2F63

680n
2F66

5F73

10n

IF12

5F66

TUN-IF-P

3F80
220R

3K3

5F70

TUN-IF-N

IF-N-DVBT2

2F90

470n

IF86

3F78

4K7

9F06

+5V-TUN-PIN
3F71

9F05

47n

2F85

100p

IF72

RES 2F95

100n

2F93
+5V-TUN-PIN

IF76

FF01

IF-AGC

FF75

2F75

PNX-IF-N

4K7
IF-AGC

OUTPUT2

IF74

3F77

RES 2F96

* 9F04

IF82

PNX-IF-AGC

100p

FF00

TUN-IF-N
TUN-IF-P

2p2
2F77

INPUT2

OUTPUT1

RES
2F76

VCC

IF77

INPUT1

2F80

IF81

GND

10n
2F78

5F71

5
4

IF73

GND2

O1
O2

2F74

PNX-IF-P

I
ISWI

2F9D

RES 2F9C

RES 2F9B

RES 2F9A

IF+

10n

ATB2012

* For BR NIM Tuner only

10n

FF81
FF82

IF89
3F76

15p

47R

2F86

3F75

15p

47R

IF87

SELECT-SAW
SCL-TUNER

RES

2F84

2F94

TUN-P6
IF88

IF90

SDA-TUNER

7F70
PDTC114EU

IF-P-DVBT2

10n

RES 2F99

RES 2F98

RES 2F81

RES 2F97
100n
4n7

2F61

IF75

X7251M
36M17

AF71
AF70

FF76
RF-AGC

2F60
2F59

10n

GND1

6p8

6p8

6p8

6p8

6p8

6p8

1
2
3

TUN-P6
TUN-P7

+5V-TUN-PIN
7F75
UPC3221GV-E1

1F75

2F71

9F01

9F00

NC

IF_OUT2

13

12

11

4MHZ_REF

IF_OUT1
10

B+_TUN

I2C_SCL

TUN

I2C_ADR

B+_LNA

RF_AGC
3

14

FF74
4n7

TUN-P1

RF_IO

16

I2C_SDA

TUNER

15

6p8

FF71

* 1T01

* For EU Hybrid Tuner only

TUN-P7

9F71
5F72 RES

1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74

30R
22u

Item No.

+5V-TUN-PIN

+5V-TUN

Component
Europe
Brazil
FA23X7
TH26X3
RES
4u7
5p6
10p
Used
RES
Used
RES
Used
RES
Used
RES
Used
RES
RES
1p0
RES
1p0
12p
15p
12p
15p
18p
22p
560n
680n
680n
820n

2F88

* Remarks

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 98

Toshiba Supply

Toshiba supply

B01G

+1V2-BRA-DR1

+3V3

IN

OUT

30R

5FA4

7FA3
LD1117DT12

30R

5FA3

+1V2-BRA-VDDC

FFAF
+1V2-FE
* FOR DVBT-2
10u

2FA4

100n

2FA3

100n

COM
2FA2

B01G

FFA2

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 99

HDMI

HDMI

B01H

HDMI CONNECTOR SIDE


1P05
DRX2+

DIN-5V

DRX2DRX1+
DRX1DRX0+

DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22

DRX-DDC-SCL
DRX-DDC-SDA

47K

DRX0DRXC+

3FBF-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23

B01H

DRX-DDC-SCL
DRX-DDC-SDA

3FBF-2

DIN-5V

47K
DIN-5V

DRX-HOTPLUG

FFB6

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 100

VGA

VGA

B01I
FFC1
CDS4C12GTA
12V

RES 6FC1

1FC1

100p

RES 2FC1

3FC5

CDS4C12GTA
12V

RES 6FC2

1FC2

100p

G-VGA

18R

1FC3

RES 6FC3

FFC4

100p

RES 2FC3

FFC3

CDS4C12GTA
12V

3FC7

9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

1FC4

FFC6
1216-02D-15L-2EC

B-VGA

18R

FFC5

47p

CDS4C12GTA
12V

RES 6FC6

47p

2FC6

10K

RES
3FC2

FFC9

RES 6FC7

47p

2FC7

10K

4K7

3FC4

CDS4C12GTA
12V

RES 6FC5

1FC5

FFC8

CDS4C12GTA
12V

RES
3FC1

47p

2FC5

FFC7

9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

9FC3

VGA-SCL-EDID-HDMI

9FC4
RES

VGA-SCL-EDID

RES 6FC8

1FC6

47p

+5V-VGA
CDS4C12GTA
12V

17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2FC4

VGA
CONNECTOR

3FC6

RES 2FC2

1E05

R-VGA

18R

FFC2

2FC8

B01I

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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110420

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 101

Temp sensor & headphone

Temperature sensor + headphone

B01J

SCL

A2

1K0

3FD2

9FD2 RES

9FD1 RES

100n

IFD3

IFD5

RES

A1

9FD5

SDA

IFD1

1K0

+VS

2FD1

1K0
2

A0

100R

OS

1K0
3FD7

3FD4

IFD4

3FD6

SCL-SSB

100R

IFD2

7FD1
LM75BDP

GND

3FD3

SDA-SSB

LTST-C190KGKT

RES

RES
3FD1

+3V3

6FD1

RES
1329

1
2
3

502382-0370

1328
MSJ-035-69A-B-RF-PBT-BRF

FFDA

AMP1

2
3
1

22n

FFDB
22n
2FDD

CDS4C12GTA
12V
2FDC

6FD3
RES

CDS4C12GTA
12V
1FD3

6FD2
RES

1FD2

1K0

1K0
3FDG-4

3FDG-1

AMP2

B01J

FFDC

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_025_110420.eps
110420

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 102

Tuner Brazil

B01K

Tuner Brazil

B01K

5FE0

IF63

IF64

+2V5-BRA

+1V2-BRA-VDDC

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

100n
2FE4

2FE3

1u0

2FE0

30R

AGND
5FE3

IF65

IF66

+3V3-BRA-FLT

5FE4
+3V3-BRA

30R
1u0

100n
2FF6

100n
2FF5

100n
2FF4

100n
2FF3

2FF2

1u0

2FE6

30R

AGND
5FE5

IF67

IF68
+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25
5FE9

+5V
30R

18p

4 2

2FG3

18p

2FG2

25M4

1u0

100n
2FG1

2FG0

30R
1FE0

IN

OUT

INH

BP

FF03

+2V5-BRA

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

10n

100n

IF17
IF18

30
29

BFE2

28
27

BFE3

100n
2FH6

100n

24
25

2FH7

100n

26

AGND

39

AGND

PBVAL
RERR

0
XSEL
1

RLOCK
P
ADI_AI
N

RSEORF
SBYTE

P
ADQ_AI
N

SLOCK
P
AD_VREF
N

SRCK

AD_VREF

SRDT
STSFLG1

DTCLK

21
58
53
54
55

33R TS-BR-VALID

9F27-1

TS-FE-VALID

3FG6-3

33R

TS-BR-SOP

9F27-2

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

DFE8

DFE9
5FG0
3FG7
3FG6-2

60

11
SCL-SSB
SDA-SSB

3FE8

100R
3FE9

IF49
100R

45
46

AGCI
0
SLADRS
1

CKI
SCL
SDA

AGND

TN
VSS

SCL
SDA

33R

9F28

TS-BR-CLOCK

33R TS-BR-DATA

9F27-4

30R
5FG2

DFF1
30R

3FE5
18K

10
51

1u0

DFE7

DFF2

IF28
IF-AGC

AGND

42
6
5
12
14

3FG2-1

RESET-SYSTEMn
10K

3FG2-2
10K

3FG4-2
4K7

3FG4-1
4K7

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

PLLVSS

10K IF29

SYRSTN

17

3FE7

STSFLG0

0
TSMD
1

AD_DVSS

1
41

10K

AD_AVSS

3FE6

AGCCNTR

S_INFO

31

AGCCNTI

DTMB

23

+3V3-BRA-FLT

10n

DFE6

61

38

3FG6-4

IF27
40

AGND

1n5

59
52

2FH4

* To be drawn near PNX85500

2FH3

2FH5

1u0

43
FIL

2FH2

VDDS

DR2VDD

16
36
56
63

20

13
35
49
64

34
DR1VDD 48

VDDC

10n

2FG4

IF+
IF-

2FH8

3
2

PLLVDD

18

AD_AVDD

19

32

7FE0
TC90517FG

AGND

AD_DVDD

AGND

22

COM
AGND

AGND

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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110420

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 103

10-2 B02 310431365381


NANDflash - conditional access

PNX85500 NAND Flash - Conditional Access

B02A

7S00-5
PNX85500

D22
ALE
NAND
C21
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

XIO

B22
OE_
C22
WE_

XIO-OEn
XIO-WEn

CLK_BURST
CE1_
CE2_
NAND RDY2
RDY1
WP_

INPACK
XIO-D14
XIO-D15

B21
E21
D21
A20
F21
A21

IS26

INPACK

3S15
10K

+3V3
NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08

10K
RES

NAND-ALE
NAND-CLE

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15

3S1V

FLASH

10K

3S1W

+3V3

IS00

7S00-11
PNX85500
3S01-1 8
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

7 3S01-2 2
3 33R
33R 5 3S02-4 4
7 3S02-2 2
33R
33R 8 3S02-1 1
6
3 33R
3S02-3
33R 5 3S01-4 4
33R

P21
P22
P23
P24
P25
P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25

CA-DATAENn

K26
3S03

CA-MICLK

N23
10R
L25

CA-MOCLK

N24
3S31
CA-MIVAL
33R

N25

CA-MOSTRT

L22

CA-MOVAL

L23
J21
L24

CA-RDY

L26

CA-RST

J23

RES
9S01

CA-MISTRT

J24
+3V3

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

10K

3S1X

+3V3

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

ADD_EN
DATA_DIR

VS

K23
1
K24
2

CD

K21
1
K22
2

DATA_EN
I
MCLK
O

CA-VS1n
CA-MOCLK

9S00

CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

3S1U RES

560R
560R

RES

560R
560R

RDY
RST
VCCEN
VPPEN

T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP

TS-FE-DATA

TS-FE-DATA

3S23

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-CLOCK

3S24

TS-FE-VALID

3S28

TS-FE-ERR

470R
470R

TS-FE-SOP

3S29

RES 470R

100n

7S02
5

33R

RES 470R

3S04
2S09

B02A

1
4
2
1

SPB SSB
TV550 2K11 4DDR EU SD

74LVC1G08GW

2011-03-07

3104 313 6538


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110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 104

SDRAM

PNX85500: SDRAM

B02B

3S07

180R 1%

3S22

DDR2-VREF-CTRL2

2S12

CLK

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
VREF

1
2

N5
N4

DDR2-CLK_N
DDR2-CLK_P

3S30
10R

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K
RES

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

FS01

DDR2-VREF-CTRL3

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

2S24

FS02

100u 2.0V

3S06

180R 1%

3S20

180R 1%

+1V8

IS42
261R

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

1%

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

100p

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100n
2S25

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S17

DDR2-BA2

H1
H2
G1

100p
2S20

7S00-8
PNX85500
DDR2-BA0
DDR2-BA1

180R 1%

B02B

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 105

Digital video in

PNX85500: Digital video in

B02C

7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
U26
RX1_A
N

P
RX0_A
N

DDC_A

Y26
SCL
Y25
SDA

V25
P
RX2_A
V26
N
HOT_PLUG_A

HDMIA-RX0+
HDMIA-RX0-

DDCA-SCL
DDCA-SDA
IS10

T24

W25
P
W26
RXC_A
N

HDMIA-RXC+
HDMIA-RXCIS01

3S0W

W24

RREF

12K
10u

+3V3

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

RES
2S2E

B02C

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_029_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 106

Audio

B02D

PNX85500: Audio

B02D
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R

220n

2S3J
2S2S

10u RES

1u0 RES

100u 4V

1u0

2S41

4R7
2S42

3S51
AC8
3S3F

AF5

56R

DBS8

AE5

AD7
AE7
AF7
AD6
AE6
AF6

10

3S3G-2
2
7

IS1S

7S05-3
LM324 8

3S39

-AUDIO-R

100R

ADAC(3)

33R

4 3S3G-4 5

11

ADAC(4)

33R

AD4
OSCLK
AD1
I2S_OUT
SCK
AD2
WS
POS
VR_AADC
NEG
AE1
1
AF2
VREF_AADC
2
AE3
I2S_OUT_SD 3
AF3
VCOM_AADC
4

3S3H

3 3S36-3 6

10K

10K

5 3S36-4 4
2S2H

ADAC(5)

33R
3S3U

47p

ADAC(6)

+24V-AUDIO-VDD

33R

SPDIF_OUT
SPDIF_IN1

1n0

IS1A

IS03

ADAC(2)

1n0
2S38

AD8

1
2
3
4
5
6

ADAC(2)

33R

1n0
2S39

IS1B

1u0

AB9
AB8

AC6
P
AB6
N

1n0
2S3A

3S10
100R

2S2L

AF8
L
AIN5
AE8
R

ADAC(1)
3S3G-3

1n0
2S3B

1u0

1n0
2S3C

33R

2S3D

2S32

IS07
3

ADAC(5)

7S05-1
LM324 1

AUDIO-OUT-L

2
11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

11
3S6N

14

7S09-1
74LVC00APW
1

IS1D

&

SPDIF-OPT

47R

3
2
+3V3

+3V3

&
6

14

+3V3-ARC
7S09-3
74LVC00APW
9

&
8

5
+3V3

10

2S3L

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n
68R

3S25

IS1E

22K
2S2J

+3V3-ARC
7S09-4
74LVC00APW
12

14

SEL-HDMI-ARC

3S32

10K

47p

+3V3-ARC
7S09-2
74LVC00APW
4

3S34

&
11

+3V3

13
7

SPDIF-OUT-PNX

14

IS19

ADAC

AD9
L
AIN4
AC9
R

1 3S3G-1 8
IS1N

1u0

7
10K

ADACR

AE9
L
AIN3
AF9
R

100n

22K

AD10
L
AIN2
AC10
R

2S33

10u
2S3G

IS1Q

3S13-2

47p

2S36

AUDIO
AC7
AE10
L
P
AIN1
ADACL
AB7
AF10
R
N

1u0
3S17-2

100n
2S3H

AUDIO-IN4-R

8
10K

10u
2S3E

1 22K

2S3F

AUDIO-IN4-L

+AUDIO-L

+24V-AUDIO-VDD

100n

3S13-1

3S17-1

3S38
100R

11

7S00-2
PNX85500

1u0
1

7S05-4
LM324 14

13

10K

2S30

22K
IS1P

IS02

8 3S36-1 1
2S2G

1u0

6
10K

4
12

ADAC(1)

10K

1u0
3
3S17-3

+2V5

2 3S36-2 7

2S3Q

AUDIO-IN3-R

22K

4S14

2S2Y

2S31

3S13-3

1u0

10K

INH

IS1M
IS0V

4 3S17-4 5
10K

IS0R

3S13-4

BP

IS13

2S2Z

3S16-4 5
10K

FS03

2S34

100R

10K

IN

COM

1u0
3S16-3 3

AUDIO-IN3-L

2S2V

22K

OUT

IS12

7
10K

100n

2
3S16-2

100R
3S53-4

FS08

2S2T

IS1J

2 3S12-2

1u0

3S19

AUDIO-IN1-R

3S53-3

10u

22K

2S2W

2S2R

7S08
LD3985M25

100R

1 3S16-1 8
10K

IS1H

3S12-1

9S06
RES

1
AUDIO-IN1-L

+24V-AUDIO-VDD

+3V3

3S53-2

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 107

MIPS

B02E

PNX85500: MIPS

B02E
+3V3

7S00-3
PNX85500

CONTROL

+3V3
+3V3

3S80
3S81

10K

RES 3S21
+3V3
10K
3S62

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS
GPIO6

GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

IS04
PNX-SPI-CS-BLn

+3V3

5K6

SELECT-SAW

3S55

+3V3

FS64

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

10K

3S64

Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

B26
SDA
A25
SCL

1 3S58 2
100R

B25
SDA
3
A24
SCL

1 3S5Y 2
100R

B24
SDA
4
A23
SCL

1 3S60 2
100R

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS
BL_PWM

10K
CLK_54_OUT

3S83
+3V3

RXD1-MIPS

2 3S57

SDA-UP-MIPS
SCL-UP-MIPS

1
100R

2 3S5W

1
100R
1
100R

3S6A

4K7

SDA-SET
SCL-SET

SDA-SET
SCL-SET

3S6C

4K7

3S5Z

SDA-SSB
SCL-SSB

SDA-SSB
SCL-SSB

3S6E

2K2

3S61

SDA-TUNER
SCL-TUNER

SDA-TUNER
SCL-TUNER

3S6G

2K2

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

RES
1F10

3S69

SDA-UP-MIPS
SCL-UP-MIPS

4K7
3S6B

4K7

3S6D

2K2

3S6F

2K2

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

1
10K

10K
8 3S6H-1
3
6 3S6H-3
10K
2
10K

FS57

+3V3-STANDBY

+3V3

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5
10K

BOOST-PWM

+3V3

9S09

1
100R

3S27

3D-LR

DS52

10K
3S82

IS17

1 3S56 2
100R

10K

+3V3

BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS

C25
SDA
C26
SCL

3S26

10K
3S40

3S6J

BOOTMODE

RES 10K

IS05

3S45
+3V3

10K
+3V3
TXD1-MIPS

3S72

10K

+3V3
IS40
PXCLK54

47R

RES

+3V3
2S89
100n

+3V3

+3V3

7S01
PCA9540B

VDD

SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I 2 C
-BUS
CTRL

SC0

SCL-DISP

SC1

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-DISP
SCL-BL
SDA-DISP
SDA-BL

3S65

3S66 4K7
1
3S67 4K7
2
1
3S68 4K7
1
2
4K7
2

VSS
6

3S84

FS31

9S10
IS08
SCL-SET

SDA-SET

IS09

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13

SDA-BL

7S00-4
PNX85500

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
RXD ETH
AB4
2
AC1
3

ETH-RXDV
ETH-RXER
SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

IS50

RXCLK

TXCLK

0
1
TXD
AC2
2
RXDV
Y4
3
RXER
ETH
TXEN
W2
TXER
CC_DAT3
W1
COL
CLK
W6
CRS
CMD
W5
0
MDC
SDIO
W4
1 DAT
MDIO
W3
2
U6
SDCD
V6
SDWP

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_031_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 108

Video out - LVDS

B02F

PNX85500: Video out - LVDS

B02F

7S00-7
PNX85500
PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

9S90
9S91

LVDS

N
A
P
N
B
P

C10
N
CLK
B10
P

N
P

N
P

CLK

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
D10
P

9S94
9S95

PX3CLKPX3CLK+

N
P

D9
E9

PX3CPX3C+

A11
N
D
B11
P

D11
N
E11
P

PX3DPX3D+

PX1EPX1E+

C12
N
E
B12
P

E12
N
D12
P

PX3EPX3E+

PX2APX2A+

A14
N
A
B14
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B
B15
P

E15
N
D15
P

PX4BPX4B+

CLK

E17
N
D17
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
D19
P

PX4EPX4E+

PX1CPX1C+

A9
B9

PX1DPX1D+

PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+

9S92
9S93

LOUT1 LOUT3

N
C
P

C17
N
CLK
B17
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

LOUT2 LOUT4

9S96
9S97

PX4CLKPX4CLK+

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_032_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 109

Standby controller

PNX85500: Standby controller

B02G
POL

+1V1

B02G

2S13

100n

1u0
2S10

30R

RES
5S04

IS3B

3S1E
10K
+3V3-STANDBY

3S3L

10K

3S3M
10K
3S3P
10K
RES 3S3S
10K
3S3T
10K

+3V3-STANDBY
3S1H
10K

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM
LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

3S1G

RXD-UP
TXD-UP

10K
3S2A

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

AC20
0
AD20
1
AE20
2
AF20
3
P2
AA21
4
AB21
5
AC21
6
AD21
7

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n
RXD-UP
TXD-UP
DETECT2

AE21
0
AF21
1
AA22
2
AB22
P3
3
AC22
4
AD22
5

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS

AD23
0
AE26
1
AE25
P5
2
AE24
3

DETECT2

10K
RES

SPI-PROG
PNX-SPI-WPn

7S20
NCP303LSN28
2

FS45
1

AF26

AC17
XTAL_OUT
RESET_IN

STANDBY

EA
ALE
PSEN
MC

AE17

10p
2S4F
+3V3-STANDBY

10p

AF17
AA26

RESET-STBYn

AB24

EA

IS3F

AB23

ALE

AC26

AC23
SDA
AC24
SCL

AD26
0
AC25
PWM
1

PSEN
3S2F
100R

100R

3S2G

SDA-UP-MIPS
SCL-UP-MIPS

100R

3S2K

3S2H
100R

LED1
LED2

AE23
SDO
AF25
SDI
SPI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
AF18
P0
4
AA19
5
AB19
6
AC19
7

3S44

EA
ALE

IS3E

10K

3S43

IS3D

10K 3S42

10K

PSEN
RES

SDA-UP-MIPS
SCL-UP-MIPS

3S6V
4K7
RES

LED1

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

4K7

RES

3S41

10K

LED2

10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

3S6W
3S1P

RES
10K
RES 3S3Y
10K
10K

3S2S
RES
3S3W
4K7

3S2L
RES
10K
RES
10K
10K

3S46
3S47

+3V3-STANDBY

3S2M
RES
3S49

4K7

+3V3-STANDBY

INP

IS2U
5

OUTP
CD

1K0

+3V3-STANDBY

1 3S2V 2

10K

SPI-PROG

2
4
1

FS0Z

RESET-STBYn

NC GND
3

100n
3S1L

AF22
4
AE22
P6
5

2S4E

7S00-9
PNX85500
XTAL_IN

2S4G

100n

100K
RES

KEYBOARD

2S4K

3S1J

9S0E

RESET-SYSTEMn

RES

10K
RES

9S0D

3S1K

DS50

VDD_XTAL

10K
3S1D
27K

VDDA_ADC2V5

RES
10K
RES
3S1F

AD17

2S4D
1n0

3S1B
3S1C

VSS_XTAL

+3V3-STANDBY

VDDA_1V1_DCS

AA17

IS20

54M

100n

1S02

9S24

1u0
2S11

RES

2S37

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_033_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 110

Power

PNX85500: Power

B02H

5S80

IS3Q

+1V1
2S5A

RES 10u

100n

2S6A

B02H

30R

5S81

2S5B

RES 10u

100n

2S6B

+2V5
30R

5S82

IS3S

100n

+3V3
2S5D

2S4M

100n

U22

VDD_3V3_SBY

10u

VSSA_USB

VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

10u

100n

10u
2S4U

100n

2S4Y

10u

2S50

100n

2S4Z

6.3V
10u

100n

c000

SENSE+1V2

Y17
D13
T20

POL

Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_USB

+1V2
30R

R21

R20

VSSA_2V5_LVDS_BG

100n

2S45

+2V5-AUDIO

5S87
+2V5
1u0

2S56

100n

2S55

30R

5S88
30R

10u

100n
2S57

2S5M

+2V5-LVDS

+2V5
100n
2S58

30R

10u

2
100n
2S6K

2S6H

5S89

5S90
+2V5
10u

100n
100n

2S53

2S4T

30R

2SHW

5S92
1u0

100n
2S59

+3V3
30R

100n
2S6L

2S6M

IS58

VDD_1V1_DDR

VSSA_1V1_LVDS_PLL

VDDA_2V5_LVDS_BG

30R

2S46

VDDA_2V5_DCS

AA7

+2V5

30R

5S84

AA9
2S52

VDDA_2V5_ADAC

5S95

Y12

RES 1u0
2S4W

+1V1
IS3L

2S51

VDDA_2V5

5S83

B13

AA15
Y15
VDDA_1V2
AA13

VDDA_2V5_AADC

2S6P

100n

100n
2S6C

2
100n
2S6N
1

Y19
Y18
IS3K

VDDA_1V1_LVDS_PLL

+3V3

30R

+3V3-STANDBY
2S4V

VDD_1V1

W20
P20
M20
K20
V7
Y8

100n
1 2S6G 2

5S85
2S6F

VDD_2V5_LVDS

100n

2S4N

C7
C9
C11
C14
C16
C18

2S4P

+2V5-LVDS

N6
N7

VDD_2V5

VDD_3V3

220u 6.3V

100n
2S6E 2

U20
U21

2S6D

HDMI_VDDA_2V5

+2V5

30R

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

A13

1u0

2S21

100n

2
1

2S5P

VDD

C13

J7

30R

VDD_1V8

HDMI_AGND

2S29

220u 2.5V

5
100n

7
2

100n
2S5J-4

100n
2S5J-2

5S94
+1V1

10u
RES

VSS

2S4S

VSS

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

U24
V24

100u

2S23

5
100n

100n
2S5H-4

6
3
2
8
100n
2S5J-1

100n
2S5J-3 6

4
3

100n
2S5K-4

100n
2S5K-3

100n
2S5K-2

2S5K-1
1
AA16
AA8
Y11
Y14
Y16
Y9

VSS

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

100n
2S5H-3

100n
2S5H-2

8
100n
2S5H-1
1

100n
2S5G-4

100n
2S5G-3

7
2

100n
2S5G-2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

+1V1

30R

5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

VSSA

RES 10u

c001

SENSE+1V1

7S00-12
PNX85500

100n

2S5C

100n
2S68

100n
2S67

100n
2S66

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

2S26

100u
2S60

+1V8

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_034_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 111

Analog video

PNX85500: Analog video

B02I
2S87

AV1-CVBS

Y-SVHS

2S8A

47R

3S5B

22n

56R

Connectivity

3S59

47R

22n

3S05

B02I

2S7J

AV1-R

2S22

3S4J

56R

22n

C-SVHS
22n

EU: SCART1

CVBS-MON-OUT1
22n

560R

3S5E

2S7K

AV1-B

56R

3S4L

AP:

3S08

560R

47p

2S7H

2S40

IS4V

22n

2S7M

YPBPR1-SYNCIN1

10n
2S7L
56R

3S4P

AV3-Y

22n
7S00-1
PNX85500

2S8G

9S18

22n

AB14
AF14
AE14
AC14
AD14

2S7R

AV4-Y

SCART2
YPBPR2

22n
9S19

EU:

AF15
AE15
AC15
AD15

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75
BS15

PNX-IF-AGC

10K

BS10

IS11

3S76
10n

2S76

AA14

PNX-RF-AGC

47K

9S20

22n

2S14

BS13

AGND
2S7U

2S15
22n

AD11
AC11

+CVBS
AV4-PR

2S16
22n

22n

IS5C

2S18
22n

AC12
AF13

22n

CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CURREF
CVBS_Y2
SYNCIN2
1
Y_G2
2
PR_R_C2
3
PB_B2
REF 4
5
R
6
G VGA
B
IF_AGC
HSYNC_IN
IN
RF_AGC
VSYNC
OUT
SCL VGA_EDID
P
TUNER N
SDA

2S19

56R

3S4T

AB15
AC13
AD13
AE13

22n

AV2-CVBS

AP:

ANALOG_VIDEO

2S7P

AV3-PB

10n

YPBPR1

2S75

56R

YPBPR1

3S4R

AP:

22n

2S7N

AV3-PR

EU:

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S77

PNX-IF-P

10n

2S7E

AV4-PB
9S21

22n

2S78

PNX-IF-N

10n

2S84
56R

3S50

R-VGA

22n

2S85
56R

3S52

G-VGA

22n

2S86

100R

2 3S5V-2 7

100R

100R
3 3S5T-3 6

4 3S5V-4 5

V-SYNC-VGA

100R

1 3S5T-1 8

100R

H-SYNC-VGA

2 3S5T-2 7

AP: VGA

22n
4 3S5T-4 5

56R

EU: VGA

3S54

B-VGA

100R

VGA-SCL-EDID

RES

3 3S5V-3 6

RES

1 3S5V-1 8

100R
VGA-SDA-EDID

100R

* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ

SPB SSB
TV550 2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_035_110421.eps
110421

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 112

10-3 B03 310431365381


Audio

Audio

B03A

+AVCC
7D03-1
BC847BS(COL)

+24V-AUDIO-POWER
FD14

3D09

+24V-AUDIO-POWER

B03A

1u0

3
3D02-3

7D15-2
BC847BS(COL)
4

4K7

220R

ID18

6
5
18
17

2D16

ID29

11
7
4
2

1u0

2D17

ID30

1u0
ID37

AUDIO-MUTE-UP

IN
L

2D22
220n

2D26
RES

8
3D14-1
220n

7
3D14-2
22K

2D12

PVCC
BSR

CLASS-D
AUDIO AMP

6
3

4
ID19

GND-AUDIO

AVCC

47n

3D14-3
22K

5
3D14-4
22K

22K

2D08

47u 35V
220n

47u 35V
2D32

7D10-1
TPA3123D2PWP

2D23

ID15

GND-AUDIO

10
12

2D29

GND-AUDIO

1
3

FD03

4K7

+AUDIO-L

7D15-1
BC847BS(COL)
1

47u 35V
2D20

19
20

4K7

2D34

3D02-2

3D02-4

47n

ID28

A-PLOP

4K7

1u0
FD08

ID27
47u 35V
2D07

2D24

2D19

ID14

2D28

3D02-1
8
1

FD01

GND-AUDIO

220n

2D05

10u 35V

22K

-AUDIO-R

220R
5D08

5D07

ID12

220n

3D16
ID11

2D06

4R7

R
OUT
L

0
GAIN
1

BSL

16

ID32

2D10
220n

15

21

ID06

22u

22

5D01

ID09
ID31

2D09

25V 100u
2D36

5D05

5D02

ID10

22u

ID05

220R

ID08

25V 100u

5D04

ID07

2D11

220R

RIGHT-SPEAKER

LEFT-SPEAKER

25V 100u
2D35

220n
VCLAMP
BYPASS
MUTE
SD

25V 100u

PGND
GND_HS
25

EMC

2D21
220n

3D10-1
220n
1

2D27
RES

7
3D10-2
22K
2

GND-AUDIO

DETECT2

GND-AUDIO

26
27
28
29

LEFT-SPEAKER

VIA
VIA

VIA

VIA

37
36
35
34

GND-AUDIO

10n

GND-AUDIO

GND-AUDIO

GND-AUDIO

40
39
38

2D03

7D10-2
TPA3123D2PWP

V_NOM
2D14

GND-AUDIO

3D01-4
47K

100p

GND-AUDIO

3D10-3
22K

GND-AUDIO

+3V3-STANDBY
ID35

7D11-2
BC847BS(COL)
4

4n7

ID34

1D50

3D10-4
22K

EMC 4n7
RES 2D31

FD15

CD10

22K

RES 2D30

MAINS SWITCH DETECT

4K7

47K

3D01-3

7D11-1
BC847BS(COL)
1

3D15

+3V3-STANDBY

6
6

23
24

8
9

AGND

13
14

FD09

A-STBY

VIA
30
31
32
33

1735

LEFT-SPEAKER
3

100K 6

3D06-4
100K

10n

4
RIGHT-SPEAKER
1

ID33
1D52

GND-AUDIO
4

2041145-3

2041145-4

100K

RIGHT-SPEAKER

1
2
3

100K
3D06-1

10n
2D13

3D06-2

FD02

1D38
1
2
3
4

2D02

V_NOM

3D06-3 FD07

GND-AUDIO

2D01

220R
GND-AUDIO
3 7D03-2
BC847BS(COL)

FD05
FD06

5D03

5
1

10u

SPB SSB TV550


2K11 4DDR EU SD

GND-AUDIO

2011-03-07

3104 313 6538


19050_039_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 113

DC/DC

B03B

DC/DC

B03B

5U03 RES
30R
5U02

FU05

IU22
+12V
1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03
22u

47u

2U16

2U15

8
47R
1

47R
3U23-1

3U23-2

3u6

5 6
IU23

1n0

2U17

IU09

47R

7U02-2
SI4952DY

3U23-4

47R
3U23-3

220p

+1V8
IU11

IU15

IU08

5 6 7 8

IU12

3U14
IU07

20

VIN

V5FILT
VREG5

3U28
GND-SIG

18
19

FU04

1u0

2U05

10K

10u

100n

2U14

RES 100u 2.0V

22u

2U13

IU17

IU25

GND

+1V1

IU18
1u0

2U10

GND-SIG

1n0

2U09

GND-SIG

3U21

FU00

SENSE+1V1

IU19

GND-SIG

RES 100p

22K

3U10

GND-SIG

CU00

5K6

FU08

3U19

FU09

IU04

100p RES

3U22
1K0 1%
3U09

330R 1%

1K0 1%

3U08
+1V8

2U08

IU20

100n

RES
2U29

3U17

1% 330R

3U18

1% 1K0

100R 1%

2U07

10K

7
17

47u

1
2

2U12

TEST

10R
RES

1
TRIP
2

22
15

3U20

1
2

+1V1

47R

PGND

FU01

2u0
47R
3U24-1

1
VFB
2

5U01

FU06

24
13

3U24-2

1
2

47R

SW

12V/1V1 CONVERSION

1
12

47R
3U24-3

1
VO
2

1 2 3

3U24-4

1
2

4
IU14

1n0

GND-SIG

DRVH

5 6 78

IU16

23
14

2U11

IU02

12K

GND-SIG

1
EN
2

2U06

3U00

3U01

3U03

22K

21
16

1
2

2U04

1
2

+3V3-STANDBY

5
8
IU01

DRVL

7U04
SI4778DY

6U00

1n0 RES

2U03
IU03

4
9

+1V1
+1V8

1
VBST
2

220p

STPS2L30A

3
10

ENABLE-1V8

3R3

2U01

100n

2
11

IU24

GND-SIG
3U02

3U05

7U03
TPS53126PW

IU13

10R

2U02
100n

7U00
BC847BW

3R3

2U22
IU06

IU05

RES

1 2 3

3R3

10u

2U00

10R

3U04

1n0

3U27

2U18

7U01
SI4778DY

IU21

CU01
CU02
CU03
CU04
CU05

GND-SIG

GND-SIG

GND-SIG

GND-SIG
GND-SIG

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_040_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 114

DC/DC

DC/DC

B03C

+3V3-STANDBY

+3V3

RES 10K

+5V +3V3-STANDBY

3U75

3U74

RES 10K

LED-2

IU43

LED-1

To be connect directly to 1M59 with 3mm Track width

3U41

LED2

3U59

LED2

10K RES

10K RES

7U42 RES
BC847BW

IU47
7U43
BC847BW

3U70

LED1

3U53

LED1

10K

***
1M99

+3V3

10K

**

+12V_AL
FU07

3D-LR

100p

ENABLE-3V3-5V

100K
IU41

BL-SPI-SDO
BL-SPI-CSn
BL-SPI-CLK

+3V3-STANDBY

RES 100p

2U43

RES 100p
2U52

100R

RES
3U67
100R
RES
3U84
100R
RES
3U76
MAINS-OK
RES 100R

7U48-1
BC857BS(COL)

3U66

FU56
FU57
FU74
FU68

2U51

1n0

2U48

***

2U56

1n0

RES 100p

100p RES
2U72

BL-SPI-SDO-1
BL-SPI-CSn-1
BL-SPI-CLK-1
MAINS-OK-1

3U83-4

3U44
100R

+12VIN

1-2041145-3

RES 2U57

FU54

3D-LR-1

10K

100n

+3V3

FU50

FU77
FU78

1K0 RES

3U56

FU49

**
GND_AL

3U83-1

**

GND_AL

IU64

3U82

FU48

3U71

GND_AL

1
2
3
4
5
6
7
8
9
10
11
12
13

100K

3U69

IU44
IU45
9U42
RES

2U71

*
**

RES 10K

optionally 1M99 is a 9 pin connector

10K

3U68

9U41

STANDBY

7U48-2
BC857BS(COL)

100R

3U62-4

100K

FU51

100R
100R

FU53

FU55

***

4U00

3U42

BACKLIGHT-PWM_BL-VS

3U43

BACKLIGHT-BOOST

***
POWER-OK

Items

100p

1n0

10n

2U44

2U45

2U46

100K

3U65

1n0

1K0

2U53

4U00
4U01
1M99
1M95
2U56

+12VD

RES 10K

3U61

7
10K

2
7

DETECT2

5
IU50

3U60-4

7U41-2
BC847BS(COL)
8

22K

4K7

IU62

6
1
7U41-1
BC847BS(COL)
1

LAMP-ON

IU55

3U64

FU72

3U80

2U55

+3V3-STANDBY

100R

4U01

10K
3U62-1

3K3

3U45

3U60-2

IU63

3U73

ENABLE-1V8

10K

3U60-1

IU57
1

ENABLE-3V3n

22K

IU52

RES 10K

IU56

FU73

22K

3U81

3U60-3

3U63

+3V3

GND-AUDIO

3U62-2

7U40-1
BC847BPN(COL)

1K0

3U72

10n

2U50

100p
RES

2U49

+24V-AUDIO-POWER

IU49
6

10K

GND_AL

3U83-2

3
IU61

22K

IU51
T 3.0A 32V

FU66

FU76

***

+12V

+12VIN

FU52

+12VIN

1U40

3U62-3

3
2U54

FU67
LAMP-ON-1
BACKLIGHT-PWM_BL-VS-1
BACKLIGHT-BOOST-1
POWER-OK-1
FU62
+24V

1-2041145-4

6
IU40

100K

10n

1u0 RES

+3V3-STANDBY

6U40

STANDBY-1

BZX384-C6V2

10n
FU58
FU59
FU60
FU61
FU63
FU75

IU48

3U83-3

1n0
RES

1
2
3
4
5
6
7
8
9
10
11
12
13
14

3
4

1u0
2U47
1M95

7U40-2
BC847BPN(COL)

10K

2U68

2U58

B03C

Optional table for Ambilight


Emmy
( +24V AL)
yes
yes
no
yes
no

Sundance / Infinity
( +12V AL)
no
no
yes
yes
yes

BlockBuster
(For non-Amblight sets)
no
no
no
yes
no

Dream Catcher
Core Range

2U44

3U43

1M95

0R

open

13 POLE

100p

100R

14 POLE

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_041_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 115

DC/DC

B03D

DC/DC

+3V3

B03D

7UC0
LF25ABDT

+12V

IN

OUT

1u0

2UA4

2K2

3UA0

COM

FUA0
+2V5-REF

7UA0
TS2431

FUA4

CUA0

IUB6

+2V5-LVDS

+5V-TUN

3U15-1

IU26

+3V3

+5V

3U16-1

100R

3UB0

1u0

2UB0

7UA3
PHD38N02LT

IUB4

3U15-2

3U15-3

3U16-2

FUA3

3U15-4

+1V2

3U16-3

100R
4

3U16-4

100R

100R

1u0

2UB2

RES 1u0

2UB1

100R

100R

22R

+3V3

100R
7

100R

IUA5

470R

2
470R
3UB7-3
6
3
3UB7-4470R
5
4

+5V

2UB8

7UA7-2
4
BC847BS(COL)

+1V8

470R

3UB7-2

+2V5-REF

3UB6-2

3U12
7
IUB3
1K0 IUB2
3UB6-3
3
6
6
1K0
3UB6-4
4
5
2
1K0
3UB6-1
IUB5
7UA7-1
1
8
3 1
BC847BS(COL)
1K0
3UB7-1
3U13
8
1
5
2

22u

+12V

330R
1%

7UA6
BC817-25W

330R
1%

+5V5-TUN

+2V5

NOT FOR 5000 SERIES

ENABLE-1V8
5

3UB1

RESERVED
5UA0

1K0

30R
8

RES

+12V

7UA5
LDS3985M50

RES

IU30

3U29-3

RES
5

3U29-4

RES

3U26-1

3U26-3

NC

IN

OUT

INH

BP

+5V-TUN

IUB1

COM

1
3UB3

RES
3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V

470R
+3V3

NC

RES

470R
3U26-2

K
REF

470R
1

3UB2

4K7

7UA4
TS431AILT

470R

+5V5-TUN

470R

1u0

RES
7U06-1
BC847BS(COL)
1

2UB7

+3V3

3U29-2

4K7

3
RES
7U06-2
BC847BS(COL)
4

1
3U25-1

100K RES

470R
IU29

1u0

3U29-1

100n
2UB6

2UB5

3U25-2

100K RES

IUA6

SENSE+1V2

3U25-3

100K RES

100K RES

3U25-4

RES

22n
2UB4

470R
4

3U26-4

RES

330p
RES

470R

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_042_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 116

DC/DC

DC/DC

B03E
5UD0

IUD0

+12V

IUD6

33K
1%

22u

IU27

3U06

120K

RES

12

68K
3UD1

1%
3UD0

VIA

10

4n7
3UD2

15

13

7UD0-2
ST1S10PH

7U05-1
BC847BS(COL)
RES 1

10K

2UD7

RES 2UE9

100n

+1V1
RES 2U27

SS36

220u 16V

SW

FUD3
+5V

3u6

VFB
GND
P HS

6UD0

IUD7

2UD6

SYNC

5UD1

2UD4

VIN

IUD3

SW

22u

INH

RES 1n0

2UD3

ENABLE-3V3-5V

22u
2UD5

1
A

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10PH

+5V5-TUN

30R

14

11

5UD3

7U05-2
RES
4

3U07

100n
IU28

RES

33K
1%

12

1M0
3UD5

3UD4

VIA

10

15

13

IUD2
7UD1-2
ST1S10PH

BC847BS(COL)

10K

RES 2U28

2UE4

22u

22u
2UE3

2UE2

+1V1

220u 16V

+3V3
3u6

VFB
GND
P HS

FUD2

5UD2

1% 100K

SYNC

IUD4

SW

VIN

4n7
3UD3

INH

2UE1

ENABLE-3V3-5V

SW

7UD1-1
ST1S10PH

10u

14

11

7UD2
LD1117DT25
3

IN

S1D

OUT

+2V5
2UE6

100n

2UE5

COM

22u 16V

IUD5

(*) FOR 5000 SERIES ONLY


(**)

NOT FOR 5000 SERIES

7UD3
LD1117DT33
IN

OUT

+3V3

100n

COM

22u 16V

2UE8

6UD1
+5V

2UE7

10u

2UD9

10u

30R

IUD1

+12V

2UE0

**

2UD8

B03E

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_043_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 117

Temperature sensor & AmbiLight

B03F

Tempsensor + Ambilight

B03F

5UM1

IUM0

1UM0

+3V3
30R

FUM0

V-AMBI

T 1.0A 63V

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_044_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 118

Fan control

Fan Control

B03G

+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
6
3

IUT1

100n

2US3

7
7US1-1
LM339P
14

3US7

10K

3US5-2

10K

+12V

10K

3US2

3US4-1

+3V3

IUS6

10K

7US2
BC807-25W

12
+12V

IUS7

11

7US1-2
LM339P
13

IUT2

IUS4 3US5-4
5
4

10

FAN-CTRL2

10K

22R

BC807-25W
7US3

IUS8

12

3US6

IUS9

47R

3US3

+12V

10K

3US5-1

3US9

+3V3

10K

FAN-DRV
+3V3

10K

10K

3US4-3

7US1-3
LM339P
2

+12V

IUS5

3US4-4

+12V

+12V

10K

+12V

3US4-2

RES

12

TACH01

9US0
TACH02

7US1-4
LM339P
1

FUS0

12

B03G

TACHO

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_045_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 119

Vdisp switch

Vdisp-Switch

B03H

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

7UU0
SI4835DDY

47R
3UU0-2

6
FUU0

IUU1

2
IUU2

1u0

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

+3V3-STANDBY

47K

47K
3UU0-1

2
3

7UU2-1
PUMD12
1

47K

6
3UU0-3

22n

2UU2

+VDISP-INT

47K RES
2UU1

3UU1

IUU0

IUU4 3UU3-3 IUU5 3UU3-4


4
5
6
3
47K RES

VDISP-SWITCH

2UU0

3UU3-1

6
5

FUU1
3UU2

+3V3

47K RES
RES 100n

RES
7UU1
SI3441BDV

+12VD

4
PUMD12
7UU2-2

B03H

+3V3

4K7 RES

LCD-PWR-ONn

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_046_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 120

10-4 B04 310431365381


Analogue externals A

B04A

Analogue externals A

B04A

DEBUG

DEBUG

FE70

3E37

AP-SCART-OUT-R

IEC0

3EA7-1

IE67

2EA4

AUDIO-OUT-L

8 470R 1
FEA0

7E01-1 6

1n0

2E87

1E00

CDS4C12GTA
12V

RES 6E01

100p

2E01

100R

1u0 16V
AP-SCART-OUT-L

IEC1
2
1
PUMH7

FEA2

AUDIO-IN1-R

RES

FE71

3E07

IEC2

IE68

2EA5

AUDIO-OUT-R

5 470R 4
FEA1

7E01-2 3

1n0

2E88

1E31

RES 6E03

100p

2E06

CDS4C12GTA
12V

3EA7-4
1K0

1u0 16V
AP-SCART-OUT-R

5
4
PUMH7
RES
FE72

3E38

AP-SCART-OUT-L

3E24

1n0

2E90

1E53

CDS4C12GTA
12V

RES 6E07

100p

2E10

100R

A-PLOP

2K2
RES

DEBUG
3E08

AUDIO-IN1-L

4K7

3E17

1R0

5K6

3E06

1K0

3EA1

100n

2EB1

3E73
IE59

5E80
10u

CVBS-MON-OUT1

330R

BC847BPN(COL)

18K

2u2

18p

2E81

2E98

IE70
2

IE60
1 3EB1 2
1
820R

IE51
AV2-BLK

4p7

39p

7E06-1

3 BC847BPN(COL)

2E97

2E99

39K

1u0

7E06-2

3E18 2

2EB3

IE61

4K7

IE89

1 3EB3 2

100p

2E14

9E01

2E15

100p
100p

2E18

1E55

12V

CDS4C12GTA

+3V3

IE13

3E19

1n0

2E91

3EA2

RES

1E18

150p

FE80
CDS4C12GTA
12V

18R

1E12

FE74

RES 6E26

3E77

1u8

2E84

150p

5E74

IE90

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FE75

RES 6E22

4K7

3E32
3E76 18R

* EU

49045-0011
25
26

3E31
12K

2E83

IE05
+5V

FE73
IE18

AV1-STATUS

FEA5

CDS4C12GTA
12V

150p

2E80

150p

2E79

18R

RES

AV1-G

AV2-STATUS

DEBUG

3E75

BEC3

1u8

RES 6E23

AV1-B

5E73

1E54

6E09
RES

100p

2E04
3E74 18R

FEA4

CDS4C12GTA
12V

1K0

FEA3

1E01
FE85

3E78

+5V

18R

RES

IE96

3EB6-1

100n

100p

2E12

1E19

CDS4C12GTA
12V

FE81

18R

150p

2E86

150p

2E85

1u8

3E79

2E74

BEC5

5E76

RES 6E28

FEA6

AV1-R

IE91
8

470R
IE92

7E05
BC847BW

CVBS-OUT-SC1

470R

100n

2E24

4K7

3E44

3EB6-4

3E45
68R

+3V3

RES
3E48
3

68R
3E42

100p

RES 2E75

1E22

6E29
RES

FEA8

AV1-CVBS

12V

FE82

4K7

CDS4C12GTA

3E43

7E09
BC847BW
2

75R

FEA7

AV1-BLK

3E62

100p

2E44

1E25

12V

RES 6E32

CDS4C12GTA

FE84
27R

1X06
EMC HOLE

CVBS-OUT-SC1

1X02
REF EMC HOLE

3EB6-2

470R

3EA7-3

3 3EB6-3 6

3 470R 6

470R

100p

RES 2E76

1E23

12V

CDS4C12GTA

RES 6E30

FE83

3EA7-2
2 470R 7

** Provision for ESD

SPB SSB TV550


2K11 4DDR EU SD

DEBUG

2011-03-07

3104 313 6538


19050_047_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 121

Analogue externals B

Analogue externals B

B04B

YPBPR
1E08-3
* GREEN
MSP-8033SH-02-NI-FE-RF-PBT-BRF

3E87

FE54

1E08-2
BLUE
MSP-8033SH-02-NI-FE-RF-PBT-BRF

FE51

3E89

1E08-1
RED
MSP-8033SH-02-NI-FE-RF-PBT-BRF

CDS4C12GTA
12V

RES 6E51

1E28

100p

2E67

3E90

FE42

FE5B

AV3-PB

FE5C

AV3-PR

18R

CDS4C12GTA
12V

RES 6E52

1E39

100p

2E68

AV3-Y
YPBPR1-SYNCIN1

18R

FE48

FE5A

18R

CDS4C12GTA
12V

RES 6E40

1E43

2E27

100p

YPBPR AUDIO
1E03-1
RED
MSP-8032SH-01-NI-FE-RF-PBT-BRF
2

FE43

AUDIO-IN3-R

100p

1K0
2E72

CDS4C12GTA
12V

RES 6E06

1E29

1n0

2E39

FE5D

3E97
FE50

1E03-2
FE49

FE5E

AUDIO-IN3-L

1K0
100p

CDS4C12GTA
12V

3E96

RES 6E38

1E42

1n0

2E40

MSP-8032SH-01-NI-FE-RF-PBT-BRF
4

2E71

* WHITE

VGA ( OR DVI ) AUDIO

IE09
AUDIO-IN4-L

1K0
100p

CDS4C12GTA
12V

3E21

RES 6E19

V_NOM

1n0
1E37

2E36

FE02

2E35

1E09
MSJ-035-12D-B-AG-PBT-BRF
2
3
1

FE01
IE10
AUDIO-IN4-R

100p

1K0
2E38

CDS4C12GTA
12V

3E20

RES 6E20

V_NOM

1n0
1E38

2E37

FE03

1E10
3150-831-030-H1
2
VCC

1R0

SPDIF-OPT

CDS4C12GTA
12V

RES 6E53

V_NOM

100p
1E80

100n

GND
MT
7 6 5 4

FE55

RES 2E77

VIN

3E9C

+3V3

2E73

B04B

** Provision for ESD

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_048_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 122

Ethernet & Service

Ethernet & Service

B04C

IE07

5E08
+3V3

+3V3-ET-ANA

+3V3-ET-ANA

47R
3E53-3

IE50

47R

+3V3

6E43
IE38

IE32

FE57

1E06

2
3
1

UART
SERVICE
CONNECTOR

47R

MSJ-035-69A-B-RF-PBT-BRF
FE58

ETH-TXD(3)
ETH-TXER

10u

2E48

100n

2E49

12

ETH-TXCLK

10K

3E34

10K

3E72

3E68
RES
3E35
RES

X1
ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3

9E42

14

ETH-CRS

RXD1-MIPS
32

RBIAS

VSS
14

33

+3V3

10K

10K

13

RES
7E11-2
74HC4066PW
4
1

X1
IE39

MDC
MDIO

+3V3

RES

RXD-UP

ETH-RXCLK

10K

RES
3E9E

RES

3E65

RES
7E11-1
74HC4066PW
1
1

RES
3E9D

+3V3

IE64

10K

14

ETH-RXER

3E64

CRS

ETH-RXDV

IE63

13

REGOFF
1
LED
2
INTSEL

BAS316

20

RES
6E48

ETH-TXP
ETH-TXN

100n

29
28

1
2
3

502382-0370

RES
2E69

ETH-RXP
ETH-RXN

26

RXER
RXD4
0
PHYAD
1
RXCLK

0
1
2 TXD
3
4
INT
TXER

17
16

ETH-MDC
ETH-MDIO

P
N

31
30

14

22
23
24
25
18

TX

RXDV

TXEN

RES
1E71
TXD
RXD

RES
7E13
PDTC144EU

RES
7E12
PDTC144EU

AV2-BLK

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

P
N

12K1
1%

21

RX

TXCLK

COL
CRS_DV
MODE2

+3V3

ETH-TXEN

27

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

15

1K5

FE56

IO

RST

10K

10K
10K

1A 2A
VDD

3E40

19

RES 3E71
RES 3E80

3E51

CLKIN
1
XTAL
2

11
10
9
8
3E70
RES

4n7

100n
2E53

2E52
10p

2E54

10p

10K
3E33

2E55

10K
10K
10K
10K

7E10-1
LAN8710A-EZK

10p

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

ETH-COL

PROVISION FOR BUH


CR

RES 2E70

47R
3E53-4

+3V3

25M

5
4

3E69
RES
10K

IE06

3E53-1

IE33

1M0
1E70
NX3225GA

RES
RES
RES
RES

3E66
3E67
3E81
3E82

3E30

IE26

+3V3

RESET-ETHERNETn

1E86

RXD1-MIPS

IE49

7 3E53-2 2

1E85

TXD1-MIPS

BZX384-C5V1

100n

100n
2E66

10u
2E63

2E62

30R

BZX384-C5V1
6E44

B04C

TXD-UP

1
1

7E10-2
LAN8710A-EZK
34
35
36

VIA
VIA

14

43
44
45

X1

RES
7E11-3
74HC4066PW
8

40
41
42

VIA

10

TXD1-MIPS

RES
7E11-4
74HC4066PW
11
1

1
X1

12

37
38
39

VIA

+3V3-ET-ANA

+3V3-ET-ANA

22R

22R
3E98

3E26

49R9
1%

3E99

3E95

49R9
1%

3E25

49R9
1%

3E22

49R9
1%

CONFIGURATION RESISTOR SETTINGS

Resistor

POP

EMPTY

ETHERNET CONNECTOR
ETH-TXP

1E87
3 ACM2012 2

FE27

1N00
FE60

ETH-RXP

FE29

1E88
3 ACM2012 2

ETH-RXN

FE31

FE30
FE61

22n

9
10
2E60

5
4

15p

CDA5C16GTH
16V

6E47-4

CDA5C16GTH
16V
RES

6
6E47-3
3

CDA5C16GTH
16V
RES

6E47-2

RES

6E47-1

RES 27n
RES 15p
2E59

0 ohm

RES

RES

5E04
2E09
15p
3E39

2E58
RES

5E03

RES 27n

2E08

RES 15p
0 ohm

RES

15p

3E29

2E57
RES

5E02

RES 27n

2E07

RES 15p
0 ohm

RES

15p

3E28

RES 2E56

5E01
2E05

RES 27n
0 ohm

RES

3E27

RES 15p

FE28

CDA5C16GTH
16V
RES

ETH-TXN

FE34

1
2
3
4
5
6
7
8
11
12

3E64 (RES)

PHYADD(0) = 1

PHYADD(0) = 0

3E65 (RES)

PHYADD(1) = 1

PHYADD(1) = 0

3E66 (RES)

PHYADD(2) = 1

PHYADD(2) = 0

3E67 (RES)

RMII mode selected

MII mode selected

3E68 (RES)

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69 (RES)

MODE(0) = 0

MODE(0) = 1

3E70 (RES)

MODE(1) = 0

MODE(1) = 1

3E71 (RES)

MODE(2) = 0

MODE(2) = 1

INTERRUPT FUNCTION

INTERRUPT FUNCTION

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

5450-323-183-H3

FE32

3E72

ETH-INTSEL
ETH-REGOFF

FE33

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_049_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 123

HDMI

HDMI

ARX2+

MICOM-VCC33

10K

1u0

FEC3
2EC2

10u

2ECV

100n

2EC0

FEC0

3ECH

ARX1ARX0+

65
66

BRX2+

ARX0ARX0+

67
68

BRX2BRX1+

ARX1ARX1+

69
70

ARX2ARX2+

71
72

AIN-5V

BRX1BRX0+

BIN-5V

BRX0BRXC+

BRX-DDC-SCL
BRX-DDC-SDA
BIN-5V

BIN-5V

1u0

BRX-HOTPLUG

BIN-5V

2 3ECM-2 7

CIN-5V

1P02
CRX2+

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

1u0

CRX2CRX1+
CRX1CRX0+

CRX-HOTPLUG
3E23
RES
7E02
BC847BW

PCEC-HDMI

47K

CIN-5V

20
22

3ECD
100R

+3V3-STANDBY

1 3ECM-1 8

4
3ECN-4

10R

DRX-DDC-SDA
DRX-DDC-SCL

1u0

1
2

BRX0BRX0+

3
4

BRX1BRX1+

5
6

BRX2BRX2+

7
8

6
100K

IE44

2ECP

41
42
39
40

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

5
100K

IE45

2ECQ

5EC2
30R

ARC-eHDMI+
2ECC

CIN-5V

IEC4

DIN-5V

eHDMI+

22K
RES

7EC0
BC847BW

33
34

DRX-HOTPLUG

47K

FECM
FECN

CRX-DDC-SCL
CRX-DDC-SDA

10p

FECK
FECL

3 3ECA-3 6

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

5 3ECA-4 4

CIN-5V

CRX0CRXC+

FECA

2ECN

35
36

CRX-HOTPLUG

HDMI CONNECTOR 1

FECJ

IE43

BRXCBRXC+

20
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

10R

BRX-DDC-SDA
BRX-DDC-SCL

7
100K

BRX-DDC-SCL
BRX-DDC-SDA

47K

FECE
FECF

3 3ECM-3 6

2
3ECN-2

1 3ECA-1 8

FECC
FECD

47K

BRXCPCEC-HDMI

7 3ECA-2 2

BRX-HOTPLUG

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

CEC-HDMI

IEC5

CEC_D

N
R0X0
P

100n

2EC3

10K

49

DSCL4
DSDA4

N
R0XC
P

10u

RES 2ECW
R4PWR5V

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI

51

9EC2

CEC-HDMI

RES

N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
N
R1XC
P

TX2

N
P

TX1

N
P

TX0

N
P

TXC

N
R1X0
P

N
P

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

4K7

55

50

52

IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

PCEC-HDMI

FECY

3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53

10
28

N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P

IEC6
9EC0

38

37

9
27
64
DSDA0
DSCL0

+5V-EDID

N
R3X2
P

3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10p

29
30

(CBUS) HPD0
R0PWR5V

10K
3ECP-3

2ECM

31
32

1u0

IE42

10p
2ECY

10R
ARX-DDC-SDA
ARX-DDC-SCL

8
100K

30R

RES

1
3ECN-1

3ECP-1

SBVCC33

3ECM-4

ARXCARXC+

HDMI CONNECTOR 2

100n

100n
2EC8

100n
2EC7

2EC6
AIN-5V

RES 2ECX

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23

VCC33

ARX-HOTPLUG

MICOM_VCC33

20
22
24

1P03

3 3EC1-3 6

47K
47K

ARX-HOTPLUG

8 3EC1-1 1

AIN-5V

7EC1
SII9187B

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
FEC5

+3V3

+3V3-HDMI

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

RES
5EC3

FEC7

AIN-5V

ARX0ARXC+

FEC1
FEC2

SII9187B = 0xB2

FECB

ARX2ARX1+

48307-0012

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

73

EPAD
IEC7

3ECE

22K

FECP

30R
220u 16V

RES 2EC1

+3V3

HDMI CONNECTOR 3
1P04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23
25
26

B04D

I2C Address
5EC0

FECW
+3V3-STANDBY

6EC1
+5V

+5V-VGA

7EC1

3ECN

3ECF

NON-INSTAPORT

9187B

4X 100K

100K

BLOCKBUSTER

INSTAPORT

9287B

4X 100K

100K

SUNDANCE

BAT54
IE11

3ECG
3ECF

4R7

B04D

FECZ

100K

DDCA-SDA

2ECU

DDCA-SCL

IE65

2 3ECU-2 7

IE66

10K
4 3ECU-4 5

+3V3

10K
1u0
1

SPB SSB TV550


2K11 4DDR EU SD

+5V-EDID

2011-03-07

3104 313 6538


19050_050_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 124

Headphone

Headphone

B04E

+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

A-STBY

FEE0
RESET-AUDIO

7EE0-1
PUMD12
1

2EE0

6
22K

3EE1-3

3EE1-1

22K

3EE1-2

22K

47p
3EE1-4

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

2EE3

IEE2

1u0

ADAC(4)

IEE1
2EE4

3EE0-1
10K

IEE3
2

8
4

3EE0-4
10K

1u0

5
IEE4

5
2EE2

AMPLIFIER

3EE0-3

2EE6

IEE7

3EE2-4

FE36

VO

SHUTDOWN
BYPASS

VIA
GND GND_HS

2EE7

IEE8

3EE2-2

FE35
7

AMP2

33R

4V 100u

10
11

AMP1

33R

3EE2-1

33R

IEE5

10K
22K

A-PLOP

4V 100u

3EE2-3
33R

IN-

1u0

IEE6

VDD

IEE0
ADAC(3)

RES 3EE3

B04E

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_051_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 125

10-5 B05 310431365381


DDR

B7
A8

3B00-2

2p2

7
33R
6 3B00-3
33R
7
33R
5
33R

3B12
33R

3B13
2B44
RES

NU|RDQS

2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
33R
3B02-4
4
8
33R

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

DDR2-DQS2_P
DDR2-DQS2_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

RES
240R

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B24
33R

2B17
100n
2B37
100p
VDD

VDDL

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

E2

A9
C1
C3
C7
C9

E1

DQS

0
1 BA
2

A3
E3
J1
K9

33R

DQ

0
1
2
3
4
5
6
7

C8
C2
3
D7
D3
1
D1
D93B00-4 4
B1
B9 3B00-1 1

VREF

VDDQ

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B05-3
3B04-3
D7
D3
D1
D93B04-4
B1
B93B04-1

3
3

4
1

B7
A8
2B45

0
1 BA
2

NU|RDQS

2 3B04-2 7
33R
6
6 33R
33R
33R 2
7 3B05-2
1
8 3B05-1
33R
5
5 3B05-4
4
33R
33R
8
33R

3B15
RES
2p2

3B14
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

+1V8

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

3B23

SDRAM

B05A

DDR2-VREF-DDR

E7

3B01
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

RES
240R

2B41

2B36
100p
2B08
100n

DDR2-ODT

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

A3
E3
J1
K9

DDR2-BA2

VDDL

A7
B2
B8
D2
D8

G2
G3
G1

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

DDR2-BA0
DDR2-BA1

+1V8
DDR2-VREF-DDR

3B25
33R

DQS

B7
A8
2B46

NU|RDQS

3B17
RES
2p2

3B16
33R

DDR2-DQS0_P
DDR2-DQS0_N

33R

A2

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

VSSQ

L3
L7

DDR2-A14

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

2B35
100n
2B39
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B34

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
3B11-3 3
C2
3B10-3 33R 3
D7
D3
D1
D93B10-4 4
B1
B93B10-1 1

B7
A8
2B47

0
1 BA
2

NU|RDQS

2
6
6 33R
2
1
5 3B11-1
33R
4
8
33R

3B19
RES
2p2

3B10-2

3B20

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

180R 1%

5
33R
7
33R
5
33R
8
33R

2 3B07-2 7
33R
3
6 3B07-3
33R
1
8 3B08-1
33R
3
6 3B08-3
33R

3B21

0
1
2
3
4
5
6
7

C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1

180R 1%

DQ

0
1 BA
2

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

E2

E1

SDRAM

+1V8

FB00
7
33R

7 3B11-2
8 33R
33R
5 3B11-4
33R

3B18
33R

DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15

DDR2-VREF-DDR

DDR2-DQS1_P
DDR2-DQS1_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14
1X20
HOOK1

VSSDL

1X21
HOOK1

1X22
HOOK1

1X23
HOOK1

1X24
HOOK1

VSSQ
A7
B2
B8
D2
D8

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

F9
E8
F8
F2
G8
F7
G7
F3
B3

7B01
EDE1108AGBG-1J-F

VREF

E7

RES
240R

3B06

2B43

2B26
100n
2B38
100p

DDR2-ODT

VDDQ

A3
E3
J1
K9

DDR2-BA2

VDDL

A7
B2
B8
D2
D8

DDR2-BA0
DDR2-BA1

G2
G3
G1

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A3
E3
J1
K9

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F

A9
C1
C3
C7
C9

100n

100n
2B25

100n
2B24

100n
2B23

DDR2-VREF-DDR

100n
2B22

DDR2-CLK_N

100n
2B21

DDR2-CLK_P

100n
2B20

240R

DDR2-CLK_N

100n
2B19

3B28

DDR2-CLK_P

47u
2B18

3B27
240R

DDR2-CLK_P
DDR2-CLK_N

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

2B42

3B22
240R

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F

AT T-POINT

+1V8

DDR2-VREF-DDR

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

100n
2B01

47u
2B00

+1V8

47u
2B09

DDR

2B40

B05A

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_061_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 126

10-6 B06 310431365381


Display interfacing-Vdisp

Display interfacing-Vdisp

B06A

1G03
T 3.0A 32V

5G01

FG0H

1G00

+VDISP-INT
100n

T 3.0A 32V
RES

2G43

+VDISP
30R
RES
5G02

22u
RES

30R
RES
2G44

B06A

RES
3G28
2K2

IG11

RES
6G00
LTST-C190KGKT

For Development use only

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_052_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 127

Video out - LVDS

Video out - LVDS

B06B

47p

47p

47p

47p

47p

2G24

2G25

2G26

2G27

2G78

47p

47p

47p

2G76

2G79

47p
2G75

2G7A

47p
2G77

1n0

1n0

10K

2G9B

10K

RES 3G35

9G0K-4
9G0K-3
9G0K-2
9G0K-1

5
6
7
8

RES

2G9A

10K

RES 3G34

+VDISP

RES 3G33

+3V3

FG2J

2G95

100n

FG30
FG31
FG32
FG33

PX3APX3A+
PX3BPX3B+
PX3CPX3C+
PX3CLKPX3CLK+

47p
47p
47p
47p
FG1C
FG1D
FG1E
FG1F
FG1G
FG1H
FG11
FG1J

PX3DPX3D+
PX3EPX3E+

FG1K
FG1L
FG1M
FG1N

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

FG12
FG13
FG14

PX4CLKPX4CLK+
PX4DPX4D+
PX4EPX4E+

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FG15
FG16
FG17
FG18
FG19
FG1A
FG1B
FG1Q
FG1P

CTRL-DISP
BACKLIGHT-BOOST
3D-LR
3D-VS-DISP
CTRL-DISP
CTRL-DISP
3D-LR-DISP

FG04

RES 3G38
RES 3G37
RES 3G2Z
RES 3G36
RES 3G30
RES 3G31
3G39

100R
100R
100R

FG34
FG2H
FG2G

100R
100R
100R
100R
100R
100R
100R

FG35
FG2R
FG2K
FG2L
FG2M

PX1APX1A+
PX1BPX1B+
PX1CPX1C+

FG2E
FG2F
FG1Y
FG1Z
FG20
FG21

PX1CLKPX1CLK+

FG22
FG23

PX1DPX1D+
PX1EPX1E+

FG24
FG25
FG26
FG27

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

FG28
FG29
FG2A
FG2B
FG2C
FG2D

PX2CLKPX2CLK+

FG1R
FG1S

PX2DPX2D+
PX2EPX2E+

FG1T
FG1U
FG1W
FG1V

2G28
2G29

47p
47p

FG2P
100n

100n

SDA-DISP
SCL-DISP

100n

100n

2G94

FI-RE41S-HF
50
51
48
49
46
47
44
45
42
43

2G91

2G93

2G96
2G99
2G97
2G98

RES 3G32
3G2W
3G2Y

CTRL-DISP

100n

EMC 100n
RES 2G9D

2G92

FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53

4
3
2
1

RES 9G0G

FG2N

+VDISP

EMC 100n
RES 2G9C

TO DISPLAY

EMC 100n
RES 2G9E

1G50
EMC
RES 2G9F

B06B

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1G51

TO DISPLAY

1X05
REF EMC HOLE

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_053_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 128

AmbiLight CPLD

AmbiLight CPLD

B06C

B06C

5GA0

FGA0

+3V3

VINT

DEBUG ONLY

100n

100n
2GA2

2GA1

1u0

2GA0

30R

+3V3

FGA1

+3V3

VIO

10K
RES

3GA4

RES
1G37
5GA1

11
9
24
10

10p
RES

26

15
35

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

3GA1

19
20
21
22
23
27
28

4
3G10-4
2
3G10-2
3G12
3
3G11-3

RES
47R
5
33R
3
7 3G10-3
33R
3G13
10R
1
6 3G10-1
33R

IGA1
CPLED2

TCK
TDI
TDO
TMS

IGA3
GCK2
+3V3
3

+3V3
6

AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

33R
8
33R

RES
7GA1-1
BC847BS(COL)
1

GTS1

+3V3
3
RES
7GA2-2
BC847BS(COL)
4

GTS2

GND
4
17
25

+3V3

RES
7GA1-2
BC847BS(COL)
4

GCK3

AMBI-PROG_B1
AMBI-BLANK_R1

6
33R

10p

29
30
31
32
37
38

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

9GA1 RES

10p
2G19

33R
2
33R

5
6 100R
7 100R
8 100R
100R

IGA2
PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

10p
2G18

1
3G14
33R
7
3G11-2

10p

10p
2G12

10p
2G11

10K

2G10

8
3G11-1

4
3
2
1

CPLED3
5
6
7
8
12
13
14
16
18

10p
2G17

36
34
33

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

3G15

33R

IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

10p
2G16

3GA3

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G15

PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

2
3
39
40
41
42

3GA5-4
3GA5-3
3GA5-2
3GA5-1

SD51022

VCCINT VCCIO
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

10p
2G14

43
44
1

2G13

PXCLK54
GCK2
GCK3

2GA6

100n

2GA5

1u0

2GA3

7GA0
XC9572XL-10VQG44C0100

VIO

RES
RES
RES
RES

GCK3
GTS1
GTS2
GSR

30R

VINT

1
2
3
4
5
6

+3V3

+3V3
6

6 330R 3

RES
3GA6-3

RES
3GA6-4

5 330R 4

RES
3GA6-1

FGA3
+3V3

8
100n

2GA4

SD51022

BACKLIGHT-PWM

9GA0

LTST-C190KGKT

FGA5
FGA2

RES
6GA3

FGA4

LTST-C190KGKT

FGA6

1
2
3
4
5
6

RES
6GA2

100R
100R
100R
100R

LTST-C190KGKT

8
7
6
5

RES
6GA1

1
2
3
4

LTST-C190KGKT

3GA2-1
3GA2-2
3GA2-3
3GA2-4

RES
6GA0

RES
RES
RES
RES

8 330R 1

RES
1G36
1
2
3
4
5
6

RES
3GA6-2

DEBUG ONLY
RES
1G35

RES
7GA2-1
BC847BS(COL)
1

7 330R 2

GSR

BACKLIGHT-PWM_BL-VS

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_054_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 129

SPI buffer

SPI-Buffer

B06D

RESERVED

+3V3

20
3EN1
3EN2
G3
PNX-SPI-CLK

PNX-SPI-SDO

RES
7GE0
74LVC245A
1

PNX-SPI-CSBn

IGE0

19

1
2

17
16
15
14
13
12
11

RES
7GE1
PDTC114EU

RES 3GE0-3 3

6 47R

3
4
5
6
7
8
9

RES
RES
RES
RES
RES

8 47R
1 47R
4 47R
47R
47R

3GE0-1 1
3GE1-1 8
3GE1-4 5
3GE3
3GE4

BL-SPI-CLK
BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

18

10K

100n

RES
3GE2

+3V3

RES
2GE0

B06D

PNX-SPI-CLK

RES 8

9GE0-1

BL-SPI-CLK

PNX-SPI-SDO

RES 6

9GE0-3

BL-SPI-SDO

BL-SPI-SDI

RES

9GE1

RES

9GE2

PNX-SPI-CS-BLn

IGE1

RES 5 9GE0-4

PNX-SPI-SDI

*
** 4

BL-SPI-CSn

Buffer

*
**

Direct

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_055_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 130

10-7 B07 310431365381


DVBS-FE

DVBS-FE

B07A
STV0903BAC

100n

10n

2R15

100n

2R14

10n

2R09

+3V3-DEMOD

GND_HS

130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

VDD1V0

10n

10n

2R52

10n

2R51

100n

2R50

100n

2R49

100n

2R48

2R47

100n

2R46

22u

2R16

VIA

21
38
54
76
80
92
96
106

+3V3-DEMOD

30R

VDD3V3

2
3
100n

2R17

+1V-DVBS

11
12

VDDA2V5

8
7

IM
IP

60
56
RES 2R21

DISECQ-DET
F22-DISECQ-TX

1n0

128
20
126
NC
107
NC
47p
IR04
97
98
3R00 IR03
19
18

RES 2R22
SCL-SSB
SDA-SSB

100R
RES 2R23

3R01
47p
100R

SCLT
SDAT

RESET-DVBS
9R00
RES

3R11
+3V3-DVBS
10K

IR02

62
58
26
23
24
29
27

FR02
FR03
FR04
FR05
FR06

FR07

XTALO

VS
AGCRF1

I2C-ADDRESS : D0
DIRCLK
CLKI
CLKI2
CLKOUT27
N
I1
P

N
Q1
P

0
1
2
3
D
4
5
6
7
CLKOUT
STROUT
DPN
ERROR

0
CS
1
DISEQCIN1
DISEQCOUT1
FSKRX_IN
FSKRX_OUT
NC
SCL
SDA
SCLT
1
SDAT

RESETB
STDBY
TCK
TDI
TDO
TMS
TRST

COMP

0
1

1
2
3
4
5
6
GPIO 7
8
9
10
11
12
13

52

SENSE+1V0-DVBS

63
64
65
67
68
70
71
73
74
75
78
79
82
83
84
86
87
89
90
91
94
95
108
109
111
115
116
119
120

AGC

2R53

1K0

47n

* To be drawn near PNX85500


3R03
3R04
3R05
3R06

47R
47R
47R
47R

NC

NC
NC
NC

TS-DVBS-DATA 4
TS-DVBS-CLOCK
TS-DVBS-SOP 2
TS-DVBS-VALID 1

9R03-4 * 5
9R04 *
9R03-2 * 7
9R03-1 * 8

TS-FE-DATA
TS-FE-CLOCK
TS-FE-SOP
TS-FE-VALID

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

40
41
101
50
49
47
46
44
43
37
35
34
32
30
55

FR00

3R02

16

IR05

3R07
120K

DISECQ-RX

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

100n

2R26

100n

2R25

100n

2R24

100n

100n

2R19

+2V5-DVBS
2R18

VDDA1V0

5
9
13
114
118
123
127

NC

QM
QP

129

IR00

5R00
+3V3-DVBS

NC

59
104
103
100

MAIN

XTALI

6p8

GNDA

NC

124

2R20 RES

10n

100n

2R13

10n

2R12

100n

2R11

10n

2R06

2R05
2R08

100n

2R07

+1V-DVBS

XTAL
1
4
6
10
14
113
117
121
125

1K0

100n

10n

2R10

100n

2R03

10n

2R02

100n

2R01

2R00

100n

2R04

+1V-DVBS

POWER_VIA

3R10

15
17
22
25
28
31
33
36
39
42
45
48
51
53
57
61
66
69
72
77
81
85
88
93
99
102
105
110
112

+1V-DVBS

122

10K

7R01-2
STV0903BAC

3R13

B07A

+3V3RF
3R12

IR06

2R43

2R62
100p

2R45

1n0

2R29

SM15T

FR01

1R00
310430133871

I2C-ADDRESS : C6

QP
QN
RF_OUT

AGC
AS
NC

VIA

RF_IN
GND
RF LNA LT MIX DIG BB VCO
5
3
9 10 15 17 25 26

10u

2R61

1n0

1n0
2R35

SATELLITE
TUNER

2R40

1K0

100p

21
20
7 NC
34
35
36
37
38
39
40
41
42

XTAL

3
3R08-3
2
3R08-2
10p

SCL
SDA

IP
IN

18
19

3R09

2R56

XTAL_CMD

32

4
6 3R08-4
100R
1
7 3R08-1
100R

5
100R

QP
QM

8
100R

IP
IM

SYN HS
29 33

0p56

5R02

27n

2
3
4
5
2R28

2R27

220u 6.3V

23
24

XTAL_OUT

27p

10n

LNB-RF1

16

SYN

1
2
3
4

+3V3RF

IR01

10u

6R00

5R01

10p

2R39

NC

1R01
1826-N96-R11-02
+3V3-DVBS

9R02
RES

28

VCO

10p

AGC

27

10p

12
13

IR08

22

2R55

IR07

SCLT
SDAT

14

2R54

11

XTAL_IN

1 2
10p

10p

NC

16M

2R38

31

LNA LT MIX DIG BB


VSS

2R41

7R02
STV6110AT

3 4
30

10K

10K

3R15 RES

3R14 RES

10p

1n0
2R34

+3V3RF

1n0
2R33

1R10
NX3225GA

2R37
+3V3RF

1n0
2R32

2R31

4R7

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_056_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 131

10-8 B08 310431365381


DVBS supply

DVBS supply
5T00

B08A

IT00

SYNC
A
4

VFB
GND
P HS
9
8

+1V-DVBS

3T00 RES

15

14

11

+3V3-DVBS

1%

IT24

SENSE+1V0-DVBS

4n7
3T21

100n

2T06

4n7
2T36

3K3

12

22K
3T02

VIA

10

47K

1K0 1%
2T10 RES

IT02
13

IT20

3T03

FT06

IT18

2u0

RES 3T01

7T00-2
ST1S10PH

5T01

IT01

SW

VIN

22u

A
INH

RES 1n0

2T03

+2V5-DVBS

22u
2T05

2T04

7T00-1
ST1S10PH

22u

22u

2T02

22u

2T01

2T00

30R

SW

+5V-DVBS

1K0 1%
LD3985M25
7T01
IN

BP

+2V5-DVBS
IT19

COM
2

5T02

INH

30R

100n

2T07

FT07

OUT

1u0

1u0

IT03

2T39

BAS316

2T08

6T02 RES

BAS316

10n

6T00 RES

BAS316

2T09

6T01 RES
+5V-DVBS

7T02
LD1117DT33
FT08

OUT

+3V3-DVBS
16V

IN

2T12

100n

2T11

COM
1

22u

+24V

100u 35V

IT05

5T03

FT00

220n
2T17

2T14

47n

2T16

2T13

220n

IT04

3R3

100u 35V
2T15

3T04

7T04-1
BC847BS(COL)
1

IT09

10K

4u7

RES 2T22

4u7

RES 2T38

10u

1n0

IT11

RES 2T37

10u

2T24

2T23

6T04

SS24

16
17
18
19
20
21
22
23
24
25
26

22R

3T11

33u

100u 25V

+V-LNB

IT17

1n0

IT12

GND_HS

3T29
3T08

5T04

IT32

15

10u

2T35

IT21

10K

GND

13
12
6
8

3T10
3R3

47n

2T26

1n0

2T25
3T06

100K

IT27

IT08
3T07

ILIM2
SEQ
BP

VIA2

6
+3V3

BOOT2
SW2
EN2
FB2

IT26

2T27

9
10
11

BOOT1
SW1
EN1
FB1

IT10

2T20

PVDD2

1K0

1n0

2T21

2
3
5
7

IT07

+24V

10K

PVDD1

14

7T03
TPS54283PWP
IT25

IT06

22R

3T05

22u

6T03

SS24

33u

220u 16V
2T19

2T18

+5V-DVBS

RES
3T31

IT29

3T23

IT13

33K

2T41
RES
2T28

1n0
FT04

4u7

RES
3T24

SENSE+1V0-DVBS

15K

220p

2T40
2T31 RES

RES
2T29

47K
5%
RES

47K

3T16

3T15

IT14

3K3
5%

3T17

7T04-2
BC847BS(COL)
4

2T30 RES

5
IT23

22n

3T14
2K2

BZX384-C
13V

1K0

IT22

6T05
+24V

22n
3T12

3K3

3T13 RES

+V-LNB
3

IT15

3T25

V0-CTRL

330K
3K3

3T28
100K
RES

RES 10n
IT16

RES 10K

100n
RES

3T26
2T43

RES 2T34

IT30

2T42

22n

RES
33K

3T19

3K3
5%

3T18

18K
5%
22u

2T33 RES

22u

22n
3T20

RES 3T09

+5V-DVBS

2T32 RES

B08A

SPB SSB TV550


2K11 4DDR EU SD

FT05

2011-03-07

3104 313 6538


19050_057_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 132

DVBS supply

B08B

DVBS supply

B08B
+12V

+12V

+3V3-DVBS

3T22

220R

22u

RES

5T50

3T50

100R

100n

2T51

2T50

RES

100u 35V

IT50

IT28

220n

2T52

V0-CTRL

IT60
5T52

VUP

NC

BYP

A_GND
34
35
36

6T50

220n

2T53

2K2

IT55
DISECQ-DET

IT64
6T54 RES

RES
7T51
BC817-25W

IT68

BAS316

IT69

IT59
9T52 RES

VIA
VIA

10n

10u

3T58 RES

2T62 RES

2T60

2K2

1R0

IT67

3T59 RES

STPS2L30A

+3V3-DVBS
10K

6T51

1
2
3
7
8
16
17
23
24
25
26
31
32

3T57 RES

2T61

20
7T50-2
LNBH23Q

BAT54 COL

18

VCTRL

470n

VIA

DISECQ-RX

39
40

VIA
37
38

2T59

470n

15
2T58

2T57

470n

RES

100u 35V

IT58

30R
2T56

100u 35V

2T55

+V-LNB

TTX

11

IT66

3T62

150R

27

EXTM

15R

22R

IT57

5T51

DSQOUT

IT54
22

3T54 RES

30

DSQIN

LNB-RF1

3T53

21

RES

14

VOTX

22K

3T27

13

DETIN

3T52

1n0

9T51

VCC_L

VCC
12

IT63

IT65

RS1D

RES

9T50
RES

VORX

28

IT52

220u

RES

IT56

F22-DISECQ-TX
6T53

STPS2L30A

6T52

RS1D

6T55

10K

29

ADDR

GND_HS

DISECQ-DET

10

10K 3T55 RES


2T54 RES
IT61
IT62
10K
3T56 10n

ISEL
LX

P_GND

LNB-RF1

100R

SCL
SDA

IT53

33

3T60 RES
+12V

9
6

3T61

SDA-SSB

100R

IT51

41
42

SCL-SSB

19

7T50-1
LNBH23Q

3T51

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_058_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 133

10-9 B09 310431365381


Connectors comp

Connectors comp

B09A

FC76
FC78
3C70

100R

FC79

AMBI-TEMP-1

cC70
100n

2C70

1u0

2C71

FC81

GND_AL
NC

FC83

+24V

1C86

FC82
AMBI-POWER

100n
RES

2C95

+12V_AL

1C87

100n

FC84

2C94

T 2.0A 63V

2C96

T 2.0A 63V
RES

Option table for Ambilight

27

ITEMS

BLOCKBUSTER

EMMY

SUNDANCE
/ INFINITY

1C86

1C87

3C76

100p

RC

IC73

100R

2C78

IC74

3C77

100p

LED-2

TO
LED PANEL

100R

FC90
FC91
FC92
FC93

2C79
IC75

3C78

100p

100R

2C80

FC94
+5V

100p
FC95

KEYBOARD

28

1
2
3
4
5
6
7
8

FC89

+3V3-STANDBY

LED-1

**

1M19

FC88

100n

FC77

47n RES

2C81

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP

2C77

2C93

6C02

V-AMBI

100p

100R

3C79
10R

100p

FH34SRJ-26S-0.5SH(50)

2C82

100n
RES

RES

FC75

3C75

LIGHT-SENSOR

**

6C05

FC74

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

2C76
FC87

RES
BZX384-C5V6

FC73

AMBI-PWM-CLK_B2

BZX384-C5V6

FC72
V-AMBI

6C03 RES

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

FC71

AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

AV2-STATUS

1M59

FC70

AMBI-SPI-CLK-OUT

+3V3

5C55-1

30R

BZX384-C5V6

FC9C

100K
RES

5C55

3C74

B09A

1
2
3
4
5
6
7
8
9
10
11

GND_AL GND_AL
RES 3C96
+3V3-STANDBY
+T 0R4
1
2
3
4

9C02-1
9C02-2
9C02-3
9C02-4

8
7
6
5
12

FC85
FC63

RES 3C82

FC86

100R
RES 3C83
100R

FAN-CTRL2

FC64

+3V3

RES 3C92

*
*

FC96
FC97

FC98

RES
3C94
RES
3C95

1u0

FC9B

47R

1
2
3
4

TEMPERATURE
SENSOR

FC9A

47R

2041145-4

100R

RES 3C93

SDA-SET

RES
1M71

100p

SDA-BL

100R
RES 3C81 100R

9C00
RES
9C01
RES

SCL-SET

RES 3C80

100p
RES 2C84

TACH02

FC62

20

FH52-18S-0.5SH

RES 2C83

SCL-BL

1u0
2C91

19

RES 3C91

10p

10K

13

**

RES 3C90

100R
TACH01

2C90

**

+T 0R4

10p
RES 2C87

+5V

RES 2C86

FAN-CTRL1

+3V3
FC61

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

FH52-11S-0.5SH

3C97

* HOTEL TV

RES
1M21

1M20

FC9D

3D-LED

10K
FAN-DRV

RES 5C53
+12V

T 1.0A 63V
IC78

**

1u0

30R
RES
1C85

+3V3

RES 2C85

FC99
RES 5C54

RESERVED

30R

Option table for Leading Edge

Items

BlockBuster / Emmy

Sundance / Infinity

1M19

Yes

No

1M20

No

Yes

1M21

No

No
1

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_059_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 134

10-10 B10 310431365381


DVBT2

DVBT2

B10A

+1V2-DVBT2-M

+1V2-DVBT2-C

2FJ4
100n
2FJ3
100n
2FJ2
100n

2FJC
100n
2FJB
100n
2FJA
100n
2FJ9
100n
2FJ8
100n
2FJ7
100n
2FJ6
100n

B10A

+1V2-DVBT2-P
2FJJ

+2V5-DVBT2-A

+3V3-DVBT2-D

100n
+3V3-DVBT2-R

2FJE
100n
2FJF
100n

2FJP
100n

2FJD
100n

2FJL
100n
+2V5-DVBT2-X
2FJK

2FKB

IF-N-DVBT2

3FJM

RES 9FJ4

IFJ5

2FJY
DVBT2-IFN

DVBT2-IFN

IFJ0

47

3FJ0

46
1K0

9FK5

50
49

3FJB
2FJ1

150K
100p

3FJA
3FJ9

100R
330K

53

1M0

3FJN

3FJ2
2FJN

5
7FJ1-2
BC847BPN(COL)

58
57

IFJ4

10K
3FJ8

+3V3-DVBT2-D

45

54

44

11
27
59

52

8
19
40
41
MVDD

R
VDD

TSCLK
TSVALID
TSSYNC
TSERR_GPIO2

XTALI
XTALO

0
1
2
3
TSDATA
4
5
6
7

AINP
AINM

RFAIN

IFAGC
RFAGC_GPIO1

SCL
SDA

TUNERCLK
TUNERDAT

I2C ADDRESS
0xD8, 0xDC

DFJ1
1

GPIO0

10K

3
+3V3-DVBT2-D

IF-AGC

32

IFJ8

RES 3FJ4
4K7

RES 3FJ3

33

TESTMODE

A0

4K7

VIA

DFJ2
REMOVE IN
NEXT LAYOUT

34

9FJ0
37

RESET-SYSTEMn

OSCENBN

RESETN

DFJ4
38

OSCMODE

DFJ3
PLLBPN

IFJA

5
4
3
2
12
13
16
17
22
23
24
25
28
29

RES 9FJ1

3FJG
3FJF-2 2
3FJF-3 3
3FJF-4 4

7
6
5

47R
47R
47R
47R

9FK1
9FK2
9FK3

3FJF-1

47R

9FK4

IFJ9

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP
TS-DVBT2-ERR
TS-FE-DATA

REMOVE IN
NEXT LAYOUT
9FJ2
3FJH
3FJJ

47R
47R

SCL-SSB
SDA-SSB

66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

XVSS
48

PVSS
43

6
10
15
21
26
31
35
55
60

51
5FJ1

FFJ0

+3V3-DVBT2-D

+3V3

GND_HS MVSS
9
18
39
42

VSS

AVSS

65

62

6p8

DFJ0

IFJ3
3FJ7

1
7FJ1-1
BC847BPN(COL)

64
63

1K0

4n7

RF-AGC

DVDD

47p

+5V-TUN-PIN

CVDD

IFJ1

5FJ9
820n

7
14
20
30
36
56
61

12p

AVDD

2FJV

100n

RES 2FJM

7FJ0
CXD2820R

2
4

1FJ0
41M
680n

10p

100n

100R

10n

47p

DVBT2-IFP

100R

10n

IFJ2

2FJW
DVBT2-IFP

5FJ0

3FJK

RES 9FJ3

RES 2FJ5

2FKA

IF-P-DVBT2

12p

2FJH

2FJT
820n

2FJG

100n
5FJ8

5
6
7
8

+1V2-FE
IFJB

5FJ5
+3V3-DVBT2-R

30R

IFJE
+1V2-DVBT2-C

+1V2-FE
2FK4

1u0

2FK1

30R
1u0

220u 16V

5FJ2
10u
2FKG

9FK6-4
9FK6-3
9FK6-2
9FK6-1

RES 2FKF

4
3
2
1

+1V2

1u0

2FK0

30R

RES 5FK2
+5V

7FK1
LD3985M25
5FJ6

+1V2-DVBT2-M
30R
1u0

IFJF

+2V5-DVBT2-A
30R

2FK5

COM

IFJC

+2V5-DVB

1u0

BP

5FJ3
+2V5-DVB

2FK2

INH

FFJ1

1u0

OUT

2FKE

5FJ4

IFJD

5FJ7

IFJG
+1V2-DVBT2-P

+2V5-DVBT2-X
30R

1u0

1u0

2FK6

30R
2FK3

1u0

2FKC

IN

10n

30R

2FKD

+3V3

30R
5FK1

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_060_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 135

10-11 B11 310431365381


FPGA-Backlight dimming

100n

100n
2H10

100n
2H09

100n
2H08

1u0
2H07

RES
2H04

10u

2H03

77
78

BL-DIM12
BL-DIM11
FPGA-SYS-CLK

83
84

BL-DIM9

5H01

FH02

+3V3

BL-DIM8
BL-DIM7

85
86

BL-DIM6
BL-DIM5

88
89

VCCA-O
100n

100n
2H21

100n
2H20

100n
2H19

100n
2H18

100n
2H17

100n
2H16

100n
2H15

100n
2H14

2H13

1u0

1u0

RES
2H12

RES
2H11

30R

90
93

BL-DIM4
BL-DIM3

94

BL-DIM2
BL-DIM1
3H08

98
99

RES
1K0

97
82

56
57

3D-LED
7H01
PDTC144EU
DBG

3 6H01

DBG

59
60

+3V3

470R

LTST-C190KGKT

SP3A-DONE

DBG 3H17

61
62

+3V3
VCCA-O

VCCA-O

3
7

512K
FLASH

3H19
10R

FH04

SP3A-MISO

DBG
1H06

HOLD
VSS

4K7

1K0

IH09

72
73

FH07

100

1H05
DBG 3H15-4
DBG 3H15-3
DBG 3H15-2
DBG 3H15-1
FH13

7H02
M25P05-AVMN6

70
71

54

PROG-B
1
2
3
4
5
6

IH07
IH08

68

FH05

SP3A-DONE

3H11 RES

3H12
IH11

64
65

4
3
2
1

5
6
7
8

FH14

100R
100R
100R
100R

1
2
3
4
5
6

+3V3

FH09
FH10
FH11
FH12

1
2
75
76

IO_L02P_0|GCLK4
IO_L02N_0|GCLK5

24
27

IO_L03P_2|RDWR_B
IO_L03N_2|VS1

BANK2

IO_L04P_2|VS2
IO_L04N_2|VS0

IO_L03P_0|GCLK6
IO_L03N_0|GCLK7

IO_L06P_2
IO_L06N_2|D6

IO_0|GCLK11
IO_L05P_0

IO_L07P_2|D5
IO_L07N_2|D4

IO_L05N_0
IO_L06P_0|VREF_0
IO_L06N_0|PUDC_B

IO_L08P_2|GCLK14
IO_L08N_2|GCLK15

IP_0

IO_L09P_2|GCLK0
IO_L09N_2|GCLK1

IP_0|VREF_0
IO_L10P_2|INIT_B
IO_L10N_2|D3
IO_L01P_1
IO_L01N_1

BANK1

IO_L02P_1|RHCLK0
IO_L02N_1|RHCLK1

IO_L04P_1|IRDY1|RHCLK6
IO_L04N_1|RHCLK7

3H05

29
31

3H06
3H07

SP3A-LED-3

36
37

SP3A-LED-2
SP3A-LED-1

40
41

IH01

43
44

IH02
IH03

48
49

IH04

IP_2|VREF_2

IO_L02P_3
IO_L02N_3

SP3A-CCLK
10R

3H10

SP3A-MOSI

DONE

BL-SPI-CLK-1
BL-SPI-CSn-1

5
6

BL-SPI-SDO-1

AUDIO-SPEAKERn

12
13

IO_L04P_3|LHCLK2
IO_L04N_3|IRDY2|LHCLK3

FH16
3H13

15
16

IO_L05P_3|TRDY2|LHCLK6
IO_L05N_3|LHCLK7

47R

3H14

IO_L06P_3
IO_L06N_3

3D-LR-DISP
SCL-BL
SDA-BL

47R

19
20

3D-LR
3D-VS

BL-DIM

+3V3
IP_3|VREF_3

SD51022
DBG

3
4

9
10

IO_L03P_3|LHCLK0
IO_L03N_3|LHCLK1

TMS
TDI
TDO
TCK

3H09

10R

BANK3

PROG_B

SP3A-MISO

46

IO_L01P_3
IO_L01N_3

IP_1|VREF_1

RES
1K0
RES
1K0
1K0 RES
SP3A-LED-4

39

IO_2|MOSI|CSI_B

SP3A-CSO-B

33
35

52
53

IO_L12P_2|D1
IO_L12N_2|CCLK

IO_L05P_1
IO_L05N_1
IO_L06P_1
IO_L06N_1

10R

50
51

IO_L11P_2|D2
IO_L11N_2|D0|DIN|MISO

IO_L03P_1|RHCLK2
IO_L03N_1|TRDY1|RHCLK3

3H04

28
30

32
34

IO_L05P_2
IO_L05N_2|D7

IO_L04P_0|GCLK8
IO_L04N_0|GCLK9

1K0

23
25

IO_L02P_2|M2
IO_L02N_2|CSO_B

BANK0

1K0
3H02

VCCINT
IO_L01P_2|M1
IO_L01N_2|M0

1K0

VCCAUX

3H03 RES

3H01

45
26

67

17
38
66
81

B11A

VCCINT

21

IP_3
GND

9H10
RES

8
14
18
42
47
58
63
69
74
80
87
91
95

DBG

SP3A-CSO-B

8
6

FH08

VCC

BL-DIM10

100n

FH06

SP3A-CCLK

*
5

2H22

FH03

SP3A-MOSI

100n

2H23

RES
4K7

3H18

IH13

IH05
IH06

IO_L01P_0|VREF_0
IO_L01N_0

VCCA-O

VCCO_3 11

COM

1u0
2H06

VCCINT

VCCO_2

FH01

OUT

1u0
2H05

100n

2H01

IN

1u0
RES 2H02

+3V3

VCCO_0

7H03
LD1117DT12

VCCO_1

7H08
XC3S50A-4VQG100

79
96

VCCA-O

22
55
92

FPGA-Backlight dimming

B11A

BL-DIM
BL-DIM1

BL-DIM

FH17

CH01

BACKLIGHT-PWM_BL-VS

3D-VS

FH18

CH02

3D-VS-DISP

SP3A-LED-4

SP3A-LED-3
+3V3

INP
OUTP
CD

NC GND

PROG-B

SP3A-LED-2
SP3A-LED-1
5 330R 4

7H05
3225

100n

2H24

VALUE

LTST-C190KGKT

DBG 3H16-4
DBG
6H05

6 330R 3

DBG 3H16-3
DBG
6H04

LTST-C190KGKT

7 330R 2
LTST-C190KGKT

DBG 3H16-2
DBG
6H03

8 330R 1
LTST-C190KGKT

DBG 3H16-1
DBG
6H02

10n

IH14

2H25

+3V3

7H06
NCP303LSN28
2

IH12

3H20

FPGA-SYS-CLK

47R
3H21
47R RES

FPGA-SYS-CLK
PXCLK54-FPGA

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_062_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 136

Connectors

Connectors

B11B

B11B
1H59
AMBI-SPI-CLK-OUT

* optionally 1H99 is a 9 pin connector

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

5H55
RES

30R

AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1
V-AMBI

AMBI-PWM-CLK_B2

IH60

AMBI-TEMP-1
+12V_AL_BRG

2H50

GND_AL_BRG

3H50

100R

BL-DIM2

3H51

RES
100R

BL-DIM3

3H52

RES
100R

BL-DIM4

T 2.0A 63V RES

FH84

T 2.0A 63V
RES

GND_AL_BRG

(WIFI)
RES
1H24

2H70

IH61

1u0

2H69
+3V3-STANDBY

1
2
3
4
5
6

+3V3-1

USB-WIFI-DDn
USB-WIFI-DDp

1u0 RES

1H95

FH34SRJ-26S-0.5SH(50)

GND_AL_BRG

2H56

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28

100n
RES

AUDIO-SPEAKERn

10R

502386-0370

27

2H53

3H63

3H64

1H87

+12V_AL_BRG

RES

FH62

100p

502386-0570

STANDBY-1
1M54
FH58

+12VIN
BL-DIM5
BL-DIM6
BL-DIM7
BL-DIM8
BL-DIM9
BL-DIM10
BL-DIM11
BL-DIM12

GND-AUDIO

2H58

RES 100n

+24V

100n
RES

2H57

+24V-AUDIO-POWER

100R

3H57

100R

3H59

100R

3H61

100R

100R
100R
100R

1
2
3
4
5
6
7
8
9

FH50

3H54
3H55

FH51
FH52
3H56
FH53
3H58
FH54
FH55
3H60 FH56
FH57

100R

9H50

BACKLIGHT-BOOST-1

***

1X03
REF EMC HOLE

POWER-OK-1

9H51

1n0

1n0
2H67

2H66

2H65

1n0

1n0

1n0

1n0

1n0
2H63

BACKLIGHT-PWM_BL-VS-1

2H62

BL-DIM1

2H60

3H53
100R RES

***

1n0

LAMP-ON-1

2H61

100n
RES

2H59

2041145-9

1-2041145-4

2H64

FH61

2H51

RES

4K7

1
2
3

FH82

1H86
+24V

+3V3

1W35

GND_AL_BRG
NC

100n

***

2H55

1n0

2H54

1-2041145-3

RES

+12VIN

FH83

100n RES

GND_AL_BRG

2H52

1
2
3
4
5
6
7
8
9
10
11
12
13

V-AMBI

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS

100n RES

GND_AL_BRG

100n

***
1H99

BL-SPI-SDO-1
BL-SPI-CSn-1
BL-SPI-CLK-1
MAINS-OK-1

3D-LR-1

5C55-1
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

1X09
REF EMC HOLE

GND_AL_BRG

SPB SSB TV550


2K11 4DDR EU SD

2011-03-07

3104 313 6538


19050_063_110503.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 137

10-12 310431365381 SSB Layout

CH01

CH02

1H99

1H59

5H55

1H95

2H06

3H10

3H54

2H08

3U65

2C70

7T03

2UE1
3UD3

2UD9
3U26

5UD3

2UE4

2T33

6GA0

3UD5
3UD4

2UD4 2UD5

2UD6 6UD0

IUS9

2UE2

3US9 3US6

2U15

2UE3

7US3

2US3

IUT1

3US3

3US2

IU15

2UD8

6GA1 3GA6

2UU2

3GA5

7GA1

5G01

1G36

2G44

1G03

3GA2

3G15

6G00

1G35
9GA0

2GA4

3GA1

3B11

7GA0

3B26

IGA3
IGA2

5R01

3S3Y

7S02

3S04

3S02 3S01

3S24

3S23

3S29

3S62
3S21
3S3S
3S1K

3S2A

3S3N

3S1B
3S1L

3S3T

3B13

3S3R

3S1J

3B12

2S4D

2S4E
3B23

2B44

3S28

3S03

9S01

3S3Q

7S00

3B02

7B02

3B00

3S1C

2R28

2R29

3R14
3R15

2R45

2R32

2R46

2R33

2R31

5R02

3R08

2R62

2R40

2R38

3R09

2R39

2R54

2R34

1R10
2R37

6T55
7T50

2T55

2T56

6T52

3S42

2F58
3F58

1E71

5T51

5T50

6T51
6T53

IF61

1F75

3FLE

7F70

6E51

3E89

2E67

9FLD

2FL6

2FL7

3F78

IF89

5F70

2F9D

5D05

9FLC

1FL5

2F91
3F72

6F72

9FLH

9FLJ

7FL5

BS13

2S4M

2F92 2F94
2F90 3F71

3S83

2F40

3S84

2FKG

2S87

2S78

7F52

2S7N

3S59

2S77

7F58

2S8G
9S18

3S4R

2S7L

2S7R

2S7P

9S19

2S7U
9S20

3S4T

3S4P

3S4J 2S7J

2S7H

2S7E
9S21

3S4K

2S7K

1P09

2C71

3F59
3F60

2S2Z

3S4L

BS10

1F10

2S41

3S6H

CC70

2S7M

3S13
3S12

5D02 5D01

9F27

3S3W
3E17

2S2Y

2S30

2S33

2S2W
2S2V

2S31

2S34

2S32

3S6J

3S26

2S2T

IS13

9F28

3S3G
3S2M

3S53

2D35

3S3M

3S43
3S44

9S06

3S3H

3S3U

DBS8

1S02
2S2R

7S08

2D06

2G29

5T52

3S54

2S4G

3S00

3B04

2D09
2D10

DS50

3S50

3S27

2D12

3S52

BS15

3S3F

2B45

3B15
3B14

4S14

2D07

2S4F

7B03

7D10

2D36

1R01

2R43

3S6K

IF62
3S81
3S80

3B24

5D04

1P08

3E90
2E68

9FLF

9FLK

9FLG

3FLC

9FL3

9FLL

3FL7
3F65

3FL2

1P07

1F52

2EE5

2F88
9F71

2F9B

5F72

1FD2

6FC7

2F97

6FC5

3FC3

1E01

1P02

1FC3 1FC4 1FC2

3FC5

6FC6
3FC1

2FC6

9FC5

3FC6
2FC1

2FC2

6FC1

6FC8
2FC8

1FC5

1P03

1FC6

9FC4

6FC2

1FC1

1E37

6E01

9FC6

2FC4

2FC7
3FC2

3FC7

1E38

2ECC

2FC3

5EC2

2FC5

3E38

3E08

3E07

9EC3

2E01

2E87

1E00

1P05

6FC3
6FC4

1E09

2E91

2E18

2E90

2E88

2E15

2F60

9FC3

3E37
2E14

1329

2FDC

3FDG

3ECM

3E79

2E76
2E44

2FDD

2ECN
2ECM

3FC4

2ECP

2E80

5E74

6E23

3E75

2E84

3E76

7EC1

2E06

2E10

6E07

3E78

6E26

3E77

2E86

6E22

6E09

3E32

6E28

6E30

BEC5

2EC1

BEC3

2E04

3E31

2E24

6E29

3E44

2E85

3E42

7E09

3EE2

1E18
1E55
1E12
1E54
1E53
1E31

3E9C

5E76

2E73

3ECN IE42

3E74

5E73

2E79

2E83

6FD2

2F81

2EE4

2EE7

6E03

2EE3

6FD3

6E32

1E80

1T01

1FD3
3ECG

2ECU

2E77

1N00

2F9A

2F99
IE09

3ECP

3E43

6E53

6EC1

1F51

3ECF

2E12

3C95

2EE1

2E75

3C94

2C87

IE11

1P04

IEE6
2EE2

3E62

2C90

2C86

2C81

IEE5

7EE1
3EE0

IC74

2EE0

2E05
3E27

1E87

2E62

1E88

6E47

6C05
2C91

IEE4
3EE3

IEE3

5E01

2EE6

3C79

5E02

1E10

2C82

2E60

6C03

2E63

2E56

3E28

3E26

IC75

3E98

3C77

IE10

3F63 3F62

2E27

6E40

2E40

2E71

3EE1

2E57

3C78

2C78

7EE0

3E25 3E22

2C93

2C80

5E08

3C96
3C97

3C76

3E40

2E66

2E07

9C02

3E96

3E72
3C74

6C02
2C77

6E38

3E68

3E35

3C75

2E72

3E34

2E39

IE07

2C76

3E87

2F86
3F75

3E97

3FL4
9FLE

2F93

3F64

1E86

2E54

2G75
2G77

1E39

2E55

6E06

7E10

2G27
2G76

1E43

1E42

1E29

3E33

3F34

2F9C

1E85

3E30

2G9B

1E70

3G38

2G78

IF86

5F73

9F04

2F98

2E52
3E51

2G26

1328 1E06

3E65

3E66

3E67

3E70

3E69

2E48

3E64

2E49

9E42

3G39

2G25

1E08

1E03

2G9A
2E53

2G24

1E25
1E23
1E22
1E19

2G79

3E80

2G7A

9F05 9F06

6E52

1E28

9F00 9F01

2G28

3E71

1G51

3B05

2D23

2D24

2D17

5D07

2D11

1M19
1M211M20

3S3L

2S2S

1D52

2D08

1735 1D38

1D50

2D34

9R02

2R56

9S00

2S09

3S31

7R01

3T22

3R06

2T57
2T50

3R05

2D32
2D20

3R04

3B07

2R20

3B17

2R41

3R03
3B16

2R27

1R00
7R02

3B08

2D05

3B25

2B46

5D08

7B00

2D19

2R55

7F20

9S93

9S91

9S90

2G96

9S92

2S4P

3B10

2G99

3R12

IGA1

2R35

3B19

2G98
2G97

2R61

2B47

7B01

3B18

2F01

3G28

IG11

1G50

1P00

1G37
7GA2

9UU1 9UU0

5G02

1G00
2G43

2U16

5U01

5C53

3U29

2T18

5UD0

2UE6

2C85

3C82

5C54

2U17

6U00

3C93
3C92

1C85

7US2

2U09

IU17

2U11

2C83
2C84

3U24

5T03

IUD4

7UD1
IUD2

IUS6

2T00

2T19

IUD1

IUT2

2U18

IU18

5U00

3C90

IUS5

2T01

6GA2

2UD2

6GA3

2UD1

2T32

2U27

2UD7

3UD2

3UD1

3U06

2U28

3U07

7UD0

3US7

IU23

5UD1

2UE0

3US5

7US1

7U05

5UD2

9US0

3US4

3U23

7U01 7U04 7U02


3C80
3C81

7UU0

1M71

IUS4

2UE9

IUS3

IU57

2UD0

3UD0

5U03

5U02

2U19

2U25

2U23

2U24

2UE7

2U20

2UE8

IUD0

2UD3

7T00

2T22 2T12

2C95

5T00

3G11

3C70

2G13

3U81

7UD3

5T01

1C87
1C86

1UM0

5UM1

3U44

3U56

2U43

2U50

2U52

3U67

2U51

3U84

2U72
3U76

2U48

2U68

1F24 2T14 2T17 5T04

2C94

5C55

3U64

4U00

3U45

2U54

2U49

3U71

2D30

2U47

2U53

3U42

2U45

2U44

3U43

2U46

1M59

1M99

CXXX

3U66

1M95

2C96

IH06

3G13

IH05

3G12

IH09 IH08 IH07


3H09

3G14

3H21

3G10

7H01

3C83

2H53

2H50

9H51

9H50

2H55

3H51

2H54

3H50

3H52

2H56

2H58

2H57

1H06

3H20

2U58

3H15

2H22

7H05

2H11

4U01

3H53

2H66

2H67

3H57

3H55

3H56

2H65

3H59

2H64

2H63

3H60

3H58

2H60

2H62

2H61

2H02

2H19

2H69

IH04

6H01

3H17

2H52

1H05

2U56

IH03

7H08

2H10

IH01

2H59

6H02
IH02

1H86
1H87

2H51

2H24

6H03

3H61

3H16

6H04

2H01

3C91

1H24

6H05

2H16

3H64

7H03

2H15

2H70

1M54

3H08

2H03

3H63

1W35

Overview top side

1E05

SSB Layout Top

2011-04-14

3104 313 6538


19050_001_110414.eps
110414

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 138

FH62

3H03

3H01

2H14

2H04

IH61

3H02

2H07

2H13
FH07

FH61

Overview bottom side

FH01

FH18

2H21

3H14

5H01
2H12

9H10

3H13

3H11

IH60

FH02

3H06
3H05

FH17

FH83
3H07

2H20

FH82

FH57
FH09

7H06

FH11

FH84

FH56

3H18
3H19

FH51

FH50

IH13
2H25

IH14

FH54

FH08

7H02

IH11

FH13

FH12

IH12
2H18
2H09

FH14

FH03
3H12

2G16

2G11

2G10

FC71

2G12

2G14

2UB8
IUB5

3U69

3UB6
IU26

3U13

7F02

FGA4

2UB3

3UB4

IF13

3U05

FU00

IU14
3U02

2U00

CU01

CU02

3UU2

3UU1

7UU2

FUU1

2UU1

FG1P
3E48

FG32

2G94
2G95

3D06

3D02

2D16

2G91

2F71
2F79
IF82

3FG4

2FF5

7FE0

DFE8

7FJ1

2FF4

2E58

FG2H

FC89

5E03

FC87

3E99
FC88

2E59

5E04

3E39

FC93
IC73

FE28

2E08

FE27

IEE7

5FA4

2FF9

2FA3

FG34

2E09

3E95
3E29

FF63
5FA3

3G32
3G35

FC9D

FE34

FE5E

2FA4

5FE8

IF69

2FG1

2FF1

IE63

FG04

FE31

FE29

FE32
3FE9

2FF2

2FE3

3FE8

FF62
FF61

3G2W

2E70

IE39

FE33

FE43

FE54

3G2Y

FG35

IE32

FE5A

FE50

2FF8

3E82
3E81

FE42

2FE4

IF68

2FH4

7FE3

DFF1

FG2F

3G37
FG2G

DFE7

DFF2
IF67

FG2E

FG2L

FG2R

FEC6

FFAF

IEE8

FC90
FE30

FE55

IEE0

FC91
2C79

FEC5

FE61

FC92

2F59

FECZ
FC94

3E21

3EC5

FEA4

FEC2

FE60

FC9A

3EC1

IEE2

2ECY

FECJ

2ECX

3ECJ

3ECL

FECR

2EC7

2EC3
FECY

5EC3

3ECK

FEC7

3EC3

IE45

FEC3

2EC2

IE43

3ECH

2E37

2E38

2E36

6E19

2ECW

2ECQ

FE03

FE02

FE01

2E35

3E20

7FA3
2FA2

FF76

FEE0

FEC1

IE44

FFA2

FC9B

IE12

6E20

9EC2

2EC8

2EC0

2EC6

FFC4
FFC7

FFC2

2ECV

IE51

FE74

3E73

5EC0

3ECU

3ECD

IEC4

FEA3
3ECE

IE18

7EC0 7E02

FE72

3E23
FEA8
FECE

FEC4

IEC5

9EC0

FEA2

IEC7
IEC6

FECM

FE36

FEA6

FECA

FECW

FFC8

FE82

IE65

IE66
FEC0

FFC1
FFC6

FEA7

FEA5

FE35

FECB

FF74

2F61

FG1Z

3G30
3G36

IEE1

FFC9

FG20

FG2K

IF49

2FH3

FG24

FG21

3G2Z

IE06

DFE9

IF18

2FE8

5FE9

FG29

FG22

FG1Y

3G34

IE38

DFE6
IF17

FF03

FFDB

FG28

FG25

FG23

IE26
IE64

2FF0

2FG6

5FE5

2D22

FG26

IE33

IF65
5FE7

2F84 3F76

FG27
FE48

3FG7

2FE6 BFE3

FF81

2FH2

FFDA

ID06

IE50

IF29

BFE2

2FG4

FG2A

3G31

2FH7

2FG7

FG1R

FG2D

ID08

3G33

2FH6

2FG8
FFDC

FG1S

FG2B

FE5D

2FH5

3D14

3FG6

2FE0

5FE3

2FG9

FL33

3FG2

FE5C

3FE6

2FF3

2FE5
2FG3

5FE0

IE49

FG1T

FG1U

FG2C

FG2M

FF82

FF65

3FE7

IF27

1FE0

IF66
2FG2

2FF6

2D26

FE51

3F77
3FE5

FG1Q

FG1H

9G0K

7D03

3D16

CD10
ID31
3E24

ID05

9G0G

2F78
2F74

IF28

2FF7

IFLB

3FJN

3D10
ID07

FEA1

IE92

IF76

2F75

IF64

9FK5

2D21

2G9D

3EB6

IE96

2D27

2EA4

IEC1

FEA0
IEC0

7E01

3EA7

IEC2

5FG0

AF70

FL40

FFB1

IU56

2B36

2B03
2B04

2B02
2B05

2B07
IS07

3S32

2S2J

3S51
2S42

2EA5

7E05

2E74

9E01

3E19

IE91

FG2P

IF74

3F80
3F81

5FG2

FL43

FL41

3FBF

3U11

2B11

2B12

2S29

2B06

2S39

3S72

2S38

2S3A

2S3C

3S39

2S2H

FD02

FE49

IF14

2FH8

IF63

9FC2

FD06

3S0Z

3S38

FE5B

2FG0

3FLG

2F63
2F64

IF48

9FC1

2D14

2D13

ID10

3E53

IF15

AF71

5FE4

FFC5

IU09

3D01
2B16

2B14

3D09

3S20

2S24

C001

2S3E

2B08

2S4R

2S4Q

IS1A
IS1B

2S3F
2S3B

2S3D
2S2G

2D01

5D03

FD14

FG2N

IF78

5F66

2F66

IFLA

IFLE

FF00

FFB4

CU04
CU03
2D31

2B26
3S6P

2S68

2S45
2S3G

2S3H
3S10
3S08

3S37

3S34

3S6L
IS1P

3S36

FD05
ID32

ID09

IS12

IE70

IF12

FF64

FFB3

ID28

2B41

3E45

IE60

2E98

7E06

3EA1

2E99

IE13

3EB1

IE59

2E97

6E43 6E44

3FLF

3FLD

9F03
9F02

IF10

IF11

FL32

FFB2

ID29

2B00

3B03

IF73

7F75

FF01

2FL8
2FL1

FFC3

3U80

2UU0

2UB2

2UB1
FUA3

2B39
2B35

3B20

2B19

2B21

3S6Q

2S60
5S93

2S23

2S52
3S09
2S18

2S2L
2S40

2S19
IS4V

2S8A

3S5B

ID19
FD09

IF81

IF77

2F85

FG1V

3S06
3S07

2S64

2S5P

2S4S

2S17

2S26

2S67
5S88

2S5H

2S5J
5S89

2S28

5S87

2S5A
2S58

5S81
5S90

5S04

2S55

2S4V

2S11

IS3L

2S4Z

2S15

2S50
5S84
3S75
2S16

3S05

2S22

ID37

IE90

IF75

2FL9

3FLA

2FLD

FF75

3FLB

2S56

2S59
2S6K

2S6H

3S40

C000
3S49

3S3P

5E80

2FLA

FF71

FFB6

ID30

ID18

2B01

3S1D

2E81

2EB3

FE56

IE61
3EB3

FE58
IFLC

3FLH

2S53

5S92
2S6M

2S5D

2S5C

2S6A

2S2E

IS05

IE89
3EA2

3F32

3B28

ID27

IE68

2EB1
FE57

FFB5

ID15

FS52

IF90

2FL4

FG1W

7D15

2D29
FD03

IS1D

2F96

IF59

IS0R

FD08

FS57

3E18

FF57

IFLG

FF66

IS03

7S05

3S47
IF80

IF72

3E9E
3E9D

3F79
IF79

IFL3

IE67

IS1J

IS1H

3E06

FF29

2FKD
IFL1

2FL2

IS50

IS06

3S5E

7E11

5F71

IF58

2D28
FD01

FD15

IS1S

FS53

7E13

5F74

2F73 2F80
2F72 2F82
2F77
2F76 AF73

IF50

FF55

9FK6

FL36

IFLD

2S14

3S5V
3S6N

3S5T

IS1E

3S11

3S6M

IF52

FF56

2F95

ID33

ID14
2B09

FS08

IS1M

IS02

7E12
IS11

2E69

9FJ4

2F65
3F82
AF72

5FJ8

2FKB

1FJ0

9FJ3

3FJK

3F52

IFJ2

2FJW

2F49

2FJ5

2FJY

6E48

5F76

2D02

2B40

IS1N

FS03

2FKA

2FJG

3FJ0

5FJ4

5FJ7

5FJ6

2FK3

IFJD

2FK6

2FJH

2FJJ

IS19

FD07

ID11

2S36

IS1Q

3FJM

5FJ9

IFJ0
2FJK

2FJ2

2FJ8

3FJ4
3FJ3
9FJ0
5FJ5

2FK4

7FK1

IFL2

2FK5

IS5C

IS20

3S16 3S17

2F52

3F43

3F41

3F42

IFJE

IFJ1

FFJ1

2FKF

IS3E

2FK2

IFJ5

FF44

9S24

IS2V

FS50

IS0V

5FJ0 2FJT

IFJG
IFJF

IS5G

IS44

DFJ2

DFJ4

IS5J

IF53

IF16

2FKE

2S75

IFJB

IF54

IFJ8

IS4W

IS5H

FS44

2F62
2F70

2FJP

2FJV

FF42

2S76

3S2L

3FJB

2FJ1

3FJA

3FJ9

IFJC

2FJ9
FF41

IS5E
3S5S

2S3J

2FK1

2FJ7 2FJF
2FJL
3FJ7
3FJ8

IFJ3

7FJ0

IS1K

2B17

2B13

2S6G

IS3F
FS49

IFJ4

5FJ3

3F40

2FJA

9FK3

5FJ1

2S3M

IFJA

2FJ6

3S25

2FK0

2FJN

DFJ3

ID12

2B37
2B15

FS02

2S46

IS2Z

3S46

IS42

2S20

2S51

3S2S

5FJ2

3F45

3FJ2

3S0V

2S65

IS3D

2S84

3S19

2B10
2S6D

2S6N

3S76

IS5D

3S1G
3S1H

ID34

3D15

3S22

2S86

9FK4

DFJ0

3FJJ

IS3B

ID35

7D11

3S30

2SHW

FS45

FS10

2B18

2S6E

IS5F

FS11

3B06

3B01

IE05

IFJ9

DFJ1

FFJ0

2FJE

2S5K

2S43

2S4T

2S85

2G9C

2B20

3B22

5S95

2S10

FG31

FS01

3S33

2S4U
DS52

IS4Z

7S09

IS1L

2S21

5S83

2S5G

2S13

IS2U

2S3L

3FJF

9FJ1

2FJC

2FJD

9FJ2

FF48

2FLC

FG30

2B24

2D03

2S4Y

2S2K

FS0Z

9FK1

9FK2

3FJH

2S27

9S0D

3S2H

3S55

7S20

IT51

2S4K

3S1F

3S1P
IF51
FF04

FF43

2FJ4

3S0W

3S64
3S45

2S6C

IS16

2S3Q

FF49

5S80

2S6B

2S4W

FS51

3FJG

2FJ3

2FJB

3F44

FF47

IS3Q

2S5B

3S2K

3S41

9S0E

IT54

2S6L

IS01

9S09

FC95

2FJM

FF46

5S85

IS10
FS64

3S2V

3T62

5S82

3S1T

3S1S

3S1R

3S1U

9R03

2T59

3S82

IS3S

IS04

9R04

IT64

3T53

IT69

IT67

2T37

3T27

6T50

IT57

2T58

3T55

IT61

FF45

2S6F

2R22

7T51

2T60 2T53

IT53

3T60
3T52

IT52

3T58
2T54

IT62

IT59

IT68

3T54

FR01

9T52

IT28

3T50

IT50

IT55

3S69

3F06

2T61

2T52

IT60

2T38

3S6V

3S1X

2R15

2R26

2R25

2R21

3T56
9T50
9T51

6T54

IT58

2T51

3T59
2T62

3S6W

3S1E

2S62

5S94

2S57

2S37

3S1W

IS3K

2S5M

2S6P

2R23

IS25

3S56

IS58

IT63

2S63

IS26

3S57

IR04

2R09

2S25

2S61

3S5Y

2R52

2R17

3S6D

3S2F

2G93

3B27
2B22

3S6F

3S5Z

3S2G
3S6A

IR03

3T57

2FL3

2B42

3S15

3S60
3S6E

IS40

2R51

FG1D

3B21

3S58
3S5W

FG1F

FG1C
2G92

2S66

3R01

IT66

2FLB

2B27
2B29

9S12

FG1G

FG1E

FG33

2S4N

5R00

2R14

3T51

2FL5

2B31

9S08

3S1V

2R07

3T61

IFLF

3B09

2B23

3S67

9S96

9S97

3S65

2B38

IS08
9S11

2R08

IR00

IT65

IFL4

2B33

9S95

FS31

2S89

IF87

FG1L

FG1J

FG11

2B25

3S6C
IS00

IF88

9F25
9F26

9S94

FG1K

2GA1

2S12

3S6B

9C00

FG12

FG1M

2G9F

7S01

9C01

FG14

FG1N

2B28

3GE3

9S10
9S13

3F19

FG16

2B34

3GE4

3R00

5FK1

3U15

2GA3

2GA5

5GA1
2GE0

5GA0
2GA0

3F20

IF22

FG1A

FG18

FG13
FB00

3S61

2R16

IT56

CUA0

9GA1

7GE0

3GA4
2GA6

3GA3

3S68

IS17

3F22

3R13

2R06

2B32

2R13

2R24

FG2J

FG15

2B43

FGA0

3S6G

2R19

FUU0

FG19

2R50

2R18

3UU0

FG1B

IS09

2R12

2R00
IR01

7UU3

FG17

2B30

2R49
FR03

IUU3

IGE1

2GA2

3GE1

9GE2

2F03
3F21

2R10

2R04

3F12

2R11

FR07

3R02

FR00

7UU1

3UU3
IUU4

FGA1

2R01

IR07

IUD5

IUU2

IUU5

3GE0

IGE0

IF23

2F20

2R02
FR02

FUD2

FGA6

3GE2

3S66

9GE1

3F24
3F23
IF21

3R11

2F21

3R10

2R05

2R03

2R47

IC78

2U14

FU03

FG0H

3F07

FR06

FC99

FGA5

2R48

FR04

FC97

2G9E

9GE0

9R00

FR05

2U29

IUU0
FGA3

7GE1

2R53

FC98
3U21
IU19
2U10

IUU1

3F05

IR02

2UB6

2UB5

3F02

IUB1

2UE5

IF07

IR05

IU40

2UB0

7UA5

IUB6

7UA3

3U41

3U16

5UA0

FGA2

IF05

3R07

7U48

3U20
IU01

FUA4

IU44

3F03

IU21

IUB2

3U12

7UA6
2UB7

7U42

6UD1

IU47

3U59
IU43

9U41

IUB3

7U43

7F00

2F00

3F11

3F01

2F02

7F01

3F10

3F04

2U71

7UC0

7UA7

3U74

7U06

IUB4

IF03
IF01

IF06

FC96

3U03
CU05

2U13 2U12

7UD2

7F05

2F06

IF08

3F09

2UB4

3UB2
3UA0

IF04

IU30

FU05

FU06

2U04

IU02

IU64

3U83

3UB1

IUA6

IU07

IU12

IU25

IU41

3U53
FUD3

IU06

2U05

3UB0

2UA4

3U25

IF02

3U17

FU02

IU50

3U61

3UB7

3U75

3U18

7U03

IU10
FU04

3U82

3UB5
IUA5
IUS7

3U68

6R00

3UB3

7UA0

IUB0

FU76

2U02

IU29

3U70

2U08

IU13

IU61

IU52

7UA4

7F03

FUA0

IU45

3U19

2U07
3U09

IU20

IU04

3U14

3U63

FS2Y

FU62

IU08

FC63

9U42

3U10
3U22

2U21

IUS8

7F04

2FD1

3U60

FU55

2U03

IU24

2U01

IU05

FU72
IU11

7U41

FC62

2F04

2F05
3FD6

3FD4

3FD3

9FD1

3FD1
IFD5

3FD7

9FD5

3FD2

3F54
3F66

IFD1

IFD3

6FD1

7FD1

7F54

FF58

IFD2

FU53

IU55

FU08

CU00

IU16

FU07

3F08

FL37

IU48

IU63

FS2W

FU52

FU09
3U01

3U27

3U73

IUD6

IF55

2FKC

IU49

3U62

IU27

FU51

3U00

2U55

FC85

FU67

2U06

FC86

9FD2

9CH0

2F53

3F69
3F53

7F53
3F67

5FK2

FU66

FU75

FU01
IU22

2U22

IUD3
IT06

FU61

FU63

IUD7

IF57

FL42

FU60

3U72

6U40

FU57

FU73

IF56

FF50

IU51

FU68

2U57

FU74
FU56

IU62

IFD4

IF47

FU59

FU78

FU58

IU28

3F68

IR06

FU54

FUS0

IT16

2T11

IR08

FU50

FC61
FC64

7U00

FU49

FU48

FU77
IT05

3U08

3FLJ

2G15

1U40

3T31

3T07

3T14
3T17

FC9C

3U28

3T20

FC70
FC72

IU03

2T31

FUM0

IUM0

FC78

FC79

3U04

2T30

IT14

3T24

2T25

IT15

2T28

9FL1 9FL2

FC76
FC82

7U40

IT13

3T12

2T21

2T23
2T24

3T29

IT17

3T05

FT05

2T40

FL38

IT21

3T08

6T05

3T04

2T13

IT27

IT32

IT07

2T35
3T23

IT29

IT08

FC73

2G19

7T04

3T06

6T03

2T20

2T43

2G18

FT00

2G17

2T26

IT25

3T13
2T34
3T09 3T15
3T19 3T16
3T18

7T01

IT23

FC74

FC75

FC84

FL31

FC77
IT22

IT04

3T25
3T28
3T26
2T42

IT30

FT04

FL30

FL39

FC83

2T15 2T16

IT12

IT26

3T10

IT03

IT11

2T27

6T04
IT10

FH05

FC81

3T11

IT09

2T41

7T02

IT24

FT07

2T29

2T10 2T36

FT08

6T02

3T00 3T21

FT06

3T03

6T00

3T02

2T39
6T01 2T08

2T05

IT18

2T04

3T01
IT02

IT20

2T06

5T02

2T09

IT19

2T07

2T02

IT00

2T03

FH16
FH06

2H17

2H05

IT01

2H23

FH04

FH55
FH52

FH10

3H04

FH53

FH58

FE80
FE71

FE73
FE75

FE81

3ECA
FECF

FECD
FE70

FE85

FE83
FE84

FECK
FECL

FECP

FECC

FECN

FECG

SSB Layout Bottom

2011-04-14

3104 313 6538


19050_002_110414.eps
110503

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 139

10-13 B01 310431365392


Common Interface

B01A

Common Interface

B01A
+3V3

3F01

19
IF01

3F02

CA-MOCLK

100R
CA-MOVAL
CA-MOSTRT

3F03-2 2

3F03-1

3
4
5
6
7
8
9

8
100R

7
100R

IF02

IF03

CA-CD1n
CA-CD2n

3EN1
3EN2
G3

CA-DATAENn

1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn
MOCLK
MOVAL

10

MOSTRT

MDO0
+3V3
2F02

19

MDO1
RES
MDO2

100n

20

7F01
74LVC245A
1

MDO3

3EN1
3EN2
G3

IF05
CA-MDO0

3F04-1 1

8 100R

2
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO0

17
16
15
14
13
12
11

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

10

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3
18

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

CA-WP

100n

20

7F02
74LVC245A

RES

1 3F09-1 8
10K
2 3F09-2 7
10K
3F09-3
3
6
10K
4 3F09-4 5
10K
1

MDO7

8
10K
7
10K
3 3F10-3 6
10K
4 3F10-4 5
10K
3F10-2

3F12
10K
2 3F11-2 7
10K
3 3F11-3 6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K

20

100n

3EN1
3EN2
G3

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

17
16
15
14
13
12
11

1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

18

+3V3
2F05

8-BIT DATA
3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

10

XIO-D00

RES

100n

20

7F04
74LVC245A

+3V3
2F06

CONTROL
7F05
74LVC245A

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

18

1
2

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D11

+3V3

IF08

+5VCA

+3V3

1P00

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY
+5VCA

2F04 RES

XIO-A08

IF04

3F10-1

+3V3

7F03
74LVC245A

+3V3

1 3F08-1 8
10K
2 3F08-2 7
10K
3F08-3
3
6
10K
4 3F08-4 5
10K

MDO5
MDO6

100K

4 3F07-4 5
10K
2 3F07-2 7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

MDO4

CA-RDY

IF07

3F06

CA-RST
RES

100n

20

7F00
74LVC245A
1

0R4

20

22u 16V

RES 2F01

+T

2F00

TRANSPORT STREAM FROM CAM

+5VCA

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n
71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X03
REF EMC HOLE

1X01
REF EMC HOLE

1X10
HOOK1

1X04
EMC HOLE

1X07
REF EMC HOLE

1X08
REF EMC HOLE

1X11
HOOK1

92789-055LF

10

+5V

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_001_110704.eps
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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 140

Flash

Flash

B01B

12

7F20
NAND04GW3B2DN6F

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

0
1
2
3
IO
4
5
6
7

NC

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

100R
3F22-3 3
10K
3F22-1 1
5 100R

16
17
9
8
18
19
7

100R

100R
IF22

3F24

+3V3
2K2
NAND-RDY1n

CLE
ALE
CE
RE
WE
WP
R
B

VSS
13

3F19

10K

IF23

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


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div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 141

USB Hub

B01C

USB Hub

B01C
+3V3

USB-OVR1
3FL2

100K
3FLE-2
100K
3FLE-4
100K
3FLE-3

26
IFLA

7
9F26
9F25

IFL1 17
IFL2 18

9FLC
9FLD

13
14

6
9
10

100K
3FLF
10K

RESET-USBn
USB1-DM
USB1-DP
USB-DM
USB-DP
USB2-DM
USB2-DP
USB-WIFI-DDn
USB-WIFI-DDp

IFL3

9FLK
9FLL

USB2-DM
USB2-DP

53
51
5
6
42
41
54
1
2
44
43
52

3FLG

+3V3

10K
USB-OVR1
3FLH
+3V3
10K

VBUSPOWER
RESET

PWR2
OVR2

DD+

SPI_CS
SPI_SCK
SPI_SD

DD1DD1+
DD2DD2+

VIA

RES

NC

1P08
Y
Y
Y
Y

1F24
N
Y
N
Y

3FLG
N
Y
Y
N

3FL2
N
N
Y
Y

3FL4
N
N
Y
Y

3FL7
N
Y
N
Y

3F32
Y
Y
Y
Y

3F34
N
Y
Y
Y

7FL5
CY7C65621
CY7C65621
CY7C65631

9FLE 9FLC/D 9F25/6 9FL2


Y
N
N
N
N
N
Y
N
Y
N
N
Y
N
N
N
Y

2FLB 1n0

2FLC 1n0

10n

10n
2FL3

2FLA 1n0

10n
2FL5

2FLD

2FL2 100n

100n
2FL1
IFLB

1P08
+5V-USB1

FL36
FL37

USB1-DM
USB1-DP

FL32

3
10K
15K
10K

+T

3F34-4

0R4

FL43

USB2 (BOT)
1P07

+5V-USB1
+5V-USB2

3F34-3

FL40
FL41

USB2-DM
USB2-DP

100K
+3V3
+3V3

3F34-2

FL42

3F34-1

1
2
3
4
5

7
USB-16-PBT-B-30-CU1-BRF

100K
1

58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

IFLF

USB-16-PBT-B-30-CU1-BRF

+5V
4

9FLE

3FLA
3FLB
3FLC

100K

IFLC
IFLD
IFLE

1
2
3
4
5

3F32

31
32
25
48
49

USB1 (TOP)
6

100K

37
38
29
30

100K
3FL4-1

+5V-USB2

100K
+3V3

+5V

RES
RES
RES
RES

1
2
3
4

9FL1-1
9FL1-2
9FL1-3
9FL1-4

8
7
6
5

1
2
3
4

9FL2-1
9FL2-2
9FL2-3
9FL2-4

8
7
6
5

(WIFI)

RES 3FLJ
+T

0R4

RES
1F24
+3V3-1

FL38
FL39
FL30

USB-WIFI-DDn
USB-WIFI-DDp

1
2
3
4
5
6

502386-0570

GND
HS

4
8
12
16
20
24
28
34
40
47
50
56
1P07
N
N
Y
Y

+3V3
PWR1
OVR1

GND

SCENARIO
1x USB
1x USB + WIFI
2x USB
2x USB + WIFI

100n

100n

GREEN2
AMBER2

SELFPWR

9FLH
9FLJ

+3V3

46

XOUT

35
36

100K
3FL4-2

FL33

9FL3

45

GREEN1
AMBER1

10K

10K

100K
3FL4-3

0R4

FL31

3FL4-4

9FL3
N
N
N
Y

57

3FLE-1

9FLF
9FLG

+5V

3FLD

22

VCC
XIN

3FL7

IFLG

21

3
7
11
15
19
23
27
33
39
55

12p

2FL7

7FL5
CY7C65621-56LTXCT
IFL4

+3V3

2FL9

1u0
2FL8

+T
4

24M

12p

2FL6

4
2

1FL5

2FL4

+5V

9FLF/G 9FLH/J 9FLK/L


N
N
N
N
N
Y
Y
N
N
N
Y
Y

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_003_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 142

SD Card

SD-Card

B01D

3F40
+3V3
22u 16V

+T
2F40

B01D

FF45

+3V3-SD

0R4

+3V3

3F41-1

IF47

47K

SDIO-DAT3

3F41-2

SDIO-CMD

SDIO-DAT3

3F44-1

SDIO-CMD

FF47

100R

47K
SDIO-CLK

SDIO-CLK

3 3F41-3 6

3F42-3

3F41-4

FF48

47K

SDIO-DAT0

SDIO-DAT0

SDIO-DAT1

SDIO-DAT1

SDIO-DAT2

SDIO-DAT2

47K

3F44-4

+3V3-SD
5

100R

FF49

3 3F43-3 6

FF41

10K

1P09-1
7

100R

3F45 RES

47K

3F43-2

100R
2

3F44-2

4
7

3F43-4
100R

FF42
FF43

3F42-2

FF46

1P09-2
SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
2

14
16

SCDA7A0200

100R

1 3F42-1 8

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_004_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 143

PNX85500 Control

PNX85500-Control

B01E

+3V3-STANDBY

512K
FLASH

PNX-SPI-SDO
IF52

10K
RES

3F66

10K

IF50
5

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

47K

+3V3

+3V3

3F68 RES

RES 3F67

IF51

3F52

7F52
M25P05-AVMN6

VCC
PNX-SPI-SDI

+3V3

100n
RES

100p

2F52

2F49

+3V3-STANDBY

10K

+3V3-STANDBY

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

2
1

FF04

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

DEBUG ONLY
IF58

2F58 RES

IF59

1
2
3

0
1
2

WC
SCL

SDA

100R
FF62

FF63

ADR

3F63

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

3F58

(8K 8)
EEPROM

RES
1F52

3F62

SDA-SSB

7F58

FF61

SCL-SSB

100n

10K

B01E

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 144

Tuner

Tuner

B01F

B01F

IF10

220R

AF73

15p

2F65 RES
1p0

2F70 RES

3F79-4

820R

AGC CONTROL

VAGC

IF16
330n
3F82 RES

10n

RES 5F76

10n

IF80

2F73

9F03

2F79

2F62

220R

10n
IF78

*
AF72

3F79-1

5F74

2F82

IF76

2F72

9F02

2F75

PNX-IF-N

3F77
IF79

FF01

10n

1K0
2F92

3F72

BA591

4K7

220R
3F81
220R

2F91 RES

2F63

IF13
IF-

10n
IF14

2F64

IF15

15p

10n

IF12

680n
2F66

TUN-IF-P

5F73

3F80
3K3

5F70

TUN-IF-N

IF-N-DVBT2

2F90

470n

IF86

6F72

3F78

9F06

+5V-TUN-PIN
3F71

9F05

47n

2F85

RES 2F95

100p

100p

IF72

5F66

IF-AGC

100n

2F93

OUTPUT2

IF74

2p2
2F77

INPUT2

RES
2F76

OUTPUT1

5F71

IF77

INPUT1

VCC

10n
2F78

2F80

IF81

IF73

GND2

5
4

2F74

PNX-IF-P

O1
O2

GND

4K7
IF-AGC

+5V-TUN-PIN

IF+

10n

ATB2012

* For BR NIM Tuner only

10n

FF81
FF82

IF89

47R
3F75

15p

47R

2F94

TUN-P6
SDA-TUNER

7F70
PDTC114EU

IF-P-DVBT2

* For EU Hybrid Tuner only

TUN-P7

9F71
5F72 RES
+5V-TUN-PIN

+5V-TUN
30R
22u

IF88

IF90

SELECT-SAW
SCL-TUNER

10n

15p
2F86

IF87

RES

3F76

2F88

1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74

IF82

PNX-IF-AGC

RES 2F96

* 9F04

TUN-IF-N
TUN-IF-P

FF75

Component
Europe
Brazil
FA23X7
TH26X3
RES
4u7
5p6
10p
Used
RES
Used
RES
Used
RES
Used
RES
Used
RES
RES
1p0
RES
1p0
12p
15p
12p
15p
18p
22p
560n
680n
680n
820n

I
ISWI

2F9D

RES 2F9C

RES 2F9B

RES 2F9A

RES 2F99

RES 2F98

RES 2F81

RES 2F97
100n
4n7

2F61

2F60
2F59

FF00

2F84

Item No.

IF75

X7251M
36M17

AF71
AF70

FF76
RF-AGC

* Remarks

10n

GND1

6p8

6p8

6p8

6p8

6p8

6p8

1
2
3

TUN-P6
TUN-P7

+5V-TUN-PIN
7F75
UPC3221GV-E1

1F75

2F71

9F01

9F00

IF_OUT2

NC

13

12

IF_OUT1

11

4MHZ_REF

10

B+_TUN

I2C_SCL

TUN

I2C_ADR
5

B+_LNA

RF_AGC

14

FF74
4n7

TUN-P1

RF_IO

16

I2C_SDA

TUNER

15

IF11

6p8

FF71

1T01

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 145

Toshiba Supply

Toshiba supply

B01G

+1V2-BRA-DR1

+3V3

IN

OUT

30R

5FA4

7FA3
LD1117DT12

30R

5FA3

+1V2-BRA-VDDC

FFAF
+1V2-FE
* FOR DVBT-2
10u

2FA4

100n

2FA3

100n

COM
2FA2

B01G

FFA2

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 146

HDMI

HDMI

B01H

HDMI CONNECTOR SIDE


1P05
DRX2+

DIN-5V

DRX2DRX1+
DRX1DRX0+

DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22

DRX-DDC-SCL
DRX-DDC-SDA

47K

DRX0DRXC+

3FBF-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23

B01H

DRX-DDC-SCL
DRX-DDC-SDA

3FBF-2

DIN-5V

47K
DIN-5V

DRX-HOTPLUG

FFB6

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 147

VGA

VGA

B01I

FFC1
CDS4C12GTA
12V

RES 6FC1

1FC1

100p

RES 2FC1

3FC5

CDS4C12GTA
12V

RES 6FC2

1FC2

100p

G-VGA

18R

RES 6FC3

1FC3

100p

RES 2FC3

FFC4

CDS4C12GTA
12V

3FC7
FFC3

9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

1FC4

FFC6
1216-02D-15L-2EC

B-VGA

18R

FFC5

47p

CDS4C12GTA
12V

RES 6FC6

47p

2FC6

10K

RES
3FC2

FFC9

RES 6FC7

47p

2FC7

10K

4K7

3FC4

CDS4C12GTA
12V

RES 6FC5

1FC5

FFC8

CDS4C12GTA
12V

RES
3FC1

47p

2FC5

FFC7

9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

9FC3

VGA-SCL-EDID-HDMI

9FC4
RES

VGA-SCL-EDID

RES 6FC8

1FC6

47p

+5V-VGA
CDS4C12GTA
12V

17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2FC4

VGA
CONNECTOR

3FC6

RES 2FC2

1E05

R-VGA

18R

FFC2

2FC8

B01I

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 148

Temperature sensor & headphone

Temperature sensor & headphone

B01J

+VS
SDA

A1

SCL

1K0

3FD2

9FD2 RES

9FD1 RES

100n

IFD3

IFD5

A2

RES

9FD5

2FD1

1K0
IFD4

IFD1

100R

100R

A0

1K0

3FD4

OS

1K0
3FD7

SCL-SSB

3FD6

SDA-SSB

IFD2

7FD1
LM75BDP

GND

3FD3

LTST-C190KGKT

RES

RES
3FD1

+3V3

6FD1

RES
1329

1
2
3

502382-0370

1328
MSJ-035-69A-B-RF-PBT-BRF

FFDA

AMP1

2
3
1

22n

FFDB
22n
2FDD

CDS4C12GTA
12V
2FDC

RES

6FD3

CDS4C12GTA
12V
1FD3

6FD2
RES

1FD2

1K0

1K0
3FDG-4

3FDG-1

AMP2

B01J

FFDC

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 149

Tuner Brazil

B01K

Tuner Brazil

B01K
5FE0

IF63

IF64

+2V5-BRA

+1V2-BRA-VDDC

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

100n
2FE4

2FE3

1u0

2FE0

30R

AGND
5FE3

IF65

IF66

+3V3-BRA-FLT

5FE4
+3V3-BRA

30R
1u0

100n
2FF6

100n
2FF5

100n
2FF4

100n
2FF3

2FF2

1u0

2FE6

30R

AGND
5FE5

IF67

IF68
+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25
5FE9

+5V
30R

18p

4 2

2FG3

18p

2FG2

25M4

1u0

100n
2FG1

2FG0

30R
1FE0

IN

OUT

INH

BP

FF03

+2V5-BRA

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

10n

100n

IF17
IF18

30
29

BFE2

28
27

BFE3

100n
2FH6

100n

24
25

2FH7

100n

26

AGND

39

AGND

PBVAL
RERR

0
XSEL
1

RLOCK
P
ADI_AI
N

RSEORF
SBYTE

P
ADQ_AI
N

SLOCK
P
AD_VREF
N

SRCK

AD_VREF

SRDT

DTCLK

STSFLG1

DTMB

AGCCNTI

21
58
53
54
55

3FG6-4

33R TS-BR-VALID

9F27-1

TS-FE-VALID

3FG6-3

33R

TS-BR-SOP

9F27-2

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

DFE8

DFE9
5FG0
3FG7
3FG6-2

60

SCL-SSB
SDA-SSB

3FE8

100R
3FE9

IF49
100R

45
46

SLADRS

CKI
SCL
SDA

AGND

PLLVSS

11

SYRSTN
AGCI

TN

0
1

SCL
SDA

TS-BR-CLOCK

33R TS-BR-DATA

9F28
4

9F27-4

30R
5FG2

DFF1
30R

3FE5
18K

10
51

33R

DFF2

IF28
IF-AGC

AGND

42
6
5
12
14

3FG2-1

RESET-SYSTEMn
10K

3FG2-2
10K

3FG4-2
4K7

3FG4-1
4K7

VSS

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

AD_DVSS

10K IF29

STSFLG0

0
TSMD
1

17

3FE7

1
41

AD_AVSS

10K

31

3FE6

AGCCNTR

S_INFO

23

1u0

DFE7

IF27
40

+3V3-BRA-FLT

10n

DFE6

61

38

AGND

1n5

59
52

2FH4

* To be drawn near PNX85500

2FH3

2FH5

1u0

43
FIL

2FH2

VDDS

DR2VDD

16
36
56
63

20

13
35
49
64

10n

2FG4

IF+
IF-

VDDC

2FH8

3
2

34
DR1VDD 48

18

AD_AVDD

19

PLLVDD

7FE0
TC90517FG

AGND

32

AGND

AD_DVDD

AGND

22

COM

AGND

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 150

10-14 B02 310431365392


NANDflash - conditional access

PNX85500: NANDflash - conditional access

B02A

B02A

P21
P22
P23
P24
P25
P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25

CA-DATAENn

K26
3S03

CA-MICLK

N23
10R
L25

CA-MOCLK

N24
3S31
CA-MIVAL
33R

CA-MOSTRT

N25
L22
L23

CA-MOVAL

J21
CA-RDY

L24

CA-RST

L26
J23

RES
9S01

CA-MISTRT

J24
+3V3

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

+3V3

7S00-5
PNX85500

FLASH

ADD_EN
K23
1
K24
VS
2

DATA_DIR
DATA_EN

CD

I
MCLK
O

CA-VS1n
CA-MOCLK

9S00

K21
1
K22
2

CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

3S1U RES

560R
560R

RES

560R
560R

RDY
RST
VCCEN
VPPEN

DATA
ERR
TNR_SER1 MICLK
MIVAL
SOP

T21
T23
T22
R23
R22

TS-FE-DATA

TS-FE-DATA

3S23

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-CLOCK

3S24

TS-FE-VALID

3S28

TS-FE-ERR

470R
470R

TS-FE-SOP

3S29

RES 470R

NAND-ALE
NAND-CLE

D22
ALE
NAND
C21
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

B22
OE_
C22
WE_

XIO-OEn
XIO-WEn

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15
XIO

CLK_BURST
CE1_
CE2_
NAND RDY2
RDY1
WP_

INPACK
XIO-D14
XIO-D15

3S15
10K

+3V3

B21
E21
D21
A20
F21
A21

IS26

INPACK

NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08

10K
RES

7 3S01-2 2
3 33R
33R 5 3S02-4 4
33R
7 3S02-2 2
33R 8 3S02-1 1
6
3 33R
3S02-3
33R 5 3S01-4 4
33R

3S1V

10K

3S01-1 8
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

3S1W

7S00-11
PNX85500

10K

3S1X

+3V3

IS00

100n

7S02
5

33R

3S04
2S09

RES 470R

1
4
2
3

74LVC1G08GW

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 151

SDRAM

SDRAM

B02B

180R 1%

3S07

3S22

DDR2-VREF-CTRL2

2S12

CLK

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
1
VREF
2

N5
N4

DDR2-CLK_N
DDR2-CLK_P

3S30
10R

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K
RES

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

FS01

DDR2-VREF-CTRL3

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

2S24

FS02

100u 2.0V

180R 1%

3S06

3S20

180R 1%

+1V8

IS42
261R

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

1%

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

100p

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100n
2S25

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S17

DDR2-BA2

H1
H2
G1

DDR2-BA0
DDR2-BA1

100p
2S20

7S00-8
PNX85500

180R 1%

B02B

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_013_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 152

Digital video in

Digital video in

B02C

7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
U26
RX1_A
N

P
RX0_A
N

HDMIA-RX0+
HDMIA-RX0-

Y26
SCL
Y25
DDC_A
SDA
V25
P
V26
T24
RX2_A
N
HOT_PLUG_A

HDMIA-RXC+
HDMIA-RXC-

W25
P
W26
RXC_A
N

DDCA-SCL
DDCA-SDA
IS10

IS01

3S0W

W24

RREF

12K
10u

+3V3

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

RES
2S2E

B02C

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_014_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 153

Audio

B02D

Audio

B02D
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R

3 3S12-3 6

3S16-3

IN

100R

BP

INH

IS13

COM

2S2Z

6
10K

4S14

+2V5

4
12

ADAC(1)
IS02

1u0

2 3S36-2 7

10K

2S2Y

10K

8 3S36-1 1
2S2G

AD9
L
AIN4
AC9
R

2S32
1u0
3S10
100R

2S2L
IS1B

1u0

IS19

AF8
L
AIN5
AE8
R

100u 4V

1u0

2S41

4R7
2S42

AD7
AE7
AF7
AD6
AE6
AF6

100n

AE5

3S39

-AUDIO-R

100R

ADAC(4)

3S3H

ADAC(5)

3 3S36-3 6

10K

10K

5 3S36-4 4
2S2H

33R
3S3U

47p

ADAC(6)

+24V-AUDIO-VDD

33R

SPDIF_OUT
SPDIF_IN1

IS07
3

ADAC(5)

7S05-1
LM324 1

AUDIO-OUT-L

2
11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

3S6N

14

7S09-1
74LVC00APW
1

IS1D

&

SPDIF-OPT

47R

3
2
+3V3

+3V3

22K
2S2J

7S09-3
74LVC00APW
9

&
6

14

+3V3-ARC

&

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n
3S25

+3V3

2S3L

10

+3V3-ARC
7S09-4
74LVC00APW
12

14

SEL-HDMI-ARC

IS1E

3S32

10K

47p

+3V3-ARC
7S09-2
74LVC00APW
4

3S34

&
11

+3V3

13
7

SPDIF-OUT-PNX

11

14

10u
2S3G

100n
2S3H

DBS8

7S05-3
LM324 8

11

2S3D

AF5

56R

33R

AE1
1
AF2
2
VREF_AADC
AE3
I2S_OUT_SD 3
AC8
AF3
VCOM_AADC
4

3S3F

10

ADAC(3)

33R

4 3S3G-4 5
IS1S

AD8
IS1A

IS03

ADAC(2)

3S3G-2
2
7

AD4
OSCLK
AD1
SCK
AD2
WS

I2S_OUT
AB9
POS
AB8
VR_AADC
NEG

ADAC(2)

33R

1n0

7
10K

1
2
3
ADAC
4
5
6

68R

3S3G-3

1n0
2S38

3S17-2

ADAC(1)
3

AC6
P
ADACR
AB6
N

AE9
L
AIN3
AF9
R

33R

1n0
2S39

2S33
1u0

IS1Q

3S13-2
22K

8
10K

10u
2S3E

3S17-1

2S3F

AUDIO-IN4-R

IS1P

3S13-1
1 22K

AD10
L
AIN2
AC10
R

1u0

1 3S3G-1 8
IS1N

1u0

1n0
2S3A

22K

AUDIO-IN4-L

3S51

2S30

1n0
2S3B

6
10K

+24V-AUDIO-VDD
2S36

AUDIO
AE10
AC7
L
P
AIN1
ADACL
AF10
AB7
R
N

1u0
3
3S17-3

3S13-3

+AUDIO-L

47p

7S00-2
PNX85500

1n0
2S3C

AUDIO-IN3-R

22K

1u0
2S31

2S3Q

4 3S17-4 5
10K

3S19

AUDIO-IN3-L

IS0R

100n

22K
3S13-4

10K

4 3S12-4 5

3S38
100R

11

9S06
RES

AUDIO-IN2-R

3S16-4 5
10K

7S05-4
LM324 14

13

IS1M

22K
IS0V

220n

2S3J

FS03

2S2S

1u0
3

OUT

10u RES

5
IS12

2S2V

22K

AUDIO-IN2-L

FS08

2S34

7
10K

100R
3S53-4

3S16-2

1u0

2S2T

AUDIO-IN1-R

IS1J

2 3S12-2

3S53-3

100n

22K

2S2W

10u

1u0 RES

100R

1 3S16-1 8
10K

IS1H

3S12-1

7S08
LD3985M25

2S2R

1
AUDIO-IN1-L

+24V-AUDIO-VDD

+3V3

3S53-2

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_015_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 154

MIPS

MIPS

B02E

B02E
+3V3

7S00-3
PNX85500

CONTROL

DS52
BOOST-PWM

+3V3
+3V3
+3V3

3S80
3S81

10K

RES 3S21
+3V3
10K
3S62

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS
GPIO6

IS17

9S09 RES

GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

IS04
PNX-SPI-CS-BLn

+3V3

SELECT-SAW

B26
SDA
A25
SCL

1 3S58 2
100R

B25
SDA
3
A24
SCL

1 3S5Y 2
100R

B24
SDA
A23
4
SCL

1 3S60 2
100R

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS

5K6

3S55

+3V3

FS64

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

10K

3S64

Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

BL_PWM

10K
CLK_54_OUT

3S83
+3V3

RXD1-MIPS

4K7

SDA-SET
SCL-SET

SDA-SET
SCL-SET

3S6C

4K7

3S5Z

SDA-SSB
SCL-SSB

SDA-SSB
SCL-SSB

3S61

SDA-TUNER
SCL-TUNER

SDA-UP-MIPS
SCL-UP-MIPS

1
100R

2 3S5W

1
100R
1
100R

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

3S6E

SDA-TUNER
SCL-TUNER

4K7
3S6B

4K7

3S6D

2K2

3S6F

2K2

2K2

3S6G

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

2K2
3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

1
10K

10K
8 3S6H-1
3
6 3S6H-3
10K
2
10K

FS57

+3V3-STANDBY

+3V3

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5
10K

10K
3S82 RES

BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS

3S6A

2 3S57

RES
1F10

3S69

SDA-UP-MIPS
SCL-UP-MIPS

1
100R

3S27

+3V3

3D-LR

1 3S56 2
100R

10K

10K
3S40 RES

C25
SDA
C26
SCL

RES 3S26

+3V3

3S6J

BOOTMODE

RES 10K

IS05

3S45

10K
+3V3

+3V3
TXD1-MIPS

3S72

10K

+3V3
IS40
PXCLK54

47R

RES

+3V3
2S89
100n

+3V3

3S84

7S01
PCA9540B

VDD

SC0
SC1

SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I 2 C
-BUS
CTRL

SCL-DISP

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-DISP
SCL-BL
SDA-DISP
SDA-BL

3S65

3S66 4K7
2
1
3S67 4K7
2
1
3S68 4K7
2
1
4K7

VSS

FS31

9S10 RES
7S00-4
PNX85500

IS08
SCL-SET

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
RXD ETH
AB4
2
AC1
3

IS50

RXCLK

ETH-RXDV
ETH-RXER

AC2
RXDV
Y4
RXER

SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

W2
W1
W6
W5
W4
W3
U6
V6

TXCLK
0
1
2
3
TXEN
TXER
COL
CRS
MDC
MDIO

TXD
ETH

CC_DAT3
CLK
CMD
0
SDIO
1 DAT
2
SDCD
SDWP

SDA-SET

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

IS09

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13 RES

SDA-BL

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_016_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 155

Video out - LVDS

B02F

Video out - LVDS

B02F

7S00-7
PNX85500
PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

C10
N
CLK
B10
P

PX1CPX1C+

A9
B9

PX1DPX1D+

N
A
P

LVDS

N
B
P

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
D10
P

PX3CLKPX3CLK+

N
P

N
P

CLK
LOUT1 LOUT3
C

N
P

D9
E9

PX3CPX3C+

A11
N
D
B11
P

D11
N
E11
P

PX3DPX3D+

PX1EPX1E+

C12
N
E
B12
P

E12
N
D12
P

PX3EPX3E+

PX2APX2A+

A14
N
A
B14
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B
B15
P

E15
N
D15
P

PX4BPX4B+

PX2CLKPX2CLK+

C17
N
CLK
B17
P

CLK

E17
N
D17
P

PX4CLKPX4CLK+

PX2CPX2C+

A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
D19
P

PX4EPX4E+

PX2DPX2D+
PX2EPX2E+

N
C
P

LOUT2 LOUT4

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_017_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 156

Standby controller

Stand-by controller

B02G
POL

+1V1

B02G

100n

1u0
2S10

2S13

30R

RES
5S04

IS3B

10K

+3V3-STANDBY
3S1H
10K

3S1G

RXD-UP
TXD-UP

10K
3S2A

RXD-UP
TXD-UP
DETECT2

DETECT2

10K
RES
3S1K
10K
RES

RESET-SYSTEMn
3S1J
100K
RES

KEYBOARD
2S4E
100n

3S1L
10K

SPI-PROG

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS
SPI-PROG
PNX-SPI-WPn

AC17

AF26

VDD_XTAL

ALE
PSEN
MC

AA26

SPI

AD23
0
AE26
1
P5
AE25
2
AE24
3

RESET-STBYn

AB24

EA

AB23

ALE

AC26

AC23
SDA
AC24
SCL

AD26
0
AC25
PWM
1

AE21
0
AF21
1
AA22
2
P3
AB22
3
AC22
4
AD22
5

AF22
4
P6
AE22
5

EA

3S2F
100R

100R

100R

3S2K

3S2H
100R

AE23
SDO
AF25
SDI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
P0
AF18
4
AA19
5
AB19
6
AC19
7

ALE

PSEN

3S2G

IS3F

3S44

IS3E

10K

3S43

IS3D

10K 3S42

10K

EA

PSEN
RES

SDA-UP-MIPS
SCL-UP-MIPS

SDA-UP-MIPS
SCL-UP-MIPS

3S6V

RES

LED1

LED1
LED2

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

4K7

3S1P

RES

3S41

10K

LED2

10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

3S6W

4K7

RES
10K
RES 3S3Y
10K

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

10K

3S2L

3S2S
RES
3S3W
4K7

RES
10K
RES
10K
10K

3S46
+3V3-STANDBY

3S47
3S2M
RES
3S49

4K7

+3V3-STANDBY

+3V3-STANDBY

7S20
NCP303LSN28
2

FS45
1

INP

IS2U
5

OUTP
CD

1K0

10K
3S3T

RESET_IN

STANDBY

+3V3-STANDBY

10p

AF17

1 3S2V 2

RES 3S3S

AC20
0
AD20
1
AE20
2
AF20
3
AA21
P2
4
AB21
5
AC21
6
AD21
7

XTAL_OUT

AE17

FS0Z

RESET-STBYn

NC GND
3

10K

LCD-PWR-ONn
EJTAG-DETECTn
SPLASH-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

XTAL_IN

10p
2S4F

3S3P

LCD-PWR-ONn
EJTAG-DETECTn
SPLASH-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

100n

10K

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

7S00-9
PNX85500

2S4K

3S3M

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

2
4

9S0E

3S3L

10K

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

2S4G

RES

+3V3-STANDBY

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

DS50

9S0D

3S1E
10K

10K
3S1D
27K

AD17

RES
10K
RES
3S1F

VDDA_ADC2V5

2S4D
1n0

3S1B
3S1C

VSS_XTAL

+3V3-STANDBY

VDDA_1V1_DCS

AA17

IS20

54M

100n

1S02

9S24

1u0
2S11

RES

2S37

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_018_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 157

Power

B02H

Power

B02H
5S80

IS3Q

2S5A

RES 10u

100n

2S6A

+1V1
30R

5S81

2S5B

RES 10u

100n

2S6B

+2V5
30R

5S82

IS3S

100n

100n
2S68

100n
2S67

100n
2S66

+3V3

VDD_3V3_SBY

2S5D

2S4M

100n

1
10u

2S4P

100n

2S4N

VSSA_USB

VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

100n

2S4Y

10u

2S50

100n

2S4Z

6.3V
10u

100n

+1V2
30R
c000

SENSE+1V2

Y17
D13
T20

POL

Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_USB

30R

R21

R20

100n

2S45

+2V5-AUDIO

5S87
+2V5
1u0

2S56

100n

2S55

30R

5S88
30R

10u

100n
2S57

2S5M

+2V5-LVDS

10u

100n
2S58

100n
2S6K

+2V5
30R

2S6H

5S89

5S90
+2V5
10u

100n
100n

2S53

2S4T

30R

2SHW

5S92

+3V3
1u0

100n
2S59

2
100n
2S6L
1

IS58
2S6M

C13

VDD_1V1_DDR

VSSA_2V5_LVDS_BG

VDDA_2V5_LVDS_BG

AA7

+2V5

30R

5S84

AA9

2S46

VDDA_2V5_DCS

5S95

Y12

RES 1u0
2S4W

+1V1
IS3L

2S52

VDDA_2V5_ADAC

5S83

B13

2S51

VDDA_2V5_AADC

10u

100n

Y19
Y18

AA15
Y15
VDDA_1V2
AA13
VDDA_2V5

2S6P

+3V3-STANDBY

IS3K
VDDA_1V1_LVDS_PLL

+3V3

30R

100n

100n
2S6C

2
100n
2S6N
1

W20
P20
M20
K20
V7
Y8

100n
1 2S6G 2

5S85

10u
2S4U

VDD_1V1

C7
C9
C11
C14
C16
C18

2S4V

VDD_3V3

+2V5-LVDS

N6
N7

2S6F

VDD_2V5_LVDS

U22

VDD_2V5

220u 6.3V

100n
2S6E 2

U20
U21

2S6D

HDMI_VDDA_2V5

+2V5

30R

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

HDMI_AGND

1u0

2S21

100n

2
1

2S5P

VDD

VSSA_1V1_LVDS_PLL

J7

30R

VDD_1V8

A13

2S29

220u 2.5V

5
100n

100n
2S5J-4

7
2

100n
2S5J-2

3
5S94

+1V1

10u
RES

VSS

2S4S

VSS

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

U24
V24

100u

2S23

5
100n

6
3

100n
2S5H-4

100n
2S5H-3

8
100n
2S5H-2
8
100n
2S5J-1

100n
2S5J-3 6

4
3

100n
2S5K-4

6
100n
2S5K-3

7
2

100n
2S5K-2

2S5K-1
1
AA16
AA8
Y11
Y14
Y16
Y9

VSS

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

100n
2S5H-1

100n
2S5G-4

100n
2S5G-3
3

100n
2S5G-2
2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

+1V1

30R

5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

VSSA

RES 10u

c001

SENSE+1V1

7S00-12
PNX85500

100n

2S5C

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

100u
2S60

2S26

+1V8

30R
2

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_019_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 158

Analog video

Analog video

B02I
2S87

AV1-CVBS

2S8A

Y-SVHS

47R

3S5B

22n

56R

Connectivity

3S59

47R

22n

3S05

B02I

2S7J

AV1-R

C-SVHS

2S22

3S4J

56R

22n

22n

EU: SCART1

CVBS-MON-OUT1
22n

560R

3S5E

2S7K

AV1-B

56R

3S4L

AP:

3S08

560R

47p

2S7H

2S40

IS4V

22n

2S7M

YPBPR1-SYNCIN1

10n
2S7L
56R

3S4P

AV3-Y

7S00-1
PNX85500

2S8G

AV2-CVBS

9S18

22n

AB14
AF14
AE14
AC14
AD14
2S7T

YPBPR2-SYNCIN2

10n
2S7R

AV4-Y

YPBPR2

22n
56R

SCART2

3S4V

EU:

AF15
AE15
AC15
AD15

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12

BS13

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75
BS15

10n

2S76

PNX-RF-AGC

47K

56R

3S4W

IS11

3S76

AA14

2S7U

PNX-IF-AGC

10K

BS10

AGND

22n

2S14

AD11
AC11

+CVBS
AV4-PR

2S15
22n

IS5C

2S16
22n

AC12
AF13

22n

CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
PR_R_C1
CVBS2_OUT
PB_B1
RESREF
CVBS_Y2
CURREF
SYNCIN2
Y_G2
1
PR_R_C2
2
PB_B2
3
REF 4
R
5
6
G VGA
B
HSYNC_IN
IF_AGC
IN
RF_AGC
VSYNC
OUT
SCL VGA_EDID
P
TUNER N
SDA

2S18
22n

AB15
AC13
AD13
AE13

22n

22n

56R

3S4T

AV3-PB

AP:

ANALOG_VIDEO

2S7P

2S19

56R

22n

10n

YPBPR1

2S75

YPBPR1

3S4R

AP:

22n

2S7N

AV3-PR

EU:

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S77

PNX-IF-P

10n

2S7E
56R

3S4Y

AV4-PB

22n

2S78

PNX-IF-N

10n

2S84
56R

3S50

R-VGA

22n

2S85
56R

3S52

G-VGA

22n

2S86

100R

2 3S5V-2 7

100R

100R
3 3S5T-3 6

4 3S5V-4 5

V-SYNC-VGA

100R

1 3S5T-1 8

100R

H-SYNC-VGA

2 3S5T-2 7

AP: VGA

22n
4 3S5T-4 5

EU: VGA

3S54

56R

B-VGA

100R
VGA-SCL-EDID

RES

3 3S5V-3 6

RES

1 3S5V-1 8

100R
VGA-SDA-EDID

100R

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_020_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 159

10-15 B03 310431365392


Audio

Audio

B03A

+AVCC
7D03-1
BC847BS(COL)

3D09

+24V-AUDIO-POWER
FD14

+24V-AUDIO-POWER

B03A

1u0

3
3D02-3

7D15-2
BC847BS(COL)
4

4K7

220R

AVCC

47n
ID19
ID18

IN

2D16

ID29

ID30

1u0

BSR
R
OUT
L
BSL

16

ID32

2D22
220n

2D26
RES

8
3D14-1
220n

7
3D14-2
22K
2

220n

ID06

22u

22
21

5D05

5D02

ID10

15

5D01

ID09
ID31

25V 100u
2D36

2D10

2D09

22u

ID05

220R

ID08

25V 100u

5D04

ID07

2D11

220R

RIGHT-SPEAKER

LEFT-SPEAKER

25V 100u
2D35

220n
VCLAMP
BYPASS
MUTE
SD

ID37

AUDIO-MUTE-UP

PVCC

0
GAIN
1

11
7
4
2

1u0

2D17

2D12

CLASS-D
AUDIO AMP

18
17
GND-AUDIO

3D14-3
22K

5
3D14-4
22K
4

22K

2D08

47u 35V
220n

47u 35V
2D32

47u 35V
2D20

7D10-1
TPA3123D2PWP

2D23

ID15

GND-AUDIO

10
12

2D29

GND-AUDIO

1
3

FD03

4K7

+AUDIO-L

7D15-1
BC847BS(COL)
1

19
20

4K7

2D34

3D02-2

3D02-4

47n

ID28

A-PLOP

4K7

1u0
FD08

ID27
47u 35V
2D07

2D24

2D19

ID14

2D28

3D02-1
8
1

FD01

GND-AUDIO

220n

2D05

10u 35V

22K

-AUDIO-R

220R
5D08

5D07

ID12

220n

3D16
ID11

2D06

4R7

25V 100u

PGND
25

GND_HS

EMC

2D21
220n

2D27
RES

8
3D10-1
220n

7
3D10-2
22K
2

GND-AUDIO

DETECT2

GND-AUDIO

26
27
28
29

LEFT-SPEAKER

VIA
VIA

VIA

GND-AUDIO

VIA

37
36
35
34

GND-AUDIO

10n

GND-AUDIO

GND-AUDIO

40
39
38

2D03

7D10-2
TPA3123D2PWP

V_NOM
2D14

GND-AUDIO

3D01-4
47K

100p

GND-AUDIO

3D10-3
22K

GND-AUDIO

+3V3-STANDBY
ID35

7D11-2
BC847BS(COL)
4

4n7

ID34

1D50

3D10-4
22K

RES 2D31

FD15

EMC 4n7

CD10

22K

RES 2D30

MAINS SWITCH DETECT

4K7

47K

3D01-3

7D11-1
BC847BS(COL)
1

3D15

+3V3-STANDBY

6
6

23
24

8
9

AGND

13
14

FD09

A-STBY

VIA
1D38

30
31
32
33

1735

LEFT-SPEAKER
3

100K 6

3D06-2

3D06-4
100K

10n

4
RIGHT-SPEAKER
1

ID33
1D52

GND-AUDIO
4

2041145-3

2041145-4

100K

RIGHT-SPEAKER

1
2
3

100K
3D06-1

FD02

1
2
3
4

2D02

V_NOM

3D06-3 FD07

GND-AUDIO

10n
2D13

GND-AUDIO

2D01

220R
3 7D03-2
BC847BS(COL)

FD05
FD06

5D03

5
2

10u

SPB SSB
TV550 2K11 4DDR EU SD

GND-AUDIO

2011-05-09

3104 313 6539


19051_021_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 160

DC/DC

DC/DC

B03B

B03B

5U03 RES
30R
5U02

FU05

IU22
+12V
1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03
22u

47u

2U16

47R

2U15

7
47R
3U23-1

3U23-2

47R

3u6

5 6
IU23

1n0

2U17

IU09

7U02-2
SI4952DY

3U23-4

47R
3U23-3

220p

+1V8
IU11

IU15

IU08

5 6 7 8

IU12

3U14
IU07

20

VIN

3U28
GND-SIG

18
19

FU04

1u0

2U05

10u

10K

100n

2U14

RES 100u 2.0V

22u

2U13

IU17

IU25

GND

+1V1

IU18
1u0

2U10

GND-SIG

1n0

2U09

GND-SIG

3U21

FU00

SENSE+1V1

IU19

GND-SIG

RES 100p

22K

2U07

3U10

GND-SIG

CU00

FU08

5K6

FU09

IU04

3U19

3U22
1K0 1%
3U09

330R 1%

1K0 1%

3U08
+1V8

100p RES

IU20

100n

RES
2U29

3U17

1% 330R

3U18

1% 1K0

100R 1%

2U08

10K

V5FILT
VREG5

7
17

47u

1
2

2U12

TEST

10R
RES

1
TRIP
2

22
15

3U20

1
2

+1V1

47R

PGND

FU01

2u0
47R
3U24-1

1
VFB
2

5U01

FU06

24
13

3U24-2

1
2

47R

SW

12V/1V1 CONVERSION

1
12

47R
3U24-3

1
VO
2

1 2 3

STPS2L30A

1
2

5 6 78
4
IU14

1n0

GND-SIG

DRVH

23
14

2U11

IU02

12K

1
EN
2

2U06

3U00

3U01

3U03

22K
GND-SIG

21
16

1
2

2U04

1
2

+3V3-STANDBY

5
8
IU01

DRVL

7U04
SI4778DY-GE3
IU16

3U24-4

1n0 RES

2U03
IU03

4
9

+1V1
+1V8

1
VBST
2

220p

6U00

3
10

ENABLE-1V8

3R3

2U01

100n

2
11

IU24

GND-SIG
3U02

3U05

7U03
TPS53126PW

IU13

10R

2U02
100n

7U00
BC847BW

3R3

2U22
IU06

IU05

RES

1 2 3

3R3

10u

2U00

10R

3U04

1n0

3U27

2U18

7U01
SI4778DY-GE3

IU21

CU01
CU02
CU03
CU04
CU05

GND-SIG

GND-SIG

GND-SIG

GND-SIG
GND-SIG

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_022_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 161

DC/DC

DC/DC

B03C

B03C
+3V3-STANDBY

+3V3

RES 10K

+5V +3V3-STANDBY

3U75

3U74

RES 10K

LED-2

IU43

3U69

RES 10K

optionally 1M99 is a 9 pin connector

10K

3U68

9U41

IU44

LED-1

3U41

IU45
9U42
RES

LED2

LED2

10K RES

3U59
10K RES

7U42 RES
BC847BW

IU47
7U43
BC847BW

+3V3

3U70

LED1

LED1

**

3U53
10K

10K

1M99

+3V3
3D-LR

100R

2U71

BL-SPI-SDO

RES
3U67
100R
RES
3U84
100R
RES
3U76
MAINS-OK
RES 100R

BL-SPI-CSn
BL-SPI-CLK

+3V3-STANDBY
4

RES 100p

RES 100p

2U43

RES 100p
2U52

2U51

RES 100p

100p RES
2U72

1n0

2U48

**

2U56

1n0

1-2041145-3

3U66

FU56
FU57
FU74
FU68

BL-SPI-SDO-1
BL-SPI-CSn-1
BL-SPI-CLK-1
MAINS-OK-1

ENABLE-3V3-5V

100K
IU41

100R
+12VIN

7U48-1
BC857BS(COL)

FU07

3U83-4

100K

FU77
FU78

FU54

3D-LR-1

RES 2U57

10K
3U44 RES

FU50

3U83-1

+12V_AL

GND_AL

1K0 RES

3U56 RES

FU49

100n

GND_AL

IU64

3U82

FU48

3U71

GND_AL

1
2
3
4
5
6
7
8
9
10
11
12
13

STANDBY

7U48-2
BC857BS(COL)
5

100R

3U62-4

100K

1n0
RES

100R

FU53

LAMP-ON
3U42 RES
3U43

RES 10K

3U61

3U62-3

10K

10K

5
IU50

3U60-4

10K

7U41-2
BC847BS(COL)
8

22K

4K7

IU62

6
1
7U41-1
BC847BS(COL)
1

10K RES

100R

DETECT2

3
3U80

2U55
3U73

+3V3-STANDBY

ENABLE-1V8

FU72

IU63

3U62-1

3K3

3U45

FU51

3U60-2

IU56

FU73

22K

3U60-1

IU57
1

ENABLE-3V3n

22K

IU52
RES 10K

GND-AUDIO

3U81

3U60-3

3U63

+3V3

1K0

3U72

100p
RES

2U49

+24V-AUDIO-POWER

3U62-2

7U40-1
BC847BPN(COL)

10n

FU66

2U50

T 3.0A 32V

IU49
6

22K

IU51

+12VIN

FU52

BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST

100R

4U01
FU55

**

4U00

IU55

3U64

POWER-OK

**
Items

10n
2U46

2U45

100p
RES
1n0
2U44

100K

3U65

1n0

2U53

1K0

GND_AL
+12VIN

+12V

IU61

1U40

FU76

**

3U83-2

3
2U54

FU67
LAMP-ON-1
BACKLIGHT-PWM_BL-VS-1
BACKLIGHT-BOOST-1
POWER-OK-1
FU62
+24V

1-2041145-4

6
IU40

100K

10n

BZX384-C6V2

+3V3-STANDBY

1u0 RES

STANDBY-1

6U40

FU58
FU59
FU60
FU61
FU63
FU75

IU48

3U83-3

10n

2U58

1
2
3
4
5
6
7
8
9
10
11
12
13
14

3
4

1u0
2U47
1M95

7U40-2
BC847BPN(COL)

10K

2U68

4U00
4U01
1M99
1M95
2U56

Optional table for Ambilight


Emmy
( +24V AL)
yes
yes
no
yes
no

Sundance / Infinity
( +12V AL)
no
no
yes
yes
yes

BlockBuster
(For non-Amblight sets)
no
no
no
yes
no

Dream Catcher
Core Range

2U44

3U43

1M95

0R

open

13 POLE

100p

100R

14 POLE

+12VD

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_023_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 162

DC/DC

B03D

DC/DC

+3V3

B03D

7UC0
LF25ABDT

+12V

IN

OUT

1u0

2UA4

2K2

3UA0

COM

FUA0
+2V5-REF

7UA0
TS2431

FUA4

CUA0

IUB6

+2V5-LVDS

+5V-TUN

3U15-1

IU26

+3V3

+5V

3U16-1

100R

3UB0

1u0

2UB0

7UA3
PHD38N02LT

IUB4

3U16-2

3U16-3

100R
4

FUA3

3U16-4

100R

100R

1u0

2UB2

RES 1u0

2UB1

100R

3U15-4

+1V2

+3V3

100R

3U15-3

22R

100R

3U15-2
100R

IUA5

470R

2
470R
3UB7-3
6
3
3UB7-4470R
5
4

+5V

2UB8

7UA7-2
4
BC847BS(COL)

+1V8

470R

3UB7-2

+2V5-REF

3UB6-2

3U12
7
IUB3
1K0 IUB2
3UB6-3
3
6
6
1K0
3UB6-4
4
5
2
1K0
3UB6-1
IUB5
7UA7-1
1
8
3 1
BC847BS(COL)
1K0
3UB7-1
3U13
8
1
5
2

22u

+12V

330R
1%

7UA6
BC817-25W

330R
1%

+5V5-TUN

+2V5

NOT FOR 5000 SERIES

ENABLE-1V8
5

3UB1

SENSE+1V2

RESERVED
5UA0

1K0

30R
8

RES

+12V

7UA5
LDS3985M50

RES

IU30

3U29-3

RES
5

3U29-4

RES

3U26-1

3U26-2

3U26-3

NC

IN

OUT

INH

BP

+5V-TUN

IUB1

COM

1
3UB3

RES
3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V

470R
+3V3

NC

RES

470R
2

K
REF

470R
1

3UB2

4K7

7UA4
TS431AILT

470R

+5V5-TUN

470R

1u0

RES
7U06-1
BC847BS(COL)
1

2UB7

+3V3

3U29-2

4K7

3
RES
7U06-2
BC847BS(COL)
4

1
3U25-1

100K RES

470R
IU29

1u0

3U29-1

100n
2UB6

2UB5

3U25-2

100K RES

IUA6

3U25-3

100K RES

100K RES

3U25-4

RES

22n
2UB4

470R
4

3U26-4

RES

330p
RES

470R
2

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 163

DC/DC

DC/DC

B03E
5UD0

IUD0

+12V

FUD3

2UD7
4n7
3UD2

33K
1%

22u

100n
IU27

3U06

120K

RES

12

68K
3UD1

1%
3UD0

15

13

VIA

10

7U05-1
BC847BS(COL)
RES 1

10K

IUD6
7UD0-2
ST1S10BPH

RES 2U27

+1V1

220u 16V

SS36

RES 2UE9

+5V
3u6

HS

6UD0

IUD7

2UD6

VFB

GND
A
P

5UD1

22u

INH

IUD3

22u
2UD5

VIN

RES 1n0

2UD3

ENABLE-3V3-5V

SW

2UD4

SW

1
A

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10BPH

+5V5-TUN

30R

14

11

5UD3

FUD2
+3V3

7U05-2
RES
4

3U07

100n
IU28

RES

33K
1%

12

1M0
3UD5

3UD4

VIA

10

15

13

IUD2
7UD1-2
ST1S10BPH

BC847BS(COL)

10K

RES 2U28

2UE4

+1V1

220u 16V

22u

22u
2UE3

3u6

HS

5UD2

2UE2

VFB

GND
A
P

IUD4

1% 100K

INH

4n7
3UD3

SW

VIN

2UE1

ENABLE-3V3-5V

SW

7UD1-1
ST1S10BPH

10u

14

11

7UD2
LD1117DT25
3

IN

S1D

OUT

+2V5
2UE6

100n

2UE5

COM

22u 16V

IUD5

(*) FOR 5000 SERIES ONLY


(**) NOT FOR 5000 SERIES

7UD3
LD1117DT33
IN

OUT

+3V3

100n

COM

22u 16V

2UE8

6UD1
+5V

2UE7

10u

2UD9

10u

30R

IUD1

+12V

2UE0

**

2UD8

B03E

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 164

Temperature sensor & AmbiLight

B03F

Temperature sensor + Ambilight

B03F

5UM1

IUM0

1UM0

+3V3
30R

FUM0

V-AMBI

T 1.0A 63V

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 165

Fan control

Fan control

B03G
+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
6
3

IUT1

100n

2US3

7
7US1-1
LM339P
14

3US7

10K

3US5-2

10K

+12V

10K

3US2

3US4-1

+3V3

IUS6

10K

7US2
BC807-25W

12
+12V

IUS7

11

7US1-2
LM339P
13

IUT2

IUS4 3US5-4
5
4

10

FAN-CTRL2

10K

22R

BC807-25W
7US3

IUS8

12

3US6

IUS9
47R

3US3

+12V

10K

3US5-1

3US9

+3V3

10K

FAN-DRV
+3V3

10K

10K

3US4-3

7US1-3
LM339P
2

+12V

IUS5

3US4-4

+12V

+12V

10K

+12V
3US4-2

RES

12

TACH01

9US0
TACH02

7US1-4
LM339P
1

FUS0

12

B03G

TACHO

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 166

Vdisp switch

Vdisp switch

B03H

FUU0

RES
7UU1
SI3441BDV

+12VD

6
5
2
1

47K RES
2UU1

47R

IUU2

1u0

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

3UU0-3
+3V3-STANDBY

47K

2
3

7UU2-1
PUMD12
1

47K

47K

3UU0-1

3UU0-2

IUU1

IUU4 3UU3-3 IUU5 3UU3-4


6
3
4
5
47K RES

VDISP-SWITCH

FUU1
3UU2

+3V3

47K RES
RES 100n

3UU1

IUU0

2UU0

4
PUMD12
7UU2-2

3UU3-1

+VDISP-INT

22n

7UU0
SI4835DDY
RES

*8
*7
*6
*5
*8
*7
*6
*5

2UU2

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

B03H

+3V3

4K7 RES

LCD-PWR-ONn

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 167

10-16 B04 310431365392


Analogue externals A

B04A

Analogue externals A

B04A

DEBUG

DEBUG

FE70

3000

AP-SCART-OUT-R

IEC0

3EA7-1

IE67

2EA4

AUDIO-OUT-L

8 470R 1
FEA0

7E01-1 6

1n0

2E87

1E00

CDS4C12GTA
12V

RES 6E01

100p

2E01

100R

1u0 16V
AP-SCART-OUT-L

IEC1
2
1
PUMH7

FEA2

AUDIO-IN1-R

RES

FE71

3002

IEC2

IE68

2EA5

AUDIO-OUT-R

5 470R 4
FEA1

7E01-2 3

1n0

2E88

1E31

RES 6E03

100p

2E06

CDS4C12GTA
12V

3EA7-4
1K0

1u0 16V
AP-SCART-OUT-R

5
4
PUMH7
RES
FE72

3001

AP-SCART-OUT-L

3E24

1n0

2E90

1E53

CDS4C12GTA
12V

RES 6E07

100p

2E10

100R
A-PLOP

2K2
RES

DEBUG
3003

AUDIO-IN1-L

4K7

3E17

1R0

5K6

3E06

1K0

3EA1

100n

9E01

3E73
10u

CVBS-MON-OUT1
18p

IE59

330R

BC847BPN(COL)

18K

2u2

5E80
2E98

2E81

2
IE60
1
1 3EB1 2
820R

IE51
AV2-BLK

4p7

IE70

39p

7E06-1

3 BC847BPN(COL)

2E97

2E99

39K

1u0

7E06-2

3E18 2

2EB3

IE61

4K7

IE89

1 3EB3 2

2E18

100p
100p

2EB1

100p

2E15

1E12

+3V3

IE13

3E19

1n0

2E91

3EA2

RES

2E14

150p

FE80

1E18

1u8

18R
RES 6E26

3E77
2E84

150p

5E74

1E55

FE75

RES 6E22

4K7

3E32
3E76 18R

IE90

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FE74

12K

* EU

49045-0011
25
26

3E31

12V

AV1-STATUS

2E83

IE05
+5V

FE73
IE18

FEA5

CDS4C12GTA
12V

150p

2E80

150p

2E79

18R

RES

AV1-G

AV2-STATUS

DEBUG

3E75

BEC3

1u8

CDS4C12GTA

5E73

CDS4C12GTA
12V

FEA4

RES 6E23

AV1-B

1E54

6E09
RES

100p

2E04
3E74 18R

CDS4C12GTA
12V

1K0

FEA3

1E01
FE85

3E78

+5V

18R

RES

IE96

3EB6-1

100n

100p

2E12

1E19

CDS4C12GTA
12V

FE81

18R

150p

2E86

150p

1u8

3E79

2E74

BEC5

5E76

RES 6E28

FEA6
2E85

AV1-R

IE91
8

470R
IE92

7E05
BC847BW

CVBS-OUT-SC1

470R

100n

2E24

4K7

3E44

3EB6-4

3E45
68R

+3V3

RES
3E48
3

68R
3E42

1E22

100p

3EA7-2

3E62

100p

2E44

RES 6E32

27R

1E25

FE84

12V

FEA8

CDS4C12GTA

AV1-CVBS

RES 2E75

RES

6E29

4K7

12V

FE82
CDS4C12GTA

3E43

7000
BC847BW
2

75R

AV1-BLK

FEA7

3EB6-2

2 470R 7

470R

3EA7-3

3 3EB6-3 6

3 470R 6

470R

CVBS-OUT-SC1
100p

RES 2E76

1E23

12V

CDS4C12GTA

RES 6E30

FE83

SPB SSB
TV550 2K11 4DDR EU SD

DEBUG

2011-05-09

3104 313 6539


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110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 168

Analogue externals B

Analogue externals B

B04B

B04B

YPBPR
1E08-3
* GREEN
FE54

3E87

3E89

IE20

1 3E88-1 8
1K0

FE5C

10K

2E41

+3V3

3E90

AV3-PR

18R

CDS4C12GTA
12V

RES 6E52

1E39

100p

2E68

FE44
AUDIO-IN2-L

IE21

3 3E88-3 6
1K0

2E42

FE42

AV3-PB
AUDIO-IN2-R

FE48

2
1

FE5B

18R

3E91

1E08-1
RED
MSP-8033SH-02-NI-FE-RF-PBT-BRF

CDS4C12GTA
12V

RES 6E51

1E28

100p

2E67

YPBPR1-SYNCIN1

RESET-AVPIP

FE51

AV3-Y

100p

1E08-2
BLUE
MSP-8033SH-02-NI-FE-RF-PBT-BRF

FE5A

18R

CDS4C12GTA
12V

RES 6E40

1E43

100p

2E27

100p

MSP-8033SH-02-NI-FE-RF-PBT-BRF

3E92 18R

YPBPR AUDIO
1E03-1
RED
MSP-8032SH-01-NI-FE-RF-PBT-BRF
2

FE43

1E03-2
* WHITE
MSP-8032SH-01-NI-FE-RF-PBT-BRF
4

1u8

BE04

3E93
150p

5E40

2E31

100p

2E72

FE07
150p

AV4-PB

18R

RES

FE5E

AUDIO-IN3-L

FE45

YPBPR2-SYNCIN2
FE46
3E85 18R
FE52
FE47

3E86
18R

1u8
150p

VGA ( OR DVI ) AUDIO

BE05

2E33

2E32

AV4-Y

5E41

IE22
150p

100p

1K0
2E71

CDS4C12GTA
12V

3E96

RES 6E38

1E42

FE41

RES
3E83

AUDIO-IN4-L

14

18R

1K0
5E42

BE06

3E84
18R

1u8
150p

IE23
2E28

AV4-PR

2E29

100p

CDS4C12GTA
12V

FE53

13
12
11
10
9
8
7
6
5
4
3
2
1

IE09

3E21

RES 6E19

V_NOM

1n0
1E37

2E36

FE02

2E35

1E09
MSJ-035-12D-B-AG-PBT-BRF
2
3
1

150p

1n0

AUDIO-IN3-R

1K0

1EP2
FE49

2E40

CDS4C12GTA
12V

RES 6E06

1E29

1n0

2E39

FE5D

3E97
FE50

2E30

FE01

RES
AUDIO-IN4-R

100p

1K0
2E38

CDS4C12GTA
12V

RES 6E20

V_NOM

1n0
1E38

2E37

IE10

3E20

FE03

+3V3

2 3E88-2 7

1E10
3150-831-030-H1
2
VCC

1R0

FE55

SPDIF-OPT

CDS4C12GTA
12V

RES 6E53

V_NOM

100p
1E80

RES 2E77

100n

GND
MT
7 6 5 4

1K0

2E73

VIN

3E9C

1K0
4 3E88-4 5

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 169

Ethernet & Service

Ethernet & service

B04C
IE07

5E08
+3V3

+3V3-ET-ANA

6E43
IE38

IE32

FE57

1E06

2
3
1

UART
SERVICE
CONNECTOR

47R

MSJ-035-69A-B-RF-PBT-BRF
FE58

ETH-TXER

10u

2E48

100n

2E49

12

ETH-TXCLK

10K

3E34

10K

3E72

3E68
RES
3E35
RES

14

+3V3
ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3

9E42

ETH-CRS

RXD1-MIPS

RES
7E11-2
74HC4066
4
1

32

RBIAS

VSS
14

33

+3V3

10K

10K

RES
7E12
PDTC144EU

RES
7E13
PDTC144EU
AV2-BLK

X1
IE39

MDC
MDIO

13

X1

RES

RXD-UP

ETH-RXCLK

10K

RES
3E9E

RES

3E65

RES
7E11-1
74HC4066
1
1

RES
3E9D

+3V3

IE64

10K

14

ETH-RXER

3E64

CRS

ETH-RXDV

IE63

13

REGOFF
1
LED
2
INTSEL

RES
6E48

20

BAS316

ETH-TXP
ETH-TXN

100n

29
28

1
2
3

TXD
RXD

502382-0370

RES
2E69

ETH-RXP
ETH-RXN

26

RXER
RXD4
0
PHYAD
1
RXCLK

0
1
2 TXD
3
4
INT
TXER

17
16

ETH-MDC
ETH-MDIO

P
N

31
30

14

ETH-TXD(3)

TX

RXDV

TXEN

RES
1E71

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

22
23
24
25
18

P
N

12K1
1%

21

RX

TXCLK

COL
CRS_DV
MODE2

+3V3

ETH-TXEN

27

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

15

1K5

FE56

IO

RST

10K

10K
10K

1A 2A
VDD

3E40

19

RES 3E71
RES 3E80

3E51

CLKIN
1
XTAL
2

11
10
9
8
3E70
RES

4n7

100n
2E53

2E52
10p

2E54

10p

10K
3E33

2E55

10K
10K
10K
10K

7E10-1
LAN8710A-EZK

10p

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

ETH-COL

PROVISION FOR HOTEL TV


CR

RES 2E70

47R
3E53-4

+3V3

25M

5
4

3E69
RES
10K

IE06

3E53-1

IE33

1M0
1E70
NX3225GA

RES
RES
RES
RES

3E66
3E67
3E81
3E82

3E30

IE26

+3V3

RESET-ETHERNETn

1
IE50

47R

+3V3

+3V3-ET-ANA

47R
3E53-3

IE49

1E85

RXD1-MIPS

7 3E53-2 2

1E86

TXD1-MIPS

BZX384-C5V1

100n

100n
2E66

10u
2E63

2E62

30R

BZX384-C5V1
6E44

B04C

TXD-UP

RES
7E11-3
74HC4066
8

7E10-2
LAN8710A-EZK
34
35
36

VIA
VIA

14

43
44
45

X1

40
41
42

VIA

TXD1-MIPS

10

RES
7E11-4
74HC4066
11
1

1
X1

12

37
38
39

VIA

CONFIGURATION RESISTOR SETTINGS


+3V3-ET-ANA

+3V3-ET-ANA

ETHERNET CONNECTOR
ETH-TXP

FE27

1E87
3 ACM2012 2

ETH-TXN

FE28

ETH-RXP

FE29

1E88
3 ACM2012 2

ETH-RXN

FE31

1
FE30
FE61

22n

9
10
2E60

5
4

CDA5C16GTH
16V

6E47-4

CDA5C16GTH
16V
RES

6
6E47-3
3

7
2

CDA5C16GTH
16V
RES

6E47-2

8
RES

6E47-1

RES 27n

CDA5C16GTH
16V
RES

FE34

1
2
3
4
5
6
7
8
11
12

5450-323-183-H3

RES 15p

3E64 (RES)

PHYADD(0) = 1

PHYADD(0) = 0

3E65 (RES)

PHYADD(1) = 1

PHYADD(1) = 0

3E66 (RES)

PHYADD(2) = 1

PHYADD(2) = 0

3E67 (RES)

RMII mode selected

MII mode selected

3E68 (RES)

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69 (RES)

MODE(0) = 0

MODE(0) = 1

3E70 (RES)

MODE(1) = 0

MODE(1) = 1

3E71 (RES)

MODE(2) = 0

MODE(2) = 1

3E72
15p

2E59

0 ohm

RES

RES

5E04
2E09
15p
3E39

2E58
RES

5E03

RES 27n

2E08

RES 15p
0 ohm

RES

15p

3E29

RES

2E57

5E02

RES 27n

2E07

RES 15p
0 ohm

RES

15p

3E28

RES 2E56

5E01

RES 27n

2E05

RES 15p
0 ohm

3E27

EMPTY

1N00
FE60

RES

POP

22R

22R
3E98

3E26

49R9
1%

3E99

3E95

49R9
1%

3E25

49R9
1%

3E22

49R9
1%

Resistor

FE32

INTERRUPT FUNCTION

INTERRUPT FUNCTION

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

ETH-INTSEL
ETH-REGOFF
2

FE33

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_031_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 170

HDMI

HDMI

B04D

ARX1ARX0+

AIN-5V

69
70

ARX2ARX2+

71
72

BIN-5V

47K

7 3ECA-2 2

BIN-5V

3 3ECM-3 6

2
3ECN-2

10R

BRX-DDC-SDA
BRX-DDC-SCL

7
100K
1u0

47K

1 3ECA-1 8

HDMI CONNECTOR 1

CIN-5V

2 3ECM-2 7

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

1u0

CRX-HOTPLUG
3E23
RES
7E02
BC847BW

PCEC-HDMI

100R

+3V3-STANDBY

1 3ECM-1 8

4
3ECN-4

10R

BRX1BRX1+

5
6

BRX2BRX2+

7
8

IE44

41
42
39
40

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

DRX-DDC-SDA
DRX-DDC-SCL

5
100K

1u0

5EC2

ARC-eHDMI+
2ECC

IE45

2ECQ

30R
CIN-5V

IEC4

DIN-5V

eHDMI+

22K
RES

7EC0
BC847BW

3ECD

5 3ECA-4 4

47K

CIN-5V

20
22

3
4

DRX-HOTPLUG

47K

FECM
FECN

CRX-DDC-SCL
CRX-DDC-SDA

10p

FECK
FECL

3 3ECA-3 6

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

FECA

BRX0BRX0+

2ECP

CIN-5V

CRX0CRXC+

1
2

6
100K

CRX2CRX1+
CRX1CRX0+

BRXCBRXC+

CRX-HOTPLUG

1P02
CRX2+

33
34

2ECN

BRX-DDC-SCL
BRX-DDC-SDA

20
22

IE43

35
36

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

10K

1u0

2EC2

9EC0

CEC-HDMI

CEC_D

N
R0X0
P

100n

2EC3

49

DSCL4
DSDA4

N
R0XC
P

10u

RES 2ECW

10K

R4PWR5V

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI
9EC2

51

CEC-HDMI

RES

N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
N
R1XC
P
N
R1X0
P

TX2

N
P

TX1

N
P

TX0

N
P

TXC

N
P

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

55

50

52

4K7
IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

PCEC-HDMI

FECY

3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53

10
28

N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P

IEC6
IEC5

38

37

DSDA0
DSCL0

+5V-EDID

N
R3X2
P

3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10p

29
30

(CBUS) HPD0
R0PWR5V

10K
3ECP-3

2ECM

31
32

1u0

ARX-DDC-SDA
ARX-DDC-SCL

IE42

10p
2ECY

10R

8
100K

ARX1ARX1+

BRX-HOTPLUG

FECJ

+3V3

30R

RES

1
3ECN-1

RES 2ECX

BRX2BRX1+

BRXCPCEC-HDMI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

5EC3 RES

3ECP-1

3ECM-4

SBVCC33

AIN-5V

BRX2+

BRX0BRXC+

100n

100n
2EC8

VCC33

ARX-HOTPLUG

BRX-HOTPLUG

BIN-5V

10u

2ECV

2EC0
100n
2EC7

2EC6

3EC7

2K2

7EC1
SII9287B

67
68

BRX1BRX0+

FECE
FECF

3ECH

SII9187B = 0xB2

FECB

ARX0ARX0+

BRX-DDC-SCL
BRX-DDC-SDA

MICOM-VCC33

FEC7

AIN-5V

HDMI CONNECTOR 2

FECC
FECD

FEC3

GND

65
66

BIN-5V

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

73

EPAD

3ECE

22K

IEC7
FECW
+3V3-STANDBY

6EC1
+5V-VGA

+5V

7EC1

3ECN

3ECF

NON-INSTAPORT

9187B

4X 100K

100K

BLOCKBUSTER

INSTAPORT

9287B

4X 100K

100K

SUNDANCE

BAT54 COL
IE11

3ECG
3ECF

4R7

FECP

220u 16V

1u0

2EC4

FEC0

ARXCARXC+

48307-0012

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23

VOUT

30R

MICOM_VCC33

20
22
24

1P03

EN
EN

+3V3

9
27
64

47K
47K

ARX-HOTPLUG

8 3EC1-1 1

FEC5

5EC0
3

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
AIN-5V

3 3EC1-3 6

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

FECT

FLG

+3V3-HDMI

ARX0ARXC+

FEC1
FEC2

6EC2

3EC6

ARX2ARX1+

BZX384-C 2.4V

RES

ARX2+

3K3

1P04

VIN

RES 2EC1

HDMI CONNECTOR 3

100n

7EC2
RT9715EGB
FECS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23
25
26

I2C Address

+5V

30R

+3V3

5EC4

B04D

FECZ

100K

DDCA-SDA

2ECU

DDCA-SCL

IE65

2 3ECU-2 7

IE66

10K
4 3ECU-4 5

+3V3

10K
1u0

SPB SSB
TV550 2K11 4DDR EU SD

+5V-EDID

2011-05-09

3104 313 6539


19051_032_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 171

Headphone

Headphone

B04E

+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

A-STBY

FEE0
RESET-AUDIO

7EE0-1
PUMD12
1

2EE0

5
3EE1-3

3EE1-1

22K

3EE1-2

22K

22K

47p
3EE1-4

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

IEE2
ADAC(4)

2EE3
1u0

IEE1
2EE4

3EE0-1
10K

IEE3
8

2
4

3EE0-4

10K

1u0

6
IEE4

5
2EE2

AMPLIFIER

3EE0-3

2EE6

IEE7

3EE2-4

FE36
5

VO

SHUTDOWN
BYPASS

VIA
GND GND_HS

2EE7

IEE8

3EE2-2

FE35
7

AMP2

33R

4V 100u

10
11

AMP1

33R

3EE2-1

33R

IEE5

10K
22K

A-PLOP

4V 100u

3EE2-3
33R

IN-

1u0

IEE6

VDD

IEE0
ADAC(3)

RES 3EE3

B04E

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_033_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 172

10-17 B05 310431365392


DDR

DDR2-CLK_P
DDR2-CLK_N

3B28

DDR2-CLK_P

240R

DDR2-CLK_N

DDR2-BA2

DDR2-ODT
RES
240R

3B01
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B23

C8
C2
3
D7
D3
1
D1
D93B00-4 4
B1
B9 3B00-1 1

NU|RDQS

2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
33R
3B02-4
4
8
33R

B7
A8

3B00-2

2p2

7
33R
6 3B00-3
33R
7
33R
5
33R

3B12
33R

3B13
2B44
RES

0
1 BA
2

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

DDR2-DQS2_P
DDR2-DQS2_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

F9
E8
F8
F2
G8
F7
G7
F3
B3

RES
240R

3B24
33R

2B17
100n
2B37
100p
VDD

VDDL

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

E2

A9
C1
C3
C7
C9

E1

DQS

A3
E3
J1
K9

33R

2B41

2B36
100p
2B08
100n
G2
G3
G1

DDR2-BA0
DDR2-BA1

DQ

0
1
2
3
4
5
6
7

VREF

VDDQ

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B05-3
3B04-3
D7
D3
D1
D93B04-4
B1
B93B04-1

3
3

4
1

B7
A8
2B45

0
1 BA
2

NU|RDQS

2 3B04-2 7
6
33R
6 33R
33R 2
33R
7 3B05-2
1
8 3B05-1
33R
5
5 3B05-4
4
33R
33R
8
33R

3B15
RES
2p2

3B14
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

+1V8

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

3B27
240R

SDRAM

B05A

DDR2-VREF-DDR

E7

DDR2-CLK_N

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

A3
E3
J1
K9

DDR2-CLK_P

240R

VDDL

A7
B2
B8
D2
D8

3B22

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

AT T-POINT

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

+1V8

DDR2-VREF-DDR

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

100n
2B01

47u
2B00

+1V8

47u
2B09

DDR

2B40

B05A

+1V8
DDR2-VREF-DDR

3B25
33R

DQ

0
1
2
3
4
5
6
7

DQS

C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1

B7
A8
2B46

0
1 BA
2

NU|RDQS

5
33R
7
33R
5
33R
8
33R

3B17
RES
2p2

2 3B07-2 7
33R
3
6 3B07-3
33R
1
8 3B08-1
33R
3
6 3B08-3
33R

3B16
33R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

DDR2-DQS0_P
DDR2-DQS0_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

2B35
100n
2B39
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B34

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

2B43

2B26
100n
2B38
100p
E2

E1

SDRAM

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B11-3 3
3B10-3 33R 3
D7
D3
D1
D93B10-4 4
B1
B93B10-1 1

B7
A8
2B47

0
1 BA
2

NU|RDQS

2
6
6 33R
2
1
5 3B11-1
33R
4
8
33R

3B19
RES
2p2

3B10-2

7
33R

DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15

7 3B11-2
8 33R
33R
5 3B11-4
33R

3B18
33R

DDR2-DQS1_P
DDR2-DQS1_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ
A7
B2
B8
D2
D8

3B21

180R 1%

DDR2-VREF-DDR

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

F9
E8
F8
F2
G8
F7
G7
F3
B3

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

3B20

180R 1%

FB00

RES
240R

3B06

7B01
EDE1108AGBG-1J-F

VREF

A3
E3
J1
K9

DDR2-BA2

DDR2-ODT

VDDQ

A7
B2
B8
D2
D8

G2
G3
G1

DDR2-BA0
DDR2-BA1

VDDL

E7

+1V8

VDD

A3
E3
J1
K9

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A9
C1
C3
C7
C9

100n

100n
2B25

100n
2B24

100n
2B23

100n
2B22

100n
2B21

100n
2B20

100n
2B19

47u
2B18

2B42

DDR2-VREF-DDR

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_034_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 173

10-18 B06 310431365392


Display interfacing-Vdisp

Display interfacing Vdisp

B06A

1G03
T 2.0A 63V

5G01

FG0H

1G00

+VDISP-INT
100n

22u
RES

30R
RES

T 2.0A 63V
RES

RES 2G43

+VDISP
30R
RES
5G02

2G44

B06A

RES
3G28 DBG
2K2

IG11

6G00

RES
DBG

LTST-C190KGKT

For Development use only

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_035_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 174

Video out - LVDS

Video out - LVDS

B06B
47p

10p

10p

1n0

47p

10n

47p

47p

10n

10n

2G75

2G76

2G78

RES 2G79

2G7A

RES 2G24

2G25

2G26

2G27

10K
RES 3G35

RES 2G77

10K
RES 3G34

+VDISP

10K

+3V3

RES 3G33

B06B

RES

9G01 RES

FG30
FG31
FG32
FG33

2G96
2G99
2G97
2G98
PX3APX3A+
PX3BPX3B+
PX3CPX3C+
PX3CLKPX3CLK+

47p
47p
47p
47p
FG1C
FG1D
FG1E
FG1F
FG1G
FG1H
FG11
FG1J

PX3DPX3D+
PX3EPX3E+

FG1K
FG1L
FG1M
FG1N

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

FG12
FG13
FG14

PX4CLKPX4CLK+

FG18

PX4DPX4D+
PX4EPX4E+

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FG15
FG16
FG17

FG19
FG1A
FG1B
FG1Q
FG1P

1G50

FG04

FG2L
FG2M
FG2E
FG2F
FG1Y
FG1Z
FG20
FG21

PX1CLKPX1CLK+

FG22
FG23

PX1DPX1D+
PX1EPX1E+

FG24
FG25
FG26
FG27
2G28
RES

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

FG28
FG29
FG2A
FG2B
FG2C
FG2D

PX2CLKPX2CLK+

FG1R
FG1S

PX2DPX2D+
PX2EPX2E+

FG1T
FG1U
FG1W
FG1V

47p
2G29

47p

RES

FG2P
100n

100n

100n

2G95

RES
RES
RES
RES
RES
RES

FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53

FG36
FG34
FG2H
FG2G
FG37
FG35
FG2R
FG2K

2G91

100n

LAMP-ON
BACKLIGHT-PWM_BL-VS
CTRL-DISP
3D-LR
3D-VS-DISP
CTRL-DISP
CTRL-DISP
SPLASH-ON
PX1APX1A+
PX1BPX1B+
PX1CPX1C+

100R
100R
100R
100R
100R
100R
100R
100R
100R
100R
100R
100R

EMC 100n
RES 2G9D

2G94

FG2J

3G16
3G32
3G2W
3G2Y
3G17
3G38
3G37
3G2Z
3G36
3G30
3G31
3G39

RES 9G0G

FG2N

+VDISP

TO DISPLAY

EMC 100n
RES 2G9C

100n

FI-RE41S-HF
50
51
48
49
46
47
44
45
42
43

RES

EMC 100n
RES 2G9E

2G93

3D-LED
CTRL-DISP
SDA-DISP
SCL-DISP

EMC
RES 2G9F

100n

9G0K-4
9G0K-3
9G0K-2
9G0K-1
2G92

SPLASH-ON

4
3
2
1

5
6
7
8

LAMP-ON

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1G51

TO DISPLAY

1X05
REF EMC HOLE

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_036_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 175

AmbiLight CPLD

Ambilight CPLD

B06C

B06C

5GA0

FGA0

+3V3

VINT

5GA1

100n

100n
2GA2

2GA1

1u0

2GA0

30R

DEBUG ONLY

FGA1

+3V3

VIO

+3V3

100n

29
30
31
32
37
38
11
9
24
10

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

10K
RES
10p
RES

IGA1
CPLED2
IGA2

19
20
21
22
23
27
28

TCK
TDI
TDO
TMS

PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

9GA1 RES

3GA1

4
3G10-4
2
3G10-2
3G12
3
3G11-3

RES
47R
5
33R
3
7 3G10-3
33R
3G13
10R
1
6 3G10-1
33R

IGA3
GCK2
+3V3
3

+3V3

AMBI-SPI-CS-EXTLAMPSn

6
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

33R
8
33R

RES
7GA1-1
BC847BS(COL)
1

GTS1

+3V3
3
RES
7GA2-2
BC847BS(COL)
4

GTS2

GND
4
17
25

+3V3

RES
7GA1-2
BC847BS(COL)
4

GCK3

AMBI-PROG_B1
AMBI-BLANK_R1

6
33R

10p

33R
2
33R

5
6 100R
7 100R
8 100R
100R

CPLED3
5
6
7
8
12
13
14
16
18

10p
2G19

1
3G14
7
33R
3G11-2

10p

10p
2G12

10p
2G11

10K

2G10

8
3G11-1

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

10p
2G18

36
34
33

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

3G15

33R

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

10p
2G16

3GA3

4
3
2
1

SD51022

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G15

PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

2
3
39
40
41
42

3GA5-4
3GA5-3
3GA5-2
3GA5-1

RES
RES
RES
RES

GCK3
GTS1
GTS2
GSR

VCCINT VCCIO
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

10p
2G14

43
44
1

2G13

PXCLK54
GCK2
GCK3

15
35

7GA0
XC9572XL-10VQG44C0100

VIO

1
2
3
4
5
6

+3V3

26

VINT

2GA6

3GA4

RES
1G37

10p
2G17

2GA5

1u0

2GA3

30R

+3V3
6

+3V3

RES
3GA6-3

6 330R 3

RES
3GA6-4

5 330R 4

100n

2GA4

LTST-C190KGKT

FGA3

RES
6GA3

FGA5

LTST-C190KGKT

FGA4

FGA2

8
SD51022

RES
3GA6-1

FGA6

1
2
3
4
5
6

RES
6GA2

100R
100R
100R
100R

LTST-C190KGKT

8
7
6
5

RES
6GA1

1
2
3
4

LTST-C190KGKT

3GA2-1
3GA2-2
3GA2-3
3GA2-4

RES
6GA0

RES
RES
RES
RES

8 330R 1

RES
1G36
1
2
3
4
5
6

RES
3GA6-2

DEBUG ONLY
RES
1G35

RES
7GA2-1
BC847BS(COL)
1

7 330R 2

GSR

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_037_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 176

SPI buffer

SPI buffer

B06D

RESERVED

+3V3

20
3EN1
3EN2
G3
PNX-SPI-CLK

PNX-SPI-SDO

RES
7GE0
74LVC245A
1

17
16
15
14
13
12
11

PNX-SPI-CSBn

IGE0

19

RES
7GE1
PDTC114EU

RES 3GE0-3 3

6 47R

3
4
5
6
7
8
9

RES
RES
RES
RES
RES

8 47R
1 47R
4 47R
47R
47R

3GE0-1 1
3GE1-1 8
3GE1-4 5
3GE3
3GE4

BL-SPI-CLK
BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

18

10K

100n

RES
3GE2

+3V3

RES
2GE0

B06D

PNX-SPI-CLK

RES 8

9GE0-1

BL-SPI-CLK

PNX-SPI-SDO

RES 6

9GE0-3

BL-SPI-SDO

BL-SPI-SDI

RES

9GE1

RES

9GE2

PNX-SPI-CS-BLn

IGE1

RES 5 9GE0-4

PNX-SPI-SDI

*
** 4

BL-SPI-CSn

Buffer

*
**

Direct

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_038_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 177

10-19 B07 310431365392


DVBS-FE

DVBS-FE

B07A

7R01-1

STV0903BAC

100n

10n

2R15

100n

2R14

10n

2R09

+3V3-DEMOD

130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

VDD1V0

10n

10n

2R52

10n

2R51

100n

2R50

100n

2R49

100n

2R48

2R47

100n

2R46

22u

2R16

VIA

21
38
54
76
80
92
96
106

+3V3-DEMOD

30R

VDD3V3

2
3
100n

2R17

+1V-DVBS

11
12

VDDA2V5

8
7

IM
IP

60
56
RES 2R21

DISECQ-DET
F22-DISECQ-TX

1n0

128
20
126
NC
107
NC
47p
IR04
97
98
3R00 IR03
19
18

RES 2R22
SCL-SSB
SDA-SSB

100R
RES 2R23

3R01
47p
100R

SCLT
SDAT

RESET-DVBS
9R00
RES

3R11
+3V3-DVBS
10K

IR02

62
58
26
23
24
29
27

FR02
FR03
FR04
FR05
FR06

FR07

XTALO

VS
AGCRF1

I2C-ADDRESS : D0
DIRCLK
CLKI
CLKI2
CLKOUT27
N
I1
P

N
Q1
P

0
1
2
3
D
4
5
6
7
CLKOUT
STROUT
DPN
ERROR

0
CS
1
DISEQCIN1
DISEQCOUT1
FSKRX_IN
FSKRX_OUT
NC
SCL
SDA
SCLT
1
SDAT

RESETB
STDBY
TCK
TDI
TDO
TMS
TRST

COMP

0
1

1
2
3
4
5
6
GPIO 7
8
9
10
11
12
13

52

SENSE+1V0-DVBS

63
64
65
67
68
70
71
73
74
75
78
79
82
83
84
86
87
89
90
91
94
95
108
109
111
115
116
119
120

AGC

2R53

1K0

47n

* To be drawn near PNX85500


3R03
3R04
3R05
3R06

47R
47R
47R
47R

NC

NC
NC
NC

TS-DVBS-DATA 4
TS-DVBS-CLOCK
TS-DVBS-SOP 2
TS-DVBS-VALID 1

9R03-4 * 5
9R04 *
9R03-2 * 7
9R03-1 * 8

TS-FE-DATA
TS-FE-CLOCK
TS-FE-SOP
TS-FE-VALID

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

40
41
101
50
49
47
46
44
43
37
35
34
32
30
55

FR00

3R02

16

IR05

3R07
120K

DISECQ-RX

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

100n

2R26

100n

2R25

100n

2R24

100n

100n

2R19

+2V5-DVBS
2R18

VDDA1V0

5
9
13
114
118
123
127

NC

QM
QP

129

GND_HS

IR00

5R00
+3V3-DVBS

NC

59
104
103
100

MAIN

XTALI

6p8

GNDA

NC

124

2R20 RES

10n

100n

2R13

10n

2R12

100n

2R11

10n

2R06

2R05
2R08

100n

2R07

+1V-DVBS

XTAL
1
4
6
10
14
113
117
121
125

1K0

100n

10n

2R10

100n

2R03

10n

2R02

100n

2R01

2R00

100n

2R04

+1V-DVBS

POWER_VIA

3R10

15
17
22
25
28
31
33
36
39
42
45
48
51
53
57
61
66
69
72
77
81
85
88
93
99
102
105
110
112

+1V-DVBS

122

10K

7R01-2
STV0903BAC

3R13

B07A

+3V3RF
3R12

IR06

2R43

SATELLITE
TUNER
I2C-ADDRESS : C6

QP
QN
RF_OUT

AGC
AS
NC

VIA

RF_IN
GND
RF LNA LT MIX DIG BB VCO
5
3
9 10 15 17 25 26

10u

2R61
3R09

2R40

1K0

100p

21
20
7 NC
34
35
36
37
38
39
40
41
42

XTAL

3
3R08-3
2
3R08-2
10p

SCL
SDA

18
19

2R56

XTAL_CMD

IP
IN

32

4
6 3R08-4
100R
1
7 3R08-1
100R

5
100R

QP
QM

8
100R

IP
IM

SYN HS
29 33

1
2
3
4

2R62
100p

2R45

1n0

2R29

SM15T

FR01

1R00
310430133871

1n0

1n0
2R35

XTAL_OUT

10p

23
24

SYN

0p56

5R02

27n

2
3
4
5
LNB-RF1

16

28

VCO

27p

10n

2R28

2R27

220u 6.3V

10u

10p

2R39

NC

+3V3RF

IR01

6R00

5R01
+3V3-DVBS

9R02
RES

27

2R55

AGC

22

10p

12
13

IR08

14

MIX DIG BB
VSS

10p

11

XTAL_IN

1 2
10p

1R01
1826-N96-R11-02

2R41

NC

16M

2R38

31

IR07

SCLT
SDAT

LNA LT

2R54

7R02
STV6110AT

3 4
30

10K

10K

3R15 RES

3R14 RES

10p

1n0
2R34

+3V3RF

1n0
2R33

1R10
NX3225GA

2R37
+3V3RF

1n0
2R32

2R31

4R7

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_039_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 178

10-20 B08 310431365392


DVBS supply

DVBS supply
5T00

B08A

IT00

INH

+1V-DVBS
2T04

HS
9

3T00 RES

15

IT20
14

11

+3V3-DVBS

IT24

SENSE+1V0-DVBS

4n7
3T21

100n

2T06

47K

4n7
2T36

1%

12

3K3

VIA

10
3T03

1K0 1%
2T10 RES

IT02
13

22K
3T02

7T00-2
ST1S10BPH

FT06

IT18

2u0

VFB

GND
A
P
8
4

5T01

IT01

RES 3T01

RES 1n0

2T03

SW

VIN

+2V5-DVBS

22u

SW

22u
2T05

7T00-1
ST1S10BPH

22u

22u

2T02

22u

2T01

2T00

30R

+5V-DVBS

1K0 1%
LD3985M25
7T01
IN

OUT

INH

30R

BP

FT07

5
4

+2V5-DVBS
IT19

COM
2

100n

5T02

2T07

1u0

1u0

IT03

2T39

BAS316

2T08

6T02 RES

BAS316

10n

6T00 RES

BAS316

2T09

6T01 RES
+5V-DVBS

7T02
LD1117DT33
OUT

FT08

+3V3-DVBS
16V

IN

2T12

100n

2T11

COM
1

22u

+24V

100u 35V

IT05

5T03

FT00

220n
2T17

2T14

47n

2T16

3R3

2T13

220n

IT04

100u 35V
2T15

3T04

10K

13
12
6
8

10K

SW-LNB

3R3
5T04

4u7

RES 2T22

4u7

RES 2T38

10u

1n0

IT11

RES 2T37

10u

2T24

2T23

6T04

SS24

16
17
18
19
20
21
22
23
24
25
26

22R

3T11

33u

100u 25V

+V-LNB
IT32

GND_HS

IT17

1n0

IT12

3T29
3T08

3T10

IT09

15

GND

7T04-1
BC847BS(COL)
1

10u

2T35

IT21

IT10

47n

2T26

1n0

2T25
3T06

100K

IT27

6
3T07

ILIM2
SEQ
BP

VIA2

IT08

+3V3

BOOT2
SW2
EN2
FB2

IT26

2T27

9
10
11

BOOT1
SW1
EN1
FB1

PVDD2

1K0

1n0

2T21

2
3
5
7

IT07

+24V

10K

PVDD1

2T20

14

7T03
TPS54283PWP
IT25

IT06

22R

3T05

22u

6T03

SS24

33u

220u 16V
2T19

2T18

+5V-DVBS

RES
3T31

IT13

9T00

LNB-FB
IT29

3T23
33K

2T41
RES
2T28

1n0
FT04

4u7

RES
3T24

SENSE+1V0-DVBS

15K

220p

2T40
2T31 RES

RES
2T29

47K
5%
RES

47K

3T16

3T15

IT14

3K3
5%

3T17

7T04-2
BC847BS(COL)
4

2T30 RES

5
IT23

22n

3T14
2K2

BZX384-C
13V

1K0

IT22

6T05
+24V

22n
3T12

3K3

3T13 RES

+V-LNB
3

IT15

3T25

IT30

3K3

2T42

3T28
100K
RES

RES 10n
IT16

RES 10K

100n
RES

3T26
2T43

RES 2T34

V0-CTRL

330K

22n

RES
33K

3T19

3K3
5%

3T18

18K
5%
22u

22u

2T33 RES

22n
3T20

RES 3T09

+5V-DVBS

2T32 RES

B08A

SPB SSB
TV550 2K11 4DDR EU SD

FT05

2011-05-09

3104 313 6539


19051_040_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 179

DVBS supply

B08B

DVBS supply

B08B

+12V

+3V3-DVBS

+12V

3T22

220R

22u

RES

5T50

3T50

100R

100n

2T51

2T50

RES

100u 35V

IT50

IT28

220n

2T52

V0-CTRL

IT60
5T52

27

BYP

A_GND
34
35
36

6T50

220n

2T53

2K2

IT55
DISECQ-DET

10n

10u

3T58 RES

2T62 RES

2T60

2K2

1R0

IT67

3T59 RES

+3V3-DVBS
10K

STPS2L30A

3T57 RES
6T51

1
2
3
7
8
16
17
23
24
25
26
31
32

IT66

IT64
6T54 RES

RES
7T51
BC817-25W

IT68

BAS316

2T61

20
7T50-2
LNBH23Q

BAT54 COL

18
NC

VUP

470n

IT69

IT59
9T52 RES

VIA
VIA

VIA

DISECQ-RX

39
40

VIA
37
38

2T59

470n

15
2T58

RES 2T57

470n

100u 35V

IT58

30R
2T56

2T55

100u 35V

+V-LNB

VCTRL

11

3T62

150R

IT57

5T51

TTX

15R

22R

30

EXTM

IT54
22

3T54 RES

14

DSQOUT

DSQIN

LNB-RF1

3T53

21

RES

RS1D

IT65

VOTX

22K

3T27

13

VCC_L

VCC
IT63

9T51

DETIN

3T52

1n0

9T50
RES

VORX

28

IT52

220u

RES

IT56

RES

6T53

STPS2L30A

6T52

6T55

RS1D

10K
F22-DISECQ-TX

12

ADDR

GND_HS

3T56

29

ISEL
LX

P_GND

DISECQ-DET

10

10K 3T55 RES


RES
IT61
IT62
10K
10n

2T54

SCL
SDA

IT53

33

LNB-RF1

100R

IT51

41
42

+12V

9
6

3T61
3T60 RES

100R
SDA-SSB

19

7T50-1
LNBH23Q

3T51

SCL-SSB

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_041_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 180

10-21 B09 310431365392


Connectors comp

Connectors comp

B09A
5C55-1

30R

V-AMBI

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP

FC77

FC76
FC78
3C70

100R

FC79

AMBI-TEMP-1

cC70
100n

2C70

1u0

2C71

FC81

GND_AL
NC

FC83
+24V

1C86

FC82
AMBI-POWER

100n
RES

1C87

2C95

100n

FC84
+12V_AL

2C94

T 2.0A 63V

T 2.0A 63V
RES

Option table for Ambilight

27

2C96

ITEMS

BLOCKBUSTER

EMMY

SUNDANCE
/ INFINITY

1C86

1C87

3C75

100p

100R

2C77

3C76

100p

IC73

100R

2C78

IC74

3C77

100p

2C93
47n RES

RC

LED-2

TO
LED PANEL

100R

FC90
FC91
FC92
FC93

2C79
LED-1

3C78

100p

100R

2C80

FC94
+5V

100p
FC95

KEYBOARD

28

3C79
10R

100p

FH34SRJ-26S-0.5SH(50)

2C82

100n
RES

**

1
2
3
4
5
6
7
8
9
10
11

RES 3C96
+3V3-STANDBY
+T 0R4
1
2
3
4

9C02-1
9C02-2
9C02-3
9C02-4

8
7
6
5
12

FC86

100R
RES 3C83
100R

FC64

FC97

FC98

RES
3C94
RES
3C95

+3V3

30R

RES 5C53
+12V

IC78

**

1u0

04 6288 018 000 846+

FC9D

3D-LED

FC99
RES 5C54

20

FC9B

47R

2041145-4

TEMPERATURE
SENSOR

FC9A

47R

1
2
3
4

1u0

FAN-DRV

* RES 3C93
10K

T 1.0A 63V

+3V3

* RES 3C92
100R

RES
1C85

FAN-CTRL2

19

Option table for Leading Edge

Items

BlockBuster / Emmy

1M19

Yes

No

1M20

No

Yes

1M21

No

No

100p

RES 3C82

100p

FC63

9C00
RES
9C01
RES

SDA-SET

RES
1M71

FC96

RES 2C85

SDA-BL

100R
RES 3C81 100R

100p
RES 2C84

TACH02

SCL-SET

RES 3C80

FC85

20

FH52-18S-0.5SH

RES 2C83

SCL-BL

FC62

1u0
2C91

19
3C91

2C97

* RES

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

10p

10K

13

**

3C90

100R
TACH01

2C90

**

+T 0R4

10p
RES 2C87

* RES

+5V

1M22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

FH52-11S-0.5SH

3C97

RES 2C86

FAN-CTRL1

+3V3
FC61

RES
1M21

1M20

GND_AL GND_AL

* HOTEL TV

1
2
3
4
5
6
7
8

FC89

+3V3-STANDBY

IC75

**

1M19

FC88

100n

FC75

FC87
LIGHT-SENSOR

2C81

FC74

6C02

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

2C76

RES

FC72
V-AMBI

6C05

FC73

RES
BZX384-C5V6

AMBI-PWM-CLK_B2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

BZX384-C5V6

FC71

6C03 RES

AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

AV2-STATUS

1M59

FC70

AMBI-SPI-CLK-OUT

+3V3

BZX384-C5V6

FC9C

100K
RES

5C55

3C74

B09A

Sundance / Infinity

RESERVED

30R
2

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_042_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 181

10-22 B10 310431365392


DVBT2

DVB-T2

+1V2-DVBT2-M

2FJ4
100n
2FJ3
100n
2FJ2
100n

2FJC
100n
2FJB
100n
2FJA
100n
2FJ9
100n
2FJ8
100n
2FJ7
100n
2FJ6
100n

+1V2-DVBT2-C

B10A

+1V2-DVBT2-P
2FJJ

+2V5-DVBT2-A

+3V3-DVBT2-D

100n
+3V3-DVBT2-R

100n
+2V5-DVBT2-X

2FJE
100n
2FJF
100n

2FJP
100n

2FJD
100n

2FJL

2FJK

2FKB

IF-N-DVBT2

3FJM

RES 9FJ4

IFJ5

2FJY
DVBT2-IFN

DVBT2-IFN

47
IFJ1

3FJ0

46
1K0
50
49

5FJ9
9FK5

3FJB
2FJ1

150K
100p

3FJA
3FJ9

100R
330K

53

1M0

3FJN

3FJ2
2FJN

RF-AGC
5
7FJ1-2
BC847BPN(COL)

64
63

1K0

MVDD

3FJ7
1
7FJ1-1
BC847BPN(COL)

IFJ4

10K
3FJ8

+3V3-DVBT2-D

R
VDD

45

54

44

8
19
40
41

11
27
59

7
14
20
30
36
56
61

DVDD

XTALI
XTALO

0
1
2
3
TSDATA
4
5
6
7

AINP
AINM

RFAIN

58
57

IFAGC
RFAGC_GPIO1

SCL
SDA

TUNERCLK
TUNERDAT

I2C ADDRESS
0xD8, 0xDC

DFJ1
1

GPIO0

10K

3
+3V3-DVBT2-D

IF-AGC

IFJ8

RES 3FJ4
4K7

RES 3FJ3

32

33

TESTMODE

A0

4K7
DFJ2
REMOVE IN
NEXT LAYOUT

VIA
34

9FJ0
37

RESET-SYSTEMn

OSCENBN

RESETN

DFJ4
38

OSCMODE

DFJ3
PLLBPN

IFJA

5
4
3
2
12
13
16
17
22
23
24
25
28
29

RES 9FJ1

3FJG
3FJF-2 2
3FJF-3 3
3FJF-4 4

7
6
5

47R
47R
47R
47R

9FK1
9FK2
9FK3

3FJF-1

47R

9FK4

IFJ9

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP
TS-DVBT2-ERR
TS-FE-DATA

REMOVE IN
NEXT LAYOUT
9FJ2
3FJH
3FJJ

47R
47R

SCL-SSB
SDA-SSB

66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

XVSS
48

PVSS
43

6
10
15
21
26
31
35
55
60

51
5FJ1

FFJ0

+3V3-DVBT2-D

+3V3

GND_HS MVSS
9
18
39
42

VSS

AVSS

65

62

6p8

TSCLK
TSVALID
TSSYNC
TSERR_GPIO2

DFJ0

IFJ3

4n7

2
4

CVDD

47p

+5V-TUN-PIN

820n

52

12p

AVDD
IFJ0

2FJV

100n

RES 2FJM

7FJ0
CXD2820R

2
4

1FJ0
41M
680n

10p

100n

100R

10n

47p

DVBT2-IFP

100R

10n

IFJ2

2FJW
DVBT2-IFP

5FJ0

3FJK

RES 9FJ3

RES 2FJ5

2FKA

IF-P-DVBT2

12p

2FJH

2FJT
820n

2FJG

100n
5FJ8

5
6
7
8

+1V2-FE
IFJB

5FJ5
+3V3-DVBT2-R

IFJE
+1V2-DVBT2-C

+1V2-FE
30R
2FK4

1u0

2FK1

30R

1u0

220u 16V

5FJ2
10u
2FKG

9FK6-4
9FK6-3
9FK6-2
9FK6-1

RES 2FKF

4
3
2
1

+1V2

1u0

2FK0

30R

RES 5FK2
+5V

7FK1
LD3985M25
IFJC

+2V5-DVB

5FJ6

+1V2-DVBT2-M

1u0

30R
2FK5

IFJF

+2V5-DVBT2-A
30R
1u0

BP

COM

5FJ3
+2V5-DVB

2FK2

INH

FFJ1

1u0

OUT

2FKE

5FJ4

IFJD

5FJ7

IFJG
+1V2-DVBT2-P

+2V5-DVBT2-X
2FK6

1u0

1u0

30R

30R
2FK3

1u0

IN

10n

30R

2FKD

+3V3

30R
5FK1

2FKC

B10A

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_043_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 182

10-23 B12 310431365392


DVBS DC/DC TPA54231

DVBS DC/DC TPA54231

B12A

B12A
IK08

5K00
+5V-DVBS

22u

2K12

22u

2K11

6K03

SS24

22R

3K13

10u

IK12
1n0

2K13

+24V

IK13
1n0

2K14

220n

6K00

13V
BZX384-C

2K00

+24V

IK06
3K00
33K

COMP
BOOT
PH
VSENSE

2K03
220p

GND-+5V

3K12
+5V-DVBS
22K

GND
7

4K7

10n

1n0

VIN
EN
SS

IK01

6
1 2K01
100n
8
IK09
5

22K
3K11

7K02-1
BC847BS(COL)
1

10K

2K04

RES 2K05

1K0

7K02-2

IK05

3K06

3K07

2K2
5

3K03

100K

3K04

10K

3K05

IK07

IK00

4n7
2
3
4

BC847BS(COL) 3
IK04

2K02

7K00
TPS54231DRG4

+24V

3K10

+3V3

CK00
GND-+5V

GND-+5V

GND-+5V

GND-+5V

GND-+5V
GND-+5V

GND-+5V

IK02

3K01 RES

2K07

7K03
TPS54231DRG4

IK03

3K02

IK11

33K

4n7
1% 47K
7K01
TS2431

2
3
4

+5V-DVBS

RES

VIN
EN
SS

COMP
BOOT
PH
VSENSE

IK10

6
1 2K10
8
5

2K08
220p

100n

GND
7

10n

22u
2K09

2K15

1K0

3K08

GND-LNB

SW-LNB
CK01

GND-LNB

1X09
REF EMC HOLE

BAS316

6K01

100p

LNB-FB
2K16

6K02
+V-LNB

GND-LNB

1K0

PDZ20-B
3K09

GND-LNB

GND-LNB

6K04

IK14

SS24

+5V-DVBS

220n

2K06

+24V

SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_044_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 183

10-24 310431365392 SSB Layout

5UD3

2UE4

2T32

2T33
7GA2

2UU2

3GA5

5T01

1G36

2G44

1G03

3GA2

3G15

6G00

2GA4

1G35
9GA0

3GA1

3B11

7GA0

3B26

IGA3
IGA2

2F01

5R01

9S00

2S09
3S3Y

7S02

3S04

3S24

3S23

3S29

3S21
3S3S
3S1K

3S1J
3S3T

3B13

3S3N

3S2A

3S3R

2B44

3S28

3S3Q

3S03

3S62

2S4E

3B12

3S1B
3S1L

7B02

9S01

3B23

2S4D

3B02

3S02 3S01

3S31

3B00

3S1C

2R28

2R29

3R14
3R15

2R45

2R32

2R46

5R02

2R31

2R55

3R08

2R62

2R54

3R09
2R40

2R38

2R39

2R41

2T55

2T56

6T52

3S42
2S78

3FLE

7F70

IF89

3E89

6E51

2E28

2E67

3E92

9FLC
9FLD

2FL6

2FL7

3F78

2F91
3F72

6F72

2E30

2E29

BE06

3E88

1F75

5E40
3E93

2E42

5D05

7F58

2F58

3E85

9FLH

9FLJ

1FL5

7FL5

2E31

3F58

1E71

2E32

IF61

2F92 2F94
2F90 3F71

BS13

2S4M

2FKG

3S83

3F59
3F60

7F52

3S84

2S7T

BE04

5T51

1P09

2C71

2S77

5E41
3E86

9F28

3S44
2S87
3S59

2S7L

2S7N

2S7U

2S8G
9S18

3S4P

3S4R

3S4J 2S7J

3S4W

2S7R
2S7P

3S4V

3S4T

2S7E

2S7H

2S7K
3S4L

3S4K

2S30

2S33

2S2Z

3S4Y

BS10

1F10

2S41

3S6H

CC70

2S7M

3S13

2E33

BE05

9F27

3S3W
3E17

2S2Y

2S2V

2S31

4S14

2S2S

3S6J

2S32

2S34

7S08

3S26

2S2T

2S2W

3S2M

IS13

3S12

2D35

3S3M

3S43

3E91

9S06

3B04

3S3U

DBS8

1S02
3S3G

2S2R

3S53

5D02 5D01

3S54

2S4G

2F40

3S3F

2B45

2D09
2D10

DS50

3S50

2D06

2G29

3S52

BS15

3B14

3S3H

2D07

3B15

3S27

2D12

6T55
7T50

5T50

3S80
2S4F

7B03

7D10

2D36

1R10
2R37

6T51
6T53

IF62
3S81

3B24

5D04

5T52

5D07

2D11

1R01

2R43

3S6K

3B05

2D23

2D24

2D17

3S3L

3S00

1D52

2D08

1735 1D38

1D50

2D34

7R01

2R34

3R06

2T57
2T50

3R05

2D32
2D20

3R04

3B17

3T22

2R20

2R27

1R00
7R02

3R03
3B16

3B07

2D05

3B25

2B46

5D08

7B00

2D19

9R02

7F20

2R56

3B10

7S00

3B08

2G96

2R33

2G99

2S4P

2G97

2R35

IGA1

3R12

3B19

2R61

2B47

7B01

3B18

2G98

1G51

5T00

1P00

7GA1

5G01

3G28

5F70

2F9D

5E42

1P08

3E90
3E84

3E83
2E68

9FLF

9FLK

9FLG

3FLC

9FL3

9FLL

3FL7
3F65

3FL2

2F88
9F71

2F9B

2F86
3F75

5F72

3F64

1P07

3F63 3F62

1T01

1F52

1E86

1328 1E06

IE11

2F9A

2F99
IE09

1FD2

6FC5
3FC4
3FC3

1E01

1P03

1P02

1FC6

3FC5

6FC1
6FC6
3FC1

3FC7

9FC5

3FC6
2FC6

2FC1

9FC6

9FC4

1FC3 1FC4 1FC2

6FC2

6FC8
2FC8

1FC5

1E00

2FC7
3FC2

1E37

2FC2

1E38

2FC4

2ECC

2FC3

5EC2

6E01

2FC5

9EC3

2E01

1E09

2E90

2E88

3000

1P05

6FC3

1FC1

3001

3002

3E77

6FC7

2F97

9FC3

2E91

2E18

2E15

2E14

2E12

2F60

3ECM

6FC4

2E87

1E25
1E23
1E22
1E19

1329

2FDC

3FDG

2F81

2E80

5E74

6E23

3E75

2E84

3E76

3003

6E22

7EC1

3E79

2E76
2E44

2FDD

2ECN
2ECM

2E06

2E10

6E07

6E09

3E32

BEC5

2EC1

BEC3

2E04

3E31

3E44

2E24

6E26

3E78

2E85

6E28

2E86

7000

3EE2

2E75

3E9C

1E18
1E55
1E12
1E54
1E53
1E31

2E73

5E76

6E29

2EE7

3ECN IE42

6FD2

3E74

5E73

2E79

2E83

2ECP

2EE4

6E03

2EE3

6FD3

6E30

1E80

1F51

3ECP

2E77

1N00

IE10

1FD3
3ECG

2ECU

3FL4
9FLE

2F9C

2F93

3ECF

3E43

6E53

6EC1

3F34

2F98

2EE1

6E32

3C95

2C81

IEE6
2EE2

3E62

3C94

2C87

IEE5

7EE1

1E10

2C90

2C86

2EE0

2E05

IC74

6C05
2C91

IEE4
3EE3

3EE0

6E47

3E27

1E88

2E62
3E98

5E08

5E01

2EE6

3C79

2E60

6C03
2C82

5E02

1P04

2E63

2E56

3E28

3E26

3C96
3C97

9C02

IC75

3E42

2E57

3C78
3C77

2E71

2EE5

3E25 3E22

2C93

2C80
2C78

3E96

IEE3

2E66

2E07
3C76

1E87

3C74

6C02
2C77

3E68

6E40

3E72
3E40

3E35

3C75

2C97

3E34

2C76

3E87

3EE1

IE07

2G75
2G77

1E39

3E97
2E40

2G76

1E43

1E42

1E29

6E38

2E54

7EE0

2G27

2E55
3E30

7E10

3G17

2G78

3E33

2E72

1E70

3E51

3G38

6E06

2E52

2G26

2E39

3G39

3G16
2G25

1EP2

2E53
2G24

IF86

5F73

9F04

1E85

2E27

3E65

3E70

3E69

3E66

3E67

2E48

2E49

3E64

9E42

3E71

3E80

1E03

9G01

2G79

1E08

9F05 9F06

6E52

1E28

9F00 9F01

2E41

2G28

2G7A

1M19
1M20
1M22
1M21

3K09

6GA1 3GA6

1G37

IG11

1G50

2T19

2U27

3UD2
3UD0

3U06

2UD7
3UD1

2UD9
3U26

6GA3

3UD3

6GA0

3UD4

2UD6 6UD0

IUS9

2UD4 2UD5

5UD2

2UE1

2UE2

3US9 3US6

2U15

2U28

IUD2

3US3

3US2

IUT1

IU15

2UD8
3UD5

9UU1 9UU0

5G02

1G00
2G43

2U16

5U01

5C53

7UU0

5C54

2T18

IUD4

2UE3

2C85

3C82

IUS6

3U29

7US3

3C93
3C92

1C85

IUS5

2UD2

2T00

5T03

5UD0

2UE6

6U00

IU17

2US3

3U24

7US2

2U09

7UD0

IUD1

7UD1

2U18

IU18

2U17

3C90

2C83
2C84

2U11

3C91
3C83

5U00

3C80
3C81

5UD1

2UE0

3US5

7US1

3US7

IU23

7U05

2UD1

IUT2

9US0

3U23

1M71

7U01 7U04 7U02

3US4

IUS4

2UE9

IUS3

3U07

7UD3

2UD0

2T01

6GA2

2UE8

5U03

5U02

2U19

2U25

2U23

2U24

2UE7

IU57

7T00

2T22 2T12

9T00

3C70

2C70

2G13
3G13

3G12

3G14

2C96

7T03

IUD0

2U20

6K01

2T14 2T17 5T04

2C95

3G10

3G11

3U65

2UD3

6K02

2K11 2K12

5K00

2C94

5C55

3U81

3U64

4U00

1F24
1C87
1C86

1UM0

5UM1

2U56

3U56

3U66

2U43

3U44

3U67

3U84

2U52

2U51

2U72
3U76

2U48

3U71

2U68

2U49

2U54

2D30

3U45

2U47

2U53

3U42

2U58

3U43

2U45

2U44

4U01

2U46

1M59

1M99

CXXX

2U50

1M95

2K15

Overview top side

1E05
LAYOUT
SPB SSB
TV550 2K11 4DDR EU SD

3104 313 6539


19051_045_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 184

Overview bottom side

2K00

2K09

2G10

2G16

2G11

2G17

2G14

3U69

3UB6
IU26

3U13

7F02

FGA4

3S58
3S5W

3S06

2F66

5F66

IF14

2S60

2UB3
2UB4

3UB4

3S6P

5S93

5S89
5S87

2S23

2S3J

6E44

3FE5

IU13

3U27
3U02

2U00
CU02

CU01
3UU2

2UU1

3UU1

3U05

7UU2

FG11

9G0K
3D16

7D03

2G94

FG1R

FG2C

FG1S

FG29

2FF3

3FE7

3FE6

3G34

IF17

DFE8

3E82
FE31

FE43

FC9D

FC89

FE33
FE29

FE34
FC87

FE5E

FE54

3E95
2E58

3E29
FE27

2FA4

5FA4

FG34

FG04

3G35

FE28

5E03

3E99
FC88

2E59

5E04

3E39

FC93
IC73

IEE7

FEC6

FFAF

FC90
FE30

2FA3

FG37
3G2Y
3G2W
FG2H

IE39

2FF4

2FE3
5FE8

2FF9

IF69

FG1Z

FG2F

3G32

FF63
5FA3

FG1Y

FG2E

3G37
FG2G

2E70

IE33

FE32
3FE9

3FE8

2FG0

2FF2

2FF1

2FG1

FF61

FG2L

FG35

IE32

FE50

2FF8

3G36

FE5D

FE49

FE5A

IF68

2FH4

7FE3

FG20

3G2Z

IE06

FE42

2FE4

DFE7

DFF2
DFF1

IE63

FG2R

IF49
IF67
FF62

2FH3

FG21

FG2K

DFE9

IF18

2FE8
5FE5

FG22

FG36

3G30
IE38

DFE6

2FG6
2FG4

FG24

FG25

IF29

7FE0

FF03

2FH2

7FJ1

FG28

FG23

3G33

IE26
IE64

2FF0

IEE0

FC91
2C79

IEE1
FEC5

2F59

FE61

FC92
FC94

3EC3

3EC5

FEA4

FEC2

FE60

FC9A

3EC1

IEE2
FECJ

2ECX

2ECY

3ECJ

FECR

2EC7

2EC3
FECY

FC9B

IE12

FFC2
FFC1

FECA

FECW

FFC8

FECT

FECM

FEA7

FEA5

FE82
FE36

FEA6
IE65

IE66

3ECU

FEC0
2EC4

IEC7

FECS
IEC6

IEC5

9EC0

7EC0 7E02
3ECD

3EC7

3EC6

6EC2

FE74

3E73

5EC0

5EC4

2EC0

2EC6

FFC7

2ECV

IE51

9EC2

7EC2

5EC3

3ECK

FEC7

3ECL

FEC3

2EC2

3ECH

2E37

2E38

FE02

IE43

6E20

FFC4

3E21

2E36

6E19

IE45

2ECW

2ECQ

FE03

FE01

2E35

3E20

7FA3

FEE0

FEC1

IE44

FFA2

IEC4

FEA3
3ECE
FEA2

IE18

FE72

FE35

3E23
FEA8
FECE

FE80

FEC4
FE71

FE73
FE75

FE81

3ECA
FECF

FECD
FE70

FE85

FE83
FE84

FECK
FECL

FECP

FECC

FECN

FECG

FECB
FF76

2FA2

2F61

3FJN

9FK5

3D02

FG27

2FF5

2FF7

2F84 3F76

3FG2

2EC8
9FC1

ID08

ID06
FE45

FG26

3FG4

FECZ

FF74

9FC2

FG2A

IE20

FE48

IF27

FE55

3FBF

3D14

FG2B

FE41

6E43

IE50

IF82

FE46

IE23

2E09

5FE7

2FG7

FFC9

FG1T

FG1U

FG2D

IE21

FE5C

2F79
3F77

2D26

FE44

FE51

IE49

3FG7

2FE6 BFE3

FF81

5FE9

FFB2

2U57

IF73

2F71

FE52

3E53

IF76

2F75

BFE2

FFDB

FFC6

CU04
CU03
2D31
ID14

2G91

3G31

2FH7

FFDC

FFC5

2D21

2D27

ID07

IE22

FG2M

2FH6

FL33

FFB4

FU72

CD10
2B07

2B06
3S72

2S39

2S38

2S3A
3S39

2G9D
2E74
3E48

3E81

2FH5

2FG8

FFC3

3D10

ID05

IE92
3E45

3E19

3E24

7E01

IEC1

FEA1

2E08

2FE0

5FE3

2FG9

FFB3

2D16

2B03

2B02

2B36

2EA4

FE53

5FE0

IF65

FL40

FFB1

FU73

3B20

2B11

2B12
3S34

3S32

2S2J
2S2H

2S2G

2B08

C001

IS19
2S3E

2B04

2S3H

2S3F
2S3B

2S3C

2S3D

3S5B

2S8A
3S37

2S22

2S29

2S3G

2S4Q

2S4R

2S45

2S50
5S84
3S75

3S09
3S10

2S18

2S2L
2S40

3S08

2S19

2S16

2B05

FEA0
IEC0

IEE8

2FG3

IF63

IF48

FFB6

3D06

2B16

2B14

3D09

3S20

2S24

5S90

2S53

2S52

2S68

2S42

3EA7

IEC2

3FG6

5FE4
FF00

FFB5

3U80

2UU0

2UB2

2UB1
2UB0

3U15
2B39

2B28

2B19

2B21

3D01

2S4S

2S5P

2S17

3S07

3S6Q

2S5J

2S64

2EA5

7E05

3EB6

IE96

3EB1

2E98

IE91

9G0G

2F78
2F74

IF28

FF82

FFDA

FD02

FG2P

2FE5
IF66

FF64

FL32

FL41

2S26

2S67
5S88

2S6P

2S5H

2S6H

5S81
5S04

2S37

5S92

2S5A
2S59

2S6M

2S58
2S55

2S4V

2S4Z

2S15
3E18

9E01

3EA1
3EB3

2E99

IE13

FE5B

1FE0

2FF6

FF65

FD06

3S0Z

FG2N

IF64
IFLB

2D14

2D13

ID10

FE07

5FG0

5FG2

AF70

FF66

IE59

2E97

IF74

3F80
3F81

2FH8

FL43

2D01

5D03

FD14

FE47

IF78

2F63
2F64

FG1W

FD05
ID32

ID09

ID31

IF15

AF71

2FG2

3FLH

3FLF

3FLD

3FLB

IFLD

IF13
IFLA

IFLE

3FLG

3F32

9F03
9F02

IF10

IF11

FG1V

2B41

IS12

IE70

7F75

FF01

ID28

2B00

3B03

3S38

IF81

IF12

2FL2

2S14

C000
3S49

IF75

2FL9

3FLA

2FLD

FF75

IF77

ID29

3S1D

3S3P

7E13

5E80

2FL8
2FL1

IFL3

2EB3

FE56

IE61

2E81

IE60

FF57

FE58
IFLC

2F85

ID19
FD09

IE68

IE89
3EA2

2FLA

FF71

ID37

IE90
2EB1

FE57

IF90

2FL4

ID30

ID18

2B01

IS1D

2F96

2FKA

2FKB

IFLG

IF59

3B28

FS57

7E06

IF80

IF72

2FLC

2S6K

2S5D

2S5C

2S6A
3S40
3S47

3F79
IF79

FL36

2S2E

9S0D

3S5V
3S6N

5F71

IF58

FF29

ID15

FS52

3E06

9FK6

IS0R

FS53

3E9E

2F95

2FKD
IFL1

IFL4

3S5T

3S11

3S6M

5F74

2F73 2F80
2F72 2F82
2F77
2F76 AF73

IF50

FF55

7E11

9FJ3

AF72
IF52

FF56

3E9D

3FJK

IS1H

3S36

IS1P

7E12

2E69

3FJM

5FJ9

1FJ0

2FJH

5FJ4

2FK3

5FJ7

2FK4

5FJ6

3FJ0

2FJK

2FJ2

2FJ8

3FJ4
3FJ3
9FJ0
5FJ5

7FK1

2FJG

IFJ0

IFJD

2FK6

2F65
3F82

3F52

IFJ2

2FJW

2F49

2F52

3F43

3F41

2FJ5

2FJY

IS02
3S5E

7D15

2D29

ID27

IS07

7S05

IS1J

FD08

FD15

IS03

FS03

6E48

2D28
FD01

FD03

IS1S

IS1Q

5FJ8

IFJ1

2FJJ

IE67

3S16 3S17

9FJ4

IFJF
DFJ4

2FK5

IS50

IS06

2FK2

IFJ5
IFJG

IS5C

IS20

IS0V

DFJ2
IFJ8

IS3E

IE05

5FJ0 2FJT

2FJV

IFJE
FF41

FFJ1

9S24

IS2V

ID33

2B09

2B40

IS1N

IS4V

IS3F

5F76

2D02

FS08

IS1M

IS5G

FD07

ID11

2S36

IS1B

IS44

IF16

2FKF

IS5J

IF53

IF54

FF44

IS2Z

FS50

2F62
2F70

2FJP

IS4W

3S5S

IFJB

IS11

3FJ9

IFJC

IS1A

IS5H

FS44

2B17

2B13

3S51

2FK1

2FJ7 2FJF
2FJL
3FJ7
3FJ8

IFJ4

5FJ3

3F40

7FJ0

2FKE

2S76

3S2L

3FJB

2FJ1

3FJA

2FJ9

FF42

IS5E

2S75

3S1H

IS1E
FS49

IS1K

2B15

FS02

2S6G

3S76

IS5D

3S1G

3S05

2FJ6

IFJ3

9FK3

5FJ1

2S3M

IFJA

3S25

2FJN

DFJ3

ID12

2B37

IS3D

3S46

IS42

2S46

3S2S
3S19

3S0V

2S65

2S20

2S51

2S86
2S84

5FJ2

2FK0

3F45

3FJ2
DFJ0

2FJA

3F42

IS1L

2B10
2S6D

2S6N

3B01

2S10

FS10

ID34

3D15

3S22

IS3L

ID35

7D11

3S30

2SHW

FS45

FS11

2B18

2S6E

IS5F

2S85

9FK4

DFJ1

FFJ0

3FJJ

2S43

2S13

IS2U

7S09

3B06

3S33

2S4U
DS52

FG31

2G9C

2B20

3B22

2S5G

3S6L

9FK1
IFJ9

FF43

2FJE

9S09

2S21

5S83

2S5K
5S95

IS4Z

2S3L

9FJ1

3FJF

2FJC

9FJ2

FF48

2FL3

2B24

FS01

2D03

2S4Y

2S2K

FS0Z

2S3Q

3FJH

3S0W

3S64
3S45

IT51

2S4K

3S2H

3S55

7S20

3S41
3S1P
IF51

9FK2

2FJ4

2S27

2S4T

3S2V

IT54

2S6B

5S94
2S4W

FS51

3FJG

2FJB

2FJD

2FJ3

IF47

3F44

FF47

5S80

2S5B

3S2K

9S0E

3T62

2S6L

IS01

IS16

3S1F

IT67

IS3Q

2S6C
IS05

FC95

FF04

IT69

6T50

3T27

7T51

2FJM

FF49

5S85

IS10
FS64

9R04

3T54

3T60
3T52

2T58

3T55

IT57

2T37

FF46

5S82

3S1T

3S1S

3S1R

3S1U

3S82

IS3S

IS04

9R03

IT59

IT68

3T53

IT53

IT61

FF45

2S6F

2R22

9T52

IT28

3T50

2T60 2T53

IT62

3T58
2T54

IT55

3F06

2T61

IT50

3T59
2T62

2T38

3S69

IT64

3T61

IT52

3S6V

3S1X

2R15

2R26

2R25

2R21

6T54
2T52

IT60

IT56

3S6W

3S1E

2S62

IS3K

2S5M

2S57

2S28

3S1W

2S56

IS25

3S56

2S11

3S2F

IS3B

2R23

2R52

3S57

IR04

2R09

IT58

2T51

2S63

IS26

3S5Y

3S6A

IR03

2T59

3T56
9T50
9T51
IT63

2FLB

FG30

FG32

2B26

FR03
2R17

3S6D

3S2G

FG1D

2G93

3B27
2B22

3S6F

3S5Z

2R51

IS58

3T57

2FL5

2B42

3S15

3S6E

IS40

5R00

2S61

2R08

FG1F

FG1C
2G92

2S25

3S1V
3S60

FG1E

FG33

2S66

3R01

IT66

IFLF

2B31

9S08

3S6G

3T51

IFL2

3B09

2G95

9S12

FG1G

3B21

3S67

2S4N

2R07

IT65

9F25
9F26

2B27

2B33
2B29

3S65

2B23

IS08
9S11

2S89

IS00

FG1L

FG1J

FG1H

2B38

3S6C

FG1M

FG1K

2B25

3S6B

9C00

IF87

IF88

FL37

2B35

FGA0

FG16

FG14

FG1N

2G9F

7S01

9C01

FG1A

FG18

FG12

2B34

2GA1

2S12

3F19

FG1Q

FG13
FB00

3GE4

FS31

3R00

5FK1

FUD2

2GA3

2GA5

5GA1
2GE0

5GA0
2GA0

3GE3

9S10
9S13

3F22

3F20

IF22

2R00

FR01

2UB6

9GA1

2GA2

3GE1

9GE2

7GE0

3GA4
2GA6

3GA3

3S68

2B32

3S61

2R14

FG2J

FG15

2B43

2R13

IR00

FUU0

FG19

IS09

2R11

2R12

2R16

3UU0

FG1B

2B30

2F20

FR07

2R24

7UU3

FUU1

FG17

IS17

3F23

3R13

2R06

3GE2

3S66

9GE1

3F24
IF23

3F12

2R49

2R19

IUU3

FGA1

IGE0

IF21

2R02

2R18

7UU1

3UU3
IUU4

3GE0

2R50

IR01

IUU2

IUU5

FG1P

3F21
IR02

2R10

2R04

3R10

FUA3

FGA5

3R11

FR02

IC78

2U14

FG0H

2F21

FR06

FC99

FU03

FGA6

2R01
FR04

FC97

IU40

2G9E

9GE0

2R48

2R05

2R03

FR05

FC98

2U29

IGE1

2F03

IF07

3F05

9R00

2R53

7U48

3U21
IU19

2U10

IUU0
FGA3

7GE1

3R02

CU05

3U20
IU01

IUU1

3F07

FR00

IUD5

2UE5

FGA2

IF05

IR07

CUA0

IUB1

7UA3

IUB6

7UA5

3U16

5UA0
3U41

3F03

IU21

FUA4

IU44

2UB5

3F02

3F01

2F02

7F01

3F10

FU00

IUB2

3U12

7UA6
2UB7

7U42

IF03

6R00

3U03

3UB1

2U71

6UD1

IU47
IU43

7UD2

3U59

FUD3

9U41

IUB3

7U43

7F00

2F00

3F11

2F06

7F05

IF02

IF01

IR05

FC96

2U04

3U83

7UC0

IUB4
IUB5

3U53

IF08

3R07

FU06

IU14
IU25

IU02

2U13 2U12

2UB8

7U06

IU07

FU05

2U05

IU09

IU41

7UA7

IU30

IU06
2U02

IU12

FU02

IU50

IU29
3U74

3U75

3U70

IU45

3U17

7U03

FU04

3U61

2UA4

9U42

2U08
3U18

3U14

IU10

IU64

IUA6

IU20
2U07
3U09

IU08

3U82

3UB5
IUS7

3U68

2R47

CU00

3UB0

IUA5

FU76

3U19

3U10

IU04

3UB7

3F08

3F09

IUB0

FU62

2U03

IU16

IU61

IU52

7UA4

7UA0

3UA0

FUA0

3UB3

3UB2

FS2Y

FU55

FU08

3U22

IU24

2U01

3U63
IUS8

7F03

7F04

IFD3

FU07

2F04

3FD3

2FD1

9FD2

3FD7

9FD1

6FD1

IFD1

3FD6

3FD4

IFD2

3U60

FU53

IU55

FU09
3U01

2U21

FC63

IF04

2FKC

7U41

IUD7

IU62

3U25

3F04

IU05

FU52

IU56

3U00

IU03

IU48

IU63

FU51

FU67

2U06

IU49

3U62

3U73

IUD6

FS2W

FU66

FU75

IU22

2U55

FC85

IF55

IF06

FU61

FU63

2U22

IUD3
IT06

IU27

2F05
FF58

3F54
3F66

9FD5

3F53

3F67

3FD1

9CH0

IFD5

7F53

3FD2

3F69

2F53

7F54

IF57

5FK2

FU60

3U72

6U40

FU57

FC86

7FD1

IFD4

FL42

IU51

FU68

FU01

FU74
FU56

FUS0

FC62

IF56

FF50

FU59

FU78

FU58

IU28

3F68

IR06

FU54

FC61
FC64

IT16

2T11

IR08

FU50

1U40

3T31

3T07

3T14
3T17

IT07

FU49

3U08

2T31
3T20

FU48

FU77
IT05

3U04

2T30

2T29

IT14

3T24

2G15

7U00

IT15

2T28

9FL1 9FL2

FC9C

IU11

IT13

3T12

IT17

FC70
FC72

2D22

2T23
2T24

3T29

IT08

IUM0

FC78

3U11

FT05

2T40

FUM0

FC71

FC76

FC79

3U28

IT27

IT32

FL38

IT21

FC82

7U40

IT26

2T35
3T23

IT29

3T06

FC73

2G19

7T04

3FLJ

IT25

2T20

2T43

2G18

FT00

2G12

2T26
2T27

IT04

3T13
2T34
3T09 3T15
3T19 3T16
3T18

2T07

IT30

FT04

IT23

FC74

FC75

FC84

FL31

FC77
IT22

3T08

IT10

3T10

IT03

FL30

FL39

FC83

2T15 2T16

IT12

6T03

IT09

IT11

3T25
3T28
3T26
2T42

FT07

2K13

IK13

FC81

3T11

6T04

5T02

FT08

2T41

7T01

2T09

IT20

2T06
3T03

6T02

7T02

IT24

6K03

3K10

6T00

2T10 2T36

2T39
6T01 2T08

2T05

2T04

3T02

3T00 3T21

FT06

IT18

3T01
IT02

3K00

IK08

3T05

IK00

IK12

6T05

CK00

IT19

2T03

2K14

3K11

IT00

2T02

IT01

3K12

IK09

3T04

IK01

3K06

6K04

3K05

3K13

7K00

2K04

IK05

2T13

7K02

2K01

IK07

2T25

2K10

3K07

IK06

2T21

IK11

IK04

2K03

6K00

3K04

2K06

2K07

2K08

CK01

3K08

IK14

7K03

IK10

3K03

2K16

2K02

IK03

3K02

2K05

3K01

IK02

7K01

LAYOUT
SPB SSB
TV550 2K11 4DDR EU SD

2011-05-09

3104 313 6539


19051_046_110704.eps
110704

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 185

10-25 FB01 820400091952


DC/DC converters

FB01A DC/DC converters

FB01A
+3V3
5U54

IU64

+12V

GND-1V5

CU06

IU31

GND-1V5

22u

22u
2U78

2U77

1M0

22K 1%

3U82 RES

3U77

GND-1V5

GND-1V5

GND-1V5

220K 1%

82K
3U49

RES

GND-1V5
7U75-2
RT8293AHGSP

3U50

IU24

3U39

+1V5

22K 1%

FU55

GND-AL

3n3

2U33

10n

1n0
2U81

2U30
+2V5
GND-1V5

NC
GND
GND HS

GND-AL

IU78

COMP
GND
GND HS

PGOOD

FB

1% 470K
2U90
IU84
1n0

22
23
24
25
26

ENABLE+3V3

100n

2U69

22u

2U75

3U35 DBG

330R

1n0

SS

100p

ADJ

1K8

3U11

RES 2U34

EN

220K
3U75

IU76

ENABLE+1V5

7U10-1
RT9025-12GSP
6

3U17
3R3

5K6

VOUT

3U16

100n

IU77

VIN

1n0

2U35

FU58

SW

IU30

2U79

3U14

ENABLE+2V5

10K

1n0

2U07

RES

EN

4
3

+3V3
3U09

BOOT

10u

B230LA-M3

VDD

10u

6U05 RES

+3V3

1u0

2U71

2U89

6U15

IU62

9U10

VIN

FU57 +5V

BZX384-C5V1

4K7

3U84

RES

FU54

2041145-4

1K0

3U10

1MB9 RES
1
2
3
4

2U53

6.3V 100u

IU61
GND-AL
GND-AL

IU75
2

RES 2U29

4K7

6
4K7

4 3U15-4 5

4K7
3U15-3
3

4K7

2 3U15-2 7

+12V

1 3U15-1 8

6U10 RES

+5V
2UJ9

FU75

7U75-1
RT8293AHGSP

7
BZX384-C6V2

FU53

+12V

5U75

+1V5

+12V

1n0

2U06

2041145-4

+12V-ALIN

FU56

FU52

6U09

RES

1M09
1
2
3
4

IU25

3u6

LTST-C190CKT

DBG

22u

22u
2UJ6

22u
2UJ7

2UJ8

30R

VIA
3U51

18
19
20
21

22K

VIA

10
11
12
13

VIA

VIA

1
2
3

10R

470R

470R

3U73-4 RES

470R
3U73-3 RES

470R

3U73-2 RES

3U73-1 RES

VIA

470R

VIA

470R

7U05
SI4778DY-GE3

3U72-4 RES

IU67

3U37

470R

IU66

10
11
12
13

3U72-3 RES

5
6
7
8

10u

18
19
20
21

470R
3U72-2 RES

+3V3

2U68

10u

10u
2U58

2U57

30R

7U10-2
RT9025-12GSP

IU63

3U72-1 RES

5U53
+12V

22
23
24
25
26

14
15
16
17

VIA

VIA

+12V-ALIN
RES
2UJ1

GND-AL
FU77

2UH6

1n0

GND-AL

14
15
16
17

GND-AL

1
2
3
4
5
6
7
8
9
10

3R3

3U02

1M99

IU29
1n0

47R

47R

4 3U83-4 5

47R
3 3U83-3 6

47R

2 3U83-2 7

7U06
SI4778DY-GE3

5U55

100n

5U76

FU76
+3V3
2U84

10u

22u

IU26
22u
2U85

2U70

1n0
2UH9

22u

1n0
2UH8

2U82

10u

2UJ0

30R

7U51
TPS53114APW

IU65

+12V

1
2
3

6U01

5
6
7
8
IU70

1n0

2UJ2

GND-AL

1-2041145-0

B230LA-M3

+12VD

1 3U83-1 8

FU78

VIN

GND-1V05

10R
2U64

3U81 RES

1M0

22K 1%

3U80

2U31

9
CU05

IU28
GND-3V3

7U76-2
RT8293AHGSP

VIA
GND-3V3

GND-3V3

1u0
IU68

GND-3V3
GND-3V3
GND-1V05

+3V3

68K 1%

22
23
24
25
26

GND-3V3

3U78
IU82

100p

ENABLE+3V3

FB

COMP
GND
GND HS

RES 2U32

3U60 RES

3R3

3n3

22u

22u

2U59

2U60

SENSE+1V05

10R
+1V05

470K

3U12

13K

22K 1%

470K

3U58

100n

3U59

IU27

100n

3U13

1% 8K2
RES 3U55

SW

SS

4
22p
3U56

IU58

2U61

1X10
REF EMC HOLE

IU83

10n

RES 2U74
IU57

IU01

EN

2U86

IU80
8

10

BOOT

18
19
20
21

VIA

VIA

10
11
12
13

GND-3V3
VIA

GND-1V05

14
15
16
17

1X12
REF EMC HOLE

VIN

IU81

2U87

+1V05

GND-1V05

GND-1V05
GND-1V05

3R3

2UH7
1
2

2u0

1n0

VREG5

10n

2U05

V5FILT

IU79

FU51
+1V05

IU69

3U08

VO
VFB

FSEL

14

3U57

2U63

1u0

SS
CER

5U51

10u

18K

GND-1V05

7U76-1
RT8293AHGSP

2UH5

SW
TRIP

PGND

5
IU60

3U03 1%

1n0

2UD1

IU45

15
13
IU56

12

11

ENABLE+1V05

DRVH
DRVL

EN

GND

VBST

16

Bolt-On 1
DC/DC

2011-05-12

2011-03-16

8204 000 9195


19051_069_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 186

Ambilight connectors

FB01B Ambilight connectors

FB01B

1M84

1M83

9U01-1
9U01-2
9U01-3
9U01-4

IU13
IU12

SPI-DATA-RETURN
SPI-DATA
CHIP-SELECT
PWM-CLOCK
BLANK
TEMP-SENSOR

+12V-AL

IU02
RES
RES
RES
RES

20

IU14

SPI-CLOCK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

19

GND+3V3-AL

GND-AL

IU09
IU11
IU06
IU04
IU08
IU05

LATCH
PROG

GND-AL
IU07
IU18

+3V3-AL
9U03

GND-AL
IU03
9U02-4
9U02-3
9U02-2
9U02-1

RES
RES
RES
RES

+12V-AL

IU15

18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND-AL
FH34SRJ-18S-0.5SH(50)

TEMP-SENSOR
PROG
BLANK

1M85

+3V3-AL-IN

LATCH
CHIP-SELECT

GND+3V3-AL

GND+3V3-AL-IN

GND-AL
PWM-CLOCK

+3V3-AL-IN
SPI-DATA-RETURN
SPI-DATA
IU10

GND+3V3-AL-IN
SPI-CLOCK

28 27

GND-AL

FH34SRJ-26S-0.5SH(50)
GND-AL

GND+3V3-AL-IN

9U07

IU17

IU19

10u 35V

19

+12V-AL
1u0
2UJ5 RES

2.0A 63V

+3V3-AL

RES

9U06 RES

2UJ4

+12V-AL

9U05

1u0

1U01

+12V-ALIN

+3V3

IU16

2UJ3 RES

+3V3-AL-IN

+3V3-AL
9U04

20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

FH34SRJ-18S-0.5SH(50)

GND+3V3-AL

9U08 RES

9U09 RES

GND-AL

Bolt-On 1
DC/DC

2011-05-12

2011-03-16

8204 000 9195


19051_070_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 187

10-26 FB02 820400091962


FPGA - I/O Banks

FB02A FPGA - I/O Banks

FB02A
7T00-1
XC6SLX9-2FTG256C0100

7T00-6
XC6SLX9-2FTG256C0100

POWER
G7
G9
H10
H8
J7
J9
K10
K8

B5
A5
D5
C5

VCCAUX

B13
B4
B9
D10
D7

VCCO0

VCCO_1

N10
N7
R4
R8

VCCO2

A1
A16
B11
B7
D13
D4
E9
G15
G2
G8
H12
H7
H9
J5
J8
K7
K9
L15
L2
M8
N13
P3
R10
R6
T1
T16

B6
A6
F7
E6

BL-DIM10
BL-DIM12

C7
A7
D6
C6
B8
A8
C9
A9
B10
A10

BANK2

IO_L1P_HSWAPEN_0
IO_L1N_VREF_0

IO_L36P_GCLK15_0
IO_L36N_GCLK14_0

IO_L2P_0
IO_L2N_0

IO_L37P_GCLK13_0
IO_L37N_GCLK12_0
IO_L38P_0
IO_L38N_VREF_0

IO_L3P_0
IO_L3N_0
IO_L4P_0
IO_L4N_0

IO_L39P_0
IO_L39N_0

IO_L5P_0
IO_L5N_0

IO_L40P_0
IO_L40N_0
IO_L62P_0
IO_L62N_VREF_0

IO_L6P_0
IO_L6N_0
IO_L7P_0
IO_L7N_0

IO_L63P_SCP7_0
IO_L63N_SCP6_0

IO_L33P_0
IO_L33N_0

IO_L64P_SCP5_0
IO_L64N_SCP4_0
IO_L65P_SCP3_0
IO_L65N_SCP2_0

IO_L34P_GCLK19_0
IO_L34N_GCLK18_0

IO_L66P_SCP1_0
IO_L66N_SCP0_0

IO_L35P_GCLK17_0
IO_L35N_GCLK16_0

E7
E8

BL-DIM11
BL-DIM7

E10
C10

BL-SPI-CSn-OUT
BL-SPI-CLK-OUT

D8
C8

BL-DIM8
BL-DIM9

C11
A11

3T06

CCLK

BL-DIM5
BL-DIM6

R11
T11

IT00
FPGA-TX1-A+
FPGA-TX1-A-

M12
M11

MISO
MOSI

P10
T10

FPGA-RESET-SYS
3D-LR-DISP

F9
D9

10R

10R

3T12

3T08

100R

N12
P12

9T02
BL-DIM

N11
P11

FT30

B12
A12

FPGA-TX1-CLK+
FPGA-TX1-CLK-

N9
P9

C13
A13

FPGA-TX1-C+
FPGA-TX1-C-

R9
T9

FPGA-TX1-B+
FPGA-TX1-B-

L10
M10

F10
E11

BL-SPI-SDO-OUT
BL-SPI-CLK

B14
A14

FPGA-SYS-CLK

D11
D12

M9
N8

IO_L1P_CCLK_2
IO_L1N_M0_CMPMISO_2

IO_L3P_D0_DIN_MISO_MISO1_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2

IO_L14P_D11_2
IO_L14N_D12_2
IO_L23P_2
IO_L23N_2
IO_L16P_2
IO_L16N_VREF_2
IO_L29P_GCLK3_2
IO_L29N_GCLK2_2

FT98

B15
B16

3T68
100R

10K

10K
100R
100R
100R
100R

FT01
FT02
FT03
FT04

JTAG

VAUX

A15

1
2
3
4
5
6

F13
F14

7T00-5
XC6SLX9-2FTG256C0100

E14
P14

C15
C16

SPLASH-ON

TCK

F12
G11
D14
D16

CTRL-DISP
CTRL-DISPIN

C12

DBG
1T00

2T02

IO_L64P_D8_2
IO_L64N_D9_2
IO_L65P_INIT_B_2
IO_L65N_CSO_B_2

FPGA-TX1-E+
FPGA-TX1-E-

P6
T6

FPGA-RESET-SYS
FPGA-LED-1

R5
T5

FPGA-TX2-CLK+
FPGA-TX2-CLK-

N5
P5

FPGA-TX2-D+
FPGA-TX2-D-

L8
L7

FPGA-TX2-A+
FPGA-TX2-A-

P4
T4

FPGA-TX2-E+
FPGA-TX2-E-

M6
N6

FPGA-TX2-C+
FPGA-TX2-C-

R3
T3

IT22
10R

T2
L11
P13

FT8S

100n
3T07

2T01
RES

CSO-B
PROG-B
DONE

1K0

3T05

DONE

VCCO2

RESET-FRCn

7T00-4
XC6SLX9-2FTG256C0100

BANK3

E15
E16

TDI
TMS

F15
F16

TDO
SUSPEND

G14
G16

AUDIO-SPEAKERn
RESET-FRCn

H15
H16

SD51022

3D-VS
3D-LED-S6

FT31

G12
H11
H13
H14

IO_L1P_A25_1
IO_L1N_A24_VREF_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1

3T04

IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L41N_GCLK8_M1CASN_1

IO_L30P_A21_M1RESET_1
IO_L42P_GCLK7_M1UDM_1
IO_L30N_A20_M1A11_1 IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1

IO_L43P_GCLK5_M1DQ4_1
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L44N_A2_M1DQ7_1
IO_L45P_A1_M1LDQS_1
IO_L45N_A0_M1LDQSN_1

IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1

IO_L46P_FCS_B_M1DQ2_1
IO_L46N_FOE_B_M1DQ3_1

IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1

IO_L47P_FWE_B_M1DQ0_1
IO_L47N_LDC_M1DQ1_1

IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1

IO_L48P_HDC_M1DQ8_1
IO_L48N_M1DQ9_1

IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
IO_L38N_A4_M1CLKN_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1

IO_L49P_M1DQ10_1
IO_L49N_M1DQ11_1
IO_L50P_M1UDQS_1
IO_L50N_M1UDQSN_1
IO_L51P_M1DQ12_1
IO_L51N_M1DQ13_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L53P_1
IO_L53N_VREF_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1

J11
J12

FPGA-RX2-CLK+
FPGA-RX2-CLK-

FPGA-DDR2-VREF

1%

2T00

100R

M5
N4

FPGA-DDR2-ZIO
IT06

J13
K14
K12
K11

FPGA-RX1-CLK+
FPGA-RX1-CLK-

K15
K16

FPGA-RX2-E+
FPGA-RX2-E-

N14
N16

FPGA-RX1-E+
FPGA-RX1-E-

M15
M16

FPGA-RX2-B+
FPGA-RX2-B-

L14
L16

FPGA-RX2-D+
FPGA-RX2-D-

P15
P16

FPGA-RX1-D+
FPGA-RX1-D-

R15
R16

FPGA-RX1-C+
FPGA-RX1-C-

R14
T15

FPGA-RX1-B+
FPGA-RX1-B-

T14
T13

FPGA-RX1-A+
FPGA-RX1-A-

R12 10R
T12 10R

DT72 R2
R1

FPGA-DDR2-DQ13
FPGA-DDR2-DQ10

P2
P1

FPGA-DDR2-DQ8
FPGA-DDR2-DQ15

J14
J16

3T29
3T30

SCL-SSB
SDA-SSB

L12
L13

FPGA-RX2-C+
FPGA-RX2-C-

M13
M14

FPGA-RX2-A+
FPGA-RX2-A-

FPGA-DDR2-UDQS-P
FPGA-DDR2-UDQS-N

1X11
REF EMC HOLE

1X14
REF EMC HOLE

M4
M3

100n

DT73
DT74

N3
N1

FPGA-DDR2-DQ14
FPGA-DDR2-DQ11

M2
M1

FPGA-DDR2-DQ12
FPGA-DDR2-DQ9

L3
L1

FPGA-DDR2-DQ0
FPGA-DDR2-DQ7

K2
K1

FPGA-DDR2-DQ2
FPGA-DDR2-DQ5

J3
J1

FPGA-DDR2-LDQS-P
FPGA-DDR2-LDQS-N

DT75 H2
H1

DT76

G3
G1

FPGA-DDR2-DQ1
FPGA-DDR2-DQ6
FPGA-DDR2-DQ4
FPGA-DDR2-DQ3

DT77

F2
F1
K3
J4

FPGA-DDR2-UDM
FPGA-DDR2-LDM

IO_L1P_3
IO_L1N_VREF_3

IO_L43P_GCLK23_M3RASN_3
IO_L43N_GCLK22_IRDY2_M3CASN_3

IO_L2P_3
IO_L2N_3

IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3

IO_L32P_M3DQ14_3
IO_L32N_M3DQ15_3

IO_L45P_M3A3_3
IO_L45N_M3ODT_3

IO_L33P_M3DQ12_3
IO_L33N_M3DQ13_3

IO_L46P_M3CLK_3
IO_L46N_M3CLKN_3

IO_L34P_M3UDQS_3
IO_L34N_M3UDQSN_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L36P_M3DQ8_3
IO_L36N_M3DQ9_3
IO_L37P_M3DQ0_3
IO_L37N_M3DQ1_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L39P_M3LDQS_3
IO_L39N_M3LDQSN_3
IO_L40P_M3DQ6_3
IO_L40N_M3DQ7_3
IO_L41P_GCLK27_M3DQ4_3
IO_L41N_GCLK26_M3DQ5_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L42N_GCLK24_M3LDM_3

IO_L47P_M3A0_3
IO_L47N_M3A1_3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L49P_M3A7_3
IO_L49N_M3A2_3
IO_L50P_M3WE_3
IO_L50N_M3BA2_3
IO_L51P_M3A10_3
IO_L51N_M3A4_3
IO_L52P_M3A8_3
IO_L52N_M3A9_3
IO_L53P_M3CKE_3
IO_L53N_M3A12_3
IO_L54P_M3RESET_3
IO_L54N_M3A11_3
IO_L55P_M3A13_3
IO_L55N_M3A14_3
IO_L83P_3
IO_L83N_VREF_3

DT81

1X13
REF EMC HOLE

IT23

J6
H5

FPGA-DDR2-RAS-N
FPGA-DDR2-CAS-N

H4
H3

FPGA-DDR2-A5
FPGA-DDR2-A6

L4
L5

FPGA-DDR2-A3
FPGA-DDR2-ODT

E2
E1

FPGA-DDR2-CLK-P
FPGA-DDR2-CLK-N

K5
K6

FPGA-DDR2-A0
FPGA-DDR2-A1

C3
C2

FPGA-DDR2-BA0
FPGA-DDR2-BA1

D3
D1

FPGA-DDR2-A7
FPGA-DDR2-A2

C1
B1

FPGA-DDR2-WE-N
FPGA-DDR2-BA2

G6
G5

FPGA-DDR2-A10
FPGA-DDR2-A4

B2
A2

FPGA-DDR2-A8
FPGA-DDR2-A9

F4
F3

FPGA-DDR2-CKE
FPGA-DDR2-A12

E4
E3

FPGA-DDR2-RESET-N
FPGA-DDR2-A11

DT82

FPGA-DDR2-CKE

4K7

3T00

FPGA-DDR2-RESET-N

4K7

3T01

FPGA-DDR2-CS-N

4K7

3T02

F6
F5
B3
A3

FPGA-DDR2-CS-N
FPGA-DDR2-VREF
2T68

3D-LR-FPGA-FRC

3T11

3T10
DBG
1T01

100n DBG

IO_L63P_2
IO_L63N_2

FPGA-TX2-B+
FPGA-TX2-B-

R7
T7

3T69

C14

IO_L62P_D5_2
IO_L62N_D6_2

P7
M7

100R
RES

IT02

IO_L49P_D3_2
IO_L49N_D4_2

FPGA-TX1-D+
FPGA-TX1-D-

VCCO_3

3D-LR

3T09-1
3T09-2
3T09-3
3T09-4
FT00

IO_L48P_D7_2
IO_L48N_RDWR_B_VREF_2

P8
T8

FT06

VAUX

1
2
3
4

IO_L47P_2
IO_L47N_2

IO_L13P_M1_2
IO_L13N_D10_2

BL-SPI-CSn
BL-SPI-SDO

BANK1

8
7
6
5

IO_L32P_GCLK29_2
IO_L32N_GCLK28_2

PROGRAM_B_2
CMPCS_B_2
DONE_2

E13
E12

DBG
DBG
DBG
DBG

IO_L31P_GCLK31_D14_2
IO_L31N_GCLK30_D15_2

IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2

7T00-2
XC6SLX9-2FTG256C0100

1
2
3
4
5
6

IO_L30P_GCLK1_D13_2
IO_L30N_GCLK0_USERCCLK_2

VCCO_2

D2
G4
J2
K4
N2

+1V8-FPGA

GND

VCCO_0

D15
G13
J15
K13
N15
R13

VCCO1

C4
A4

VCCINT

E5
F11
F8
G10
H6
J10
L6
L9

VAUX

9T01
RES

LCD-PWR-ON-FPGAn

100n

+1V2-FPGA

7T00-3
XC6SLX9-2FTG256C0100

BANK0

DT83

1X15
REF EMC HOLE

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_071_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 188

FPGA -Supply & Control

FB02B FPGA - Supply & Control

RES

4K7

LCD-PWR-ONn

VAUX

NC

+5V

+1V8-FPGA
IT05

100n

4K7

3T41
22n

2T84

100K

330p
3T45

RES

SENSE+1V2

1K0

100n

2T91

2T83

1K0

VALUE

3T03

CPLD-SYS-CLK

IT17

3T44

IT18

RES 3T46
1

47R

2T55

220n

2T28

220n

220n
2T27

220n
2T26

220n
2T25

2T24

2u2

3T16

FPGA-SYS-CLK

FT09
+1V8-FPGA

RES 3T43
100K

7T03
3225

IT47

2K2
RES
2T92

SENSE+1V2

3T70

7T17
BC847BW

CT10

+3V3

2T23

NC

220n

2u2
2T21

220n
2T20

220n
2T19

22u
2T18

22u

RES 2T17

22u
2T16

100n
2T15

IT45

1
4K7

REF

2T14

7T16
TS431AILT
3

IT46

+1V2-FPGA

+1V2-FPGA

+1V2-FPGA
RES 2T81

2u2
2T12

2u2
2T11

220n
2T10

220n
2T09

220n
2T08

220n
2T07

2u2

FT08

3T42

30R
RES

220n
2T06

5T01
+3V3

2u2
2T05

RES 2T04

30R

47K

+2V5

7T15
PHD38N02LT

IT16

22R
+12V

10u

9T15 RES

1u0
RES 2T36

LCD-PWR-ON-FPGAn

100n
3T71

FT07

1u0

9T14

LCD-PWR-ON-FRCn

3T40
5T00

10u
2T80

2T37

1u0
2T82

3T86

+3V3

FB02B

+1V5

7T18 RES
PDTC114EU

47R
3T21 RES

FRC-SYS-CLK

47R
VCCO2

VCCO1

+3V3

470R

MOSI
CCLK
CSO-B

FT15
FT16

DBG
3T39
6T09
DBG

IT04
Q

+1V8-FPGA

DBG

3T58
10K

7T10 DBG
BC847BW

7T13 DBG
BC847BW

S
HOLD

+3V3

W
GND

PROGRAMMING
ENGINEERING

DBG 3T49

502382-0670

FT05
3T59
+1V2-FPGA
10K

6
1
3
7

D
C

7T11 DBG
BC847BW

7T12
M25P32-VMW6TG
VCC
2
Q

+1V5

3T50

32M
FLASH

DBG
4K7

7T14 DBG
BC847BW

S
W
HOLD
VSS
4

DBG

6T11

+3V3

6SLX9-4MB-M25P40
6SLX16-4MB-M25P40
6SLX25-8MB-M25P80 ---16MB-M25P16 --- 32MB-M25P32

LTST-C190KGKT

DBG

330R

DBG

DBG
3T57
6T10 DBG

DBG
6T02

100n

10R

3T35

3T15

2T54
5

+1V05

1K0

VCC

330R

CCLK
CSO-B
MOSI
MISO
PROG-B

7T02
M25P40-VMN6

LTST-C190KGKT

1
2
3
4
5
6

FT14

DBG

1T02

4K7 RES

3T14

FT13

3T56

+3V3

6T03 DBG

DBG
3T38

MISO

30R

330R

220n

220n
2T52

220n
2T51

220n
2T50

220n
2T49

2u2
2T48

2T47

2u2

2T46

5T07

+3V3

+3V3

LTST-C190KGKT

+3V3

330R

VCCO0

30R RES

330R

+3V3

LTST-C190KGKT

+2V5

DBG

LTST-C190KGKT

220n

100n
2T45

2T44

220n

100n
2T43

220n
2T42

100n
2T41

2T40

2u2

2T39

FT12

DBG 3T13

LTST-C190KGKT
7T01
PDTC144EU
2 DBG

DONE

5T06

+3V3

+1V8-FPGA

2T13

6T00

30R

FT29

100n
2u2

5T05
+3V3

OUT
COM

RES
2T38

30R

IN

+3V3

2T22

FT11

+2V5

7T09
LD1117DT18
3

22u 16V

5T04

6T01

DBG

30R

3T17

100n

220n
2T35

220n
2T34

220n
2T33

2u2
2T32

2T31

2u2

2T30

5T03
+3V3

DBG

FPGA-LED-1

330R

FT10

30R RES

LTST-C190KGKT

5T02
+2V5

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_072_110706.eps
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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 189

FPGA - DDR

FB02C FPGA - DDR

FB02C

DT64
L2
L3

FPGA-DDR2-BA0
FPGA-DDR2-BA1
DT65

FPGA-DDR2-A0
FPGA-DDR2-A1
FPGA-DDR2-A2
FPGA-DDR2-A3
FPGA-DDR2-A4
FPGA-DDR2-A5
FPGA-DDR2-A6
FPGA-DDR2-A7
FPGA-DDR2-A8
FPGA-DDR2-A9
FPGA-DDR2-A10
FPGA-DDR2-A11
FPGA-DDR2-A12

DT66
DT67

M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
J8
K8

FPGA-DDR2-CLK-P
FPGA-DDR2-CLK-N

SDRAM
NC

0
BA
1
0
1
2
3
4
5
6 A
7
8
9
10
11
12

DQ

CK

UDM
LDM

FPGA-DDR2-UDQS-P
FPGA-DDR2-UDQS-N

3T22

3T23

33R
33R

DT70 B7
DT71 A8

LDQS

VREF

UDQS
VSS
A3
E3
J3
N1
P9

DT55

DT56

DT57

DT58

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
B3
F3

1K0 1%

FPGA-DDR2-BA2

7
3T24-3

3T24-2

3T25-3

3T25-1

3T28-4

DT54

3T28-1

3T27-1

3T27-4

DT60
3T51

5
1
4
6
7
6
7

33R

3T52

J2

6
33R
7
33R
3
33R
1
33R
4
33R
1
33R
1
33R
4
33R

2 3T25-2
33R
4 3T25-4
33R
8 3T24-1
33R
5 3T24-4
33R
3 3T27-3
33R
2 3T27-2
33R
3 3T28-3
33R
2 3T28-2
33R

FPGA-DDR2-DQ0
FPGA-DDR2-DQ1
FPGA-DDR2-DQ2
FPGA-DDR2-DQ3
FPGA-DDR2-DQ4
FPGA-DDR2-DQ5
FPGA-DDR2-DQ6
FPGA-DDR2-DQ7
FPGA-DDR2-DQ8
FPGA-DDR2-DQ9
FPGA-DDR2-DQ10
FPGA-DDR2-DQ11
FPGA-DDR2-DQ12
FPGA-DDR2-DQ13
FPGA-DDR2-DQ14
FPGA-DDR2-DQ15
FPGA-DDR2-UDM
FPGA-DDR2-LDM

33R
FPGA-DDR2-VREF
2T67

VSSDL

33R
33R

J7

3T54

DT68 F7
DT69 E8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A2
E2
L1
R3
R7
R8

100n
VSSQ
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

150R

FPGA-DDR2-LDQS-P
FPGA-DDR2-LDQS-N

3T18
VDDQ

3T20
3T53

1u0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

J1

A1
E1
J9
M9
R1

2T03
DT62
DT63

VDD
ODT
CKE
WE
CS
RAS
CAS

VDDL

K9
K2
K3
L8
K7
L7

DT61

1K0 1%

100n

100n
2T65

100n
2T64

100n
2T63

100n
2T62

2T60

100n
2T61

FPGA-DDR2-VREF

7T04
H5PS5162GFR-S5C
FPGA-DDR2-ODT
FPGA-DDR2-CKE
FPGA-DDR2-WE-N
FPGA-DDR2-CS-N
FPGA-DDR2-RAS-N
FPGA-DDR2-CAS-N

3T19

22u

2T66

1u0

220u 2.5V
2T59

+1V8-FPGA

FT17
100n

100n
2T57-4

100n
2T57-3

100n
2T57-2

100n
2T57-1

100n
2T56-4

100n
2T56-3

100n
2T56-2
2

2T56-1

RES
2T58

+1V8-FPGA

DT59

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_073_110706.eps
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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 190

Output LVDS FPGA

FB02D Output LVDS FPGA

100p

100p

DBG
1T61
FI-RE51S-HF

RES 2TH9

RES 2TH8

100p

10p
2TH6

RES 2TH7

RES

1n0

10p
2TH5

RES 2TH4

RES

10n

1n0
RES 2TH3

100p

RES 2TH2

RES 2TH1

2TH0

RES

100p

FB02D

RES
100R

CTRL-DISP
SDA-DISP
SCL-DISP

3T60
47R

3T61
RES

3D-LR
3D-VS
CTRL-DISP
FPGA-TX1-AFPGA-TX1-A+
FPGA-TX1-BFPGA-TX1-B+
FPGA-TX1-CFPGA-TX1-C+

RES 100R

FT26
FT27

100R

3T66

IT60
IT61
IT62

3T62
RES

RES
100R

CTRL-DISP

47R

3T63
3T64
100R
RES

IT68
IT69

3T65

FTG0

IT63

RES

FTF7
FTF8

FTF9
FTFA
FTFB
FTFC
FTFE

FPGA-TX1-CLKFPGA-TX1-CLK+

FTFF
FTFH

FPGA-TX1-DFPGA-TX1-D+
FPGA-TX1-EFPGA-TX1-E+

FTFJ
FTFK
FTFL
10p

FPGA-TX2-AFPGA-TX2-A+
FPGA-TX2-BFPGA-TX2-B+
FPGA-TX2-CFPGA-TX2-C+

FPGA-TX2-DFPGA-TX2-D+
FPGA-TX2-EFPGA-TX2-E+

FTFN
FTFQ
FTFR
FTFS
FTFT
FTFU
FTFV
FTFW
FTFY
FTFZ

+VDISP

2THA
10p

FTFP

FPGA-TX2-CLKFPGA-TX2-CLK+

IT64

RES
2THB

FTFM

9T22
RES

IT66

RES

IT65

60 61
58 59
56 57
54 55
52 53
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

TO DISPLAY

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 191

Output - Vdisp

FB02E Output - Vdisp

FB02E

1
2
3
4
1
2
3
4

9T10-1
RES
9T10-2
RES
9T10-3
RES
9T10-4
RES
9T11-1
RES
9T11-2
RES
9T11-3
RES
9T11-4
RES

7T05
SI4835DDY
RES

8
7
6
5
8
7
6
FT18

FT19

1T10

+VDISP

7T06
SI3443CDV

T 3.0A 32V

LCD-PWR-ONn

RES
7T19
PDTC114EU

+2V5

47R
3T36
82K

RES
2T69
IT12

2T70
IT11

1u0

IT10

100n
RES

2T72

22u

2T71

100n
3T34

7T07-1
PUMD12
1

DBG
4K7

22K

RES
3T32

3TS8

IT13
IT15

4
PUMD12
7T07-2

22K
RES

22n

3T37

4K7

3T33

2T73

RES

3T31

+3V3

47R

+12VD

IT14

6T04

DBG

LTST-C190KGKT

VDISP-SWITCH
3
IT01

1
2
7T21
PDTC114EU

1
2

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 192

FPGA - Bypass

FB02F

FPGA - Bypass

FB02F

FPGA-RX1-A+
FPGA-RX1-AFPGA-RX1-B+
FPGA-RX1-BFPGA-RX1-C+
FPGA-RX1-CFPGA-RX1-CLK+
FPGA-RX1-CLKFPGA-RX1-D+
FPGA-RX1-DFPGA-RX1-E+
FPGA-RX1-E-

2
1
4
3
2
1
4
3
2
1
4
3

9T36-2
9T36-1
9T36-4
9T36-3
9T37-2
9T37-1
9T37-4
9T37-3
9T38-2
9T38-1
9T38-4
9T38-3

7
8
5
6
7
8
5
6
7
8
5
6

2
1
4
3
2
1
4
3
2
1
4
3

9T30-2
9T30-1
9T30-4
9T30-3
9T31-2
9T31-1
9T31-4
9T31-3
9T32-2
9T32-1
9T32-4
9T32-3

7
8
5
6
7
8
5
6
7
8
5
6

FPGA-TX1-A+
FPGA-TX1-AFPGA-TX1-B+
FPGA-TX1-BFPGA-TX1-C+
FPGA-TX1-CFPGA-TX1-CLK+
FPGA-TX1-CLKFPGA-TX1-D+
FPGA-TX1-DFPGA-TX1-E+
FPGA-TX1-E-

FPGA-RX2-A+
FPGA-RX2-AFPGA-RX2-B+
FPGA-RX2-BFPGA-RX2-C+
FPGA-RX2-CFPGA-RX2-CLK+
FPGA-RX2-CLKFPGA-RX2-D+
FPGA-RX2-DFPGA-RX2-E+
FPGA-RX2-E-

2
1
4
3
2
1
4
3
2
1
4
3

9T40-2
9T40-1
9T40-4
9T40-3
9T41-2
9T41-1
9T41-4
9T41-3
9T42-2
9T42-1
9T42-4
9T42-3

7
8
5
6
7
8
5
6
7
8
5
6

2
1
4
3
2
1
4
3
2
1
4
3

9T33-2
9T33-1
9T33-4
9T33-3
9T34-2
9T34-1
9T34-4
9T34-3
9T35-2
9T35-1
9T35-4
9T35-3

7
8
5
6
7
8
5
6
7
8
5
6

FPGA-TX2-A+
FPGA-TX2-AFPGA-TX2-B+
FPGA-TX2-BFPGA-TX2-C+
FPGA-TX2-CFPGA-TX2-CLK+
FPGA-TX2-CLKFPGA-TX2-D+
FPGA-TX2-DFPGA-TX2-E+
FPGA-TX2-E-

Bolt-On 1
FPGA-FRC

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 193

FPGA - Backlight dimming

FB02G FPGA - Backlight dimming

FB02G

100n

100n
2TCA

100n
2TC9

100n
2TC8

1u0
2TC7

1u0
2TC6

RES
2TC3

10u

1u0
2TC5

77
78

BL-DIM12
BL-DIM11

83
84

CPLD-SYS-CLK
BL-DIM9

5T08

FT20

BL-DIM8
BL-DIM7

85
86

BL-DIM6
BL-DIM5

88
89

VCCA-O

+3V3
100n

100n
2TCN

100n
2TCM

100n
2TCL

100n
2TCK

100n
2TCH

100n
2TCG

100n
2TCF

100n
2TCE

2TCD

1u0

RES
2TCB

1u0
RES
2TCC

30R

IT80

90
93

IT83
IT84

94

IT91
3TCE

98
99

RES
1K0

97
82

56
57

3D-LED-S3A
DBG 3TCB

59
60

SPLASH-ON

+3V3

470R

LTST-C190KGKT

DBG

RESET-FRCn
VCCA-O

+3V3

RES
3T67

RESET-FRCn

100R

VCCA-O

3
7

100n

512K
FLASH

10R

FT87

SP3A-MISO

DT32
DT33

70
71

DT34

72
73
68
54

SP3A-DONE
FT90

DBG
1T06
1
2
3
4
5
6

W
HOLD

64
65

SP3A-PROG-B

VSS

1K0

3TC9

2TCP

RES

3TCD

DT30
DT31

DBG 3T47-1
DBG 3T47-2
DBG 3T47-3
DBG 3T47-4
FT25

7TC2
M25P05-AVMN6
FT92

FT91

DBG
1T05
1
2
3
4

8
7
6
5

100R
100R
100R
100R

1
2
3
4
5
6

+3V3

100
1
2
75
76

FT21
FT22
FT23
FT24

IO_L02P_2|M2
IO_L02N_2|CSO_B

BANK0

IO_L02P_0|GCLK4
IO_L02N_0|GCLK5

IO_L03P_2|RDWR_B
IO_L03N_2|VS1

BANK2

IO_L04P_2|VS2
IO_L04N_2|VS0

IO_L03P_0|GCLK6
IO_L03N_0|GCLK7

IO_L05P_2
IO_L05N_2|D7

IO_L04P_0|GCLK8
IO_L04N_0|GCLK9

IO_L06P_2
IO_L06N_2|D6

IO_0|GCLK11
IO_L05P_0

IO_L07P_2|D5
IO_L07N_2|D4

IO_L05N_0
IO_L06P_0|VREF_0
IO_L06N_0|PUDC_B

IO_L08P_2|GCLK14
IO_L08N_2|GCLK15

IP_0

IO_L09P_2|GCLK0
IO_L09N_2|GCLK1

IP_0|VREF_0
IO_L10P_2|INIT_B
IO_L10N_2|D3
IO_L01P_1
IO_L01N_1

BANK1

IO_L02P_1|RHCLK0
IO_L02N_1|RHCLK1

IO_L11P_2|D2
IO_L11N_2|D0|DIN|MISO
IO_L12P_2|D1
IO_L12N_2|CCLK

IO_L03P_1|RHCLK2
IO_L03N_1|TRDY1|RHCLK3
IO_L04P_1|IRDY1|RHCLK6
IO_L04N_1|RHCLK7

IP_2|VREF_2
IO_2|MOSI|CSI_B

IO_L01P_3
IO_L01N_3

BANK3

IP_1|VREF_1

IO_L02P_3
IO_L02N_3

IO_L03P_3|LHCLK0
IO_L03N_3|LHCLK1

DONE
IO_L04P_3|LHCLK2
IO_L04N_3|IRDY2|LHCLK3

PROG_B
TMS
TDI
TDO
TCK

IO_L05P_3|TRDY2|LHCLK6
IO_L05N_3|LHCLK7
IO_L06P_3
IO_L06N_3

+3V3
IP_3|VREF_3

SD51022

1K0

1K0

23
25
24
27

3TC5

28
30

3TCF

29
31

3TC7
3TCG

32
34

10R

RES
1K0
RES
1K0
1K0 RES

33
35

SP3A-CSO-B

BL-SPI-CLK-OUT
BL-SPI-CSn-OUT
BL-SPI-SDO-OUT

36
37
40
41
43
44

SP3A-LED-4

48
49

SP3A-LED-3
SP3A-LED-2

50
51

SP3A-LED-1
SP3A-MISO

52
53

3TC8

46

SP3A-CCLK
10R

39
3TC4

SP3A-MOSI
10R

IO_L05P_1
IO_L05N_1
IO_L06P_1
IO_L06N_1

3TC3

VCCINT
IO_L01P_2|M1
IO_L01N_2|M0

1K0

VCCAUX

3TC2 RES

3TC1

17
38
66
81

VCCINT

22
55
92

VCCO_3 11

45
26

IO_L01P_0|VREF_0
IO_L01N_0

VCCA-O

IP_3

3
4

BL-SPI-CLK
BL-SPI-CSn

5
6

BL-SPI-SDO

9
10

CTRL-DISPIN
AUDIO-SPEAKERn

12
13

CTRL-DISP
3D-LR-DISP

15
16

3TCH
3TCK

10R

SCL-SSB
SDA-SSB

10R

19
20

3D-LR
3D-VS

BL-DIM

21

GND
8
14
18
42
47
58
63
69
74
80
87
91
95

FT89

IT38

100n

SP3A-CSO-B

FT88

VCC

DBG

SP3A-CCLK

BL-DIM10

2T78

SP3A-MOSI

4K7

3TCC

IT37

FT86

61
62

4K7

SP3A-DONE

3 6TC1

3TCA RES

7TC1
PDTC144EU
DBG

VCCO_2

1u0
RES 2TC4

VCCINT

COM

67

VCCO_0

FT85

OUT

100n

2TC1

IN

2TC2

+3V3

VCCO_1

7T08
XC3S50A-4VQG100

7TC3
LD1117DT12

79
96

VCCA-O

SP3A-LED-4
SP3A-LED-3

1 330R 8
LTST-C190KGKT

2 330R 7

DBG 3T48-1
DBG
6T08

3 330R 6

DBG 3T48-2
6T07

LTST-C190KGKT

DBG

LTST-C190KGKT

DBG 3T48-3
DBG
6T06

4 330R 5
LTST-C190KGKT

PROGRAMMING
ENGINEERING

SP3A-LED-1
DBG 3T48-4

502382-0670

SP3A-LED-2

DBG

1
2
3
4
5
6

6T05

1T03
SP3A-CCLK
SP3A-CSO-B
SP3A-MOSI
SP3A-MISO
SP3A-PROG-B

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 194

Audio & WiHD

FB02H Audio & WiHD

FB02H

4K7

FTB1
3TB2

ITB0

FTB2

100R

1W35
1
2
3
4

2TB1

AUDIO-SPEAKERn

100n

3TB1

+3V3

502386-0370

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 195

FRC - LVDS input

FB02I

FRC - LVDS input

FB02I

FPGA-TX1-A+
3TCL

100R

3TCM

100R

3TCN

100R

3TCP

100R

3TCQ

100R

3TCR

100R

3TCS

100R

3TCT

100R

3TCU

100R

3TCV

100R

3TCW

100R

3TCY

100R

FPGA-TX1-AFPGA-TX1-B+

7T20-2
TFRCV-B1A03

FPGA-TX1-BFPGA-TX1-C+

H1
H2
J3
H3
J2
J1
K1
K2
L3
K3
L2
L1

FPGA-TX1-CFPGA-TX1-CLK+
FPGA-TX1-CLKFPGA-TX1-D+
FPGA-TX1-DFPGA-TX1-E+
FPGA-TX1-E-

M1
M2
N3
M3
N2
N1
P1
P2
R3
P3
R2
R1

FPGA-TX2-A+
FPGA-TX2-AFPGA-TX2-B+
FPGA-TX2-BFPGA-TX2-C+
FPGA-TX2-CFPGA-TX2-CLK+
FPGA-TX2-CLKFPGA-TX2-D+

LVDS_IN
PA_0
NA_0
PA_1
NA_1
PA_2
NA_2
CKPA RXIN
CKNA
PA_3
NA_3
PA_4
NA_4
PB_0
NB_0
PB_1
NB_1
PB_2
NB_2
CKPB RXIN
CKNB
PB_3
NB_3
PB_4
NB_4

FPGA-TX2-DFPGA-TX2-E+
FPGA-TX2-E-

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 196

FRC - Control

FRC - Control

FB02J

7T20-8
TFRCV-B1A03

SPI_FLASH

DEBUG
1T23

FTC9
FTD5

RXD0

EJT-TDI
EJT-TDO
EJT-TCK
EJT-TMS
EJT-TRSTN
RESET-FRCn
TXD0
RXD0
FRC-SYS-CLK

BM03B-SRSS-TBT

3
1

2TD1
EJT-TRSTN
EJT-TMS
EJT-TDO
EJT-TCK
EJT-TDI

FTA8
FTA9
FTB3
FTB4

3TD7
100R
3TD5-2 2
100R
8

2
4

+3V3

3TDG
3TDJ

3TDF

1K0

3TD8

+3V3

3TDH

TXD
RXD

C24
B24

47R
47R
4K7

RES
4K7

XTALIN
XTALOUT
I2C_SCL
I2C_SDA

A23
B22
A22
G3

FTC0

9TD1
RES

RESET_IN
RESET_OUT

AC25
AD26

3T26
220R

FTB5

502382-0670

TDI
TDO
TCK
TMS
TRESET

A24
C23

22p

SCL-FRC
SDA-FRC

C1
C3
C2
B2
D1
B23
C22

22p

4K7

4K7
3TD4

4K7

3TD3

4K7
3TD2

4K7

FTA7

9T17 RES
2TD0

3TD1

DEBUG
1T20
1
2
3
4
5
6

3TD0 RES

+3V3

3TD5-4 4
100R
3TD5-3 3
100R
3TD5-1 1
100R

TEST_CON
TEST_MODE
LMAST
CFG_PLL

TP_PHY
RX_ATESTA
RX_ATESTB
TX_ATEST
MCK2_TEST
DFT_OUT_KMNPLL

FTC1

9TD3
IT70
3TDK RES
+3V3

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GPIO 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PROBE_OUT

DATA0
DATA1
DATA2
DATA3 SF
CLK
CS

24M

TXD0

FTD6

A4
B4
C4
D5
B3
A3

SF-SI
SF-SO
SF-WPn
SF-HOLDn
SF-SCK
SF-CS

1T21

1
2
3

F3
G1
G2
T1
T2 100R
T3
U1
U2
U3
V1
V2
V3
W1
W2
W3
Y1
Y2
Y3
AA1
AA2
D2
D3
E1
E2
E3
F1
F2
A21
B21
C21
AD25

3T80

LCD-PWR-ON-FRCn
CTRL-DISP
3D-LR-DISP
VSYNC-FRC
AUDIO-SPEAKERn

RES

SCL-SSB

3T82
3T81

100R
3T75
RES

100R

100R
3TDA

CTRL-DISP
3D-LR-DISP

SPLASH-ON

10R
3TDC

RES 3T83
RES 3T85

+3V3
+3V3

4K7
4K7

9T27
RES

BL-ON

10R

3T84

BL-ON

3TDD

RES
4K7

+3V3

10R
3TDB

RES

SDA-SSB

10R
IT48
3T76
3T77
47R
3T79
100R

9T26
FTH8
47R FTH9
FTJ0
3T78
47R
3T55
100R

BL-ON
SPLASH-ON
BL-SPI-SDO
BL-SPI-CLK
BL-SPI-CSn
VSYNC-FRC
3D-LR
3D-LR-FPGA-FRC
TXD1
RXD1

TXD1

DEBUG
1T24

FTD7
FTD8

RXD1
5

FTD9

UART-3V3
FOR DEBUG

1
2
3

BM03B-SRSS-TBT

W22
T4
T5
D20
AA25
Y23

4K7

FTB6

+3V3
+3V3-SFB

IT71

RES

4K7

RESET-FRCn

9TD0
+3V3

NC GND
3

220n

2TD3

SCL-FRC

7T30
M25P16

VCC

FTB8
SDA-FRC
4

FTB9

FTC2

SFB-SI
SFB-SCK

FTC3

SFB-CS

FTC4

SFB-WPn

FTC5

BM03B-SRSS-TBT

3TDP

SF-SI

3TR1

7T60-1
SN74LVC125APW
2

S
W
HOLD
VSS

100n

FTC7
3TR2

SFB-SI
SF-SO

47R

EN

3TDT

FTC8
47R

3TDQ

SF-SCK
+3V3

3TR3

3TR4

6
SFB-SCK
1

47R

EN
7

3
9TR1

SF-CS

RES
VCC

47R

SFB-EN

7T31
M25P32-VMW6TG

47R

14

7T60-2
SN74LVC125APW
5

RES

SFB-EN

16M
FLASH

2TS1

47R

4K7

FTC6

SFB-HOLDn

RES

47R

+3V3

ITD0

14

+3V3-SFB

4K7

4K7

3TDN

4K7
3TDM

4K7

3TDL

3TDU

FTB7

100K

DEBUG
1T22

100K
3TDW

3TDV

100n

1
2
3

3TR0

30R

CD

3TDE
+3V3

5TDA

INP
OUTP

4K7

7T25
NCP303LSN28
2

+3V3

3TD9

9TD2

2TD2

RES

+3V3

D
C

32M
FLASH

S
W
HOLD
VSS

7T60-4
SN74LVC125APW
12

47R

11

47R

13

3TR8

+3V3

502382-0670

PROGRAMMING
ENGINEERING

SFB-WPn

47R

EN

3TDS

SF-HOLDn

47R

EN

BL-ON

FT99

IT74
3
RES
7T41
PDTC114EU

1
2

IT72

3D-VS

100n
4

+3V3

9T19

2TS0

3TS1

3TG3

VSYNC-FRC
SFB-HOLDn

47R

47R

IT73
RES

FT28

7T61
74LVC1G125GW
2

10R

RES
7T40
PDTC144EU

1
2
10u

SFB-EN

47R

+3V3

ITD2

RES

2TD4

4K7
3TS2

3TS0
+3V3-SFB

3TG4

3TG2 RES

SFB-EN

+3V3

ITD1

2K2

4K7
3TR7

14

3TR6
+3V3-SFB

1K0

SF-WPn

3TG6

SFB-EN

RES

3TR5

3TDR

BL-ON-OUT

1K0

47R

EN

1
2
3
4
5
6

3TG5 RES

SFB-CS

10

3TT1

14

47R

SFB-EN

1T25

1K0

3TT0

7T60-3
SN74LVC125APW
9

FB02J

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 197

FRC - DDR I/O

FB02K FRC - DDR I/O

FB02K
7T20-1
TFRCV-B1A03

MMANA_TEST
MMDIG_TEST0
MMDIG_TEST1

UMAC1-MCLK0
UMAC1-MCLK0-N

AD14
AC14
AD13
AF15
AE13
AC17

UMAC1-CAS
UMAC1-RAS
UMAC1-WE
UMAC1-CKE
UMAC1-ODT
3TE4

AE10
AD17
AD10
AB17

+1V5

240R
1%

AC9
AC18

UMAC1-MRES
ITF1
ITF2
ITF3

FTE0

100n

MMRESETN

AF14
AE14

100n

MMVREF0
MMVREF1

UMAC1-BA0
UMAC1-BA1
UMAC1-BA2

RES

MMCASN
MMRASN
MMWEN
MMCKE
MMODT
MZQ

AC12
AC15
AF13

2TF2

MMCKP
MMCKN

UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13
UMAC1-MA14

2TF3

0
1
2

AD12
AB15
AF12
AE12
AF16
AC11
AD16
AE11
AC16
AD11
AE15
AE16
AD15
AF11
AB16

1K0 1%

MMBA

UMAC1-DQM0
UMAC1-DQM1
UMAC1-DQM2
UMAC1-DQM3

RES

S0
SN0
S1
SN1
S2 MMDQ
SN2
S3
SN3

0
1
2
3
4
5
6
MMA 7
8
9
10
11
12
13
14

AF5
AF8
AE19
AF23

2TF1

AE4
AD4
DT49 AD8
AE8
DT50 AD18
DT51 AD19
AE22
AD22

0
1
2
3

1K0 1%

DT45

MMDM

3TE0

DRAM

3TE1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 MMDQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

100n

AF3
AE3
AD3
AF4
AE5
AD5
AD6
AE6
AF6
AF7
AD7
AE7
AD9
AE9
AF9
AF10
AE17
AF17
AF18
AE18
AF19
AF20
AE20
AD20
AF21
AE21
AD21
AF22
AE23
AD23
AF24
DT44 AE24

+1V5

2TF8

FTE1

100n
100n

RES
2TF5

1K0 1%

RES

DT48

1K0 1%

DT47

3TE2

DT46

3TE3

DT80

100n

UMAC1-DQS0
UMAC1-DQS0-N
UMAC1-DQS1
UMAC1-DQS1-N
UMAC1-DQS2
UMAC1-DQS2-N
UMAC1-DQS3
UMAC1-DQS3-N

DT43

2TF4

UMAC1-MD0
UMAC1-MD1
UMAC1-MD2
UMAC1-MD3
UMAC1-MD4
UMAC1-MD5
UMAC1-MD6
UMAC1-MD7
UMAC1-MD8
UMAC1-MD9
UMAC1-MD10
UMAC1-MD11
UMAC1-MD12
UMAC1-MD13
UMAC1-MD14
UMAC1-MD15
UMAC1-MD16
UMAC1-MD17
UMAC1-MD18
UMAC1-MD19
UMAC1-MD20
UMAC1-MD21
UMAC1-MD22
UMAC1-MD23
UMAC1-MD24
UMAC1-MD25
UMAC1-MD26
UMAC1-MD27
UMAC1-MD29
UMAC1-MD28
UMAC1-MD30
UMAC1-MD31

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_081_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 198

FRC - Supply analog

FRC - Supply analog

FB02L

7T20-4
TFRCV-B1A03

IT82
100n

10u
2TDB

30R

T23
U22

AVDD25_PLL_VBO
AVSS_PLL_VBO

PLL_VDD
PLL_VSS

AC13
AB14

47u

2TFB

10u

100n
2TDP

2TDQ

D7
D6
E6
E7

10u

100n
2TDN

10u

5TDH
+2V5

LVDS_AVDD_YZ_3|2
LVDS_AVDD_YZ_4|1
LVDS_AVSS_YZ_3|1
LVDS_AVSS_YZ_4|2

D19
D17
D18
E19
E17
E18

10u

100n

10u
2TDF

2TDE

30R

LVDS_AVDD_YZ_1|4
LVDS_AVDD_YZ_2|3
PLL_AVDD_Y
LVDS_AVSS_YZ_1|4
LVDS_AVSS_YZ_2|3
PLL_AVSS_Y

AVDD25_RXPLLB
AVDD25_RXPLLA
AVDD25_RX_1|1
AVDD25_RX_2|2
AVSS_RXVCOA
AVSS_RXVCOB
AVSS_RX_1|1
AVSS_RX_2|2

5TDD

IT81

+2V5
30R
2TDG

IT79

+2V5

R4
P4
M4
N4
N5
P5
M5
R5

100n
2TF9

5TDC

AVDD25_REF
AVSS_REF

30R

IT78

G23
E23
F23
G22
E22
F22

100n
2TFA

AB26
AC26

100n

10u
2TDK

2TDJ

30R

LVDS_AVDD_WX_3|2
LVDS_AVDD_WX_4|1
PLL_AVDD_X
LVDS_AVSS_WX_3|2
LVDS_AVSS_WX_4|1
PLL_AVSS_X

2TDH
10u

IT77

+2V5

AVDD25_KMNPLL
AVDD25_MCK2PLL
AVSSKMNPLL
AVSSMCK2PLL
AVSSMCK2VCO

2TDR

5TDE

AA26
AB25
AA23
AA24
AB24

+2V5

100n

100n

10u
2TDD

2TDC

30R

LVDS_AVDD_WX_1|4
LVDS_AVDD_WX_2|3
LVDS_AVSS_WX_1|4
LVDS_AVSS_WX_2|3

U23
R23
V22
T22

2TDM

+2V5

5TDG

PWR_ANA

IT75

2TDL

5TDB

2TDA

FB02L

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_082_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 199

FRC - Supply digital

FB02M FRC - Supply digital

FB02M
7T20-7
TFRCV-B1A03

7T20-5
TFRCV-B1A03

+1V05

AB1
AC1
AD1
AB2
AC2
AD2
AB3
AC3
AB4
AC4
AB5
AC5
AB6
AC6
AB7
AC7
AB8
AC8
AB9
AB10
AC10
AB11
W12
Y12
AA12
AB12
W13
Y13
AA13
AB13
W14
Y14
AA14
W15
Y15
AA15
AA16
AA17
AA18
AB18
AB19
AC19
AB20
AC20
AB21
AC21
AB22
AC22
AB23
AC23
AC24
AD24

AA3
U4
V4
W4
Y4
AA4
U5
V5
W5
Y5
AA5

+3V3

H4
J4
K4
L4
J5
K5
L5
J6
K6
L6
K7
L7
M7
N7
P7
D8
E8
L8
M8
N8
P8

+1V05

1
2
3
4
5
6 VDDF2
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10 VDDC
11
12
13
14
15
16
17
18
19
20
21

22
23
24
VDDC 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
VDDC 48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
VDDC 70
71
72
73
74
75
76
77
78
79
80

D9
E9
D10
E10
D11
E11
D12
E12
F12
G12
H12
D13
E13
F13
G13
H13
D14
E14
F14
G14
H14
D15
E15
F15
G15
H15
D16
E16
M19
N19
P19
R19
L20
M20
N20
P20
R20
T20
L21
M21
N21
P21
R21
T21
H22
J22
K22
L22
M22
N22
P22
R22
H23
J23
K23
L23
M23
N23
P23

7T20-3
TFRCV-B1A03

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
VDDM 5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VDDM 27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDDM 50
51
52

1
2
3
4
5
6
7
8
9
10
11
12 VDDF1
13
14
15
16
17
18
19
20
21
22
23

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C5
C6
C7
C8
C9
C10
C11
C12

NC

21
22
23
24
25
26
27
28
29
30 NC
31
32
33
34
35
36
37
38
39
40

61
62
63
64
65
66
67
68
69
NC 70
71
72
73
74
75
76
77
78
79
80

NC

J24
J25
J26
K24
K25
K26
L24
L25
L26
M24
M25
M26
R24
T24
T25
T26
U24
U25
U26
V24

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

VDDM

D4
E4
F4
G4
E5
F5
G5
H5
G6
H6
G7
H7
E20
D21
E21
D22
D23
D24
B25
C25
D25
C26
D26

+1V5

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B5
B6
B7
B8

VSS

VDDF
7T20-6
TFRCV-B1A03

C13
C14
C15
C16
C17
C18
C19
C20
E24
E25
E26
F24
F25
F26
G24
G25
G26
H24
H25
H26

+3V3

+1V05

10n

2TMA

10u
2TMB

10n
2TMC

10n
2TMD

10n
2TME

10n

100n
2TMR

100n
2TMS

100n
2TMT

100n
2TMU

100n
2TMV

100n

10n
2TEN

100n
2TMQ

10n
2TEM

10n
2TEL

10n
2TEK

100n
2TEJ

100n
2THE

10u
2THD

2THC

1n0

1n0
2TFF

1n0
2TFE

1n0
2TFD

1n0
2TF7

10n
2TF6

10n
2TMP

10n
2TMN

10n
2TMM

10n
2TEZ

100n
2TEY

100n
2TML

100n
2TMK

100n
2TMF

100n
2TEW

+3V3

10u
2TEV

10u
2TFC

2TEU

220u 2.5V

RES

+1V5

100n
2TEH

100n
2TEG

100n
2TEF

100n
2TEE

100n
2TED

10u
2TEC

10n

2TEB

10n
2TEA

10n
2TE8

100n
2TE7

100n
2TE6

100n
2TE5

100n
2TE4

100n
2TE3

100n
2TE2

220u 2.5V
2TE0

220u 2.5V
2THK

RES 2THL

10u
2TE1

FTH7

CT00

2TT1

SENSE+1V05

A1
B1
AE1
AF1
A2
AE2
AF2
F6
M6
N6
P6
R6
T6
U6
V6
W6
Y6
AA6
F7
J7
R7
T7
U7
V7
W7
Y7
AA7
F8
G8
H8
J8
K8
R8
T8
U8
V8
W8
Y8
AA8
F9
G9
H9
J9
K9
L9
M9
N9
P9
R9
T9
U9
V9
W9
Y9
AA9
F10
G10
H10
J10
K10
L10
M10
N10
P10
R10
T10
U10
V10
W10
Y10
AA10
F11
G11
H11
J11
K11
L11
M11
N11
P11
R11
T11
U11
V11
W11
Y11
AA11
J12
K12
L12
M12
N12
P12
R12
T12
U12
V12
J13
K13
L13
M13
N13
P13
R13
T13

1
2
3
4
5
6
7
8
9
10 VSS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VSS
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
VSS
98
99
100
101
102
103
104
105

106
107
108
109
110
111
112
113
114
115
VSS 116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
VSS 159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
VSS 204
205
206
207
208
209
210
211
212
213

U13
V13
J14
K14
L14
M14
N14
P14
R14
T14
U14
V14
J15
K15
L15
M15
N15
P15
R15
T15
U15
V15
F16
G16
H16
J16
K16
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
F17
G17
H17
J17
K17
L17
M17
N17
P17
R17
T17
U17
V17
W17
Y17
F18
G18
H18
J18
K18
L18
M18
N18
P18
R18
T18
U18
V18
W18
Y18
F19
G19
H19
J19
K19
L19
T19
U19
V19
W19
Y19
AA19
F20
G20
H20
J20
K20
U20
V20
W20
Y20
AA20
F21
G21
H21
J21
K21
U21
V21
W21
Y21
AA21
Y22
AA22
A25
AE25
AF25
A26
B26
AE26
AF26

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_083_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 200

Input - LVDS

FB02N Input - LVDS


100p

100p
RES 2S83

100p
RES 2S80

100p

100p
RES 2SA4

RES 2S85

100p
RES 2SA1

RES 2S86

10p

100p
RES 2SA3

10p
RES

RES 2S82

100p
2S84

2SA2

RES

FB02N

1G51

3S53

3D-LED-S3A
CTRL-DISPIN
SDA-SSB
SCL-SSB
BL-ON-OUT

RES 100R
FS26
FS27

FS10
FS11
FS12
FS24
FS23

100R

3S44
10R

3S40
10R
3S41

100R

3S42

3S48

BL-DIM

100R
3S51

CTRL-DISPIN
3D-LED-S6
3D-LRIN
3D-VSIN
SPLASH-ON
CTRL-DISPIN

10R

3S49
100R
RES
3S43

100R
FS22 100R

FS28
3S46
100R

FSA6

100R

FPGA-RX1-AFPGA-RX1-A+
FPGA-RX1-BFPGA-RX1-B+
FPGA-RX1-CFPGA-RX1-C+

FS30
FS29

3S45
RES
3SA1
RES

FS09

FS79
FS31
FS32
FS33

FS34
FS35
FS36
FS80
FS37

FPGA-RX1-CLKFPGA-RX1-CLK+

FS38
FS81
FS39

FPGA-RX1-DFPGA-RX1-D+
FPGA-RX1-EFPGA-RX1-E+

FS40
FS41
FS42
10p

RES
2SA6

FS43

FPGA-RX2-AFPGA-RX2-A+
FPGA-RX2-BFPGA-RX2-B+
FPGA-RX2-CFPGA-RX2-C+

RES
210p

IS51
2SA5
1 IS52

FS44
FS45
FS46
FS47
FS48
FS49

FPGA-RX2-CLKFPGA-RX2-CLK+

FS50
FS51

FPGA-RX2-DFPGA-RX2-D+
FPGA-RX2-EFPGA-RX2-E+

FS52
FS53
FS54

IS05

1T09 RES

FS93

9S21
RES

9S05-2

9S05-3

9S05-4

5
9S04 RES

RESET-FRCn

9S06

ENABLE+3V3

CTRL-DISPIN

9S01 RES

CTRL-DISP

3D-LRIN

9S02 RES

3D-LR

3D-VSIN

9S03 RES

3D-VS

4K7

1
2
FS25
DBG

52 53
54 55
56 57
58 59
60 61

FI-RE51S-HF
DBG

IS26

FROM SSB
6S00

9S05-1

3S52

T 2.0A 63V

LTST-C190CKT

+12V
RES
7S00
PDTC114EU

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

ENABLE+3V3
RES
7S01
PDTC114EU

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_084_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 201

I2C-Multiplexer & I2C-Temperature sensor


2

FB02O I C-Multiplexer & I C-Temperature sensor

FB02O

+3V3
2SG1

100n
7SG1
PCA9540B

VDD

SCL-SSB

SDA-SSB

I2 C
-BUS
CTRL

INP
FIL

SDA

SC1

SCL-BL

SD0

SDA-DISP

SD1

SCL-DISP

SCL-DISP

SDA-BL
SCL-BL

3SG2

+3V3

SCL

SC0

VSS

SCL-SSB

10K
6

SDA-DISP

3SG9

SDA-SSB

10K

SDA-BL

PROGRAMMING
ENGINEERING

SCL-SSB

9SG4

SDA-SSB

9SG5

SCL-SSB

9SG6

SDA-SSB

9SG7

SCL-DISP

RES 3SG6

+3V3

100K
3SG7
100K
RES 3SH0
100K
3SH1
100K

RES
SDA-DISP
RES

1SG2
1
2
3
4
5
6
7
8

3SH2
47R

3SH3

SCL-BL
RES

SCL-SSB

SDA-BL
RES

SDA-SSB

47R

9 10

+12V
+12VD

502382-0870

SCL

A2

1K0

3TS3

9TS2
RES

100n

9TS1
RES

ITS4

9TS3
RES

10R

ITS5

1K0

ITS2

A1

ITS3

3TS7

10R

SDA

1K0

3TS5

A0

SCL-SSB

ITS1

OS

3TS6

3TS4

SDA-SSB

GND

DTS1

+VS

7SG2
LM75BDP

2TS2

+3V3

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_085_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 202

FRC V-by-one output

FB02P FRC V-by-one output

FB02P

FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53

7T20-9
TFRCV-B1A03

V1-TX0N
V1-TX0P

BT15

3TN0

IT85

100R

3TN1
100R

V1-TX0P
V1-TX0N
V1-TX1P
V1-TX1N
V1-TX2P
V1-TX2N
V1-TX3P
V1-TX3N
V1-TX4P
V1-TX4N
V1-TX5P
V1-TX5N
V1-TX6P
V1-TX6N
V1-TX7P
V1-TX7N

2TN2
100n
2TN4
100n
2TNA
100n
2TNC
100n
2TNE
100n
2TNG
100n
2TNJ
100n
2TNL
100n

IT86

W23
V23

BT05
BT06

V1-TX4N
V1-TX4P

BT08
BT09

V1-TX5N
V1-TX5P

BT10
BT11

BT13

V1-TX7N
V1-TX7P

BT19

100R

IT90
1T51
100p

RES

IT89

100p

3TN9-4

FT94

IT88

RES

2TN9

10K

3D-LR-DISP

3TN8

3TN5
100R
3TN7
10R

100p

FT97

100R
3TN6
10R

IT87

2TN8

FT96

3TN4

RES 2TN7

CTRL-DISP
3D-LR
SCL-DISP
SDA-DISP

FT95

100p

RES

BT04

BT14

RES

2TNM

BT03
V1-TX3N
V1-TX3P

1u0

10K

BT02

BT12
+1V8-FPGA

3TN9-3

BT01
V1-TX2N
V1-TX2P

V1-TX6N
V1-TX6P

10K

3TN3

RES

10K

+3V3

3TN2

+3V3
RES

V1-LOCKn
V1-HTPDn

BT00

V1-TX1N
V1-TX1P

2TN6

2TN1
100n
2TN3
100n
2TN5
100n
2TNB
100n
2TND
100n
2TNF
100n
2TNH
100n
2TNK
100n

10K

LOCKN
HTPDN

BT17
BT18

BT16
N26
N25
P24
N24
P25
P26
R26
R25
V25
V26
W26
W25
Y24
W24
Y25
Y26

3TN9-1

0P
0N
1P
1N
2P
2N
3P
3N
TX 4P
4N
5P
5N
6P
6N
7P
7N

RES

VX1_OUT

V1-HTPDn
V1-LOCKn

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

100n

IT40
IT03
IT08
IT51
IT52
IT53
IT26

10K

FTJ1
FTJ2
FTJ3
FTJ4
FTJ5
FTJ6
FTJ7
FTJ8
FTJ9
FTK0
FTK1
FTK2

FT93
FTH3
FTH4
FTH5
FT79
FTH6
FT32
FT33
FT34
FT35
FT36
FT80
FT37
FT38
FT81
FT39
FT40
FT41
FT42
FT43
FT44
FT45
FT46
FT47
FT48
FT49
FT50
FT51
FT52
FT53
FT54

3TN9-2

FTA1
FTA2
FTA3
FTA4
FTA5
FTH1
FTH2
FTA6
FT83
FT55
FT56
FT57
FT58
FT59
FT60
FT61
FT62
FT63
FT64
FT65
FT66
FT84
FT67
FT68
FT69
FT70
FT71
FT72
FT73
FT74
FT75
FT76
FT77
FT78

2TN0

+VDISP

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_086_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 203

FRC DDR3

FB02Q FRC DDR3

FB02Q

E7
D3

UMAC1-DQM1
UMAC1-DQM0
UMAC1-MCLK0-N

RAS
ODT
CAS
CK
CK
CKE
CS
WE
RESET
DML
DMU

NC

VSS

VSSQ

DBK5

UMAC1-MD9
UMAC1-MD11
UMAC1-MD8
UMAC1-MD14
UMAC1-MD13
UMAC1-MD15
UMAC1-MD10
UMAC1-MD12

DBL5
DBL6

FTE4
RES

E3
F7
F2
F8
H3
H8
G2
H7

H1
M8
3TK3

100n

UMAC1-DQS1
UMAC1-DQS1-N

100n

DBK3
DBK4

2TNR

F3
G3

3TK1

UMAC1-DQS0-N
UMAC1-DQS0

DBL8
DBL9

1K0 1%

B7
C7

+1V5

240R 1%
UMAC1-BA0
UMAC1-BA1
UMAC1-BA2
DBK6

UMAC1-MA14

L8
M2
N8
M3

UMAC1-WE
UMAC1-MRES

J3
K1
K3
J7
K7
K9
L2
L3
T2

UMAC1-DQM3
UMAC1-DQM2

E7
D3

UMAC1-RAS
UMAC1-ODT
UMAC1-CAS
UMAC1-MCLK0
UMAC1-MCLK0-N
UMAC1-CKE

J1
J9
L1
L9
T7

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

DBM0
DBM4
DBM5

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ

0
1
2
3
4
5
A
6
7
8
9
10
11
12
13
14
BC
AP

0
1
2
3
DQU
4
5
6
7
DQSU1
DQSU2
DQSL
DQSL

VREFDQ
VREFCA

0
1
2
3
DQL
4
5
6
7

ZQ
BA0
BA1
BA2
RAS
ODT
CAS
CK
CK
CKE
CS
WE
RESET
DML
DMU

NC

VSS

VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9

DBK7

BA0
BA1
BA2

DBL4

DBL7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DBL2
DBL3

ZQ

UMAC1-MD5
UMAC1-MD0
UMAC1-MD7
UMAC1-MD1
UMAC1-MD4
UMAC1-MD2
UMAC1-MD6
UMAC1-MD3

DT35

UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13

2TK7

J3
K1
K3
J7
K7
K9
L2
L3
T2

0
1
2
3
DQL
4
5
6
7

D7
C3
C8
C2
A7
A2
B8
A3

1K0 1%

UMAC1-RAS
UMAC1-ODT
UMAC1-CAS
UMAC1-MCLK0
UMAC1-MCLK0-N
UMAC1-CKE

DQSL
DQSL

B1
B9
D1
D8
E2
E8
F9
G1
G9

L8
M2
N8
M3

DQSU1
DQSU2

DBM1

D7
C3
C8
C2
A7
A2
B8
A3
B7
C7

UMAC1-MD20
UMAC1-MD18
UMAC1-MD22
UMAC1-MD16
UMAC1-MD23
UMAC1-MD17
UMAC1-MD21
UMAC1-MD19
UMAC1-DQS2-N
UMAC1-DQS2

F3
G3

DBK1
DBK2

E3
F7
F2
F8
H3
H8
G2
H7

DBM2

UMAC1-DQS3
UMAC1-DQS3-N

DBK9
DBM3

J1
J9
L1
L9
T7

UMAC1-MD27
UMAC1-MD28
UMAC1-MD26
UMAC1-MD29
UMAC1-MD24
UMAC1-MD31
UMAC1-MD25
UMAC1-MD30

UMAC1-MA14

DBK8

DT38

DT39

DT40

DT41

10n

10n
2TLB

10n
2TLA

100n
2TL9

100n
2TL8

100n
2TL7

100n
2TL6

10n
2TL5

10n
2TL4

10n
2TL3

100n
2TL1

100n
2TL0

100n
2TKZ

100n
2TKY

10u
2TKW

10u
2TKV

2TKT

47u 16V
2TKU

10n

10n
2TKS

10n
2TKR

100n
2TKQ

100n
2TKP

100n
2TKN

100n
2TKM

10n
2TKL

10n
2TKK

10n
2TKJ

10n
2TKH

100n
2TKG

100n
2TKF

10u
2TKB

2TK9

47u 16V
2TKA

10u
2TKC
DT37

10n
2TL2

+1V5

+1V5

100n
2TKE

75R

240R 1%

UMAC1-WE
UMAC1-MRES
75R

10n
3TK7

3TK6

UMAC1-MCLK0

2TK8

3TK2
UMAC1-BA0
UMAC1-BA1
UMAC1-BA2

VDD

0
1
2
3
DQU
4
5
6
7

VREFDQ
VREFCA

100n
2TKD

RES

H1
M8
100n

100n

2TNQ

1K0 1%
2TK4

3TK4

FTE3

0
1
2
3
4
5
A
6
7
8
9
10
11
12
13
14
BC
AP

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DBL0
DBL1

1K0
1%

3TK0

+1V5

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

DT36
DBK0

VDDQ

3TK5

VDD
UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13

7T51
H5TQ1G63BFR-H9C

A1
A8
C1
C9
D2
E9
F1
H2
H9

B2
D9
G7
K2
K8
N1
N9
R1
R9

7T50
H5TQ1G63BFR-H9C

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1V5

+1V5

DT42

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_087_110706.eps
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2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 204

Power sequencing

FB02R Power sequencing

FB02R

+12V
ENABLE+1V5

3TMA

VREG5

33K

+12V

3
100K

3TM2-3
10n RES

3K3
2TM3

ENABLE+1V05
3TM6

1u0

ITMD

+1V5

47K

3T73

10n

RES

ITMH

ITMB

2
6K8
2TM5

3TMB

100K

+2V5

RES

2TM1

3
100K

3TM1-3

100K

ITMC
2 3TM1-2 7

100K

8
1

3T72
6

47K

10n

10K
2TM8

3TM9

RES

3TM5

3
3TM1-1

RES

ITM4
1u0

100K

3 3TM0-3 6

100K

2
100K

7TM4-1
BC847BPN(COL)
1

7TM3-1
BC847BPN(COL)
1

ITM8

ITMF
2

7TM0-1
BC847BPN(COL)
1

ITM9
4
5

7TM1-2
BC847BPN(COL)

+12V

3TP6

8K2 RES
1%
8K2 RES
1%

2K7

3TP8

3TP5

2K2

VREG5

K
A

7TP1
RES TS2431

100n

2TP2

7TM1-1
BC847BPN(COL)
1

RES

3TP7

2 3TMC-2 7
100R RES

ITMG

3TMC-1

8
100R RES

+2V5

100K

100K
3TM7

3
2 3TM0-2 7

RES

ITM6

ITM7
1 3TM0-1 8

100K

1u0

100K
3TM8

4 7TM0-2
BC847BPN(COL)
5

2TM6

+3V3

5 3TM0-4 4

5 3TM1-4 4

2TM4

15K

ITM5

100K
4 7TM3-2
BC847BPN(COL)

ITM3

4 7TM4-2
BC847BPN(COL)

ITM1

100K

ITM2

4 3TMC-4 5
RES
100R

3TM4

3 3TMC-3 6
100R RES

ITME
VREG5

4 3TM2-4 5

100K

22K

+12V

7 3TM2-2 2

3TM3

VREG5

ITM0

8 3TM2-1 1

ENABLE+2V5

ITMA

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_088_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 205

Connectors - Backlight

FB02S Connectors - Backlight

FB02S

3SC6
10R

BL-SPI-CLK

BL-SPI-CLK-OUT

3SC2-4

100R
BL-SPI-CLK-OUT

9T25

1F53

BL-SPI-SDO
BL-SPI-SDO-OUT

BL-SPI-SDO-OUT

3SC2-3
100R

BL-SPI-CSn

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

FSF5

6
2SC6

9T24

FSF7

10p

9T23

10p

FSF4

2SC4

SCL-BL

2SC3

10R

10p

3SEG

10p

FSF3

2SC5

SDA-BL

FSF8

FSF9

BL-SPI-CSn-OUT

FSFA

FSFC

1u0

2SC7

FSFB

FSFG
1M54

3SE7

100R

3SE9

100R

3SEB

100R
100R
100R
100R

3SED

BL-SPI-CSn-OUT

3SC2-1

17

FH52-15S-0.5SH

100R

10p

100R

2SC8

FS02
FS03
3SE8
FS04
3SEA
FS05
FS06
FS07 3SEC
FS08

BL-DIM5
BL-DIM6
BL-DIM7
BL-DIM8
BL-DIM9
BL-DIM10
BL-DIM11
BL-DIM12

10p

3SA3

2SC9

FS01

9S96

FS00

1
2
3
4
5
6
7
8
9

100R
3SC4

DBG

330R

+3V3

10u

VIN

FLG

EN
EN

VOUT

GND

6S96

7S94
RT9715EGB

10u

3S9M

2S96

2SCH

2SCG

2SBG

2SBF

2SBE

2SBD

2SBB

2SBC

100R

DBG

FSFH

LTST-C190CKT

VSYNC-FRC

2S9G

1n0

1n0

1n0

1n0

1n0

1n0

1n0

1n0

2041145-9

Bolt-On 1
FPGA-FRC

2011-05-12

2011-03-17

8204 000 9196


19051_089_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 206

10-27 310431365372 Bolt-On 1 Layout

3TC5

3TC7

9U08
2TCH

3TCE

DT58

3U78

3U80

3U81

2U32

2U31

1M83

9U02

3U10

6U10

3U09

3U11

7U76
3U14

2U79
3U50

2U89

2U34

3U82

3U17

3U75

7U10
6U15

2U53

2U35

2U29

6U09

3SG2

3SH2

9SG5

3SH3

9TS3

3S46

1G51

3SH0

2SG1

7SG1

3SH1
9SG4

3SG6

9S05
3S43
3S51

9S02
3S49

3S48

3S44

3S45

9S03

6S00

3S42

1T25

1T09

2SA3

3TN0

7S00

3T85
3S40

1T51

9SG6
3SG7

7S01
3T81

2TN0

BT15

3TN1

BT00
BT16
BT04

6U05

3TS5

9S06

3SA1

2TH2

3TS4

3T82 3T66 3T65


3T63 3T64

BT01
BT05

BT06

BT19 BT11

BT18

BT02

BT09

BT13

BT08
BT12

BT14

BT03

3T60
3T61
3T62

1T20 1T02

BT17
BT10

DTS1

3U15
2U71

3SG9

9S04

6T00

2UJ6

3TS6

3T69

3TS7

9TS2

2TS2
9TS1

3T55

3TD8

3TD0

3TD1

3TD2

3TD3

3TD4

2TH4

7SG2

2TH3

3TS0

3TS2

7T61

3U77

3T09

3T06

3T68

2TS0

6T03 3T56

6T10 3T57

1T00

2TH1

2TH6

3U49

2UJ8

2TH5

3U39

3TS3

9T27
9T26

5T05
5T04
3T12

2TH0
2TH7

2U90

3T50

6T11

2TH8

6T02 3T38

7T00

2TH9

3T58

7T13

CT10

3T49

2T16
6T01

3T59

2T15

9U10

3T51
3T52
3T54
3T53

3T23

DT77
DT83

2U69

7U75

2T22

DT81

DT74
DT73
DT72
DT82

DT80

3TS1

2U75

2T78

3T24

7T11

3TCM
3TCL

3T76
3T77
3T78

3T22

3TCS
3TCP

3TCN

3TN2
2TNM

3T25

3T28

7T14

3TN3
CT00

3U16

5U54

3T01

1T23

3T27

3T17

2TN2

3TCR

2TN4
2TN1

3TCT

7T20

2TNA
2TN3

2T01

2TNC
2TN5

3TCQ

1T22

1T61

3TCU

2TNB

5U75

1T06

3TCV

2TNE

DT68

2U30

DT69
DT70
DT71

2U05

CU05
2U86
3U12

2U84

DT57

3TCW

2TNG

2U85
3T47

3TCY

2TNJ
2TNF
2TND

1T05

2U33

3TDA

3U35

2TNL
2TNH

2T03
3T19

2UJ7

3TDC

2U81

DT60

3TDD

CU06

2TD0

2TNK

9T22

7T07

DT61

DT54

3U51

DT59

2U77

DT63

7T18

DT55

2U78

DT64

9T14
DT46

2U82

5U76

3T67

3T18

1T21

3T37
3T36

7T04

9T11 9T10
2T70

9T15
DT43

3T26

3TDB

9T17

3T33

DT45

DT50

DT47DT44

2TD1

7T06

DT56

9U01

3U13
2TCK

2TC5

DT65

2U87

3TC1

3TC3
2TCM
2TC6

2TCA

2TCL

9T23
9T24
9T25

2TM3

3TM2

2TM1

2TC9

2U70
5U55

3TCA
2TCG

DT49

9U05

2TCN

3TCF

DT34
3TM7

3TM5

DT51

3U84

6TC1
2TC3

2TC7

DT31

2TCF

2TM4

3TCG

7T08

DT30

DT33

7TM4

1T10 2T71

3TC2

3TC8

DT32

3TM1

2TM5

7TM3

DT41

9U07

3TCD

3TM6

3TMA

2TC8
2TCD

2TCE

7TM1

3TM9
3TMB

2TC4

3T48

3TC9

3TM8

DT35

2T72
3T34

1T24

1T03

2TM6

3TM0

7TP1
3TP6
3TM4

7TM0

3TP5
2TKC

3TP8
3TM3

2TKH

2TKD

2TKG

7T50

3TK6

3TK7

2TK9

2TL1

7T51

2TKW

2TKU

2TL2
2TKY

3T35

DT42

2TK8

3T39

7T10

DT39

DT36
DT40
DT37

9U06

2UJ3

2TKT

3U72 3U73

6T08
6T07
6T06
6T05

3TP7
2TP2

2UJ4

1M84

2U07

2UJ5

2U06
3SA3

3SE7

2SBB

3SE9

3SE8

2SBD

2SBC

2SBF

3SEA

2SBE

3SEB

3SEC

2SBG

2SCG

3SED

2SCH

2UJ1

1U01

3S9M

2UJ2
3T72

9U04

3TK3

6T04

1M99 1MB9

1M09

2S9G

7S94

2S96

1M54

6S96

2SC3

2SC5

3SEG

2SC6

2SC4

3SC6

2SC8

9S96

2SC9

3SC4

2SC7

5U53

2U58

2U57

1F53

9U03

DT38 DBK9

6T09

7U06

7U05

6U01
2U68

5U51

9U09

1M85

2U59

2U60

Overview top side

9SG7

1SG2
1W35

1T01

Bolt-On 1 Layout Top

3104 313 6537


19051_090_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 207

3U08
2U61

2UH6
IU29

IU68

3U83

IU57

2UH8

Overview bottom side

3U02
IU66

3U58

FSF8
FSFB

FS07

FS06

FS05

FS04

FSFC

FS08
FSF4

FSF3

FSFG

7U51

3U37
IU67

IU45

IU56

3U56

IU70

3SC2

FU56

FS03

FU53

FS02

FU55

FS01

FU54

3U55
2U74

FSF7

FSF5

2UH7

IU01
2U64

FSFA

IU60

2UJ0

3U60

FU51

U2

IU83

3U59

FSF9

IU63

FS00

3U57

2U63

FU52

2UD1

IU69

3U03

IU58

2UH5

2UH9

IU19

IU15
FU78
IU18
FU77

IU05

IU07

IU12

FU76

IU09

ITME

IU11

2TM8

7T17

ITM5

ITMD
ITMH

ITM1

IT83
FT91
IU26

2TL3

2TL5

2TK7

2TKZ

2TK4

2TNQ

3TK5

2TL8

2TKL

DBK1

2TL4
FTH7

DBM2

2TKE

DBK5

2TL7

2TLA

DBL6

DBL4
2TKM

DBK2

2TLB

DBM1

2TKJ

2TKQ

DBM3

2TKV

DBK3

2TKR

2TT1

ITMC

DBM4

FTE4

DBK8

2TL0

2TL9
2TL6

2T55

7T03

ITMB

IT05

IT91
IU02

2T81
2T82

FT08

DBL5DBK4 2TKK

2TKF

ITM8

3T21 2T36
3T03
3T16 FT00

ITM4

DBK6
DBL2

2TKS

2TKA

DBM5

3TK1

2TKB

2TC2

2TC1

IU79

2TCB

FT85

FTE3
3TK4

3T46
3T45

2TNR

DBL3
3TK0

2TKP

IT47

DBL8

3TK2
DBL0

7T15

ITMG

7TC3

IT80

DBL7
DBM0

ITMA

2T91

IU03

DBK7

DBK0

ITM3

IT84

2T80

2T37

IT16

FT92

IT38

IU27

2T83 3T44
2T84

DBL9

IT18

ITM0

ITM9

IU61

IU65

3T43

7T16

IT45

ITMF

IT37

FT29

DBL1

IT17

IT46

2TKN

3TCK

FT90

3TCH

FU58

FT87

2TCC

FT20

FT86

ITM2

3T71

ITM6

3T42
3T40 3T41

5T08

IU82

IU81
IU80

IU14
IU16

FTJ6

FT89

2T92

3TC4

FTK1
IU04

7TC1

IU13

ITM7

IU28

IU17
FT88

7TC2

IU06

3TCB

FTK2

IU10

3T70

2TCP

IU08

3TCC

FTJ5

FTJ3
FT18
FTJ4

IT60

3T31

2T69
3T32

2TEU

2THL

FTJ2

5TDG

2THK

2TDR

FT76

2TD2

FT75

FT74

3TN9

7T25

3TDH

FT78

FT77

3TDJ

3TDK

3TDG

FT72

FT73

FT84
FT71

FT70

FTB6
FT69

FT68

FT66
FT65

ITD1

FT64

FT62

2TS1

3TT0

3TDW

IT01

7T19

7T21

2TDJ

2TDP

2TDQ
2TE7

2TE0

2TE8

2TDN

3TDF

9TD1

9TD2
3TR1

3TR0

7T60

FTC4

ITD2

FTJ1

FTD6

2THD

2THE

2TMQ

2THC

2TEK

2TEC
3TR2

3TR3

FTD5

FTC9

FT67

3TR7

3TDL

2T73

2TDB

2TDA

2TEJ
2TE3

2TEB
2TEL

2TED

2TEM

2TE6
3TDU

IT78

FTC0

3TD9

3TR8

5TDA

FTB9

5TDH

ITD0

3TR5

3T84

7T30

FTC8

FTD8

9TD3

3TDE

3TR4

IT70

3TR6

3T14

FTC6

FTC5

FTD9

FTD7
FTB7

IT82

FT63
FT61
FT58

FT60

FTB5

2T54

FTA7

3TD5

FTB4

FT59
FT57

3T30
3T29
9T42

7T31

FTB8
IT13

3TD7

FS22

FTK0

3TDS

5TDE

2TF4
2TFE

2TFF

2TEY
2TEZ
2TE5
2TEN

IT61

7T02

9T36

IT62

3TDQ

FT19

3TDT
FTC7

FTC3

FT16

FT05

ITS3

3TE3

3TE2

2TF5

2TF7
2TEE

2TMC
2TMR

IT73

3TDR

3TT1

2TD4
IT04

3TDM

3TDN

3TDP

9T40

FTC1

FTC2

IT63

3T15

FT13

FTG0

2T39
2T38

2T43 FT11

ITS5

9T19

9TR1

IT72

5TDB

2TDM

2TF9

2TFA

9TD0

IT69

IT68

9T38
FTJ7

7T40

IT71

2TD3

FTFA

9T02

9T41

2TME

5TDC

FTFE

FTF9

ITS4

2TMA

3TG3

9T32

FTFR
FTFP

2TDK

2TML

2TFD

2TF6

2TFC

2TMP

2TMN

9T35
9T34

2T31
2T30

2T68

9T33

3T79

3TG2

IT15

2TFB

2TE2

2TMT
FTFB

7T12

3T10
3T11
2T02

FTFC

9T37

FT25

FT03

2TEF
2TMD

3T86

FTFH

IT14
IT11

3TS8

2TE1

2TEH

2THB

FTFK

2T42

2T41

2T45

FTH8

2THA

IT64

FTF7

2T44

2T51

FTFJ

IT65

2TDL
FTFL

FTFQ

IT00

FTF8

2T40

2T46

FTH9

FTFV

FTFF

2T34

2T18

2T06

FTJ0

FT04

2T35 FTFM

2TEA

FTFW

3T08

2T09

2TE4

IT10

IT12

3TDV

2TF3

3TE1

2TF1

3T04

FTFT

2T20

IT02

FTFN

2T33

2T25

2T08 2T23

2T52

2T12

2T49 2T19

2T32

FTFS

2T14

FTJ8

FT02

FT06

IT75

2TDD

2TMS

2T24
2T21

2T00
2T47

2T13

2T17

2T28

2T05

2T50
2T48

FT01

3T05

FT10

2T26

2T27
9T01

2T07

FTA9

FT56
FT55

FT14
FTB3

FT98

FTA8

FT83

FT15

FTA5

ITS1

7T01

ITS2

3T13

FTA4

FTA2
FTA3

ITB0

3TB1

3T80

FSA6
FS09

FS39

FS34

9S01

FS33
FS24

FT95

FS44

IT08

FT94

IS26

FS50

FS49
IS52

IS51

FS37
FS38

3S52 9S21

2SA6

FS32

FS31

FS12

FS27

IT74

3TG6

FT53

FT50

FT54
FT45
FT38

FT35

FS25

FT47

FTH6
IT40

IT26

FT49

FT42

FTH5

FT51

FT43
FT39

FT79

3TN5

FT52
FT44

3TG5

3S53

3TN8

FT48

3TN6
2TN8

IT88

3TN7

2TN6
IT85

FS81

FT46

FT41
FT34
FT32
FT93

FT28
2SA5

IT51

IT53

IT03

FTH2

3TG4

FT07

FT80

FT37

FT33
FTH3

7T41
FS11

2S82

FS43

FS52

FS10

FS80

3S41

FS28

FS30
FS40

IT52
FTH4

FTH1

FT99

2S85
FT31

2S84

FS35

FS45
FS47
FS51

FTA1
FT81

FT96

2SA2

FS36

FT26

FS23
2SA1

FS41

FS93
FS79

FS29
2SA4

2S83
FS42

FS48

FS53

IS05
3TB2

FT97

FT30

2S80

FS46

FTB2

2S86

FS54

FTA6

FT27

3T83

FS26

FTB1

IT77
2TMM

2TDF

2TMB

FTE1

2TEW

2TDH

2TEG

FTFZ

FTJ9

FU57

3T07

FTFY

IU84

2TB1

2TEV

2TMF

2TDE

3T75

FTFU

FSFH

IT22

5T07
5T06
5T00
5T01
2T04
2T11
2T10

IU76

2UJ9

ITF1

ITF3

2TDC

IT79

3TMC
5T03
5T02

DT76
DT75

IU31

IU62

2TDG

IT06

IT23

IU78

IU24

ITF2

2TMV

2T59

FT12

IU77

3TE4

2T66

9T31

IU75

DT48

2TMU

9T30

IU30

IT48

FT8S

IU64

FTE0

2TMK

2T56

7T09

FT23

2T58
IT66

2T61
FT21

FT22

FT24

IU25

5TDD
3TE0

2TF2

2T63

2T62

FU75

FT09

2T57

2T64

3T20

3T02

DT62

3T00

7T05

IT81

DT67

2T67

2TF8

DT66

2T60

3T73

2T65

FT17

IT86

FT40
FT36

2TN7
3TN4
IT87

IT90

2TN9

IT89

Bolt-On 1 Layout Bottom

3104 313 6537


19051_091_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 208

10-28 FB01 820400091992


DC/DC converters

FB01A DC/DC converters

FB01A

330R

2U53

VOUT

EN

ADJ
PGOOD

NC
GND
GND HS

VIA
18
19
20
21

7
1

VIA

VIA

10
11
12
13

VIA
14
15
16
17

ENABLE+2V5

VIN

+2V5

10u

7U10-1
RT9025-12GSP
6

2U89

B230LA-M3

7U10-2
RT9025-12GSP

4
10u

+3V3

VDD

1n0

4K7

4K7

4K7

4 3U15-4 5

6U05 RES

1u0

2U71

3U11

1K8

10K

FU57 +5V

IU62

2U35

6U15

ENABLE+3V3

9U10

BZX384-C5V1

FU58

RES

+3V3

3 3U15-3 6

4K7
2 3U15-2 7

3U10

1K0

RES

1 3U15-1 8

2UJ9

22
23
24
25
26

RES 2U29

+5V
6.3V 100u

IU61

1n0

6U09
3U84

6U10 RES

BZX384-C6V2
4K7

+12V

LTST-C190CKT

22u

3U35 DBG
DBG

22u

2UJ6

22u

+12V

+12V

3U09

2UJ7

2UJ8

+3V3

3U50

220K 1%

82K
3U49

3U39

RES

IU24

1% 470K
2U90

IU29

3U51
22K

1n0

470R

470R

3U73-4 RES

470R
3U73-3 RES

470R

3U73-2 RES

3U73-1 RES

470R

470R

3U72-4 RES

470R

3U72-3 RES

5U55

IU64

SW

SS

FB

GND-1V5

3U78
3U81 RES

1M0

22K 1%

68K 1%

18
19
20
21

VIA

VIA

10
11
12
13

VIA
14
15
16
17

IU28
GND-3V3

+3V3

100p

GND-3V3

3U80

IU82

3n3

COMP
GND
GND HS

22
23
24
25
26
VIA

VIA
ENABLE+3V3

7U76-2
RT8293AHGSP

3R3

RES 2U32

VIA

3U12

IU80
8

2U31

VIA

10
11
12
13

13K

18
19
20
21

IU27

100n

IU81
+1V5

14
15
16
17
GND-1V5

EN

2U86

1M0

3U82 RES

100p

22K 1%

3U77

22K 1%

BOOT

3U13

GND-1V5

3n3

2U33
IU31

5K6
RES 2U34

GND-1V5

3U14

GND-1V5

IU78

10n

1n0
2U81

2U30

COMP
GND
GND HS

VIA

VIN

FB

220K
3U75

IU79
2
7

10n

SS

3R3

IU76
8

7U75-2
RT8293AHGSP

3U17

100n
3

2U87

SW

3U16

1n0

EN

IU30

2U05

BOOT

2U79

22
23
24
25
26

VIN

IU77
ENABLE+1V5

22u

7U76-1
RT8293AHGSP
IU75

FU76
+3V3

10u

7U75-1
RT8293AHGSP
2

5U76
IU26

22u

2U77

22u
2U78

+1V5

22u
2U85

FU75

3u6

2U84

5U75

100n

IU25

2U70

30R
2U82

2U69

22u

2U75

IU65

+12V

30R

100n

+12V

22u

5U54

470R
3U72-2 RES

3U72-1 RES

+3V3

GND-3V3

GND-3V3

GND-3V3
GND-1V5

GND-3V3

GND-1V5

GND-3V3

Bolt-On 2
DC/DC

2011-05-25

2011-03-25

8204 000 9199


19051_092_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 209

10-29 FB02 820400092002


FPGA - I/O Banks

FB02A FPGA - I/O Banks

FB02A
7T00-1
XC6SLX9-2FTG256C0100

7T00-6
XC6SLX9-2FTG256C0100

POWER
G7
G9
H10
H8
J7
J9
K10
K8

VCCO0

B13
B4
B9
D10
D7

VCCO1

D15
G13
J15
K13
N15
R13

B5
A5
D5
C5

VCCAUX

VCCO_1

BANK2

A1
A16
B11
B7
D13
D4
E9
G15
G2
G8
H12
H7
H9
J5
J8
K7
K9
L15
L2
M8
N13
P3
R10
R6
T1
T16

B6
A6
F7
E6

BL-DIM10
BL-DIM12

C7
A7
D6
C6
B8
A8
C9
A9
B10
A10

IO_L1P_HSWAPEN_0
IO_L1N_VREF_0

IO_L36P_GCLK15_0
IO_L36N_GCLK14_0

IO_L2P_0
IO_L2N_0

IO_L37P_GCLK13_0
IO_L37N_GCLK12_0

IO_L3P_0
IO_L3N_0

IO_L38P_0
IO_L38N_VREF_0

IO_L4P_0
IO_L4N_0

IO_L39P_0
IO_L39N_0

IO_L5P_0
IO_L5N_0

IO_L40P_0
IO_L40N_0

IO_L6P_0
IO_L6N_0

IO_L62P_0
IO_L62N_VREF_0

IO_L7P_0
IO_L7N_0

IO_L63P_SCP7_0
IO_L63N_SCP6_0

IO_L33P_0
IO_L33N_0

IO_L64P_SCP5_0
IO_L64N_SCP4_0

IO_L34P_GCLK19_0
IO_L34N_GCLK18_0

IO_L65P_SCP3_0
IO_L65N_SCP2_0
IO_L66P_SCP1_0
IO_L66N_SCP0_0

IO_L35P_GCLK17_0
IO_L35N_GCLK16_0

E7
E8

BL-DIM11
BL-DIM7

E10
C10

BL-SPI-CSn-OUT
BL-SPI-CLK-OUT

D8
C8

BL-DIM8
BL-DIM9

3T06

CCLK

F9
D9

BL-DIM5
BL-DIM6

R11
T11

IT00
FPGA-TX1-A+
FPGA-TX1-A-

M12
M11

MISO
MOSI

P10
T10

FPGA-RESET-SYS
3D-LR-DISP

C11
A11

10R

10R

3T12

3T08

100R

N12
P12

9T02

N11
P11

BL-DIM
FT30

B12
A12

FPGA-TX1-CLK+
FPGA-TX1-CLK-

N9
P9

C13
A13

FPGA-TX1-C+
FPGA-TX1-C-

R9
T9

FPGA-TX1-B+
FPGA-TX1-B-

L10
M10

F10
E11

BL-SPI-SDO-OUT
BL-SPI-CLK

B14
A14

M9
N8

FPGA-SYS-CLK

D11
D12

IO_L1P_CCLK_2
IO_L1N_M0_CMPMISO_2
IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2

IO_L23P_2
IO_L23N_2

IO_L29P_GCLK3_2
IO_L29N_GCLK2_2

10K

10K

CTRL-DISP
CTRL-DISPIN

100R
100R
100R
100R

FT01
FT02
FT03
FT04

VAUX

1
2
3
4
5
6

FT98

3T68

FT26

100R

F12
G11

IT03

D14
D16
F13
F14

JTAG

A15
E14
P14

TCK

C15
C16

SPLASH-ON

E15
E16

TDI
TMS

F15
F16

TDO
SUSPEND

B15
B16

IT02

7T00-5
XC6SLX9-2FTG256C0100

3T11

3T10
2T02

IO_L64P_D8_2
IO_L64N_D9_2
IO_L65P_INIT_B_2
IO_L65N_CSO_B_2

FPGA-TX1-E+
FPGA-TX1-E-

P6
T6

FPGA-RESET-SYS
FPGA-LED-1

R5
T5

FPGA-TX2-CLK+
FPGA-TX2-CLK-

N5
P5

FPGA-TX2-D+
FPGA-TX2-D-

L8
L7

FPGA-TX2-A+
FPGA-TX2-A-

P4
T4

FPGA-TX2-E+
FPGA-TX2-E-

M6
N6

FPGA-TX2-C+
FPGA-TX2-C-

R3
T3

IT22
10R

T2
L11
P13

FT8S

100n
3T07

2T01
RES

CSO-B
PROG-B
DONE

1K0

3T05

DONE

VCCO2

RESET-FRCn

7T00-4
XC6SLX9-2FTG256C0100

AUDIO-SPEAKERn
RESET-FRCn

G14
G16

3D-SYNC-120HZ

H15
H16

SD51022

3D-VS
3D-LED-S6

FT31

G12
H11
H13
H14

IO_L1P_A25_1
IO_L1N_A24_VREF_1

BANK3

IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1

3T04

IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L41N_GCLK8_M1CASN_1

IO_L30P_A21_M1RESET_1
IO_L42P_GCLK7_M1UDM_1
IO_L30N_A20_M1A11_1 IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1

IO_L43P_GCLK5_M1DQ4_1
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L44N_A2_M1DQ7_1

IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1

IO_L45P_A1_M1LDQS_1
IO_L45N_A0_M1LDQSN_1

IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1

IO_L46P_FCS_B_M1DQ2_1
IO_L46N_FOE_B_M1DQ3_1

IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1

IO_L47P_FWE_B_M1DQ0_1
IO_L47N_LDC_M1DQ1_1

IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1

IO_L48P_HDC_M1DQ8_1
IO_L48N_M1DQ9_1

IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
IO_L38N_A4_M1CLKN_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1

IO_L49P_M1DQ10_1
IO_L49N_M1DQ11_1
IO_L50P_M1UDQS_1
IO_L50N_M1UDQSN_1
IO_L51P_M1DQ12_1
IO_L51N_M1DQ13_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L53P_1
IO_L53N_VREF_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1

FPGA-RX2-CLK+
FPGA-RX2-CLK-

J11
J12

FPGA-DDR2-VREF
FPGA-DDR2-ZIO

J13
K14
K12
K11

FPGA-RX1-CLK+
FPGA-RX1-CLK-

2T00

100R

IT23

M5
N4

IT06

DT72 R2
R1

FPGA-DDR2-DQ13
FPGA-DDR2-DQ10

K15
K16

FPGA-RX2-E+
FPGA-RX2-E-

N14
N16

FPGA-RX1-E+
FPGA-RX1-E-

M15
M16

FPGA-RX2-B+
FPGA-RX2-B-

L14
L16

FPGA-RX2-D+
FPGA-RX2-D-

P15
P16

FPGA-RX1-D+
FPGA-RX1-D-

R15
R16

FPGA-RX1-C+
FPGA-RX1-C-

R14
T15

FPGA-RX1-B+
FPGA-RX1-B-

T14
T13

FPGA-RX1-A+
FPGA-RX1-ASCL-SSB
SDA-SSB

3T29
3T30

L12
L13

FPGA-RX2-C+
FPGA-RX2-C-

M13
M14

FPGA-RX2-A+
FPGA-RX2-A-

FPGA-DDR2-UDQS-P
FPGA-DDR2-UDQS-N

M4
M3

100n

P2
P1

FPGA-DDR2-DQ8
FPGA-DDR2-DQ15

J14
J16

R12 10R
T12 10R

1%

DT73
DT74

N3
N1

FPGA-DDR2-DQ14
FPGA-DDR2-DQ11

M2
M1

FPGA-DDR2-DQ12
FPGA-DDR2-DQ9

L3
L1

FPGA-DDR2-DQ0
FPGA-DDR2-DQ7

K2
K1

FPGA-DDR2-DQ2
FPGA-DDR2-DQ5

J3
J1

FPGA-DDR2-LDQS-P
FPGA-DDR2-LDQS-N

DT75 H2
H1

DT76

G3
G1

FPGA-DDR2-DQ1
FPGA-DDR2-DQ6
FPGA-DDR2-DQ4
FPGA-DDR2-DQ3

DT77

F2
F1
K3
J4

FPGA-DDR2-UDM
FPGA-DDR2-LDM

IO_L1P_3
IO_L1N_VREF_3

IO_L43P_GCLK23_M3RASN_3
IO_L43N_GCLK22_IRDY2_M3CASN_3

IO_L2P_3
IO_L2N_3

IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3

IO_L32P_M3DQ14_3
IO_L32N_M3DQ15_3

IO_L45P_M3A3_3
IO_L45N_M3ODT_3

IO_L33P_M3DQ12_3
IO_L33N_M3DQ13_3

IO_L46P_M3CLK_3
IO_L46N_M3CLKN_3

IO_L34P_M3UDQS_3
IO_L34N_M3UDQSN_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L36P_M3DQ8_3
IO_L36N_M3DQ9_3
IO_L37P_M3DQ0_3
IO_L37N_M3DQ1_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L39P_M3LDQS_3
IO_L39N_M3LDQSN_3
IO_L40P_M3DQ6_3
IO_L40N_M3DQ7_3
IO_L41P_GCLK27_M3DQ4_3
IO_L41N_GCLK26_M3DQ5_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L42N_GCLK24_M3LDM_3

IO_L47P_M3A0_3
IO_L47N_M3A1_3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L49P_M3A7_3
IO_L49N_M3A2_3
IO_L50P_M3WE_3
IO_L50N_M3BA2_3
IO_L51P_M3A10_3
IO_L51N_M3A4_3
IO_L52P_M3A8_3
IO_L52N_M3A9_3
IO_L53P_M3CKE_3
IO_L53N_M3A12_3
IO_L54P_M3RESET_3
IO_L54N_M3A11_3
IO_L55P_M3A13_3
IO_L55N_M3A14_3
IO_L83P_3
IO_L83N_VREF_3

J6
H5

FPGA-DDR2-RAS-N
FPGA-DDR2-CAS-N

H4
H3

FPGA-DDR2-A5
FPGA-DDR2-A6

L4
L5

FPGA-DDR2-A3
FPGA-DDR2-ODT

E2
E1

FPGA-DDR2-CLK-P
FPGA-DDR2-CLK-N

K5
K6

FPGA-DDR2-A0
FPGA-DDR2-A1

C3
C2

FPGA-DDR2-BA0
FPGA-DDR2-BA1

D3
D1

FPGA-DDR2-A7
FPGA-DDR2-A2

C1
B1

FPGA-DDR2-WE-N
FPGA-DDR2-BA2

G6
G5

FPGA-DDR2-A10
FPGA-DDR2-A4

B2
A2

FPGA-DDR2-A8
FPGA-DDR2-A9

F4
F3

FPGA-DDR2-CKE
FPGA-DDR2-A12

E4
E3

FPGA-DDR2-RESET-N
FPGA-DDR2-A11

DT81

DT82

FPGA-DDR2-CKE

4K7

3T00

FPGA-DDR2-RESET-N

4K7

3T01

FPGA-DDR2-CS-N

4K7

3T02

F6
F5
B3
A3

FPGA-DDR2-CS-N
FPGA-DDR2-VREF
2T68

3D-LR-FPGA-FRC

C12

DBG
1T00

100n DBG

IO_L63P_2
IO_L63N_2

IO_L16P_2
IO_L16N_VREF_2

FPGA-TX2-B+
FPGA-TX2-B-

R7
T7

3T69

DBG
1T01

IO_L62P_D5_2
IO_L62N_D6_2

P7
M7

100R
RES

C14

IO_L49P_D3_2
IO_L49N_D4_2

IO_L14P_D11_2
IO_L14N_D12_2

FPGA-TX1-D+
FPGA-TX1-D-

VCCO_3

3D-LR

3T09-1
3T09-2
3T09-3
3T09-4
FT00

IO_L48P_D7_2
IO_L48N_RDWR_B_VREF_2

IO_L13P_M1_2
IO_L13N_D10_2

P8
T8

FT06

VAUX

1
2
3
4

IO_L47P_2
IO_L47N_2

IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2

BL-SPI-CSn
BL-SPI-SDO

BANK1

8
7
6
5

IO_L32P_GCLK29_2
IO_L32N_GCLK28_2

PROGRAM_B_2
CMPCS_B_2
DONE_2

E13
E12

DBG
DBG
DBG
DBG

IO_L31P_GCLK31_D14_2
IO_L31N_GCLK30_D15_2

IO_L3P_D0_DIN_MISO_MISO1_2
IO_L3N_MOSI_CSI_B_MISO0_2

7T00-2
XC6SLX9-2FTG256C0100

1
2
3
4
5
6

IO_L30P_GCLK1_D13_2
IO_L30N_GCLK0_USERCCLK_2

VCCO_2

D2
G4
J2
K4
N2

+1V8-FPGA

GND

VCCO_0

N10
N7
R4
R8

VCCO2

C4
A4

VCCINT

E5
F11
F8
G10
H6
J10
L6
L9

VAUX

9T01
RES

LCD-PWR-ON-FPGAn

100n

+1V2-FPGA

7T00-3
XC6SLX9-2FTG256C0100

BANK0

DT83

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_093_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 210

FPGA -Supply & Control

FB02B FPGA - Supply & Control


3T86

4K7

IT19

7T15
PHD38N02LT

IT16
1

22R
+12V

RES

IT05

2T91
100n

4K7

3T41
22n

2T84

100K

330p
3T45

RES

SENSE+1V2

1K0

100n

IT47

2K2

2T83

1K0

VALUE

3T03

CPLD-SYS-CLK

IT17

3T44

RES 3T46
1

47R

2T55

3T16

FPGA-SYS-CLK
220n

2T28

220n

220n
2T27

220n
2T26

220n
2T25

2T24

7T03
3225

+1V8-FPGA

IT18

100K
4

FT09
+1V8-FPGA

RES 3T43

3T70

7T17
BC847BW
47K

SENSE+1V2

+5V

2u2

CT10

+3V3

2T23

NC

RES 2T92

NC

220n

2u2
2T21

220n
2T20

220n
2T19

22u
2T18

22u

RES 2T17

22u
2T16

100n
2T15

IT45

4K7

REF

2T14

7T16
TS431AILT
3

IT46

+1V2-FPGA

+1V2-FPGA

+1V2-FPGA
RES 2T81

2u2
2T12

2u2
2T11

220n
2T10

220n
2T09

220n
2T08

220n
2T07

2u2

FT08

3T42

30R
RES

220n
2T06

5T01
+3V3

2u2
2T05

RES 2T04

30R

10u

VAUX

+2V5

LCD-PWR-ONn

1u0
RES 2T36

9T15

LCD-PWR-ON-FPGAn

FT07

100n
3T71

5T00

1u0
2T82

3T40

IT20

9T14
RES

LCD-PWR-ON-FRCn

1u0

2T37

10u
2T80

+3V3

FB02B

+1V5

7T18
PDTC114EU

47R
3T21 RES

FRC-SYS-CLK

47R
VCCO2

VCCO1

+3V3

+3V3

+3V3

CSO-B

FT15
FT16

IT04
Q

S
HOLD

+1V8-FPGA

3T58
10K
DBG

6T09

3T35

7T10
BC847BW
DBG

1K0
DBG

7T13
BC847BW
DBG

+3V3

502382-0670

GND
4

PROGRAMMING
ENGINEERING

FT05

10K
DBG

6
1
3
7

D
C

DBG

7T12
M25P32-VMW6TG
VCC
2
Q

32M
FLASH

+1V5

3T50
4K7
DBG

DBG

DBG

7T14
BC847BW
DBG

S
W
HOLD
VSS
4

7T11
BC847BW
6T11

3T59
+1V2-FPGA
+3V3

6SLX9-4MB-M25P40
6SLX16-4MB-M25P40
6SLX25-8MB-M25P80 ---16MB-M25P16 --- 32MB-M25P32

LTST-C190KGKT

330R
LTST-C190KGKT

3T57
6T10

3T56
6T03

+1V05

6T02

100n

10R

3T15

2T54

330R

3T39
CCLK

VCC
5

DBG

DBG

DBG

3T49

MOSI

7T02
M25P40-VMN6

DBG

DBG

330R

CCLK
CSO-B
MOSI
MISO
PROG-B

FT14

DBG

DBG

3T14
1T02

4K7 RES

FT13

LTST-C190KGKT

DBG

+3V3

3T38

220n

220n
2T52

220n
2T51

220n
2T50

220n
2T49

2u2
2T48

2T47

2u2

2T46

MISO

30R

1
2
3
4
5
6

+3V3

+3V3

330R

VCCO0

330R

FT12

DBG

30R RES

+3V3

+1V8-FPGA

470R

LTST-C190KGKT

5T06

DBG 3T13

LTST-C190KGKT
7T01
PDTC144EU
2 DBG

DONE

+2V5

5T07

RES

2T13

6T00

30R

FT29

LTST-C190KGKT

220n

100n
2T45

2T44

220n

100n
2T43

220n
2T42

100n
2T41

2T40

2u2

2T39

+3V3

OUT

100n
2u2

5T05

IN

COM

RES
2T38

30R

3
+3V3

2T22

FT11

+2V5

7T09
LD1117DT18

22u 16V

5T04

6T01

DBG

30R

3T17

100n

220n
2T35

220n
2T34

220n
2T33

2u2
2T32

2T31

2u2

2T30

5T03
+3V3

DBG

FPGA-LED-1

330R

FT10

30R RES

LTST-C190KGKT

5T02
+2V5

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_094_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 211

FPGA - DDR

FB02C FPGA - DDR

FB02C

DT64
L2
L3

FPGA-DDR2-BA0
FPGA-DDR2-BA1
DT65

FPGA-DDR2-A0
FPGA-DDR2-A1
FPGA-DDR2-A2
FPGA-DDR2-A3
FPGA-DDR2-A4
FPGA-DDR2-A5
FPGA-DDR2-A6
FPGA-DDR2-A7
FPGA-DDR2-A8
FPGA-DDR2-A9
FPGA-DDR2-A10
FPGA-DDR2-A11
FPGA-DDR2-A12

DT66
DT67

M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
J8
K8

FPGA-DDR2-CLK-P
FPGA-DDR2-CLK-N

VDD
ODT
CKE
WE
CS
RAS
CAS

SDRAM
NC

0
BA
1
0
1
2
3
4
5
6 A
7
8
9
10
11
12

DQ

CK

UDM
LDM

FPGA-DDR2-UDQS-P
FPGA-DDR2-UDQS-N

3T22

3T23

33R
33R

DT70 B7
DT71 A8

LDQS

VREF

UDQS
VSS
A3
E3
J3
N1
P9

DT55

DT56

DT57

DT58

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
B3
F3

FPGA-DDR2-BA2

7
3T24-3

3T24-2

3T25-3

3T25-1

3T28-4

DT54

3T28-1

3T27-1

3T27-4

DT60
3T51
3T52

J2

6
33R
7
33R
3
33R
1
33R
4
33R
1
33R
1
33R
4
33R

5
1
4
6
7
6
7

33R

2 3T25-2
33R
4 3T25-4
33R
8 3T24-1
33R
5 3T24-4
33R
3 3T27-3
33R
2 3T27-2
33R
3 3T28-3
33R
2 3T28-2
33R

FPGA-DDR2-DQ0
FPGA-DDR2-DQ1
FPGA-DDR2-DQ2
FPGA-DDR2-DQ3
FPGA-DDR2-DQ4
FPGA-DDR2-DQ5
FPGA-DDR2-DQ6
FPGA-DDR2-DQ7
FPGA-DDR2-DQ8
FPGA-DDR2-DQ9
FPGA-DDR2-DQ10
FPGA-DDR2-DQ11
FPGA-DDR2-DQ12
FPGA-DDR2-DQ13
FPGA-DDR2-DQ14
FPGA-DDR2-DQ15
FPGA-DDR2-UDM
FPGA-DDR2-LDM

33R
FPGA-DDR2-VREF
2T67

VSSDL

33R
33R

J7

3T54

DT68 F7
DT69 E8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A2
E2
L1
R3
R7
R8

100n
VSSQ
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

150R

FPGA-DDR2-LDQS-P
FPGA-DDR2-LDQS-N

1K0 1%

VDDQ

3T20
3T53

1u0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

J1
VDDL

A1
E1
J9
M9
R1

2T03
DT62
DT63

3T18
100n

100n
2T65

100n
2T64

100n
2T63

100n
2T62

100n
2T61

2T60

100n

FPGA-DDR2-VREF

K9
K2
K3
L8
K7
L7

DT61

1K0 1%

FT17

7T04
H5PS5162GFR-S5C
FPGA-DDR2-ODT
FPGA-DDR2-CKE
FPGA-DDR2-WE-N
FPGA-DDR2-CS-N
FPGA-DDR2-RAS-N
FPGA-DDR2-CAS-N

3T19

22u

2T66

1u0

220u 2.5V
2T59

+1V8-FPGA

100n
2T57-4

100n
2T57-3

100n
2T57-2

100n
2T57-1

100n
2T56-4

100n
2T56-3

100n
2T56-2
2

2T56-1

RES
2T58

+1V8-FPGA

DT59

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_095_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 212

Output LVDS FPGA

FB02D Output LVDS FPGA

FB02D

5U53

IU63

5
6
7
8

10u

2U68

10u

10u
2U58

30R

2U57

+12V

IU66

IU67

7U05
SI4778DY-GE3

1
2
3

3U37

3R3

3U02

10R

2UH6
IU29

5
47R

3U83-4

6
47R

3U83-3
3

47R

3U83-2

8
47R

3U83-1

7U06
SI4778DY-GE3

IU03

1n0

10u

2UJ0

1
2
3

IU70

6U01

5
6
7
8

B230LA-M3

1n0

1n0
IU02

2UH9

2UH8
9

7U51
TPS53114APW

VIN

V5FILT

VREG5

+1V05

GND-1V05

22u

2UH7
1
2

2u0

22u

10n

2U60

+1V05
IU69

2U59

FU51

3R3

VO
VFB

FSEL

5U51

3U08

SS
CER

IU56
14

10

RES 2U74

IU04

IU57

IU01

22p
3U56

IU58
10u

1u0

8K2 1%
RES 3U55

GND-1V05

3U59

SENSE+1V05

10R
3U60 RES

3U57

470K

GND-1V05

3U58

2U61

100n

+1V05
GND-1V05

22K 1%

GND-1V05

2U63

18K

TRIP

15
13

2UH5

SW

PGND

5
IU60

3U03 1%

1n0

2UD1

IU45

EN

GND

11

ENABLE+1V05

DRVH
DRVL

12

VBST

16

470K

10R
2U64
1u0

IU68

GND-1V05

GND-1V05

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_096_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 213

Output - Vdisp

FB02E Output - Vdisp

FB02E

1M99

FU77
+12VD
1n0

9T10-1 8

9T10-2 7

9T10-3 6

9T10-4 5

9T11-1 8

9T11-2 7

9T11-3 6

9T11-4 5

FT18

8
7
6
5

3
2
7T05 1
SI4835DDY
RES

FT19

1T10

P12V

7T06
SI3443CDV

T 3.0A 32V

6
LCD-PWR-ONn

RES
7T19
PDTC114EU

47R

RES
2T69
IT12

2T70
IT11

1u0

IT10

100n
RES

2T72

22u

2T71

100n

3T36
82K

3T34

7T07-1
PUMD12
1

DBG
4K7

22K

IT13
IT15

RES
3T32

3TS8

22n

4
PUMD12
7T07-2

22K
RES

3T37

4K7

2T73

RES

3T31

+3V3

47R

+12VD

3T33

1-2041145-0

FU78

2UJ2

1
2
3
4
5
6
7
8
9
10

IT14

6T04

DBG

LTST-C190KGKT

VDISP-SWITCH
3

+2V5

IT01

1
2
7T21
PDTC114EU

1
2

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_097_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 214

FPGA - Bypass

FB02F

FPGA - Bypass

FB02F

FPGA-RX1-A+
FPGA-RX1-AFPGA-RX1-B+
FPGA-RX1-BFPGA-RX1-C+
FPGA-RX1-CFPGA-RX1-CLK+
FPGA-RX1-CLKFPGA-RX1-D+
FPGA-RX1-DFPGA-RX1-E+
FPGA-RX1-E-

2
1
4
3
2
1
4
3
2
1
4
3

9T36-2
9T36-1
9T36-4
9T36-3
9T37-2
9T37-1
9T37-4
9T37-3
9T38-2
9T38-1
9T38-4
9T38-3

7
8
5
6
7
8
5
6
7
8
5
6

2
1
4
3
2
1
4
3
2
1
4
3

9T30-2
9T30-1
9T30-4
9T30-3
9T31-2
9T31-1
9T31-4
9T31-3
9T32-2
9T32-1
9T32-4
9T32-3

7
8
5
6
7
8
5
6
7
8
5
6

FTF8
FTF7
FTFA
FTF9
FTFC
FTFB
FTFF
FTFE
FTFJ
FTFH
FTFL
FTFK

FPGA-TX1-A+
FPGA-TX1-AFPGA-TX1-B+
FPGA-TX1-BFPGA-TX1-C+
FPGA-TX1-CFPGA-TX1-CLK+
FPGA-TX1-CLKFPGA-TX1-D+
FPGA-TX1-DFPGA-TX1-E+
FPGA-TX1-E-

FPGA-RX2-A+
FPGA-RX2-AFPGA-RX2-B+
FPGA-RX2-BFPGA-RX2-C+
FPGA-RX2-CFPGA-RX2-CLK+
FPGA-RX2-CLKFPGA-RX2-D+
FPGA-RX2-DFPGA-RX2-E+
FPGA-RX2-E-

2
1
4
3
2
1
4
3
2
1
4
3

9T40-2
9T40-1
9T40-4
9T40-3
9T41-2
9T41-1
9T41-4
9T41-3
9T42-2
9T42-1
9T42-4
9T42-3

7
8
5
6
7
8
5
6
7
8
5
6

2
1
4
3
2
1
4
3
2
1
4
3

9T33-2
9T33-1
9T33-4
9T33-3
9T34-2
9T34-1
9T34-4
9T34-3
9T35-2
9T35-1
9T35-4
9T35-3

7
8
5
6
7
8
5
6
7
8
5
6

FTFN
FTFM
FTFQ
FTFP
FTFS
FTFR
FTFU
FTFT
FTFW
FTFV
FTFZ
FTFY

FPGA-TX2-A+
FPGA-TX2-AFPGA-TX2-B+
FPGA-TX2-BFPGA-TX2-C+
FPGA-TX2-CFPGA-TX2-CLK+
FPGA-TX2-CLKFPGA-TX2-D+
FPGA-TX2-DFPGA-TX2-E+
FPGA-TX2-E-

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_098_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 215

FPGA - Backlight dimming

5T08

100n

100n
2TCA

100n
2TC9

100n
2TC8

1u0
2TC7

1u0
2TC6

RES
2TC3

10u

1u0
2TC5

FT20

+3V3

BL-DIM12
BL-DIM11

77
78

CPLD-SYS-CLK
BL-DIM9

83
84

BL-DIM8
BL-DIM7

85
86

BL-DIM6
BL-DIM5

88
89

VCCA-O
100n

100n
2TCN

100n
2TCM

100n
2TCL

100n
2TCK

100n
2TCH

100n
2TCG

100n
2TCF

100n
2TCE

2TCD

1u0

RES
2TCB

1u0
RES
2TCC

30R

IT80

90
93

IT83
IT84

94

IT91
3TCE

98
99

RES
1K0

97
82

56
57

3D-SYNC-120HZ
3D-LED-S3A
DBG 3TCB

59
60

SPLASH-ON

+3V3

470R

LTST-C190KGKT

DBG

RESET-FRCn

+3V3

RES
3T67

RESET-FRCn

100R

VCCA-O

100n

10R

7TC2
M25P05-AVMN6

FT91

DBG
1T05

DBG 3T47-1
DBG 3T47-2
DBG 3T47-3
DBG 3T47-4
FT25

FT92

DT34

72
73

1
2
3
4

8
7
6
5

1
2
3
4
5
6

100R
100R
100R
100R

+3V3

100
1
2
75
76

FT21
FT22
FT23
FT24

IO_L02P_2|M2
IO_L02N_2|CSO_B

BANK0

IO_L02P_0|GCLK4
IO_L02N_0|GCLK5

IO_L03P_2|RDWR_B
IO_L03N_2|VS1

BANK2

IO_L04P_2|VS2
IO_L04N_2|VS0

IO_L03P_0|GCLK6
IO_L03N_0|GCLK7

IO_L05P_2
IO_L05N_2|D7

IO_L04P_0|GCLK8
IO_L04N_0|GCLK9

IO_L06P_2
IO_L06N_2|D6

IO_0|GCLK11
IO_L05P_0

IO_L07P_2|D5
IO_L07N_2|D4

IO_L05N_0
IO_L06P_0|VREF_0
IO_L06N_0|PUDC_B

IO_L08P_2|GCLK14
IO_L08N_2|GCLK15
IO_L09P_2|GCLK0
IO_L09N_2|GCLK1

IP_0
IP_0|VREF_0

IO_L10P_2|INIT_B
IO_L10N_2|D3
IO_L01P_1
IO_L01N_1

BANK1

IO_L02P_1|RHCLK0
IO_L02N_1|RHCLK1

IO_L11P_2|D2
IO_L11N_2|D0|DIN|MISO
IO_L12P_2|D1
IO_L12N_2|CCLK

IO_L03P_1|RHCLK2
IO_L03N_1|TRDY1|RHCLK3
IO_L04P_1|IRDY1|RHCLK6
IO_L04N_1|RHCLK7

IP_2|VREF_2
IO_2|MOSI|CSI_B

IO_L01P_3
IO_L01N_3

BANK3

IP_1|VREF_1

IO_L02P_3
IO_L02N_3

IO_L03P_3|LHCLK0
IO_L03N_3|LHCLK1

DONE
IO_L04P_3|LHCLK2
IO_L04N_3|IRDY2|LHCLK3

PROG_B
TMS
TDI
TDO
TCK

IO_L05P_3|TRDY2|LHCLK6
IO_L05N_3|LHCLK7
IO_L06P_3
IO_L06N_3

+3V3
IP_3|VREF_3

SD51022

1K0

1K0

23
25
24
27

3TC5

28
30

3TCF

29
31

3TC7
3TCG

32
34

10R

RES
1K0
RES
1K0
RES
1K0

33
35

SP3A-CSO-B

BL-SPI-CLK-OUT
BL-SPI-CSn-OUT
BL-SPI-SDO-OUT

36
37
40
41
43
44

SP3A-LED-4

48
49

SP3A-LED-3
SP3A-LED-2

50
51

SP3A-LED-1
SP3A-MISO

52
53

3TC8

46

SP3A-CCLK
10R

39
3TC4

SP3A-MOSI
10R

IO_L05P_1
IO_L05N_1
IO_L06P_1
IO_L06N_1

3TC3

VCCINT
IO_L01P_2|M1
IO_L01N_2|M0

1K0

VCCAUX

3TC2 RES

3TC1

17
38
66
81

45
26

VCCO_3 11

FB02G

VCCINT

IP_3

3
4

BL-SPI-CLK
BL-SPI-CSn

5
6

BL-SPI-SDO

9
10

CTRL-DISPIN
AUDIO-SPEAKERn

12
13

CTRL-DISP
3D-LR-DISP

15
16

3TCH
3TCK

10R

SCL-SSB
SDA-SSB

10R

19
20

3D-LR
3D-VS

BL-DIM

21

GND

SP3A-LED-4

1 330R 8
LTST-C190KGKT

2 330R 7

DBG 3T48-1
DBG
6T08

3 330R 6

DBG 3T48-2
6T07

LTST-C190KGKT

DBG

LTST-C190KGKT

DBG

DBG 3T48-3

SP3A-LED-1

6T06

PROGRAMMING
ENGINEERING

SP3A-LED-2

DBG 3T48-4

502382-0670

SP3A-LED-3

DBG

1
2
3
4
5
6

6T05

1K0

FT90

DBG
1T06

HOLD

70
71

54

1
2
3
4
5
6

1T03

DT32
DT33

68

SP3A-DONE

SP3A-CCLK
SP3A-CSO-B
SP3A-MOSI
SP3A-MISO
SP3A-PROG-B

64
65

SP3A-PROG-B
SP3A-MISO

VSS

DT30
DT31

IO_L01P_0|VREF_0
IO_L01N_0

VCCA-O

8
14
18
42
47
58
63
69
74
80
87
91
95

FT87

100n

512K
FLASH

3TCD

DBG

3TC9

2TCP

RES

IT38

2T78

FT89

VCC

4 330R 5

SP3A-CSO-B

FT88

*
5

BL-DIM10

LTST-C190KGKT

SP3A-CCLK

FT86

4K7

3TCC

IT37

SP3A-MOSI

61
62

VCCA-O

4K7

SP3A-DONE

3 6TC1

3TCA RES

7TC1
PDTC144EU
DBG

VCCO_2

1u0
RES 2TC4

VCCINT

COM

67

VCCO_0

FT85

OUT

100n

2TC1

IN

2TC2

+3V3

VCCO_1

7T08
XC3S50A-4VQG100

7TC3
LD1117DT12

79
96

VCCA-O

22
55
92

FB02G FPGA - Backlight dimming

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_099_110706.eps
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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 216

Audio & WiHD

FB02H Audio & WiHD

FB02H

4K7

FTB1
3TB2

ITB0

FTB2

100R

1W35
1
2
3
4

2TB1

AUDIO-SPEAKERn

100n

3TB1

+3V3

502386-0370

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_100_110706.eps
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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 217

FRC - LVDS input

FB02I

Audio & WiHD

FB02I

FPGA-TX1-A+
3TCL

100R

3TCM

100R

3TCN

100R

3TCP

100R

3TCQ

100R

3TCR

100R

3TCS

100R

3TCT

100R

3TCU

100R

3TCV

100R

3TCW

100R

3TCY

100R

FPGA-TX1-AFPGA-TX1-B+

7T20-2
TFRCV-B1A05/H

FPGA-TX1-BFPGA-TX1-C+

H1
H2
J3
H3
J2
J1
K1
K2
L3
K3
L2
L1

FPGA-TX1-CFPGA-TX1-CLK+
FPGA-TX1-CLKFPGA-TX1-D+
FPGA-TX1-DFPGA-TX1-E+
FPGA-TX1-E-

M1
M2
N3
M3
N2
N1
P1
P2
R3
P3
R2
R1

FPGA-TX2-A+
FPGA-TX2-AFPGA-TX2-B+
FPGA-TX2-BFPGA-TX2-C+
FPGA-TX2-CFPGA-TX2-CLK+
FPGA-TX2-CLKFPGA-TX2-D+

LVDS_IN
PA_0
NA_0
PA_1
NA_1
PA_2
NA_2
RXIN
CKPA
CKNA
PA_3
NA_3
PA_4
NA_4
PB_0
NB_0
PB_1
NB_1
PB_2
NB_2 RXIN
CKPB
CKNB
PB_3
NB_3
PB_4
NB_4

FPGA-TX2-DFPGA-TX2-E+
FPGA-TX2-E-

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_101_110706.eps
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2011-Sep-09 back to

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Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 218

FRC - Control

FRC - Control

FB02J
7T20-9
TFRCV-B1A05/H

SPI_FLASH

DEBUG
1T23

FTC9
FTD5

FTD6

RXD0

EJT-TDI
EJT-TDO
EJT-TCK
EJT-TMS
EJT-TRSTN
RESET-FRCn
TXD0
RXD0
FRC-SYS-CLK

BM03B-SRSS-TBT

3
1

2TD1
EJT-TRSTN
EJT-TMS
EJT-TDO
EJT-TCK
EJT-TDI

FTA8
FTA9
FTB3
FTB4

3TD7
6
100R
3TD5-2 2
8
100R

2
4

3T26

+3V3

3TDF
47R
4K7

1K0

3TDH

RES
4K7

IN
XTAL
OUT
SCL
I2C
SDA

A23
B22
A22
G3

FTC0

9TD1
RES
+3V3

TXD
RXD

C24
B24

47R

3TDG
3TDJ

IN
RESET
OUT

AC25
AD26

220R

FTB5

502382-0670

TDI
TDO
TCK
TMS
TRESET

A24
C23

22p

SCL-FRC
SDA-FRC

C1
C3
C2
B2
D1

9T17 RES
22p

4K7

4K7
3TD4

4K7

3TD3

4K7
3TD2

4K7

FTA7

3TD8

1
2
3
4
5
6

B23
C22
2TD0

3TD1

DEBUG
1T20

3TD0 RES

+3V3

3TD5-4 4
100R
3TD5-3 3
100R
3TD5-1 1
100R

TEST_CON
TEST_MODE
LMAST
CFG_PLL

FTC1

RX_ATESTA
RX_ATESTB
TX_ATEST
MCK2_TEST
DFT_OUT_KMNPLL

9TD3
IT70
3TDK RES
+3V3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
PROBE_OUT

0
1
DATA SF
2
3
CLK
CS

24M

TXD0

A4
B4
C4
D5
B3
A3

SF-SI
SF-SO
SF-WPn
SF-HOLDn
SF-SCK
SF-CS

1T21

1
2
3

F3
G1
G2
T1
T2 100R
T3
U1
U2
U3
V1
V2
V3
W1
W2
W3
Y1
Y2
Y3
AA1
AA2
D2
D3
E1
E2
E3
F1
F2
A21
B21
C21
AD25

3T82
3T81

100R
3T75
RES

100R

3T80

100R
RES 3TDA

LCD-PWR-ON-FRCn
CTRL-DISP
3D-LR-DISP
VSYNC-FRC
AUDIO-SPEAKERn

3T83

CTRL-DISP
3D-LR-DISP

+3V3
3T85

4K7 RES
+3V3

4K7 RES

SCL-SSB
SPLASH-ON

10R

9T27
RES

3TDC
BL-ON

10R
3TDD
10R
3TDB

SDA-SSB

RES 10R
IT48
3T76
3T77
47R
3T79
100R

9T26
FTH8
47R FTH9
3T78
FTJ0
47R
3T55
100R

BL-ON
SPLASH-ON
BL-SPI-SDO
BL-SPI-CLK
BL-SPI-CSn
VSYNC-FRC
3D-LR
3D-LR-FPGA-FRC
TXD1
RXD1

3T84

BL-ON

+3V3
4K7 RES

TXD1

DEBUG
1T24

FTD7
FTD8

RXD1
5

FTD9

UART-3V3
FOR DEBUG

1
2
3

BM03B-SRSS-TBT
T4
T5
D20
AA25
Y23

4K7

FTB6

+3V3
+3V3-SFB

IT71

RES

4K7

RESET-FRCn

9TD0
+3V3

NC GND

1
2
3

SCL-FRC

7T30
M25P16

FTB8

VCC
SDA-FRC

FTB9

FTC2

SFB-SI
SFB-SCK

FTC3

SFB-CS

FTC4

SFB-WPn

FTC5

BM03B-SRSS-TBT

3TR1

16M
FLASH

S
W
HOLD
VSS

2TS1
FTC7

100n
3TR2

SFB-SI
SF-SO

47R

EN

3TDT

FTC8
47R

SFB-EN

47R

47R

7T60-1
SN74LVC125APW
2

14

4K7

+3V3

ITD0

FTC6

SFB-HOLDn

3TDP RES

SF-SI
+3V3-SFB

4K7

4K7

3TDN

4K7
3TDM

4K7

3TDL

100n
3TDU

FTB7

100K DBG

100K
3TDW

3TDV DBG

220n

2TD3

DEBUG
1T22

3TR0

30R

CD

3TDE
+3V3

5TDA

INP
OUTP

4K7

7T25
NCP303LSN28
2

+3V3

3TD9

9TD2

2TD2
SF-SCK

+3V3

3TR3

3TR4

6
SFB-SCK
1

47R

EN
7

3
9TR1

SF-CS
+3V3

RES
VCC

47R

SFB-EN

7T31
M25P32-VMW6TG

47R

14

7T60-2
SN74LVC125APW
5

RES

3TDQ

RES

D
C

32M
FLASH

S
W
HOLD
VSS

+3V3

RES

7T60-4
SN74LVC125APW
12

11

47R

13

3TR8

PROGRAMMING
ENGINEERING

SFB-WPn

47R

EN

3TDS RES

SF-HOLDn

47R

EN

FT99

IT74
3
RES
7T41
PDTC114EU

1
2

IT72

3D-VS

100n
4

BL-ON

9T19

2TS0

10R

3TS1

3TG3

VSYNC-FRC
SFB-HOLDn

47R

47R

IT73

RES
7T40
PDTC144EU

1
2
10u

FT28

7T61
74LVC1G125GW
2

RES

SFB-EN

ITD2

2TD4

4K7
3TS2

3TS0
+3V3-SFB

47R

+3V3

3TG4
+3V3
3TG2 RES

SFB-EN

1K0

ITD1

502382-0670

2K2

4K7
3TR7

47R

+3V3
14

3TR6
+3V3-SFB

3TR5

3TDR

SF-WPn

BL-ON-OUT

3TG6

SFB-EN

1K0

SFB-CS

3TG5 RES

3TT1
47R

EN
7

10

14

47R

SFB-EN

1
2
3
4
5
6

1K0

3TT0

7T60-3
SN74LVC125APW
9

1T25

FB02J

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_102_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 219

FRC - DDR I/O

FB02K FRC - DDR I/O

FB02K
7T20-1
TFRCV-B1A05/H

UMAC1-CAS
UMAC1-RAS
UMAC1-WE
UMAC1-CKE
UMAC1-ODT
3TE4

AE10
AD10
AB17
AD17

+1V5

240R
1%

AC9
AC18

UMAC1-MRES
ITF3
ITF2
ITF1

100n

0
1
MMANA_TEST

MMDIG_TEST

AD14
AC14
AD13
AF15
AE13
AC17

RES

100n

MMRESETN

UMAC1-MCLK0
UMAC1-MCLK0-N

RES

100n

0
1

AF14
AE14

RES

100n

MMVREF

UMAC1-BA0
UMAC1-BA1
UMAC1-BA2

2TF2

MMCASN
MMRASN
MMWEN
MMCKE
MMODT
MZQ

AC12
AC15
AF13

2TF3

P
N

UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13
UMAC1-MA14

RES

FTE0

2TF1

DT51

MMCK

AD12
AB15
AF12
AE12
AF16
AC11
AD16
AE11
AC16
AD11
AE15
AE16
AD15
AF11
AB16

2TF5

DT50

0
N0
1
N1
MMDQS
2
N2
3
N3

0
MMBA 1
2

UMAC1-DQM0
UMAC1-DQM1
UMAC1-DQM2
UMAC1-DQM3

1K0 1%

DT49

AE4
AD4
AD8
AE8
AD18
AD19
AE22
AD22

0
1
2
3
4
5
6
MMA 7
8
9
10
11
12
13
14

AF5
AF8
AE19
AF23

1K0 1%

DT45

0
1
MMDM
2
3

3TE0

UMAC1-DQS0
UMAC1-DQS0-N
UMAC1-DQS1
UMAC1-DQS1-N
UMAC1-DQS2
UMAC1-DQS2-N
UMAC1-DQS3
UMAC1-DQS3-N

DRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 MMDQ
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

3TE1

DT43 AF3
AE3
AD3
AF4
AE5
AD5
AD6
AE6
AF6
AF7
AD7
AE7
AD9
AE9
AF9
AF10
AE17
AF17
AF18
AE18
AF19
AF20
AE20
AD20
AF21
AE21
AD21
AF22
AE23
AD23
AF24
DT44
AE24

100n

UMAC1-MD0
UMAC1-MD1
UMAC1-MD2
UMAC1-MD3
UMAC1-MD4
UMAC1-MD5
UMAC1-MD6
UMAC1-MD7
UMAC1-MD8
UMAC1-MD9
UMAC1-MD10
UMAC1-MD11
UMAC1-MD12
UMAC1-MD13
UMAC1-MD14
UMAC1-MD15
UMAC1-MD16
UMAC1-MD17
UMAC1-MD18
UMAC1-MD19
UMAC1-MD20
UMAC1-MD21
UMAC1-MD22
UMAC1-MD23
UMAC1-MD24
UMAC1-MD25
UMAC1-MD26
UMAC1-MD27
UMAC1-MD29
UMAC1-MD28
UMAC1-MD30
UMAC1-MD31

+1V5

3TE2

1K0 1%
1K0 1%

2TF8

DT48

3TE3

DT47

FTE1

100n

DT46

2TF4

DT80

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_103_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 220

FRC - Supply analog

FRC - Supply analog

FB02L

7T20-5
TFRCV-B1A05/H

5TDH

IT82
100n

30R

10u
2TDB

+2V5

T23
U22

LVDS_AVDD_YZ_1|4
LVDS_AVDD_YZ_2|3
PLL_AVDD_Y
LVDS_AVSS_YZ_1|4
LVDS_AVSS_YZ_2|3
PLL_AVSS_Y

LVDS_AVDD_YZ_3|2
LVDS_AVDD_YZ_4|1
AVDD25_PLL_VBO LVDS_AVSS_YZ_3|1
AVSS_PLL_VBO
LVDS_AVSS_YZ_4|2
PLL_VDD
PLL_VSS

D7
D6
E6
E7
AC13
AB14

47u

2TFB

10u

100n
2TDP

2TDQ

D19
D17
D18
E19
E17
E18

10u

100n
2TDN

10u

100n

10u
2TDF

2TDE

30R

AVDD25_RXPLLB
AVDD25_RXPLLA
AVDD25_RX_1|1
AVDD25_RX_2|2
AVSS_RXVCOA
AVSS_RXVCOB
AVSS_RX_1|1
AVSS_RX_2|2

10u

IT79

+2V5

R4
P4
M4
N4
N5
P5
M5
R5

5TDD

IT81

+2V5
30R
2TDG

5TDC

100n
2TF9

AB26
AC26

100n

10u
2TDK

2TDJ

30R

30R

IT78

G23
E23
F23
G22
E22
F22

100n
2TFA

IT77

+2V5

AVDD25_KMNPLL
AVDD25_MCK2PLL
AVSSKMNPLL
LVDS_AVDD_WX_3|2
AVSSMCK2PLL
LVDS_AVDD_WX_4|1
AVSSMCK2VCO
PLL_AVDD_X
LVDS_AVSS_WX_3|2
AVDD25_REF
LVDS_AVSS_WX_4|1
AVSS_REF
PLL_AVSS_X

2TDH
10u

5TDE

AA26
AB25
AA23
AA24
AB24

100n

100n

10u
2TDD

2TDC

30R

+2V5

2TDR

LVDS_AVDD_WX_1|4
LVDS_AVDD_WX_2|3
LVDS_AVSS_WX_1|4
LVDS_AVSS_WX_2|3

U23
R23
V22
T22

2TDM

+2V5

5TDG

PWR_ANA

IT75

2TDL

5TDB

2TDA

FB02L

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_104_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 221

FRC - Supply digital

FB02M FRC - Supply digital

FB02M
7T20-6
TFRCV-B1A05/H
H4
J4
K4
L4
J5
K5
L5
J6
K6
L6
K7
L7
M7
N7
P7
D8
E8
L8
M8
N8
P8
D9
E9
D10
E10
D11
E11
D12
E12
F12
G12
H12
D13
E13
F13
G13
H13
D14
E14
F14
G14
H14
D15
E15
F15
G15
H15
D16
E16
M19
N19
P19
R19
L20
M20
N20
P20
R20
T20
L21
M21
N21
P21
R21
T21
H22
J22
K22
L22
M22
N22
P22
R22
H23
J23
K23
L23
M23
N23
P23

+1V05

+1V05

AB1
AC1
AD1
AB2
AC2
AD2
AB3
AC3
AB4
AC4
AB5
AC5
AB6
AC6
AB7
AC7
AB8
AC8
AB9
AB10
AC10
AB11
W12
Y12
AA12
AB12

+1V5

PWR_DIG_M
1|1
2|2
3|3
4|4
5|5
6|6
7|7
8|8
9|9
10|10
11|11
12|12
13|13 VDDM
14|14
15|15
16|16
17|17
18|18
19|19
20|20
21|21
22|22
23|23
24|24
25|25
26|26

W13
Y13
AA13
AB13
W14
Y14
AA14
W15
Y15
AA15
AA16
AA17
AA18
AB18
AB19
AC19
AB20
AC20
AB21
AC21
AB22
AC22
AB23
AC23
AC24
AD24

27|27
28|28
29|29
30|30
31|31
32|32
33|33
34|34
35|35
36|36
37|37
38|38
VDDM 39|39
40|40
41|41
42|42
43|43
44|44
45|45
46|46
47|47
48|48
49|49
50|50
51|51
52|52

7T20-8
TFRCV-B1A05/H

+3V3
D4
E4
F4
G4
E5
F5
G5
H5
G6
H6
G7
H7
E20
D21
E21
D22
D23
D24
B25
C25
D25
C26
D26

1|1
2|2
3|3
4|4
5|5
6|6
7|7
8|8
9|9
10|10
11|11
VDDF1 12|12
13|13
14|14
15|15
16|16
17|17
18|18
19|19
20|20
21|21
22|22
23|23

AA3
U4
V4
W4
Y4
AA4
U5
V5
W5
Y5
AA5

1|1
2|2
3|3
4|4
5|5
VDDF2 6|6
7|7
8|8
9|9
10|10
11|11

+3V3

+1V05

10n

2TMA

10u
2TMB

10n
2TMC

10n
2TMD

10n
2TME

10n

100n
2TMR

100n
2TMS

100n
2TMT

100n
2TMU

100n
2TMV

100n

10n
2TEN

100n
2TMQ

10n
2TEM

10n
2TEL

10n
2TEK

100n
2TEJ

100n
2THE

10u
2THD

1n0

1n0
2TFF

1n0
2TFE

1n0
2TFD

1n0
2TF7

10n
2TF6

10n
2TMP

10n
2TMN

10n
2TMM

10n
2TEZ

100n
2TEY

100n
2TML

100n
2TMK

100n
2TMF

100n
2TEW

10u
2TEV

2THC

+3V3

+1V5

10u
2TFC

100n
2TEH

100n
2TEG

100n
2TEF

100n
2TEE

100n
2TED

10u
2TEC

2TEB

10n

10n
2TEA

10n
2TE8

100n
2TE7

100n
2TE6

100n
2TE5

100n
2TE4

100n
2TE3

100n
2TE2

220u 2.5V
2TE0

2THL

220u 2.5V
2THK

10u
2TE1

FTH7

CT00

2TT1

SENSE+1V05

220u 2.5V
2TEU

+1V5

7T20-7
TFRCV-B1A05/H

PWR_DIG
1|1
2|2
3|3
4|4
5|5
6|6
7|7
8|8
9|9
10|10
11|11
12|12
13|13
14|14
15|15
16|16
17|17
18|18
19|19
20|20
21|21
22|22
23|23
24|24
25|25
26|26
27|27
28|28
29|29
30|30
31|31
32|32
33|33
34|34
35|35
36|36
37|37
38|38
39|39
40|40 VDDC
41|41
42|42
43|43
44|44
45|45
46|46
47|47
48|48
49|49
50|50
51|51
52|52
53|53
54|54
55|55
56|56
57|57
58|58
59|59
60|60
61|61
62|62
63|63
64|64
65|65
66|66
67|67
68|68
69|69
70|70
71|71
72|72
73|73
74|74
75|75
76|76
77|77
78|78
79|79
80|80

A1
B1
AE1
AF1
A2
AE2
AF2
F6
M6
N6
P6
R6
T6
U6
V6
W6
Y6
AA6
F7
J7
R7
T7
U7
V7
W7
Y7
AA7
F8
G8
H8
J8
K8
R8
T8
U8
V8
W8
Y8
AA8
F9
G9
H9
J9
K9
L9
M9
N9
P9
R9
T9
U9
V9
W9
Y9
AA9
F10
G10
H10
J10
K10
L10
M10
N10
P10
R10
T10
U10
V10
W10
Y10
AA10
F11
G11
H11
J11
K11
L11
M11
N11
P11
R11
T11
U11
V11
W11
Y11
AA11
J12
K12
L12
M12
N12
P12
R12
T12
U12
V12
J13
K13
L13
M13
N13
P13
R13
T13
U13
V13

PWR_DIG_VSS
1|1
2|2
3|3
4|4
5|5
6|6
7|7
8|8
9|9
10|10
11|11
12|12
13|13
14|14
15|15
16|16
17|17
18|18
19|19
20|20
21|21
22|22
23|23
24|24
25|25
26|26
27|27
28|28
29|29
30|30
31|31
32|32
33|33
34|34
35|35
36|36
37|37
38|38
39|39
40|40
41|41
42|42
43|43
44|44
45|45
46|46
47|47
48|48
49|49
50|50
51|51
52|52
53|53
VSS
54|54
55|55
56|56
57|57
58|58
59|59
60|60
61|61
62|62
63|63
64|64
65|65
66|66
67|67
68|68
69|69
70|70
71|71
72|72
73|73
74|74
75|75
76|76
77|77
78|78
79|79
80|80
81|81
82|82
83|83
84|84
85|85
86|86
87|87
88|88
89|89
90|90
91|91
92|92
93|93
94|94
95|95
96|96
97|97
98|98
99|99
100|100
101|101
102|102
103|103
104|104
105|105
106|106
107|107

108|108
109|109
110|110
111|111
112|112
113|113
114|114
115|115
116|116
117|117
118|118
119|119
120|120
121|121
122|122
123|123
124|124
125|125
126|126
127|127
128|128
129|129
130|130
131|131
132|132
133|133
134|134
135|135
136|136
137|137
138|138
139|139
140|140
141|141
142|142
143|143
144|144
145|145
146|146
147|147
148|148
149|149
150|150
151|151
152|152
153|153
154|154
155|155
156|156
157|157
158|158
159|159
160|160
VSS 161|161
162|162
163|163
164|164
165|165
166|166
167|167
168|168
169|169
170|170
171|171
172|172
173|173
174|174
175|175
176|176
177|177
178|178
179|179
180|180
181|181
182|182
183|183
184|184
185|185
186|186
187|187
188|188
189|189
190|190
191|191
192|192
193|193
194|194
195|195
196|196
197|197
198|198
199|199
200|200
201|201
202|202
203|203
204|204
205|205
206|206
207|207
208|208
209|209
210|210
211|211
212|212
213|213

J14
K14
L14
M14
N14
P14
R14
T14
U14
V14
J15
K15
L15
M15
N15
P15
R15
T15
U15
V15
F16
G16
H16
J16
K16
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
F17
G17
H17
J17
K17
L17
M17
N17
P17
R17
T17
U17
V17
W17
Y17
F18
G18
H18
J18
K18
L18
M18
N18
P18
R18
T18
U18
V18
W18
Y18
F19
G19
H19
J19
K19
L19
T19
U19
V19
W19
Y19
AA19
F20
G20
H20
J20
K20
U20
V20
W20
Y20
AA20
F21
G21
H21
J21
K21
U21
V21
W21
Y21
AA21
Y22
AA22
A25
AE25
AF25
A26
B26
AE26
AF26

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_105_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 222

Input - LVDS

FB02N Input - LVDS

RES 100R
FS26
FS27

100p

100p

100p

100p

RES 2S85

RES 2S83

100p
RES 2SA4

RES 2S86

100p
RES 2SA1

RES 2S80

10p

100p
RES 2SA3

10p
RES

RES 2S82

100p
2S84
3S53
3S51

100R
100R

3S44
10R

2SA2

3D-LED-S3A
3D-LED-S6
CTRL-DISPIN
SDA-SSB
SCL-SSB
BL-ON-OUT

RES

FB02N

1G51
FS10
FS11
FS12
FS24
FS23

3S40
10R
3S41

100R

3S42

3S48

BL-DIM

100R

CTRL-DISPIN

10R
3D-LRIN
3D-VSIN
SPLASH-ON
CTRL-DISPIN

3S49
100R
RES
3S43

FS22 100R

FS21

FS28
3S46
100R
100R

FSA6

FPGA-RX1-AFPGA-RX1-A+
FPGA-RX1-BFPGA-RX1-B+
FPGA-RX1-CFPGA-RX1-C+

FS30
FS29

3S45
RES
3SA1
RES

FS09

FS79
FS31
FS32
FS33

FS34
FS35
FS36
FS80
FS37

FPGA-RX1-CLKFPGA-RX1-CLK+

FS38
FS81
FS39

FPGA-RX1-DFPGA-RX1-D+
FPGA-RX1-EFPGA-RX1-E+

FS40
FS41
FS42
10p
FS43

FPGA-RX2-AFPGA-RX2-A+
FPGA-RX2-BFPGA-RX2-B+
FPGA-RX2-CFPGA-RX2-C+

RES
2SA6

RES
210p

IS51
2SA5
1 IS52

FS44
FS45
FS46
FS47
FS48
FS49

FPGA-RX2-CLKFPGA-RX2-CLK+

FS50
FS51

FPGA-RX2-DFPGA-RX2-D+
FPGA-RX2-EFPGA-RX2-E+

FS52
FS53
FS54

IS05

1T09 RES

FS93

9S21
RES

9S05-2

9S05-3

9S05-4

CTRL-DISPIN

RES
9S04
RES
9S06
RES
9S01

3D-LRIN

RES
9S02

3D-LR

3D-VSIN

RES
9S03

3D-VS

4K7

9S05-1

3S52

T 2.0A 63V

FS55
FS56

FS25
DBG

52 53
54 55
56 57
58 59
60 61

FI-RE51S-HF

CTRL-DISP

FROM SSB
6S00

ENABLE+3V3

DBG

RESET-FRCn
LTST-C190CKT

+12V
RES
7S00
PDTC114EU

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

ENABLE+3V3
RES
7S01
PDTC114EU

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_106_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 223

I2C-Multiplexer & I2C-Temperature sensor


2

FB02O I C-Multiplexer & I C-Temperature sensor

FB02O

+3V3
2SG1

100n
7SG1
PCA9540B

VDD

SCL-SSB

SDA-SSB

I2 C
-BUS
CTRL

INP
FIL

SDA

SC1

SD0

SD1

SCL-DISP

SDA-DISP

SCL-DISP

SDA-DISP

3SG2

+3V3

SCL

SC0

VSS

SCL-SSB

RES 3SG6

+3V3

4K7
RES 3SH0
4K7

10K
3SG9

SDA-SSB

10K
9SG4

SCL-SSB

DBG
1SG2
1
2
3
4
5
6
7
8

SCL-DISP
RES

PROGRAMMING ENGINEERING

9SG5

SDA-SSB
3SH2
47R

SDA-DISP
RES

DBG
SCL-SSB
3SH3 DBG
47R

SDA-SSB
CTRL-DISP
3D-LR-DISP

+12V
9 10

+12VD

502382-0870

A1

SCL

A2

1K0

3TS3

9TS2
RES

9TS1
RES
ITS3

ITS5

ITS4

9TS3
RES

SDA

1K0

A0

3TS7

ITS2

OS

1K0

ITS1

10R

100n

2TS2

3TS4

+VS

1K0

DTS1

3TS6

10R

7SG2
LM75BDP

GND

SCL-SSB

3TS5

DBG

SDA-SSB

DBG

LTST-C190KGKT

6T15

3SG8

+3V3

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_107_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 224

FRC LVDS output

FB02P

FRC LVDS output

FB02P
7T20-3
TFRCV-B1A05/H
LVDS_OUT-W-Z

7T20-4
TFRCV-B1A05/H

TXP_WA_0
TXN_WA_0

LVDS_OUT-X-Y
TXP_XA_0
TXN_XA_0
TXP_XA_1
TXN_XA_1
TXP_XA_2
TXN_XA_2
CLKP_XA
CLKN_XA
TXP_XA_3
TXN_XA_3
TXP_XA_4
TXN_XA_4

TXP_XB_0
TXN_XB_0
TXP_XB_1
TXN_XB_1
TXP_XB_2
TXN_XB_2
CLKP_XB
CLKN_XB
TXP_XB_3
TXN_XB_3
TXP_XB_4
TXN_XB_4

TXP_YA_0
TXN_YA_0
TXP_YA_1
TXN_YA_1
TXP_YA_2
TXN_YA_2
CLKP_YA
CLKN_YA
TXP_YA_3
TXN_YA_3
TXP_YA_4
TXN_YA_4

TXP_YB_0
TXN_YB_0
TXP_YB_1
TXN_YB_1
TXP_YB_2
TXN_YB_2
CLKP_YB
CLKN_YB
TXP_YB_3
TXN_YB_3
TXP_YB_4
TXN_YB_4

E25
E26

TX4-A+
TX4-A-

E24
F24

TX4-B+
TX4-B-

F26
F25

TX4-C+
TX4-C-

G26
G25

TX4-CLK+
TX4-CLK-

H24
G24

TX4-D+
TX4-D-

H25
H26

TX4-E+
TX4-E-

J26
J25

TX5-A+
TX5-A-

K24
J24

TX5-B+
TX5-B-

K25
K26

TX5-C+
TX5-C-

L26
L25

TX5-CLK+
TX5-CLK-

M24
L24

TX5-D+
TX5-D-

M25
M26

TX5-E+
TX5-E-

TXP_WA_1
TXN_WA_1
TXP_WA_2
TXN_WA_2
CLKP_WA
CLKN_WA
TXP_WA_3
TXN_WA_3
TXP_WA_4
TXN_WA_4

N26
N25

BT23
BT24

P24
N24
P25
P26

BT21
BT22
BT19
BT20

R26
R25
T24
R24
T25
T26

TX6-A+
TX6-A-

TX6-C+
TX6-CBT17
BT18

BT15
BT16

TX6-B+
TX6-B-

BT00

TX6-CLK+
TX6-CLKTX6-D+
TX6-DTX6-E+
TX6-E-

BT01
TXP_WB_0
TXN_WB_0
TXP_WB_1
TXN_WB_1
TXP_WB_2
TXN_WB_2
CLKP_WB
CLKN_WB
TXP_WB_3
TXN_WB_3
TXP_WB_4
TXN_WB_4

U26
U25
V24
U24
V25
V26
W26
W25
Y24
W24
Y25
Y26

BT02
BT03

BT06
BT08

BT11
BT12

TX7-A+
TX7-ABT04

TX7-B+
TX7-B-

BT05
TX7-C+
TX7-CBT09

TX7-CLK+
TX7-CLK-

BT10
TX7-D+
TX7-DBT13

TX7-E+
TX7-E-

BT14
TXP_ZA_0
TXN_ZA_0

A13
B13

TX2-A+
TX2-A-

C14
C13

TX2-B+
TX2-B-

B14
A14

TX2-C+
TX2-C-

A15
B15

TX2-CLK+
TX2-CLK-

C16
C15

TX2-D+
TX2-D-

B16
A16

TX2-E+
TX2-E-

A17
B17

TX3-A+
TX3-A-

TXP_ZB_1
TXN_ZB_1

C18
C17

TX3-B+
TX3-B-

TXP_ZB_2
TXN_ZB_2

B18
A18

TX3-C+
TX3-C-

CLKP_ZB
CLKN_ZB

A19
B19

TX3-CLK+
TX3-CLK-

TXP_ZB_3
TXN_ZB_3

C20
C19

TX3-D+
TX3-D-

TXP_ZB_4
TXN_ZB_4

B20
A20

TX3-E+
TX3-E-

HTPDN
LOCKN
TP_PHY

TXP_ZA_1
TXN_ZA_1
TXP_ZA_2
TXN_ZA_2
CLKP_ZA
CLKN_ZA
TXP_ZA_3
TXN_ZA_3
TXP_ZA_4
TXN_ZA_4
TXP_ZB_0
TXN_ZB_0

A5
B5

TX0-A+
TX0-A-

C6
C5

TX0-B+
TX0-B-

B6
A6

TX0-C+
TX0-C-

A7
B7

TX0-CLK+
TX0-CLK-

C8
C7

TX0-D+
TX0-D-

B8
A8

TX0-E+
TX0-E-

A9
B9

TX1-A+
TX1-A-

C10
C9

TX1-B+
TX1-B-

B10
A10

TX1-C+
TX1-C-

A11
B11

TX1-CLK+
TX1-CLK-

C12
C11

TX1-D+
TX1-D-

B12
A12

TX1-E+
TX1-E-

V23
W23
W22

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_108_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 225

FRC DDR3

FRC DDR3

FB02Q

E7
D3

UMAC1-DQM1
UMAC1-DQM0
UMAC1-MCLK0-N

RAS
ODT
CAS
CK
CK
CKE
CS
WE
RESET
DML
DMU

NC

VSS

VSSQ

UMAC1-DQS1
UMAC1-DQS1-N

E3
F7
F2
F8
H3
H8
G2
H7

DBK5

UMAC1-MD9
UMAC1-MD11
UMAC1-MD8
UMAC1-MD14
UMAC1-MD13
UMAC1-MD15
UMAC1-MD10
UMAC1-MD12

DBL5
DBL6

FTE4

100n

DBK3
DBK4

1K0 1%

F3
G3

3TK1

UMAC1-DQS0-N
UMAC1-DQS0

DBL8
DBL9

H1
M8
3TK3

RES

240R 1%
UMAC1-BA0
UMAC1-BA1
UMAC1-BA2
DBK6

UMAC1-WE
UMAC1-MRES

J3
K1
K3
J7
K7
K9
L2
L3
T2

UMAC1-DQM3
UMAC1-DQM2

E7
D3

UMAC1-RAS
UMAC1-ODT
UMAC1-CAS
UMAC1-MCLK0
UMAC1-MCLK0-N
UMAC1-CKE

J1
J9
L1
L9
T7

UMAC1-MA14

L8
M2
N8
M3

DBM0
DBM4
DBM5

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ

0
1
2
3
4
5
A
6
7
8
9
10
11
12
13
14
BC
AP

0
1
2
3
DQU
4
5
6
7
DQSU1
DQSU2
DQSL
DQSL
0
1
2
3
DQL
4
5
6
7

VREFDQ
VREFCA
ZQ
BA0
BA1
BA2
RAS
ODT
CAS
CK
CK
CKE
CS
WE
RESET
DML
DMU

NC

VSS

VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9

DBK7

BA0
BA1
BA2

B7
C7

+1V5

DBL7

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DBL2
DBL3

ZQ

DBL4

100n

J3
K1
K3
J7
K7
K9
L2
L3
T2

0
1
2
3
DQL
4
5
6
7

UMAC1-MD5
UMAC1-MD0
UMAC1-MD7
UMAC1-MD1
UMAC1-MD4
UMAC1-MD2
UMAC1-MD6
UMAC1-MD3

DT35

2TNR

UMAC1-RAS
UMAC1-ODT
UMAC1-CAS
UMAC1-MCLK0
UMAC1-MCLK0-N
UMAC1-CKE

DQSL
DQSL

D7
C3
C8
C2
A7
A2
B8
A3

UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13

2TK7

M2
N8
M3

DQSU1
DQSU2

VREFDQ
VREFCA

D7
C3
C8
C2
A7
A2
B8
A3

DBM1

B7
C7

UMAC1-MD20
UMAC1-MD18
UMAC1-MD22
UMAC1-MD16
UMAC1-MD23
UMAC1-MD17
UMAC1-MD21
UMAC1-MD19
UMAC1-DQS2-N
UMAC1-DQS2

F3
G3

DBK1
DBK2

E3
F7
F2
F8
H3
H8
G2
H7

DBM2

UMAC1-DQS3
UMAC1-DQS3-N

DBK9
DBM3

J1
J9
L1
L9
T7

UMAC1-MD27
UMAC1-MD28
UMAC1-MD26
UMAC1-MD29
UMAC1-MD24
UMAC1-MD31
UMAC1-MD25
UMAC1-MD30

UMAC1-MA14

DBK8

DT38

DT39

DT40

DT41

10n

10n
2TLB

10n
2TLA

100n
2TL9

100n
2TL8

100n
2TL7

100n
2TL6

10n
2TL5

10n
2TL4

100n
2TL1

100n
2TL0

100n
2TKZ

100n
2TKY

10u
2TKW

10u
2TKV

2TKT

47u 16V
2TKU

10n

10n
2TKS

10n
2TKR

100n
2TKQ

100n
2TKP

100n
2TKN

100n
2TKM

10n
2TKL

10n
2TKK

10n
2TKJ

10n
2TKH

100n
2TKG

100n
2TKF

100n
2TKE

10u
2TKB

2TK9

47u 16V
2TKA

10u
2TKC
DT37

10n
2TL3

+1V5

+1V5

100n
2TKD

75R

L8

UMAC1-BA0
UMAC1-BA1
UMAC1-BA2

UMAC1-WE
UMAC1-MRES
75R

10n
3TK7

2TK8

3TK6

UMAC1-MCLK0

240R 1%

0
1
2
3
DQU
4
5
6
7

1K0 1%

3TK2
RES

VDD

B1
B9
D1
D8
E2
E8
F9
G1
G9

H1
M8
100n

100n

2TNQ

1K0 1%
2TK4

3TK4

FTE3

0
1
2
3
4
5
A
6
7
8
9
10
11
12
13
14
BC
AP

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DBL0
DBL1

1K0
1%

3TK0

+1V5

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

DT36
DBK0

VDDQ

3TK5

VDD
UMAC1-MA0
UMAC1-MA1
UMAC1-MA2
UMAC1-MA3
UMAC1-MA4
UMAC1-MA5
UMAC1-MA6
UMAC1-MA7
UMAC1-MA8
UMAC1-MA9
UMAC1-MA10
UMAC1-MA11
UMAC1-MA12
UMAC1-MA13

7T51
H5TQ1G63BFR-H9C

A1
A8
C1
C9
D2
E9
F1
H2
H9

B2
D9
G7
K2
K8
N1
N9
R1
R9

7T50
H5TQ1G63BFR-H9C

+1V5

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1V5

10n
2TL2

FB02Q

DT42

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_109_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 226

Power sequencing

FB02R Power sequencing

FB02R

+12V
ENABLE+1V5

3TMA

VREG5

33K

+12V

3
100K

3
10n RES

3K3
2TM3

100K

3TM6

ENABLE+1V05

ITMD

+1V5

47K

3T73

10n

RES

ITMH

ITMB
1u0

RES

2TM1

3
100K

3TM1-3
6

100K

3TM2-3

2
6K8
2TM5

3TMB

100K

2 3TM1-2 7

8
1

+2V5

47K

3T72

10n

10K
2TM8

3TM9

RES

3TM5

2
100K

7TM4-1
BC847BPN(COL)
1

7TM3-1
BC847BPN(COL)
1

ITM8

ITMF
2

7TM0-1
BC847BPN(COL)
1

ITM9
4
5

7TM1-2
BC847BPN(COL)

+12V

3TP6

1
K
R

ITMJ

3TP8

7TP1
RES TS2431

100n

2TP2
RES

8K2 RES
1%

2K7
2K2

VREG5

7TM1-1
BC847BPN(COL)
1

8K2 RES
1%

3TP5
3TP7

6
2

2 3TMC-2 7
100R RES

ITMG

3TMC-1

8
100R RES

+2V5

100K

ITMC

ITM4

100K

RES

3TM1-1

100K

4 7TM3-2
BC847BPN(COL)

ITM3

1u0

100K

3 3TM0-3 6

100K
3TM7

3
2 3TM0-2 7

RES

ITM6

ITM7
1 3TM0-1 8

100K

5
1u0

100K
3TM8

4 7TM0-2
BC847BPN(COL)

ITM5

2TM6

+3V3

5 3TM0-4 4

5 3TM1-4 4

4 7TM4-2
BC847BPN(COL)

ITM1

100K

15K

2TM4

3TM4

4 3TMC-4 5
RES
100R

VREG5

4 3TM2-4 5

100K

22K

ITM2

3 3TMC-3 6
100R RES

ITME

7 3TM2-2 2

3TM3

VREG5

ITM0

8 3TM2-1 1

ENABLE+2V5
+12V

ITMA

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_110_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 227

Connectors - Backlight

FB02S Connectors - Backlight

FB02S

9T23
RES
1M54

BL-SPI-CLK
BL-SPI-CLK-OUT

FS00

1
2
3
4
5
6
7
8
9

FS01

3SA3
FS02
FS03
3SE8
FS04
3SEA
FS05
FS06
FS07 3SEC
FS08

100R

3SE7
100R

100R

3SE9

100R

3SEB

100R

3SED

100R
100R

BL-DIM5
BL-DIM6
BL-DIM7
BL-DIM8
BL-DIM9
BL-DIM10
BL-DIM11
BL-DIM12

9T24
RES

BL-SPI-SDO
BL-SPI-SDO-OUT

9T25
RES

BL-SPI-CSn
BL-SPI-CSn-OUT

100R
1n0

1n0
2SCG

2SCH

1n0

1n0
2SBG

1n0
2SBF

2SBE

1n0

1n0
2SBD

2SBC

2SBB

1n0

2041145-9

Bolt-On 2
FPGA-FRCV board

2011-05-25

2011-04-01

8204 000 9200


19051_111_110706.eps
110706

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 228

10-30 FB03 820400092022


Tcon LVDS & Control

TX0-CLKTX0-DTX0-E-

W22
LLV0+
W21
LLV0Y22
LLV1+
Y21
LLV1AB22
LLV2+
AA22
LLV2AB21
LLV3+
AA21
LLV3AB20
LLV4+
AA20
LLV4AB19
LLV5+
AA19
LLV5AB18
LLV6+
AA18
LLV63LD4
ILCG
1K0 RES
AB17
20K
AA17 3LCS
VCO-RES
Y17
SOE-A
AB16
OPT-P
AA16
OPT-N
Y16
H-CONV
AB15
GSC-A
AA15
GSP-R
Y15
GSP-A
AB14
AA14
POL-A1
Y14
GOE-A
AB13
AA13
AB12
DPM-A
AA12
AB11
FLK-A
AA11
3LDE
RES
AB10
3LDG
1K0
+3V3-TCON
AA10
10K RES
AB9
ODC-EN
AA9
FLC6
RBF
Y9
BIT-SEL

SYNC_120HZ
R_MLVDS
POL_S
VCORES_TEST_SE
M_S_SEL
SOE
I2C_EN
OPT_P
FSEL
OPT_N
RESET
H_CONV
XIN
GSC
XOUT
GSP_R
WP
GSP
DM1CLK_SCAN_BLK
INT_VCO2
DM1DAT
POL
DM2DAT
GOE
DM2CLK_SCAN_BLK2
INT_SSC2
DM3CLK
TESTC
DM3DAT
DPM
DM4CLK
TESTB
DM4DAT
FLK
DISM
INT_SSC1
SCL
TESTA
SSC_SYNC
INT_VCO1
REVERSE
ODC_BYPASS
3D_EN
RBF
SDA
C10S8
AGP_OUT
VCO_SYNC
Y10
AGP_IN
LOCAL_ON
Y11
OPC_EN
ALIGN_ON
Y13
VSYNCM_PWM_TOUT I2C_START

TX1-BTX1-CTX1-CLKTX1-DTX1-E-

BLC4

3LC2

BLC8

3LC4

BLCC

100R BLCD
3LC6

BLCG

3LC8

100R BLCH

BLCL

3LCA

100R BLCM

BLCR

3LCC

100R BLCS

BLCW

3LCD

100R BLCY

BLD1

3LCF

BLDE

100R BLDF
3LCH

BLDH

3LCK

BLDM

3LCM

100R
100R

100R

100R

BLC5
BLC9

BLD2

BLDJ

100R BLDN

TX0-B+
TX0-C+
TX0-CLK+
TX0-D+
TX0-E+
TX1-A+
TX1-B+
TX1-C+
TX1-CLK+
TX1-D+
TX1-E+

100R

TX2-ATX2-BTX2-CTX2-CLKTX2-DTX2-ETX3-ATX3-BTX3-CTX3-CLKTX3-DTX3-E-

BLDV

BLDT

3LCP

BLDZ

3LCT

BLE3

3LCW

BLE7

100R BLE8
3LCZ

BLEB

3LEL

100R BLEC

BLEF

3LD3

100R BLEG

BLEK

3LEM

100R BLEL

BLEP

3LD6

100R BLER

BLEV

3LD9

BLEZ

100R BLF0
3LDC

BLF3

3LDH

BLF7

3LDK

100R
100R

100R

100R
100R

BLE0
BLE4

BLD7

BLF4
BLF8

B8
A8
C8
C7
A7
B7
B6
A6
C6
C5
A5
B5

TX0-ATX0-A+
TX0-BTX0-B+
TX0-CTX0-C+
TX0-CLKTX0-CLK+
TX0-DTX0-D+
TX0-ETX0-E+

TX0-A+

TX2-A+
TX2-B+
TX2-C+
TX2-CLK+
TX2-D+
TX2-E+

TX1-ATX1-A+
TX1-BTX1-B+
TX1-CTX1-C+
TX1-CLKTX1-CLK+
TX1-DTX1-D+
TX1-ETX1-E+

B4
A4
C4
C3
A3
B3
A2
A1
B2
B1
C2
C1

TX2-ATX2-A+
TX2-BTX2-B+
TX2-CTX2-C+
TX2-CLKTX2-CLK+
TX2-DTX2-D+
TX2-ETX2-E+

D2
D1
D3
E3
E1
E2
F2
F1
F3
G3
G1
G2

TX3-A+
H2
H1
H3
J3
J1
J2
K2
K1
K3
L3
L1
L2

TX3-ATX3-A+
TX3-BTX3-B+
TX3-CTX3-C+
TX3-CLKTX3-CLK+
TX3-DTX3-D+
TX3-ETX3-E+

TX3-B+
TX3-C+
TX3-CLK+
TX3-D+
TX3-E+

100R

LVDS_IN

R1AM
R1AP
R1BM
R1BP
R1CM
R1CP
R1CLKM
R1CLKP
R1DM
R1DP
R1EM
R1EP

R8EP
R8EM
R8DP
R8DM
R8CLKP
R8CLKM
R8CP
R8CM
R8BP
R8BM
R8AP
R8AM

R2AM
R2AP
R2BM
R2BP
R2CM
R2CP
R2CLKM
R2CLKP
R2DM
R2DP
R2EM
R2EP

R7EP
R7EM
R7DP
R7DM
R7CLKP
R7CLKM
R7CP
R7CM
R7BP
R7BM
R7AP
R7AM

R3AM
R3AP
R3BM
R3BP
R3CM
R3CP
R3CLKM
R3CLKP
R3DM
R3DP
R3EM
R3EP

R6EP
R6EM
R6DP
R6DM
R6CLKP
R6CLKM
R6CP
R6CM
R6BP
R6BM
R6AP
R6AM

R4AM
R4AP
R4BM
R4BP
R4CM
R4CP
R4CLKM
R4CLKP
R4DM
R4DP
R4EM
R4EP

R5EP
R5EM
R5DP
R5DM
R5CLKP
R5CLKM
R5CP
R5CM
R5BP
R5BM
R5AP
R5AM

AA8
AB8
Y8
Y7
AB7
AA7
AA6
AB6
Y6
Y5
AB5
AA5
AA4
AB4
Y4
Y3
AB3
AA3
AB2
AB1
AA2
AA1
Y2
Y1

TX6-E+
TX6-ETX6-D+
TX6-DTX6-CLK+
TX6-CLKTX6-C+
TX6-CTX6-B+
TX6-BTX6-A+
TX6-A-

W2
W1
W3
V3
V1
V2
U2
U1
U3
T3
T1
T2

TX5-E+
TX5-ETX5-D+
TX5-DTX5-CLK+
TX5-CLKTX5-C+
TX5-CTX5-B+
TX5-BTX5-A+
TX5-A-

R2
R1
R3
P3
P1
P2
N2
N1
N3
M3
M1
M2

3LCE

TX6-D-

3LCG

TX6-CLK-

3LCJ

TX6-C-

3LCL

TX6-B-

3LCN

TX6-A-

TX7-CLK+
100R
TX7-C+
100R
TX7-B+
100R
TX7-A+
100R
TX6-E+
100R
TX6-D+
100R
TX6-CLK+
100R
TX6-C+
100R
TX6-B+
100R
TX6-A+
100R

TX5-ETX5-DTX5-CLKTX5-CTX5-BTX5-A-

TX4-E+
TX4-ETX4-D+
TX4-DTX4-CLK+
TX4-CLKTX4-C+
TX4-CTX4-B+
TX4-BTX4-A+
TX4-A-

TX4-DTX4-CLKTX4-CTX4-BTX4-A-

BLDW

3LCR

BLE1

3LCV

BLE5

3LCY

BLE9

3LD0

BLED

3LEN

BLEH

3LEP

BLEM

3LD5

BLES

3LD7

BLEW

3LDA

BLF1

3LDD

BLF5

3LDJ

BLF9

3LDL

BLDY
100R
100R

TX5-E+

BLE2
BLE6

TX5-D+
TX5-CLK+

100R BLEA
100R

BLEE

100R

BLEJ

TX5-C+
TX5-B+
TX5-A+

100R BLEN
100R

TX4-E+

BLET

100R

BLEY

100R

BLF2

TX4-D+
TX4-CLK+

100R BLF6
100R

BLD8

TX4-C+
TX4-B+
TX4-A+

100R

+3V3-TCON

2K2
RES 3LE5

ILC5

I2C-EN

ILC6

REVERSE

RES 3LE8

ILC7

OPC-EN

1K0
RES 3LET

ILC8

ODC-EN

27K

TCON-RST

1
2
3

8
0
1
2

WP
3LE1

SCL
ADR

SDA

3LE2 10R

SCL-DISP
SDA-DISP

10R

FLC3

WP

RES 1K0

1K0
9LC0
RES

FLC8

WC

4K7

ILC9

RES 3LE0 FLC2

(4K 8)
EEPROM

3LF1

RES 3LDZ

BC857BW
7LC2 RES

1K0 RES

P12V

3LDV

+3V3-TCON

ILCE

7LC1
M24C32-WDW6

+3V3T

3LEJ

2LC0
3LDY
FLC1

3LEH

10K

10K

3LDT
RES

RES 3LEW

3LEK

100R

1K0

RES3LE4

2K2
1K0

RES 3LEY

+3V3-TCON

+3V3-TCON

1K0
3LEB

SOE-UR

GOE

GSC-A

ILCK

3LEA

ILCL

GSC
SOE-A

RES 2LC3

10n

RES 2LC2

CTRL-DISP

3D-EN

3D-LR-DISP

10n

30R

30R

WP
10p

3LE9

GOE-A

2LC4

100R

3LEF

SOE-UL

220p

GSP

30R
3LEE

GSP-R

10p

GSP-A

30R

ILCH
FLK-A
DPM-A

ILCJ

10n

POL

100R

RES 2LC6

POL-A1

RES 3LED

2LC7

200R
3LEC

RES 2LC5

RES 3LDS

1K0
2K2

3LE3

3LCB

TX7-A-

M-S-SEL

RES 3LDR

RES 3LDW ILCD

2LC1

ALIGN-ON

RES 470n

ILCC

3LE6

RES 3LDN
2K2

VCO-RES

3LC9

TX7-B-

TX7-D+

FLC0

RES 10K

3LDP
+3V3-TCON

2K2

ILCB

3LC7

TX7-C-

TX4-E-

+3V3-TCON

+3V3-TCON

I2C-START

3LC5

TX7-CLK-

TX7-E+
100R

+3V3T

+3V3-TCON

ILCA

3LC3

TX7-D-

TX6-E-

+3V3-TCON

RES 6K8

+3V3-TCON

+3V3-TCON

3LC1

TX7-E-

TX7-E+
TX7-ETX7-D+
TX7-DTX7-CLK+
TX7-CLKTX7-C+
TX7-CTX7-B+
TX7-BTX7-A+
TX7-A-

LOCAL-ON
ALIGN-ON
I2C-START

RES 20K

RES

3LF3

OPC-EN

TX0-C-

TX1-A-

3LEZ

ODC-EN

TX0-B-

3LC0

2K2

REVERSE
3D-EN
SDA-DISP

TX0-A-

BLC1

BLC0

100n

LLV0P
LLV0N
LLV1P
LLV1N
LLV2P
LLV2N
LLV3P
LLV3N
LLV4P
LLV4N
LLV5P
LLV5N
LLV6P
LLV6N

7LC0-1
TL2435MC

LRV0+
LRV0LRV1+
LRV1LRV2+
LRV2LRV3+
LRV3LRV4+
LRV4LRV5+
LRV5LRV6+
LRV6-

RES 3LES

4K7

3LF2

4K7
3LF5

SCL-DISP

2K2

1M0

3LD1

+3V3T
3LF4

RLV0P
RLV0N
RLV1P
RLV1N
RLV2P
RLV2N
RLV3P
RLV3N
RLV4P
RLV4N
RLV5P
RLV5N
RLV6P
RLV6N

M22
M21
N22
N21
P22
P21
R22
R21
T22
T21
U22
U21
V22
V21

1K0

10n

B17
A17
B16
FLC5
M-S-SEL
A16
I2C-EN
B15
+3V3-TCON 3LEV
2K2 A15
TCON-RST
A14
A13
ILCF
B13
3LD2
C12
1K0 ILC2
C13
WP
ILC3
+3V3-TCON
C14
B14
C15
3LD8 ILC0 C16
C17
1K0 RES
C18
RES 3LDB
B12
+3V3-TCON
3LDF
2K2
A12
C11
10R
B11
RES
A11
3LF0
3LDM
C10
2K2
B10
10R
A10
C9
B9
A9
FLC7

RES

2LN8

1K0

3LN2
RES
3

10M

1LC0
10n

RES
3LN9

1K0
RES
2LN9

LRV1P
LRV1N
LRV2P
LRV2N
LRV3P
LRV3N
LRV4P
LRV4N
LRV5P
LRV5N
LRV6P
LRV6N

FLC4

LVDS_OUT
LRV0P
CONTR LRV0N

RRV0P
RRV0N
RRV1P
RRV1N
RRV2P
RRV2N
RRV3P
RRV3N
RRV4P
RRV4N
RRV5P
RRV5N
RRV6P
RRV6N

2K2
RES

RES
2K2

3LN0

3LN1 RES
1K0

E22
E21
F22
F21
G22
G21
H22
H21
J22
J21
K22
K21
L22
L21

RLV0+
RLV0RLV1+
RLV1RLV2+
RLV2RLV3+
RLV3RLV4+
RLV4RLV5+
RLV5RLV6+
RLV6-

+3V3-TCON

3D-SYNC-120HZ

A18
B18
A19
B19
A20
B20
A21
B21
A22
B22
C22
C21
D22
D21

RRV0+
RRV0RRV1+
RRV1RRV2+
RRV2RRV3+
RRV3RRV4+
RRV4RRV5+
RRV5RRV6+
RRV6-

RES 9LC1

FB03A and FB03B are obsolete

FB03C

7LC0-2
TL2435MC

RES 6K8

FB03C Tcon LVDS & Control

Bolt-On 2
TCON 37 Inch

2011-05-25

2011-04-01

8204 000 9202


19051_112_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 229

Tcon power

FB03D Tcon power

FB03D
5LG0

ILG0
+1V2-TCON

+1V2

5LG1

TO TCON CHIP
1u0

1u0
2LHW

1u0
2LHV

1u0
2LHT

2LHS

100n

100n
2LGK

100n
2LGJ

100n
2LGH

100n
2LGG

100n
2LGF

100n
2LGE

100n
2LGD

100n
2LGC

100n
2LGB

100n
2LGA

100n
2LG9

100n
2LG8

100n
2LG7

100n
2LG6

100n
2LG5

100n
2LG4

100n
2LG3

100n
2LG2

100n
2LG1

2LG0

FROM TI CHIP

30R

ILG1
+3V3-TCON

+3V3T
1u0

1u0
2LHR

1u0
2LHP

1u0
2LHN

2LHM

100n

100n
2LHL

100n
2LHK

100n
2LHJ

100n
2LHH

100n
2LHG

100n
2LHF

100n
2LHE

100n
2LHD

100n
2LHC

100n
2LHB

100n
2LHA

100n
2LH9

100n
2LH8

100n
2LH7

100n
2LH6

100n
2LH5

100n
2LH4

100n
2LH3

100n
2LH2

100n
2LH1

100n
2LH0

100n
2LGZ

100n
2LGY

100n
2LGW

100n
2LGV

100n
2LGT

100n
2LGS

100n
2LGR

100n
2LGP

100n
2LGN

100n
2LGM

2LGL

470R

TO TCON CHIP

LTST-C190KGKT

6LG0

FROM TI CHIP

3LG0

30R

+3V3-TCON
+3V3-TCON

7LC0-4
TL2435MC

7LC0-5
TL2435MC

VDD

7LC0-3
TL2435MC

OVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
OVDD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

D13
D14
D15
D16
D17
D18
D19
E13
E14
E15
E16
E17
E18
E19
F18
G18
H18
J18
K18
L18
M18
N18
P18
R18
T18
U18
V13
V14
V15
V16
V17
V18
V19
W18
W19

+1V2-TCON

1
2
3
4
LVDD
5
6
7
8
1
2
3
4
5
6
7
8
9
10
CVDD
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
MLVDD
7
8
9
10
11
12

H5
J5
K5
L5
M5
N5
P5
R5
E5
E6
E7
E8
E9
E10
E11
E12
F5
G5
T5
U5
V5
V6
V7
V8
V9
V10
V11
V12
F19
G19
H19
J19
K19
L19
M19
N19
P19
R19
T19
U19

C19
C20
D4
D5
D6
D7
D8
D9
D10
D11
D12
D20
E4
E20
F4
F20
G4
G20
H4
H20
J4
J9
J10
J11
J12
J13
J14
J20
K4
K9
K10
K11
K12
K13
K14
K20
L4
L9
L10
L11
L12
L13
L14
L20
M4
M9
M10

OGND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
OGND
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
OGND
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95

M11
M12
M13
M14
M20
N4
N9
N10
N11
N12
N13
N14
N20
P4
P9
P10
P11
P12
P13
P14
P20
R4
R20
T4
T20
U4
U20
V4
V20
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W20
Y12
Y18
Y19
Y20

Bolt-On 2
TCON 37 Inch

2011-05-25

2011-04-01

8204 000 9202


19051_113_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 230

Tcon supply

FB03E Tcon supply

FB03E

1 3LK0-1 8
10R
2 3LK0-2 7

10R
3LK0-3

10R
ILKA

4 3LK0-4 5
10R
ILK9

ILKB

2LK0
1n0

6LK1

SW
FLK0
VDD
10K

10u
3LK2

10u
RES 2LKA

33u
5LK2

10u
2LKB

RES 2LK9

5LK0

10u

2LK7

10u

10u
2LK5

10u
2LK4

2LK3

RES SS34

33u
5LK4

TCOMP
FLK6

10K

3LK9

20

9LK1

ILKF

+3V3T

18

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

EN
OUT3
RST

OUT1

CTRLP

SWB2

VGH

OUT2
CTRLN
FBN

VIA
NC

RES
47K

3LK4

9LK0

47K RES

3LK6

4K7

3LK3

22u

22u
2LKG

2LKF

B340A

SS34

6LK0

-T

5LK5

FLK3

H-VDD

10u
9
35
36

SWB1

TCOMP

SCL-DISP
SWB

10R
ILK4

SWB3

RES 6LK3

3LKB

TCOMP

27

33
ILK5

21

10R

2LKS

A0

PVINB1

ILKD
28

SDA-DISP

2K2

SCL

3LKA

10u
3LK8

PVINB3

29

10u
2LKV

SDA

32

5LK6

FLK4
+1V2

2u0

30

2LL1

9LK4

VL

2LKT

26

ILK2

22u
AVIN

2LLB

9LK3

38
39

LCD-PWR-ONn

CTRLP
VGH-S

RES

+3V3T

24
22
ILK7
7
19
23
25
34
37
40

CTRLN
VGL-FB

ILK8

GND_HS

1u0

2LKR
10u

2LL0

ILK6

2LLC

TCON-RST

1
10u

2LKW

10p

1u0

P12V

ILKC

2LKM

FLK2

22u

100n

P12V

22u
5LK3

SS

10u

RES

COMP

ILK0
11

VL

1u0 RES

12
2LKN

5LK1

41

100p

VL

ILK1

10
PGND3
31
PGND2

15K

AGND

3LK5

2LKP

ILK3

10n

13
14 PGND

2LKL

SWO

SW

17

FLK1

7LK0
TPS65168RSBR

SWI

33u

15
16

10u

10u
2LKD

2LKC

P12V

Bolt-On 2
TCON 37 Inch

2011-05-25

2011-04-01

8204 000 9202


19051_114_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 231

Tcon supply

Tcon supply

FB03F

100n

2LM4

3LM4

9LM1

VCOM-PG

150R

3LM2

3LM7

3LM8

VCOM-RFB

1u0

V+
6

ILMY

ILMZ
VCOM-OUT

V-

NC

1K0

10R

3LMZ

EP

ILMW
VCOM-LFB

100n

100K

7LM0-1
MAX9650ATA

SWB
2LM7

150R

CTRLN

ILMA

100R

3LM1

2LM5

ILM5

100n

1u0

2LM3
2LM6

ILM9

+3V3T

VIA

FLM0

7LM1
KTC3876SY

ILM7

ILM8

19
18
17
16
15

VIA

3LM6

3K9

3LM5

ILM6

1u0

VGL-FB

3K9

3LM3

RES

ILM3

2LM2

9LMC

ILM4

3LMV-4

5
47R
3LMV-3
3
6
47R
3LMV-2
2
7
47R
3LMV-1
1
8
47R
4

ILM2
ILZ3

7LM0-2
MAX9650ATA
14
13
12
VIA
11
10

6LM2

5K6

3LMY

3K6

22u
3LM0

10u
2LM1

RES 2LM0

P12V

ILM1 BAS316
2

1
BAV99 COL

1
5
8

6LM0

ILM0
9LM0

VGL

1K0
3LM9

3LMW-4
6LM1

1K0
3LMA RES

10R
3LMW-2

6LM3

VDD
1K0

10R
3LMW-1

100n

10R

9LMD

ILZ0
9LM4

9LM3

VCOM-OUT

RES

VCOM

1u0

3LME RES

VCOM-PG
ILME

1K0

VDD

SCL-DISP
SDA-DISP

3LMM

RES 3LMP

10R

ILMS

16

9LM7

1K0
3D-EN

14
15

3LMN

10R

9LM8

17
30
31
32
33

1u0

13
VCOM

A0
BKSEL

VIA

8
24 GNDA

FLM1

SCL
SDA

18

VGH

VSD

VS

GNDD

ILMH
VGH-S

1
2
3
4
5
6
7
8
OUT
9
10
11
12
13
14
15
16
1
2

2
3
4
5
6
7
10
11
12
19
20
21
22
25
26
27
28
1

V1
V2
V3
V4
V5
V6
V7
V9
V10
V12
V13
V14
V15
V16
V17
V18
9LMA

VCOM-PG

ILMV

GND_HS
29

7LM3
BUF16821AIPWP

9
23

100n

100n
2LMJ

10u
2LMH

10u
2LMG

2LMF

ILMR

100n
2LMM

2LME

SW

20R

+3V3T
20R

2LMC

ILMD

1u0

2LMN
2LMP

ILZ4
100n

4u7

RES 2LMA

BAV99 COL

2LMD

CTRLP

4u7

RES 2LMB

100K

3LMD

RES 4u7

4u7
2LM9

18K
2LM8

18K

3LMC

ILMC

ILMF BAS316 ILMG

3LMG

ILMB

3LMW-310R

3LMF

7LM2
KTA1663

VGH-S
3LMB

FB03F

Bolt-On 2
TCON 37 Inch

2011-05-25

2011-04-01

8204 000 9202


19051_115_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 232

Tcon mini-LVDS

FB03G

+3V3T

2LN6

10u

2LN5

100n

2LN4

10n

2LN3

100n

2LN2

10u

100n

2LN1

2LN0

10n

+3V3T

VDD

100n

VDD

2LN7

FB03G Tcon mini-LVDS

TF06L-80S-0.5SH(008)

1L01

82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FLN9

FLN0

FLN1
FLN2

OPT-P
VGL

FLN4

GOE
GSC

FLN7

VCOM-RFB
VCOM

FLN3

FLN5

VGH

FLN6

FLNA

H-VDD

FLN8

ZOUT-UP
V1
V2
V3
V4
V5
V6
V7
V9
V10
V12
V13
V14
V15
V16
V17
V18
GSP
POL
FLP6

BLN0
BLN1

SOE-UR
H-CONV
OPT-N

BLN5

RLV6RLV6+
RLV5RLV5+
RLV4RLV4+

BLN6
BLN7

RLV3RLV3+

BLN2
BLN3
BLN4

BLN8
BLN9
BLNA
BLNB
BLNC
BLND
BLNE

RLV2RLV2+
RLV1RLV1+
RLV0RLV0+

BLNK

RRV6RRV6+
RRV5RRV5+
RRV4RRV4+

BLNM

RRV3RRV3+

BLNF
BLNG
BLNH
BLNJ

BLNL

BLNN
BLNP
BLNR
BLNS
BLNT
BLNV

RRV2RRV2+
RRV1RRV1+
RRV0RRV0+

FLNB
82 81

H-VDD

VGL
GOE
GSC
VGH
FLNC
VCOM-LFB
VCOM
ZOUT-UP
FLND

FLNM
FLNN
FLNP
FLNR
FLNS
FLNT
FLNV
FLNW
FLNY
FLNZ
FLP0
FLP1
FLP2
FLP3
FLP4
FLP5
FLNG
FLNH
FLNJ
FLNK
FLNL
BLP0
BLP1

V18
V17
V16
V15
V14
V13
V12
V10
V9
V7
V6
V5
V4
V3
V2
V1
SOE-UL
POL
GSP
H-CONV
OPT-N

BLP5

LRV0+
LRV0LRV1+
LRV1LRV2+
LRV2-

BLP6
BLP7

LRV3+
LRV3-

BLP2
BLP3
BLP4

BLP8
BLP9
BLPA
BLPB
BLPC
BLPD
BLPE

LRV4+
LRV4LRV5+
LRV5LRV6+
LRV6-

BLPK

LLV0+
LLV0LLV1+
LLV1LLV2+
LLV2-

BLPM

LLV3+
LLV3-

BLPF
BLPG
BLPH
BLPJ

BLPL

BLPN
BLPP
BLPR
BLPS
BLPT
BLPV

LLV4+
LLV4LLV5+
LLV5LLV6+
LLV6-

FLNE
1L02

TF06L-80S-0.5SH(008)

FLNF

Bolt-On 2
TCON 37 Inch

2011-05-25

2011-04-01

8204 000 9202


19051_116_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 233

10-31 310431365402 Bolt-On 2 Layout


Overview top side

1T25

1T02 1T03

1G51
1T09

3SA3

3SE7

2SBB

3SE9

3SE8

2SBC

2SBD

2SBF

3SEA

3SEB

2SBE

3SEC

3SED

2UJ2

2SBG

1M54
2SCH

1M99

2SCG

6S00

3LCK

3TC5

3TC7

3TCF

3TC1

2TCM
2TC6

2TCA

9T23
9T24

2UJ7

9U10

3U39

3U49
2U90

3U50

2U89

3U78
3U80

3U81

2U87

2U32

2U31

7U76

5U76

6T11
6T02 3T38

2U85

2U84

7T13

6U05

2UJ8

6T03 3T56

6T10 3T57
3T49

3TS3

9TS3

3TS7

9TS2

3U75
3U77

3U82

2U34

2U33

2U30

2U81

2U78

2U77

3U17

7SG2

BLC1

3LCF

5LG0

BLCL
BLC0

3LEK
3LMA

3LCC
3LCB

3LC6

7LM0

9LM1

3LME

3LM7

9LM4

3LM8
3LM9

2U79

2U69

2U75

3LDT

2LMG

9LM8
3LMP
9LM7

3LMM
2LC1

3LEF

2LMM

1SG2

3LE0

3LDP

2LMH

7LM3

2LME

9LC0

3LDZ

3LEB

2LC4
2LC7

3LMG

3LF5

3LEV

9LMA

3LMN

3LDM

3LF4

2LMJ

3LD2

3LMF

3LDF

1LC0
3LDW

2LM3

2LMF

3LE8

7LC0

3LED

7LC2

3LM3

3LM6

2LM7

3LF3
3LF2

3LD8

3LEA

2LM6

3LMY

3LE5
ILC6

3LDB

3LDR

2LC5

3LE9

3LEC

2LC6

3LE6

3LEW

3LMB

2LM1

3LC0

2LC3

6LM0

9LMC
2LM4
3LMZ

3LM0

9LM0

3LM4

6LM2

3LMV

7LM2

7LM1

3LC2

3LC1

3LD1

2LC2

3LDS

3LEE

3LMD

3LC3

3LF0

3LM5

2LM2

3LC4

3LDY

3LDN

3LE3

3LG0

2LHR

6LG0

3LC5

3LEH

3LEZ

CXXX

2LL1

3LDG

9LM3

3LC7

2LM5

3LET

3LDE

3LM2

3LM1

3LCA
3LC9

2LMD

2LM0

3LE4

3LN1

3LN0

3LEY

2LN8

3LN2

3LCS

U1

U2

3LD4

BLPM

BLPA

BLPG

BLN8

BLP5
BLN3

BLP2

BLPL

BLNP
BLN2
BLN4

BLPF

BLPB

2LN6
2LN7

BLP3

2LN1

2LN5

2LN0

2LN4

1L02

2LN2

3LE1

BLNN

BLNF

BLP7

BLP6
BLPT

7LC1

BLNA

BLNG

BLN5

BLNB

BLN0

BLN6

BLNH

BLNC

BLNR

BLNK

2LN3

BLN1

BLN7

BLND

BLNV

BLP4

BLP0
BLPE

3LF1

BLNT

BLPV

BLNL

2LC0

BLN9

BLP9
BLP8

BLP1
BLPC

BLPJ

3LDV

BLNM

BLPS
BLPK

BLPD

BLPR

BLPN

BLPP

3LEJ

3LE2

BLNE

BLPH

BLNS

6LM3

2TCN

BLCM

3LCH

3LCD

2LN9

2LMC

9LMD

2LMB

2LMP

3T59

BLC4

7U75

3LCT
3LEL

3LCP
3LCZ

3LD6

3LD9

3LDL
3LDK

3LCW

3LEM
3LDC

3LD3

3LDH

3LDD
3LDJ

3LD5

3LEP

BLC5

1T01

5LK1

6LM1

2LMN

2LMA

CU06

BLCR
BLDM

3LCE

5LG1

2LM8

2U82

3LCG

3LMW

2LM9

2U70

3U14

BLCS
BLDN

2LGG

3LN9

3LMC

7T11

7S01

3LC8

ILZ4

DTS1

BLCY

3LD7

3LCV

3LCR

3LCN

3LCL

BLE2

3LCY

BLEA

BLE5

3LCJ

5LK6

5LK3

BLE6

9TS1
3TS6

BLF7

BLEY
BLF2

3LKB

2U86

5U75

BLES

3LK9

BLE1

9S01
9S06

BLF8

BLF9

BLD8

BLET

3T09

BLCW

BLF5

BLEN BLEM

BLEH

9S04

7S00

BLEE

9LK1

BLEK

BLEL

BLEP

3LDA

BLF6

BLER

3LEN

BLF1

BLEV

BLEJ

BLEW

2LLB

BLE9

6LK0

CU05

BLDT

BLE8

BLEB

BLD7

BLEZ

BLDV

BLDZ

BLD1

BLD2

BLDE

BLDF

3T83

3U51

6U15

3U13

1T00

3T30
3T29

2TS2

BLDH

3LD0

BLEC

3LKA

3TCG

DT77

5T04
5T05

7U10
2U53

3SG8

BLDJ

BLE0

7LK0

3T50

3T68

BLE3

BLE4

2LKW 2LL0

9LK4

3T58

3T06
BLC8

BLC9

BLCD BLCC

BLCH BLCG

3LCM

BLEF

BLEG
BLE7

9LK3

2TCL

2TC7

DT31

9T25

2TM3

3T01

3T23

3T22

3T07
2T01

7T00

3T12

BLF4

BLED

2T78

CT10

BT18

BLDY

2LKR
2LKN

2LKD

2LKC

1T06
2T16

3T17

6T01

BT17

BLF3

2LKT

2LKV

BT05

BLF0

3LK0

5LK4

3T51
3T52
3T54
3T53

3TCV
3TCU
3TCS

3TCR

DT83

7T14

BT04

BT14

5LK5

2LK0

3T47

2T15

3T76
3T77
3T78

BT16

BLDW

2LK5
2LK4
2LK3

3T24

DT81

DT72

DT80

6LK1

1T05
3T25

6T15

BT13

5LK0

2U35

DT82

3TCM

BT08

2U29

6U09

DT58

BT23

BT24

2LKM

2T22
3U35

DT68

DT74
DT73

3TCN

BT22

BT15

2U60

3LK8

2T03
3T19

3TCL

1T23

3T18

3T28

3TCP

BT21

BT01

3T27

3TCQ

BT00

BT06

2TCF

2TC3

3TCW

DT69

3TCT

7T20

BT20
CT00

BT03

BT10

DT61

DT54

DT57
DT70
DT71

BT02
BT19

1T22

5LK2

7TM4
DT60

3TCY

3TDA

BT09

3T48

2TCE

3TC9

7TM1
3TM6

2TM4

DT59

DT55

2U05

3TDC

BT12

3TC3

6TC1

7TM0

DT63

2U71

3TDD

3T67

3TCE

3U15

2TD0

DT65
DT64

3T55

2U59

9T17

6T09

7U05

5U51 7U06

6U01

2UH9

3U83

2UH8

3TDB

2TCH

2UJ6

DT46

2TCK

2TC9

7T01

6T00 3T13

3T26

2TD1

1T21

3TR1

3TDT

3TS2

3TR3

3TDP

3TDQ

9TR1

3TR7

3TDS

3TDR

3TT0

3TD4

3TCA
2TC5

2TCG

DT56

3U12

3TD2

DT43

DT34

7T04

3TD1

DT45

DT50
3TD3

BT11

DT33
3T69

2TM1

1T20

3T86
DT51

3TS0

7T61

3TD8

DT49

2TS0

3TS1

3TDN

5U53

1T24

7T08

DT30

DT32

9T15
9T14

7T18

3TD0

2U68

3TC2

3TM5

7T30

2U57

2TCD

3TM7

DT35

DT47DT44

2U58

3TM0

3TMB

DT41

3TDL

2TC8

XU10

3TC8

3TM1

7T31

3TDU

2TC4

3TCD

3TMA

2TD3

3TDM

2TM6

3TP5

2TK9

2TKC
2TKG
2TKD

3TK6

3TK7

3TM8

3TM2

DT42

3T72

7TM3

5TDA

6T08
6T07
6T06
6T05

3TM9

3T73

3TR0

3TP6
3TM4

2TM5

2TL1
2TKW

2TKU

2TS1

2TK8

3TP8
3TM3

2TKH

7T60

3TK3

DT38 DBK9

7T50

3TT1

3TR6

DT37

7T51

3TR4

2TL2

3TR2

3TP7

DT39

DT36
DT40

2TKY

2TD2

3TR8

2TP2

2TKT

6T04

9T10 9T11

3TD9

7T25

7TP1

XU11
XU07 XU13 XU15 XU16 XU06 XU14 XU02 XU01 XU03 XU05

3U16

1W35

BLNJ

1L01
2

Bolt-On 2 Layout Top

3104 313 6540


19051_117_110707.eps
110707

2011-Sep-09 back to

div. table

Circuit Diagrams and PWB Layouts

Q551.2E LA

10.

EN 234

Overview bottom side

FS25
FS46
FS56

FS93

2SA5

FTB2

FS52

IS05

FS43

FS30

9S21

IT91

IT20

2T06
FT03

2TL3

2TL5

2TK7

3TK5

2T71

3T31

1T10

2T69
3T37

7T06

2TKZ

2TKL
2TKJ

IT78

2TEN

2TD4

3TDV

2TFB

2U64

3U57

3U58

2UH7

IU68

3U08

7U51

IU02

IU66

2UH5

3U02

IU56

IU29

3U03
IU67

FTD8

2THK

2TDN

9TD2

IT71

3TDK

FTC0

IT70

3TDH

FU51

FTD6

2THD

2THE

FTC1

8204_000_92021_LCD_PWR_ONn
9TD1

2TEK

2TFA

FTD5

FTC9

3TDF
3TDG

3TDJ

2TDM

2TF9

9T19

IT72

IU01

FTB9

FTB7

2TEB
2TEL

IU57

2TDR

9TD0

3T84

3TDE

7T40

3TG2

FT30

2TED

2THL

3TDW

2TE0

5TDG

2TE3

2TE5

2TE8

2TE2

2TEC

FT99

9T32

3TG5

2TEM

2TMR

2TDL

2TE6

3TG3

3TG4

IU03

2U61

FTD9
IU45

2TMD

3TG6

3T39

2TDJ

2TE1

IU58

2UH6

2TEA

IU63

3U37

2TE4

2TMT

FTFB

5TDE

2TDQ

FTD7

2TE7

3T79

2U74

2TEU

2TF5

3TE2

2TDP
2TEJ

2TDB

2TDA

FTB8

5TDH

IT74

7T41

IU69

3T35

2TMS

9T26
9T27

5TDB

IT82

IU70

2U63

7T10

2TFF

2TFE

2TEY
2TEE

2TME

2TMC

2TMA

FTFJ

3U55

3TE3

2TF8

2TF4
2TF7

2TEZ

2TDC

2TDF

2TMB

IT75

FTH7

2TDE

2TEF

9T35

2TDK

2TML

2TFD

2TF6

2TFC

2TMP
2TMK
5TDC

3T04
FTFV

FTF9

FTF8

2TDD

2TEH

9T33
FTFE

FTFA

2UD1

IT77

FT06

FTFK

FTFP

IT00

2TDH

FTC6

IU04

2TEW

2TEG

3T05

9T34

2T68

2T31
2T30

FTFQ

FTFF

2T34

IT73
FLK3

2T44

FTF7

9T02
2T39
2T38

2T42
2T43 FT11

2T41

FT31
FT25

3T08
2T35 FTFM

2T18

2T40

2T51

FTH8

2T45

2T46

FTH9
FT04

2T09

FTFN

2TEV

2TMF

9T36

2T07
2T49 2T19

IT79

3T75

9T31

2T14

2T33

2T25

2T08 2T23

2T21

2T12

FTFL

ITF1

ITF2

FTE1

2TMM

2TMV

3T82

FTFS
FTFR

2TDG

3T80

FTFH

FTFW

3TE4
ITF3

2TMU

FTFT

2T24

2T20

2T00
2T52

2T05

IT02

IU79

2TL8

2TK4

2TNQ

2TF3

3TE1

2TF1

2TMN

3T14

7T12

IT48

3TMC

FTFY

2T32

DT48

FT14

FT10

2T26
2T28

FT26

3T10
3T11
2T02

IT19

FTA9

FTFZ

2T48

FT01

5TDD
3TE0

FT16

5T03
5T02

IT22

FTJ0

FT02

3TD7

FTB5

FT8S

DT76

IU80

IU27

3T15

ITD2
IT81

3T81

DT75

2T50

FTC8

FTE0

9T30

2T13

FU58

2TL0

2TL9
2TL6

2TF2

FTFU

2T47

3U10

3U11
FU76

2TL4

DBM2

2TKE

3T85

7T09

3U72 3U73

2T17
3U84

6U10

3U09

ITD1

2TL7

2TLA

FTA7

IT06

IT23

2T27
9T01

FTC5

ITD0

DBK1

DBM1

FTB4

IT04

2T59

5T00
5T01
2T04
2T11
2T10

DBK2

2TLB

FT05

FTB3

2T66

FT12

IU28

IU81

2T56

FT13

2T58

2T63

2T62

2T61

FT09

2T57

2T64

3T20

3T02

DT62

3T00

5T07
5T06

DBM3

FT15

7T02

DT66
DT67

2T67

FT21

IT14

FTA8

FT17

FT23

FTE4

DBK8

DBL6

DBK5

3T34

FTC7
ITMC

2T60

2UJ9

IT03

2T65

IT83

2T54

FT91

2TKM

2T72

DBM4

2TKV

DBK3

DBL4

2TT1

2T55

7T03

ITMD
ITM1

DBL2

DBL5DBK4 2TKK

2TKR

2TKQ

2TC2
3T21 2T36
3T03
3T16 FT00

ITMB

ITMH

FT08

DBK6

2TKS

2TKA

2T81
2T82

FT19

IT01

DBM5

3TK1

2TKB

IT47

FTE3

7T19

IT13

2TNR

DBL3
3TK0
3TK4

3T70

3T46
3T45

ITM8

ITM4

IT05

2TCB

2TC1

7TC3

DBL0

7T15

ITMG

2TKP

ITMA

FT92

DBL8

2T70
IT10

IT15

DBM0
3TK2

DBK0

IT84

FT22

3T33

IT11

DBL7

ITM2

2T91

FT24

IT16

FT18

IT12

7T21

ITM5

FT85

IT80

FU78
DBK7

2TKF

IT37

2T80

2T37

ITM0

ITM9

7T05

FTB6

2T83 3T44
2T84

DBL9

3TS8

7T17

3T32
3T36

DBL1

IT18

2T73

IT45

7T07

2T92

ITM7

FT89

2TM8

3TCH

3TCK

IT46

ITMF

2TKN

FT87
FT90

3T71

ITM6

ITM3

IU24

7T16

3TCC

7TC2

FT86

3TCB
3TC4

7TC1

5T08
FT20

ITME

FT88

IT38

IU82

FU77

FS08

XU09 XU08

2TCC

9S02

9S03

FS27

IU61

FS07

FS06

FS05

FS04

FS03

FT29

3T43

3S45

3S53

FSA6

FU57

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