B.

Tech (CSE)

VIII Semester

Subject: VLSI
Code:
EURCS 8614
Credits: 3
Department: CSE

Section: C
Category: IE
No. of hours: 4 per week
Academic Year: 2013-2014
INSTRUCTION PLAN

UNIT

DATES

9-12-13&
10-12-13
11-12-13
16-12-13
17-12-13
18-12-13
19-12-13
20-12-13
23-12-13
24-12-13
24&25-12-13
26-12-13
27-12-13
30-12-13

II

31-12-13
01-01-14
02-01-14
06-01-14
07-01-14
08 & 09,-0114
12 to19-01-14
20-01-14
21-01-14
22-01-14
23-01-14
27-01-14
28-01-14
29-01-14
30-01-14
03,04,05,-2-14

TOPICS

Introduction to MOS technology

VLSI era, advantages, applications
NMOS operation(enhancement and
depletion)
NMOS fabrication(PMOS)
CMOS n-well fabrication
CMOS p-well fabrication
CMOS twin tub process,
difference of MOS technology
BICMOS design flow
Thermal aspects of process
Production of E-beam mask

Ga As Technologies
Electrical properties Ids(non-saturation,
saturation)
Different pull up types of NMOS
inverter
CMOS inverter, Gm,gds,Wo,
BICMOS inverter, differences
Latch up problems
Mos and BiCmos circuit design process

Nmos -Pass transistor-Nmos pull up by

pull down

NO. OF HOURS
2
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1

PONGAL VACATION
Introduction to stick diagrams
Mos layers

1
1

Stick diagrams for NOMS inverter

Stick diagrams for CMOS inverter
Stick diagrams for CMOS-NOR, NAND
Design rules
Design layout
1.2i meter CMOS rules
Layout diagrams

1
1
1
1
1
1
3

06 to 08-02-14

MID 1

1
III

IV

10-02-14
11-02-14
12-02-14

Sheet Resistance
Area capacitance of layers
Delay units

13-02-14
17-01-14
18-02-14
19-02-14
20-02-14
24-02-14
25-02-14
26-02-14
03-03-14

Wring capacitance
Choice of layers
Scaling of MOS circuits introduction
Scaling models
Scaling factors for device parameters
Limitation of scaling
SUB SYSTEM PROCESS
Architectural issues
Switch logic

04-03-14
05-03-14
06-03-14
10-03-14
11-03-14
12,&13-03-14
17-03-14
18-03-14
19-03-14 &
20-03-14
24-03-14
25-03-14
26-03-14
&29-03-14
31-03-14
&01-04-14
02-04-14
03-04-14
07 to 09,-0414

Examples of structural design parity

generator
Bus arbitration logic for n-line bus
Multiplexers
A general logic function block
Gray code to binary code converter
PLA
ALU subsystem design
Commonly used storage/memory elements
Aspects of design tools
Test and testability Design for testability
Testing combinational logic
Testing sequential logic
Practical design for test
Scan design techniques
Built in self test

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
1
2
2
1
1

MID II

Name of the teacher: T.Venkatasuri Apparao

Signature: