TEST PATTERNS OF MULTIPLE SIC VECTORS: THEORY

AND APPLICATION IN BIST SCHEMES

ABSTRACT:
This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our
method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector
applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC
counter are developed to generate a class of minimum transition sequences. The proposed TPG is
flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to
represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results
show that the produced MSIC sequences have the favorable features of uniform distribution and
low input transition density.

EXISTING SYSTEM:
In Existing system, several low-power approaches have proposed for scan-based BIST.
The architecture in Existing System modifies scan-path structures, and lets the CUT inputs
remain unchanged during a shift operation. Using a multiple scan chains with many scan enable
(SE) inputs to activate one scan chain at a time.

EXISTING SYSTEM TECHNIQUE:

Serial Built In Self Test Technique

EXISTING SYSTEM DRAWBACKS:

High Switching activities

High power

High cost

PROPOSED SYSTEM:
This proposed system presents the theory and application of a class of minimum
transition sequences. The proposed method generates SIC sequences, and converts them to low
transition sequences for each scan chain. This can decrease the switching activity in scan cells
during scan-in shifting.

PROPOSED SYSTEM BLOCK DIAGRAM:

MSIC-TPGS FOR TEST-PER-CLOCK:

MSIC-TPGS FOR TEST-PER-SCAN SCHEMES:

PROPOSED SYSTEM TECHNIQUE:

Multiple Single Input Change (MSIC) vectors TPG scheme

PROPOSED SYSTEM ADVANTAGES:

Minimum transitions

Uniqueness of patterns

Uniform distribution of patterns

Low hardware overhead

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

Circuit verification section

Electronic system design

FUTURE ENHANCEMENT:
We will test some benchmark circuits, based on the proposed Technique.

ALTERNATE TITLES:
Title 1: Implementation of Test Patterns of Multiple Sic Vectors on FPGA

Title 2: Multiple Sic Vectors Implementation for Application in BIST Schemes

Title 3: Realization of Test Patterns of Multiple Sic Vectors Using Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification)