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For the pMOS transistor the voltages are expressed as negatives with respect to the nMOS
voltage because of the opposing majority charge carriers in nMOS and pMOS transistors.
Therefore, for pMOS transistors the transistor is OFF when:
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However in pMOS calculations
and
will be negative voltages. You can take the
magnitudes and the rules for pMOS transistors will be the same as for nMOS; therefore for
pMOS transistors the transistor is OFF when:
<
Ok, so now we've cleared up the terminology and defined the above equations defining the
switch on/off points consider a simple pMOS transistor (see attachment labelled with INPUT
(Source), and OUTPUT (Drain)) with a voltage on the gate of 0 volts (a strong logic '0').
If the input is at
volts, then:
=
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This illustrates the strong logic '1' output for a pMOS transistor.
Ok, lets look at the case for logic '0'.
If we start to reduce the input voltage from
input voltage will equal
, then:
=
And the transistor switches off - the conducting channel between the source and drain
closes. At this point the voltage at the output is also
Any further reductions in the input voltage will have no effect on the output voltage because
the transistor is switched of by virtue of the fact that
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This illustrates the weak logic '0' of the pMOS transistor - that is the output can never get
down to 0 volts (the point of a strong logic '0') because the transistor switches off before
the output can get that low.