Part 1

-- A gated RS latch described the hard way

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part1 IS
PORT ( Clk, R, S : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END part1;
ARCHITECTURE Structural OF part1 IS
SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE keep: boolean;
ATTRIBUTE keep of R_g, S_g, Qa, Qb : signal is true;
BEGIN
R_g <= R AND Clk;
S_g <= S AND Clk;
Qa <= NOT (R_g OR Qb);
Qb <= NOT (S_g OR Qa);
Q <= Qa;
END Structural;
Part 2
D_latch.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- A gated D latch described the hard way
ENTITY D_latch IS
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_latch;
ARCHITECTURE Structural OF D_latch IS
SIGNAL R, R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE keep: boolean;
ATTRIBUTE keep of R, R_g, S_g, Qa, Qb : signal is true;
BEGIN
R <= NOT D;
S_g <= NOT (D AND Clk);
R_g <= NOT (R AND Clk);
Qa <= NOT (S_g AND Qb);
Qb <= NOT (R_g AND Qa);
Q <= Qa;
END Structural;

top.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- SW[0] is the latch's D input, SW[1] is the level-sensitive Clk,
LEDR[0] is Q
ENTITY top IS
PORT ( SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(0 TO 0));
END top;
ARCHITECTURE Structural OF top IS
COMPONENT D_latch
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
BEGIN
-- D_latch (input Clk, D, output Q)
U1: D_latch PORT MAP (SW(1), SW(0), LEDR(0));
END Structural;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- A gated D latch described the hard way
ENTITY D_latch IS
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_latch;
ARCHITECTURE Structural OF D_latch IS
SIGNAL R, R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE keep: boolean;
ATTRIBUTE keep of R, R_g, S_g, Qa, Qb : signal is true;
BEGIN
R <= NOT D;
S_g <= NOT (D AND Clk);
R_g <= NOT (R AND Clk);
Qa <= NOT (S_g AND Qb);
Qb <= NOT (R_g AND Qa);
Q <= Qa;
END Structural;

Part 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- SW[0] is the flip-flop's D input, SW[1] is the edge-sensitive
Clock, LEDR[0] is Q
ENTITY part3 IS
PORT ( SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(0 TO 0));
END part3;
ARCHITECTURE Structural OF part3 IS
COMPONENT D_latch
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Qm, Qs : STD_LOGIC;
BEGIN
-- D_latch (input Clk, D, output Q)
U1: D_latch PORT MAP (NOT SW(1), SW(0), Qm);
U2: D_latch PORT MAP (SW(1), Qm, Qs);
LEDR(0) <= Qs;
END Structural;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- A gated D latch described the hard way
ENTITY D_latch IS
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_latch;
ARCHITECTURE Structural OF D_latch IS
SIGNAL R, R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE keep: boolean;
ATTRIBUTE keep of R, R_g, S_g, Qa, Qb : signal is true;
BEGIN
R <= NOT D;
S_g <= NOT (D AND Clk);
R_g <= NOT (R AND Clk);
Qa <= NOT (S_g AND Qb);
Qb <= NOT (R_g AND Qa);
Q <= Qa;
END Structural;

Part 4

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- inputs:
-- Clk: manual clock
-- D: data input
--- outputs:
-- Qa: gated D-latch output
-- Qb: positive edge-triggered D flip-flop output
-- Qc: negative edge-triggered D flip-flop output
ENTITY part4 IS
PORT ( Clk, D : IN STD_LOGIC;
Qa, Qb, Qc : OUT STD_LOGIC);
END part4;
ARCHITECTURE Behavior OF part4 IS
BEGIN
-- gated D-latch
PROCESS (D, Clk)
BEGIN
IF (Clk = '1') THEN
Qa <= D;
END IF;
END PROCESS;
PROCESS (Clk)
BEGIN
IF (Clk'EVENT AND Clk = '1') THEN
Qb <= D;
END IF;
END PROCESS;
PROCESS (Clk)
BEGIN
IF (Clk'EVENT AND Clk = '0') THEN
Qc <= D;
END IF;
END PROCESS;
END Behavior;