FET(FieldEffectTransistor)

Few important advantages of FET over conventional Transistors

1.
2.

Unipolar device i. e. operation depends on only one type of

charge carriers (h or e)
Voltage controlled Device (gate voltage controls drain
current)

3.

Very high input impedance (109-1012 )

4.

Source and drain are interchangeable in most Low-frequency

applications

5.

Low Voltage Low Current Operation is possible (Low-power

consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Self limiting device
Very small in size, occupies very small space in ICs
Low voltage low current operation is possible in MOSFETS
Zero temperature drift of out put is possiblek

6.
7.
8.
9.
10.
11.

Types of Field Effect Transistors

(The Classification)

JFET

FET
MOSFET (IGFET)

Enhancement
MOSFET
n-Channel
EMOSFET

p-Channel
EMOSFET

n-Channel JFET
p-Channel JFET

Depletion
MOSFET
n-Channel
DMOSFET

p-Channel
DMOSFET

TheJunctionFieldEffectTransistor(JFET)

Figure:nChannelJFET.

SYMBOLS

Gate

Gate

Gate

Source
n-channel JFET

Drain

Drain

Drain

Source
n-channel JFET
Offset-gate symbol

Source
p-channel JFET

BiasingtheJFET

Figure:nChannelJFETandBiasingCircuit.

Operation of JFET at Various Gate Bias Potentials

Figure:Thenonconductivedepletionregionbecomesbroaderwithincreasedreversebias.
(Note:ThetwogateregionsofeachFETareconnectedtoeachother.)

Operation of a JFET
Drain

N
Gate
-

Source

+
-

+
DC Voltage Source

OutputorDrain(VDID)CharacteristicsofnJFET

Figure:CircuitfordraincharacteristicsofthenchannelJFETanditsDraincharacteristics.

Nonsaturation(Ohmic)Region:
Thedraincurrentisgivenby

V
I

DS

Saturation(orPinchoff)Region:
I

DS

DSS
V2
P

V
V
GS
P

V
V
DS
GS
P

2I

DSS
V2
P

V
V V

GS
P
DS

DS

V2

V
V
DS
P
GS

and I

DS

1 GS
DSS
V
P

Where,IDSSistheshortcircuitdraincurrent,VPisthepinchoffvoltage

SimpleOperationandBreakdownofnChannelJFET

Figure:nChannelFETforvGS=0.

N-Channel JFET Characteristics and Breakdown

BreakDownRegion

Figure:IfvDGexceedsthebreakdownvoltageVB,draincurrentincreasesrapidly.

VDIDCharacteristicsofEMOSFET
Locusofptswhere V DS VGS V P

SaturationorPinch
offReg.

Figure:TypicaldraincharacteristicsofannchannelJFET.

Transfer (Mutual) Characteristics of n-Channel JFET

DS

1 GS
DSS
V
P

IDSS

VGS (off)=VP

Figure:Transfer(orMutual)CharacteristicsofnChannelJFET

JFET Transfer Curve

This graph shows the value of ID for a given

value of VGS

Biasing Circuits used for JFET

Fixedbiascircuit
Selfbiascircuit
PotentialDividerbiascircuit

JFET(nchannel)BiasingCircuits
ForFixedBiasCircuit
Applying KVL to gate circuit we get

DS

1 GS
DSS
V
P

VGG I G RG VGS VGS Fixed ,I G 0

and

VGS

I DS I DSS 1
VP

and VDS VDD I DS R D

Where, Vp=VGS-off & IDSS is Short ckt. IDS

ForSelfBiasCircuit

VGS I DS RS 0
I DS

VGS

RS

JFET Biasing Circuits Count

or Fixed Bias Ckt.

JFET Self (or Source) Bias Circuit

and I

DS

DSS

GS
I
1

DSS
V
P

GS

GS

R
S

GS

12
DSS
V

GS

GS 0

This quadratic equation can be solved for VGS & IDS

The Potential (Voltage) Divider Bias

DSS

GS

GS

Solving this quadratic equation gives V

GS

and I

DS

A Simple CS Amplifier and Variation in IDS with Vgs

FET Mid-frequency Analysis:

VDD

A common source (CS) amplifier is shown

to the right.

RD
R1

The mid-frequency circuit is drawn as follows:

the coupling capacitors (Ci and Co) and the

vs

vs

RT h

io

vi = v

gmv

rd

RD

RL

vo
_

_
s

vi

Rs

short the DC supply voltage (superposition)

replace the FET with the hybrid- model
The resulting mid-frequency circuit is shown below.
ii

mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:

A vi =

vo
= -g m R 'L , where R L' = rd R D R L
vi

Zi =

vi
= R Th , where R Th = R 1 R 2
ii

Zo =

vo
io

= rd R D
seen by R L

vo
Zi
= A vi

vs
R s + Zi
Zi
i
A I = o = A vi

ii
R L
A vs =

AP =

io
D

ii

bypass capacitor (CSS) are short circuits

is

VDD

po
= A vi A I
pi

Ci

Co
+

RL
R2
RSS

CSS

vo
_

FET Mid-frequency Analysis:

VDD

A common source (CS) amplifier is shown

to the right.

RD
R1

ii

vs

vi

io

+
RTh

vi = v

gmv

rd

RD

RL

vo
_

_
s

mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:

A vi =

vo
= -g m R 'L , where R 'L = rd R D R L
vi

A vs =

vo
Zi
= A vi

vs
R s + Zi

Zi =

vi
= R Th , where R Th = R1 R 2
ii

AI =

Z
io
= A vi i
ii
R L

Zo =

vo
io

AP =

po
= A vi A I
pi

= rd R D
seen by R L

vs

short the DC supply voltage (superposition)

replace the FET with the hybrid- model
The resulting mid-frequency circuit is shown below.

Rs

bypass capacitor (CSS) are short circuits

ii

io
D

The mid-frequency circuit is drawn as follows:

the coupling capacitors (Ci and Co) and the

is

VDD

Ci

Co
+

RL
R2
RSS

CSS

vo
_

Procedure: Analysis of an FET amplifier at mid-frequency:

1) Find the DC Q-point. This will insure that the FET is operating in the saturation
region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
gm =

ID
2I
= DSS
VGS - VP
VGS
VP2

gm =

ID
= K VGS - VT
VGS

(for JFET's and DM MOSFET's)

(for EM MOSFET's)

(Note: Uses DC value of VGS )

3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).

PE-Electrical Review Course - Class 4 (Transistors)

Example 7:

18 V

500

Find the mid-frequency values for Avi, Avs, AI, AP, Zi,

800 k

io

and Zo for the amplifier shown below. Assume that

Ci, Co, and CSS are large.
Note that this is the same biasing circuit used in Ex.
2, so VGS = -0.178 V.
The JFET has the following specifications:
DSS = 4 mA, VP = -1.46 V, rd = 50 k

18 V

ii
10 k

+
vs
_

+
vi
_

Ci

Co
+

S
8k

vo

400 k
2k

CSS

VDD

FET Amplifier Configurations and

Relationships:

VDD
RD

R1

io
D

ii
Rs

vs

Ci

RL

vo

C SS

RSS

_
Common Source (CS) Amplifier
ii
Rs

S
+

A vi

-g m R

R 'L

rd R D R L

Zi

R Th

Zo

rd R D

io

Ci
G

vi

RD

RSS

RL

R1

C2

R2

vo
_

VCC

A vs
Common Gate (CG) Amplifier
VDD

AI

VDD

R1

AP

ii
+
vs
_

Rs

+
vi

'
L

gmR

CD
g m R 'L
1 g m R 'L

'
L

rd R D R L
R SS

R SS R L

1
gm

R Th

Co

+
vs

CG

R2

vi

CS

Co

Ci

Co

R2
R SS

Common Drain (CD) Amplifier (also called source follower)

Zi

R
+
Z
i
s

Zi
A vi

R
+
s

Zi

Zi

R L

A vi i
R L
A vi A I

A vi

A vi

A vi A I

R SS

A vi

1
gm

Z i

R s + Zi
Zi
RL

A vi

A vi A I

where R Th = R 1 R 2

io

rd R D

+
RL

vo
_

Note: The biasing circuit is the same for each amp.

Figure:CircuitsymbolforanenhancementmodenchannelMOSFET.

Figure:nChannelEnhancementMOSFETshowingchannellengthLandchannelwidthW.

Figure:ForvGS<Vtothepnjunctionbetweendrainandbodyisreversebiasedandi D=0.

Figure:ForvGS>Vtoachannelofntypematerialisinducedintheregionunderthegate.
AsvGSincreases,thechannelbecomesthicker.ForsmallvaluesofvDS,iDisproportionaltovDS.
ThedevicebehavesasaresistorwhosevaluedependsonvGS.

Figure:AsvDSincreases,thechannelpinchesdownatthedrainendandiDincreasesmoreslowly.
FinallyforvDS>vGSVto,iDbecomesconstant.

CurrentVoltageRelationshipof
nEMOSFET

Locusofpointswhere

Figure:Draincharacteristics

Figure:Thiscircuitcanbeusedtoplotdraincharacteristics.

Figure:Diodesprotecttheoxidelayerfromdestructionbystaticelectriccharge.

Figure:SimpleNMOSamplifiercircuitandCharacteristicswithloadline.

Figure:Draincharacteristicsandloadline

FigurevDSversustimeforthecircuitofFigure5.13.

FigureFixedplusselfbiascircuit.

FigureGraphicalsolutionofEquations(5.17)and(5.18).

FigureFixedplusselfbiasedcircuitofExample5.3.

FigureThemorenearlyhorizontalbiaslineresultsinlesschangeintheQpoint.

FigureSmallsignalequivalentcircuitforFETs.

FigureFETsmallsignalequivalentcircuitthataccountsforthedependenceofiDonvDS.

FigureDeterminationofgmandrd.SeeExample5.5.

FigureCommonsourceamplifier.

For drawing an a c equivalent circuit of Amp.

Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model

AnalysisofCSAmplifier
ACEquivalentCircuit

SimplifiedACEquivalentCircuit

Voltage gain, A

v i R g v

m gs

gs
L

Input imp., Z

in

R R R
G

A o g R , R R r
v v
m L
L
D d
gs

Out put imp., Z r R

o

r R

d D

r R
d

Analysis of CS Amplifier with Potential Divider Bias

Av gm(rd || RD)

This is a CS amplifier configuration therefore the

input is on the gate and the output is on the drain.

Zo rd || RD

Av gm(rd || RD)
Av gmRD, r 10 R
d

Zi R1 || R2

Zo RD

rd 10RD

Figurevo(t)andvin(t)versustimeforthecommonsourceamplifierofFigure5.28.

AnAmplifierCircuitusingMOSFET(CSAmp.)

FigureCommonsourceamplifier.

AsmallsignalequivalentcircuitofCSAmp.

FigureSmallsignalequivalentcircuitforthecommonsourceamplifier.

Figurevo(t)andvin(t)versustimeforthecommonsourceamplifierofFigure5.28.

FigureGainmagnitudeversusfrequencyforthecommonsourceamplifierofFigure5.28.

FigureSourcefollower.

FigureSmallsignalacequivalentcircuitforthesourcefollower.

FigureEquivalentcircuitusedtofindtheoutputresistanceofthesourcefollower.

FigureCommongateamplifier.

FigureSeeExercise5.12.

FigureDraincurrentversusdraintosourcevoltageforzerogatetosourcevoltage.

FigurenChanneldepletionMOSFET.

FigureCharacteristiccurvesforanNMOStransistor.

FigureDraincurrentversusvGSinthesaturationregionfornchanneldevices.

FigurepChannelFETcircuitsymbols.Thesearethesameasthecircuitsymbolsfornchanneldevices,
exceptforthedirectionsofthearrowheads.

FigureDraincurrentversusvGSforseveraltypesofFETs.iDisreferencedintothedrainterminal
fornchanneldevicesandoutofthedrainforpchanneldevices.