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UNIVERSIDADE DE CAXIAS DO SUL

Campus Universitrio da Regio dos Vinhedos


Centro de Cincias Exatas, da Natureza e Tecnologia
RELGIO E CRONMETRO
Paulo Munari

1 INTRODUO
Este trabalho tem por objetivo criar um ULA capaz de trabalhar com nmeros na forma em complemento de um
(1), alm do testbench associado.
2 METODOLOGIA
Procedimentos:
Somador
Primeiro foi criado um soma1(somador completo de 1 bit) para auxiliar no somador, depois foi utilizado um
soma3, assim utilizando o soma1 para poder fazer um somador de 3 bits, ai sim foi utilizado o soma para fazer a operao
de soma, nesta parte da soma foi usado sinais auxiliares para trabalhar com a magnitude, foi realizado o test bench para a
soma, que est descrito abaixo na sequencia:
--soma1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity soma1 is
port(
A,B,Cin: in STD_LOGIC;
Y, Cout: out STD_LOGIC);
end soma1;
architecture imp1 of soma1 is
signal ent: std_logic_vector(2 downto 0);
begin
ent <= Cin & A & B;
with ent select
Y <= '1' when "001"|"010"|"100"|"111",
'0' when others;
with ent select
Cout <=
'1' when "011"|"101"|"110"|"111",
'0' when others;
end imp1;
--soma3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity soma3 is
port(
A,B: in std_logic_vector(2 downto 0);
Cin: in std_logic;
Y: out std_logic_vector(2 downto 0);
Cout : out std_logic);
end soma3;
architecture imp of soma3 is
signal T1,T2: std_logic;
begin
p1: entity work.soma1(imp1) port map(
A=>A(0),B=>B(0),Cin=>Cin,Y=>Y(0),Cout=>T1);
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p2: entity work.soma1(imp1) port map(


A=>A(1),B=>B(1),Cin=>T1,Y=>Y(1),Cout=>T2);
p3: entity work.soma1(imp1) port map(
A=>A(2),B=>B(2),Cin=>T2,Y=>Y(2),Cout=>Cout);
end imp;
--soma
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all; --no podemos usar duas bibliotecas diferentes, se isso for feito algumas funes no
use ieee.std_logic_unsigned.all; --funcionam como o esperado.
entity Soma is --declarao das entradas e sadas da entidade SOMA.
port(A,B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);
EXC : OUT std_logic;
Y : OUT std_logic_vector (3 downto 0)
);
end Soma;

architecture Imp of Soma is


signal MAX,MIN : std_logic_vector (3 downto 0); --sinais auxiliares usados para ordenar o max/min pelo tamanho da
magnitude
signal J1,J2,J3 : integer; --sinais auxiliares usados na converso de STD_LOGIC_VECTOR para INTEGER.

begin
--incio da ordenao dos valores de A e B pela magnitude
MAX<= (A) when (A(2 downto 0) >= B(2 downto 0)) else (B); -- se a magnitude de A for maior ou igual a de B,
MAX recebe A seno B
MIN<= (B) when (B(2 downto 0) <= A(2 downto 0)) else (A);-- se a magnitude de B for menor ou igual a de A,
MIN recebe B seno A
--fim da ordenao dos valores de A e B pela magnitude
-- incio da convero da magnitude de A e B em nmeros Inteiros
J1<= conv_integer(A(2 downto 0));--atribui o valor sem sinal de A J1 que integer
J2<= conv_integer(B(2 downto 0));--atribui o valor sem sinal de B J2 que integer
J3<=(J1+J2);--somando a magnitude de A com B como nmeros inteiros
--fim da convero da magnitude de A e B em nmeros Inteiros
PROCESS(A,B,J3,MAX,MIN,OPER) --declarao da lista de sensibilidade do processo
begin
--iniciando as sadas com valores nulos
EXC<='0';
y<="0000";
if (OPER="00") then--quando oper=00 executa lgica de soma dos nmeros sinais-magnitude
if(A(3) = B(3)) and (J3 > 7) then
Y(3)<=A(3);
EXC<='1';
y(2 downto 0)<= (A(2 downto 0)) + (b(2 downto 0));
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elsif

(A(3) = B(3)) and (J3 <= 7) then


Y(3)<=A(3);
EXC<='0';
y(2 downto 0)<= (A(2 downto 0)) + (b(2 downto 0));

else
y(3)<=(MAX(3));
Y(2 downto 0) <=((MAX(2 downto 0)) - (MIN(2 downto 0)));
end if;
end if;
end process;
end Imp;
--test bench soma
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_soma IS
END test_soma;
ARCHITECTURE behavior OF test_soma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Soma
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);--adicionar
EXC : OUT std_logic;
Y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal OPER: std_logic_vector(1 downto 0) := (others => '0');--adicionar
--Outputs
signal EXC : std_logic;
signal Y : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Soma PORT MAP (
A => A,
B => B,
OPER => OPER,--adicionar
EXC => EXC,
Y => Y
);

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-- Stimulus process
stim_proc: process
begin
A<="1000";
B<="0100";
wait for 10 ns;
A<="0010";
B<="0100";
wait for 10 ns;
A<="0010";
B<="1100";
wait for 10 ns;
A<="0100";
B<="0100";
wait for 10 ns;
A<="0100";
B<="0010";
wait for 10 ns;
A<="0000";
B<="0000";
wait for 10 ns;
A<="0010";
B<="1100";
wait for 10 ns;
A<="1100";
B<="1100";
wait for 10 ns;
A<="1111";
B<="1111";
wait for 10 ns;
A<="1000";
B<="0000";
wait for 10 ns;
A<="1010";
B<="0100";
wait for 10 ns;
A<="1010";
B<="1100";
wait for 10 ns;
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A<="1100";
B<="1010";
wait;
end process;
END;
Subtrao
Nesta parte foi realizado a subtrao e seu test bench, tambm foi usados sinais auxiliares para converter a
magnitude em inteiros para melhor trabalhar com os sinais, conforme descrito abaixo:
--subtrao
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;--no podemos usar duas bibliotecas diferentes, se isso for feito algumas funes no
use ieee.std_logic_unsigned.all;--funcionam como o esperado.
entity Subt is --declarao das entradas e sadas da entidade SUBT.
port(A,B : IN std_logic_vector (3 downto 0);
OPER : IN std_logic_vector (1 downto 0);
EXC : OUT std_logic;
Y : OUT std_logic_vector (3 downto 0)
);
end Subt;
architecture Imp of Subt is
signal MAX,MIN,AUX_B : std_logic_vector (3 downto 0);--sinais auxiliares
signal J1,J2,J3 : integer; --sinais auxiliares do tipo inteiro

begin
--INVERTENDO O SINAL DO SUBTRAENDO
AUX_B(3)<= '1' when B(3)='0' else '0';
AUX_B(2 downto 0)<= B(2 downto 0);
-- ORDENANDO PELA MAGNITUDE
MAX<= (A) when (A(2 downto 0) >= B(2 downto 0)) else (AUX_B);
MIN<= (AUX_B) when (B(2 downto 0) <= A(2 downto 0)) else (A);
-- CONVERTENDO A MAGNITUDE ME INTERIO E SOMANDO AS MESMAS
J1<= conv_integer(A(2 downto 0));--atribui o valor sem sinal de A tem t1 que unsigned
J2<= conv_integer(B(2 downto 0));
J3<=(J1+J2);
PROCESS(A,B,AUX_B,J3,MAX,MIN,OPER) --declarao da lista de sensibilidade do processo
begin
--iniciando as sadas com valores nulos
EXC<='0';
y<="0000";

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if

OPER="01" then --quando oper=01 executa lgica de subtrao dos nmeros sinais-magnitude

if(A(3) = AUX_B(3)) and (J3 > 7) then


Y(3)<=A(3);
EXC<='1';
y(2 downto 0)<= (A(2 downto 0)) + (B(2 downto 0));
elsif

(A(3) = AUX_B(3)) and (J3 <= 7) then


Y(3)<=A(3);
EXC<='0';
y(2 downto 0)<= (A(2 downto 0)) + (b(2 downto 0));

else
y(3)<=(MAX(3));
Y(2 downto 0) <=((MAX(2 downto 0)) - (MIN(2 downto 0)));
end if;
end if;
end process;
end Imp;
--test bench subtrao
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_subt IS
END test_subt;
ARCHITECTURE behavior OF test_subt IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Subt
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);--adicionar
EXC : OUT std_logic;
Y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal OPER: std_logic_vector(1 downto 0) := (others => '0');--adicionar
--Outputs
signal EXC : std_logic;
signal Y : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
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BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Subt PORT MAP (
A => A,
B => B,
OPER => OPER,--adicionar
EXC => EXC,
Y => Y
);

-- Stimulus process
stim_proc: process
begin
A<="1000";
B<="0100";
wait for 10 ns;
A<="0010";
B<="0100";
wait for 10 ns;
A<="0010";
B<="1100";
wait for 10 ns;
A<="0100";
B<="0100";
wait for 10 ns;
A<="0100";
B<="0010";
wait for 10 ns;
A<="0000";
B<="0000";
wait for 10 ns;
A<="0010";
B<="1100";
wait for 10 ns;
A<="1100";
B<="1100";
wait for 10 ns;
A<="1111";
B<="1111";
wait for 10 ns;
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A<="1000";
B<="0000";
wait for 10 ns;
A<="1010";
B<="0100";
wait for 10 ns;
A<="1010";
B<="1100";
wait for 10 ns;
A<="1100";
B<="1010";
wait for 10 ns;
A<="0100";
B<="1110";
wait;
end process;
END;
A maior/igual B
Nesta parte foi realizado a comparao e seu test bench, utilizando o sinal auxiliar GTL, conforme descrito
abaixo:
-- A maior/igual B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AmaiorigualB is --declarando as entradas e sadas da entidade AmaiorigualB


Port( A,B : IN std_logic_vector (3 downto 0);
OPER : IN std_logic_vector (1 downto 0);
GTL: OUT std_logic);
end AmaiorigualB;

architecture Imp of AmaiorigualB is


signal AUX_GTL : std_logic; -- declarao dos sinais auxiliares
begin
--lgica para comparando se A maior ou igual a B
AUX_GTL <= '0' when((A(3)='0' and B(3)='1') or ( (A(3)='1' and B(3)='0') and (A(2 downto 0)="000" and B(2
downto 0)="000"))
or ((A(3)='0' and B(3)='0') and A(2 downto 0) >= B(2 downto 0)) or ((A(3)='1' and
B(3)='1') and
A(2 downto 0) <= B(2 downto 0)))
else
'1';
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with OPER select


GTL<=AUX_GTL when "10",
'1' when others;
end Imp;
--test bench A maior/igual B
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_AmaiorigualB IS
END test_AmaiorigualB;
ARCHITECTURE behavior OF test_AmaiorigualB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AmaiorigualB
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);--adicionar
GTL : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal OPER: std_logic_vector(1 downto 0) := (others => '0');--adicionar
--Outputs
signal GTL : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AmaiorigualB PORT MAP (
A => A,
B => B,
OPER => OPER,--adicionar
GTL => GTL
);

-- Stimulus process
stim_proc: process
begin
A<="1000";
B<="0100";
wait for 10 ns;
A<="0100";
B<="0100";
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wait for 10 ns;


A<="0100";
B<="0010";
wait for 10 ns;
A<="0000";
B<="0000";
wait for 10 ns;
A<="1100";
B<="1100";
wait for 10 ns;
A<="1111";
B<="1111";
wait for 10 ns;
A<="1000";
B<="0000";
wait for 10 ns;
wait;
end process;
END;
A menor B
Nesta parte foi realizado tambm uma comparao e seu test bench, utilizando o sinal auxiliar LTL, conforme
descrito abaixo:

-- A menor B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AmenorB is--declarando as entradas e sadas da entidade AmenorB


Port( A,B : IN std_logic_vector (3 downto 0);
OPER : IN std_logic_vector (1 downto 0);
LTL: OUT std_logic);
end AmenorB;

architecture imp of AmenorB is


signal AUX_LTL : std_logic; -- declarao dos sinais auxiliares
begin
--lgica para comparando se A menor que B

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AUX_LTL <= '0' when ( (B(3)='0' and A(3)='1') or ((B(3)='0' and A(3)='0') and (B(2 downto 0) > A(2 downto 0)))
or
((B(3)='1' and A(3)='1') and (B(2 downto 0) < A(2 downto 0))))
else
'1';
with OPER select
LTL<=AUX_LTL when "11",
'1' when others;
end imp;
--test bench A menor B
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_AmenorB IS
END test_AmenorB;
ARCHITECTURE behavior OF test_AmenorB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AmenorB
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);--adicionar
LTL : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal OPER: std_logic_vector(1 downto 0) := (others => '0');--adicionar
--Outputs
signal LTL : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AmenorB PORT MAP (
A => A,
B => B,
OPER => OPER,--adicionar
LTL => LTL
);
-- Stimulus process
stim_proc: process
begin
A<="0010";
B<="0100";
wait for 10 ns;
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A<="0010";
B<="1100";
wait for 10 ns;
A<="0100";
B<="1100";
wait for 10 ns;
A<="0100";
B<="1010";
wait for 10 ns;
A<="0000";
B<="1000";
wait for 10 ns;
A<="0010";
B<="1100";
wait for 10 ns;
A<="1000";
B<="1100";
wait for 10 ns;
A<="1110";
B<="1111";
wait for 10 ns;
A<="0000";
B<="0001";
wait for 10 ns;
A<="1010";
B<="1100";
wait for 10 ns;
A<="0011";
B<="1100";
wait;
end process;
END;
Ula
Nesta parte foi realizado a Ula e seu test bench, assim unindo todas as operaes(suas entidades), conforme
descrito abaixo:
--Ula
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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entity ULA is --declarao das entradas e sadas da entidade ULA


port( A,B : IN std_logic_vector (3 downto 0);
OPER : IN std_logic_vector (1 downto 0);
EXC : OUT std_logic;
Y : OUT std_logic_vector (3 downto 0);
GTL : OUT std_logic;
LTL : OUT std_logic
);
end ULA;
architecture Imp of ULA is
signal T1,T2 : std_logic_vector (3 downto 0);--declarao dos sinais auxiliares
signal T5,T6 : std_logic;--declarao dos sinais auxiliares
begin
--Fazendo a inteligao das entidades com a entidade TOP atravs dos port-amp
M1: entity work.Soma(Imp) port map (A=>A,B=>B,OPER=>OPER,EXC=>T6,Y=>T1);
M2: entity work.Subt(Imp) port map (A=>A,B=>B,OPER=>OPER,EXC=>T5,Y=>T2);
M3: entity work.AmaiorigualB(Imp) port map (A=>A,B=>B,OPER=>OPER,GTL=>GTL);
M4: entity work.AmenorB(Imp) port map (A=>A,B=>B,OPER=>OPER,LTL=>LTL);
--lgica de funcionamento das sadas EXC e Y da entidade ULA
EXC<= '1' when (T5='1' or T6='1') else '0';
with OPER select
Y<= T1 when "00",
T2 when "01",
"0000" when others;

end Imp;

--test bench Ula


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_ula IS
END test_ula;
ARCHITECTURE behavior OF test_ula IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ULA
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OPER : IN std_logic_vector(1 downto 0);
EXC : OUT std_logic;
Y : OUT std_logic_vector(3 downto 0);
GTL : OUT std_logic;
LTL : OUT std_logic
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);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal OPER : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal EXC : std_logic;
signal Y : std_logic_vector(3 downto 0);
signal GTL : std_logic;
signal LTL : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ULA PORT MAP (
A => A,
B => B,
OPER => OPER,
EXC => EXC,
Y => Y,
GTL => GTL,
LTL => LTL
);

-- Stimulus process
stim_proc: process
begin
A<="1000";
B<="1000";
OPER<="00";
wait for 10 ns;
A<="1000";
B<="1000";
OPER<="01";
wait for 10 ns;
A<="1000";
B<="1000";
OPER<="10";
wait for 10 ns;
A<="1000";
B<="1000";
OPER<="11";
wait for 10 ns;
A<="0000";
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Paulo Munari

B<="0000";
OPER<="00";
wait for 10 ns;
A<="0000";
B<="0000";
OPER<="01";
wait for 10 ns;
A<="0000";
B<="0000";
OPER<="10";
wait for 10 ns;
A<="0000";
B<="0000";
OPER<="11";
wait for 10 ns;
A<="0100";
B<="0110";
OPER<="00";
wait for 10 ns;
A<="0100";
B<="0110";
OPER<="01";
wait for 10 ns;
A<="0100";
B<="0110";
OPER<="10";
wait for 10 ns;
A<="0100";
B<="0110";
OPER<="11";
wait for 10 ns;
A<="1010";
B<="0110";
OPER<="00";
wait for 10 ns;
A<="1010";
B<="0110";
OPER<="01";
wait for 10 ns;
A<="1010";
B<="0110";
OPER<="10";
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ULA

wait for 10 ns;


A<="1010";
B<="0110";
OPER<="11";
wait for 10 ns;
A<="1110";
B<="0110";
OPER<="00";
wait for 10 ns;
A<="1110";
B<="0110";
OPER<="01";
wait for 10 ns;
A<="1110";
B<="0110";
OPER<="10";
wait for 10 ns;
A<="1110";
B<="0110";
OPER<="11";
wait for 10 ns;
A<="1111";
B<="1111";
OPER<="00";
wait for 10 ns;
A<="1111";
B<="1111";
OPER<="01";
wait for 10 ns;
A<="1111";
B<="1111";
OPER<="10";
wait for 10 ns;
A<="1111";
B<="1111";
OPER<="11";
wait for 10 ns;
A<="0111";
B<="0111";
OPER<="00";
wait for 10 ns;
A<="0111";
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Paulo Munari

B<="0111";
OPER<="01";
wait for 10 ns;
A<="0111";
B<="0111";
OPER<="10";
wait for 10 ns;
A<="0111";
B<="0111";
OPER<="11";
wait for 10 ns;
A<="0011";
B<="1011";
OPER<="00";
wait for 10 ns;
A<="0011";
B<="1011";
OPER<="01";
wait for 10 ns;
A<="0011";
B<="1011";
OPER<="10";
wait for 10 ns;
A<="0011";
B<="1011";
OPER<="11";
wait for 10 ns;
A<="1001";
B<="0011";
OPER<="00";
wait for 10 ns;
A<="1001";
B<="0011";
OPER<="01";
wait for 10 ns;
A<="1001";
B<="0011";
OPER<="10";
wait for 10 ns;
A<="1001";
B<="0011";
OPER<="11";
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wait for 10 ns;


A<="1101";
B<="1011";
OPER<="00";
wait for 10 ns;
A<="1101";
B<="1011";
OPER<="01";
wait for 10 ns;
A<="1101";
B<="1011";
OPER<="10";
wait for 10 ns;
A<="1101";
B<="1011";
OPER<="11";
wait for 10 ns;
A<="1101";
B<="0101";
OPER<="00";
wait for 10 ns;
A<="1101";
B<="0101";
OPER<="01";
wait for 10 ns;
A<="1101";
B<="0101";
OPER<="10";
wait for 10 ns;
A<="1101";
B<="0101";
OPER<="11";
wait for 10 ns;
A<="0001";
B<="1111";
OPER<="00";
wait for 10 ns;
A<="0001";
B<="1111";
OPER<="01";
wait for 10 ns;
A<="0001";
18

Paulo Munari

B<="1111";
OPER<="10";
wait for 10 ns;
A<="0001";
B<="1111";
OPER<="11";
wait;
end process;
END;

4 CONCLUSO
A tarefa foi executada de forma mais simples, a deciso de montar o cdigo em blocos, favoreceu na questo de
encontrar falhas na hora de compilar

Eletrnica Digital II - UCS

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