Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge Rev A00 SCH

5
Discrete/UMA Schematics Document

Sandy Bridge
Intel PCH
2011-01-04
REV : A00
DY :None Installed
UMA:UMA ONLY installed
DN15: ONLY FOR DN15 installed.
DQ15:ONLY FOR DQ15 installed.
PSL: KBC795 PSL circuit for 10mW solution installed.
10mW: External circuit for 10mW solution installed.
MUXLESS:MUXLESS solution installed.
OPTIMUS:OPTIMUS solution installed.
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Tuesday, January 04, 2011
Sheet
1
of
108
Block Diagram
(Discrete/UMA co-lay)
##OnMainBoard
VRAM
1GB
1.N12P-GE-A1-GP(64Mx16b*8)
WKS P/N:72.51G63.H0U HYNIX
WKS P/N:72.41164.I0U SAMSUNG
88,89,90,91
Intel CPU
Sandy Bridge
DDRIII 1066/1333 Channel B
PCIE x 1
USB2.0 x 1
PCIE x 1
DMIx4
LVDS(Sigal Channel)
PCH
Cougar Point
RGB CRT
CRT
USB 2.0 x 3
14 USB 2.0/1.1 ports
I/O Board
Connector
PCIE x 4
Intel
Left Side:
USB x 1
DCBATOUT
VCC_CORE
Bluetooth
CAMERA
USB2.0 x 5
63
5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5
15V_S5
46
Mini-Card
OUTPUTS
1D5V_S3
0D75V_S0
DDR_VREF_S3
DCBATOUT
802.11a/b/g
SYSTEM DC/DC
10/100/
1000
NIC
Realtek
RJ45
CONN
USB3.0 X2
CONN
VCC_GFXCORE
VGA
INPUTS
SIM
WWAN
92
RT8208B
OUTPUTS
DCBATOUT
Mini-Card
SATAx1 / USB2.0x1
ACPI 1.1
VGA_CORE
TI CHARGER
40
BQ24745
INPUTS
OUTPUTS
+DC_IN_S5
+PBATT
26
DCBATOUT
SYSTEM DC/DC
INPUTS
ESATA/USB/Powershare
57
Combo
47
OUTPUTS
3D3V_S5
USB 2.0 x 1BPCIE X 1
1D8V_S0
SYSTEM DC/DC
93
G9731
17,18,19,20,21,22,23,24,25,26
USB 2.0 x 1
VOSTRO Express Card

(On daughter board)
75
SATA x 2
LPC Bus
Flash ROM
4MB 60
CardReader
LPC debug port
71
KBC
Realtek
RTS5138
32
D/A
HDD
1D5V_S3
1V_VGA_S0
NPCE795P
27
A/D
ODD
PCB LAYER
L1:Top
L4:Signal
L2:VCC
L5:GND
L3:Signal L6:Bottom
<Core Design>
56
Wistron Corporation
58

Fan Control
P2793
Touch
PAD
69
Int.
KB
Title
55
Block Diagram
Thermal
P2800
69
Size
A3
28
25
Date:
3
OUTPUTS
1D5V_S0
5V_S0
3D3V_S0
1D5V_S3
5V_S5
3D3V_S5
SD/MMC+/MS/
MS Pro/xD 74
56
NUVOTON
OUTPUTS
INPUTS
29
INPUTS
26
Switches
SPI
Azalia
CODEC
OUTPUTS
DCBATOUT
UPD720200FA
44
ISL95831HRTZ
INPUTS
TPS51311
PCIE ports (8)
54
IDT
92HD87
41
OUTPUTS
TPS51216RUKR
NEC USB3.0
PCIE x 1,USB x 1
SYSTEM DC/DC
MIC IN
AZALIA
2CH SPEAKER
1D05V_VTT
DCBATOUT
High Definition Audio
VOSTRO
Finger Print 64
Internal Digital MIC
DCBATOUT
82
LPC I/F
B
OUTPUTS
TPS51123RGER
SATA ports (6)
DCIN
INPUTS
SYSTEM DC/DC
HP1
ETHERNET (10/100/1000Mb)
CRT Board 82
PCIE x 1
45
TPS51218
RTL8111E/8105E
HDMI
51
49
0D85V_S0
INPUTS
FDIx4x2
(UMA only)
Discreet/UMA Co-lay
LCD
1D05V_VTT
DDRIII
Slot 1
15
1066/1333
ATI : Co-layout HDMI coming from UMA(default) &

dGPU by reserving Resistor(0ohm) for optional selection.
HDMI
OUTPUTS
DDRIII
Slot 0
14
1066/1333
4,5,6,7,8,9,10,11,12,13
INPUTS
PCIe x 16
(Discrete only)
42~43
OUTPUTS
SYSTEM DC/DC
83.84,85,86,87
NVidia : Co-layout HDMI coming from dGPU(Default) &

UMA by reserving Resistor(0ohm) for optional selection.
ISL95831HRTZ
INPUTS
INPUTS
DDRIII 1066/1333 Channel A
Robson-XT&
Seymour-XT&
Whistler-LP&
N12P-GE 15~25W
CPU DC/DC
48
APL5916
Project code : 91.4IE01.001

PCB P/N
: 10260-1
Revision
: A00
DDR3
800MHz
SYSTEM LDO
Document Number
Rev
A00
QUEEN 15
Sheet
1
of
108
PCH Strapping
Name
SPKR
Processor Strapping
Huron River Schematic Checklist Rev.0_7

Schematics Notes
Reboot option at power-up

Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k[
- 10-k[ weak pull-up resistor.
INIT3_3V#
Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51
GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Strap Description
Configuration (Default value for each bit is

1 unless specified otherwise)
CFG[2]
PCI-Express Static
Lane Reversal
1:
0:
CFG[6:5]
CFG[7]
PEG DEFER TRAINING
1: PEG Train immediately following xxRESETB de assertion

1
0: PEG Wait for BIOS for training
POWER PLANE
VOLTAGE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
5V
1.5V
0.75V
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3D3V_LAN_S5
3.3V
WOL_EN
Legacy WOL
3D3V_AUX_KBC
3.3V
DSW, Sx
ON for supporting Deep Sleep states
3D3V_AUX_S5
3.3V
G3, Sx
Powered by Li Coin Cell in G3

and +V3ALW in Sx
Disable Danbury:Leave floating (internal pull-down)
Low (0) - Flash Descriptor Security will be overridden. Also,

when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
HDA_SDO
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO8
2
GPIO27
11
DMI termination voltage. Weak internal pull-up. Do not pull low.
HAD_DOCK_EN#
/GPIO[33]
GPIO15
11 : x16 - Device 1 functions 1 and 2 disabled

10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
Disable Danbury:Left floating, no pull-down required.
15 -> 0, 14 -> 1, ...
PCI-Express
Port Bifurcation
Straps
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
NC_CLE
Normal Operation.
Lane Numbers Reversed
Default
Value
Disabled - No Physical Display Port attached to

1: Embedded DisplayPort.
Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
SPI_MOSI
NV_ALE
Pin Name
CFG[4]
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm

weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
D
Huron River Schematic Checklist Rev.0_7
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
Voltage Rails
DESCRIPTION
ACTIVE IN
S0
CPU Core Rail
Graphics Core Rail
S3
AC Brick Mode only

All S states
USB Table
PCIE Routing
LANE1
Card Reader
LANE2
Mini Card1(WLAN) SATA
LANE3
Mini Card2(WWAN)
LANE4
Onboard LAN
LANE5
USB3.0
LANE6
Intel GBE LAN
LANE7
Dock
LANE8
Express Card
Table
SATA
Pair
Device
Pair
Device
Touch Panel / 3G SIM
USB Ext. port 1 (HS)
I 2 C / SMBus Addresses
Fingerprint
Device
BLUETOOTH
Mini Card2 (WWAN)
CARD READER
HDD1
USB Ext. port 4 / E-SATA /USB CHARGER
HDD2
USB Ext. port 2
N/A
10
USB Ext. port 3
N/A
11
Mini Card1 (WLAN)
ODD
12
CAMERA
ESATA
13
Express Card
SMBus ADDRESSES
Ref Des
HURON RIVER ORB

Address
Hex
Bus
EC SMBus 1
Battery
CHARGER
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
EC SMBus 2
PCH
eDP
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI
<Variant Name>
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK Title
Size
A3
Date:
Wistron Corporation
Table of Content
Document Number
Rev
A00
QUEEN 15
Sheet
of
108
SSID = CPU
Signal Routing Guideline:

PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
1 OF 9
CPU1A
19 DMI_RXN[3:0]
19 DMI_RXP[3:0]
19 FDI_TXN[7:0]
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
B28
B26
A24
B23
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
G21
E22
F21
D21
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
G22
D22
F20
C21
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
A21
H19
E19
F18
B21
C20
D18
E17
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
19 FDI_FSYNC0
19 FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
19 FDI_INT
H20
FDI_INT
19 FDI_LSYNC0
19 FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
C15
D15
EDP_AUX
EDP_AUX#
C17
F16
C16
G15
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
C18
E16
D16
F15
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
19 FDI_TXP[7:0]
Note:
Lane reversal does not apply to
FDI sideband signals.
B27
B25
A25
B24
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
R402 1
2 24D9R2F-L-GP
1 R403
DY

EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
2
10KR2J-3-GP
DP_COMP
eDP_HPD
SANDY
eDP
0719 Modify:
un-stuff R403 base on Intel James feedback list.
1D05V_VTT
J22
J21
H22
PEG_IRCOMP_R
R401 1
2 24D9R2F-L-GP
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
C401
C402
C403
C404
C405
C406
C407
C408
C409
C410
C411
C412
C413
C414
C415
C416
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
C417
C418
C419
C420
C421
C422
C423
C424
C425
C426
C427
C428
C429
C430
C431
C432
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
1MUXLESS
2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_RXN[0..15]
PCI EXPRESS* - GRAPHICS
19 DMI_TXP[3:0]
SANDY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI
19 DMI_TXN[3:0]
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
Intel(R) FDI
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RXP[0..15]
D
PEG_RXN[0..15]
83
PEG_RXP[0..15] 83
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG_TXN[0..15]
PEG Static Lane Reversal
PEG_TXN[0..15] 83
PEG_TXP[0..15]
PEG_TXP[0..15] 83
SKT-BGA989C470395-1H180
62.10055.421
Stuff to disable internal graphics
function for power saving.
2nd = 62.10040.771
A00 0103 add 3rd foxcon CPU1 at XBuild batch run
3rd = 62.10055.321
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-k[ pull-Up
resistor on the motherboard.
<Variant Name>
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
of
108
SSID = CPU
1
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
2 OF 9
CPU1B
AN34
SKTOCC#
R501
TPAD14-GP
H_CATERR#
TP502
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
C502
SC47P50V2JN-3GP
22,27
20100622 V1.2
CRB : 47pf
CEKLT:43pf
H_PECI
THERMAL
62R2J-GP
H_PROCHOT#
R513
27,40,42 H_PROCHOT#
H_PROCHOT#_R
56R2J-4-GP
22,36 H_THERMTRIP#
19 H_PM_SYNC
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
EC505
A00 1229 EMI
1 MS04A03T2V2-GP-U
DY
1 R504
2 H_CPUPW RGD_R
0R0402-PAD
2
10KR2J-3-GP
R505 2 VDDPW RGOOD
1
0R2J-2-GP
22,36 H_CPUPW RGD
1R503
19,37 PM_DRAM_PW RGD
PWR MANAGEMENT
Connect EC to PROCHOT# through inverting OD buffer.
V8
SM_DRAMPWROK
DY
37 VDDPW RGOOD
BUF_CPU_RST#
EC506
R509
750R2F-GP
DY
DY
2
1K5R2F-2-GP
AR33
RESET#
R510 1
MS04A03T2V2-GP-U
PLT_RST#
18,27,71,75,82,83
CLOCKS
SKTOCC#_R
TP501
SNB_IVB#
BCLK
BCLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A28
A27
CLK_EXP_P
CLK_EXP_N
A16 CLK_DP_P_R 1 R512

2
A15 CLK_DP_N_R 1 R514 1KR2J-1-GP
2
1KR2J-1-GP
20
20
1D05V_VTT
0617 Modify:
Joseph change RN501 to R512,R514 1K 0402 Resistor.
1R502
SM_DRAMRST#
DDR3
MISC
TPAD14-GP
C26
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
R8
AK1
A5
A4
2
4K99R2F-L-GP
SM_RCOMP_0 R506 1
SM_RCOMP_1 R507 1
SM_RCOMP_2 R508 1
SM_DRAMRST# 37
2 140R2F-GP
2 25D5R2F-GP
2 200R2F-L-GP

SM_RCOMP keep routing length less than 500 mils.
JTAG & BPM
1D05V_VTT
0625 Modify:
Add C502 47p 0402 on H_PROCHOT#.
H_SNB_IVB#
MISC
SANDY
18
PRDY#
PREQ#
AP29
AP27
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCLK
XDP_TMS
XDP_TRST#
TDI
TDO
AR28
AP26
XDP_TDI
XDP_TDO
DBR#
AL35
XDP_DBRESET#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
1
1
TP511
TP512
TPAD14-GP
TPAD14-GP
0721 Modify:
SWAP RN501 pin1,2,3
base on swap report.
1D05V_VTT
RN501
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
1
1
1
1
1
1
1
1
TP503
TP504
TP505
TP506
TP507
TP508
TP509
TP510
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TCLK
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
1
2
3
4
8
7
6
5
SRN51J-1-GP
XDP_TRST#
R511 1
2 51R2J-2-GP
C501
SC220P50V2KX-3GP
SANDY
A00 1230 EMI

0623 Modify:
Reserved C501 220pF 0402 on BUF_CPU_RST#.
SKT-BGA989C470395-1H180
62.10055.421
2nd = 62.10040.771
3rd = 62.10055.321
0630 Modify:
Removed XDP1101 connector
related circuit by layout limitation.
3D3V_S0

19 XDP_DBRESET#
XDP_DBRESET#
1
2 R516
10KR2J-3-GP
0707 Modify:
Change R516 10K from 1K
0617 Modify:
Joseph Removed U501 Buffer reset to CPU circuit.
XDP_TRST#
1D05V_VTT
0719 Modify:
Add buffer for PLT_RST# based on Intel review.
3D3V_S0
BUFO_CPU_RST#
1
R517
2
DY43R2J-GP
BUF_CPU_RST#
SC1KP50V2KX-1GP
GND OUT Y
EC504
DY
VCC
IN A
EC502
IN B
PLT_RST#
U501
A00 1229 EMI
18,27,71,75,82,83
DYC503
SCD1U10V2KX-5GP
Buffered reset to CPU
R518
75R2J-1-GP
DY
SC1KP50V2KX-1GP
XDP_DBRESET#
74VHC1G09DFT2G-GP
DYR515
0R2J-2-GP
2
73.01G09.AAH
<Variant Name>
Wistron Corporation
Title
Size
A3
Date:
CPU (THERMAL/CLOCK/PM )
Document Number
Rev
A00
QUEEN 15
Sheet
of
108
SSID = CPU
3 OF 9
4 OF 9
CPU1D
SANDY
15 M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
15
15
15
M_A_BS0
M_A_BS1
M_A_BS2
15
15
15
M_A_CAS#
M_A_RAS#
M_A_W E#
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AE10
AF10
V6
SA_BS0
SA_BS1
SA_BS2
AE8
AD9
AF9
DDR SYSTEM MEMORY A
M_A_DQ[63:0]
SA_CAS#
SA_RAS#
SA_WE#
SA_CLK0
SA_CLK#0
SA_CKE0
AB6
AA6
V9
SA_CLK1
SA_CLK#1
SA_CKE1
AA5
AB5
V10
SA_CLK2
SA_CLK#2
SA_CKE2
AB4
AA4
W9
SA_CLK3
SA_CLK#3
SA_CKE3
AB3
AA3
W10
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
AK3
AL3
AG1
AH1
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
AH3
AG3
AG2
AH2
SANDY
M_A_DIM0_CLK_DDR0 15
M_A_DIM0_CLK_DDR#0 15 14 M_B_DQ[63:0]
M_A_DIM0_CKE0 15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_DIM0_CLK_DDR1 15
M_A_DIM0_CLK_DDR#1 15
M_A_DIM0_CKE1 15
M_A_DIM0_CS#0 15
M_A_DIM0_CS#1 15
M_A_DIM0_ODT0 15
M_A_DIM0_ODT1 15
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
C4
G6
J3
M6
AL6
AM8
AR12
AM15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#[7:0] 15
M_A_DQS[7:0] 15
M_A_A[15:0] 15
SANDY
14
14
14
M_B_BS0
M_B_BS1
M_B_BS2
14
14
14
M_B_CAS#
M_B_RAS#
M_B_W E#
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CLK0
SB_CLK#0
SB_CKE0
AE2
AD2
R9
SB_CLK1
SB_CLK#1
SB_CKE1
AE1
AD1
R10
SB_CLK2
SB_CLK#2
SB_CKE2
AB2
AA2
T9
SB_CLK3
SB_CLK#3
SB_CKE3
AA1
AB1
T10
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
AD3
AE3
AD6
AE6
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
AE4
AD4
AD5
AE5
M_B_DIM0_CLK_DDR0 14
M_B_DIM0_CLK_DDR#0 14
M_B_DIM0_CKE0 14
M_B_DIM0_CLK_DDR1 14
M_B_DIM0_CKE1 14
M_B_DIM0_CS#0 14
M_B_DIM0_CS#1 14
M_B_DIM0_ODT0 14
M_B_DIM0_ODT1 14
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQS#[7:0] 14
M_B_DQS[7:0] 14
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
M_B_A[15:0] 14
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
3rd = 62.10055.321
M_B_DQ[63:0]
DDR SYSTEM MEMORY B
CPU1C
2nd = 62.10040.771
3rd = 62.10055.321

<Variant Name>
Wistron Corporation
Title
CPU (DDR)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
of
108
SSID = CPU
CFG2
CFG4
CFG5
CFG6
CFG7
0707 Modify:
Removed CFG1,CFG3,CFG8~17 TP.
RSVD#AJ31
RSVD#AH31
RSVD#AJ33
RSVD#AH33
AJ26
RSVD#AJ26
RSVD#AT26
RSVD#AM33
RSVD#AJ27
AT26
AM33
AJ27
CFG4
RSVD#T8
RSVD#J16
RSVD#H16
RSVD#G16
T8
J16
H16
G16
RSVD#AR35
RSVD#AT34
RSVD#AT33
RSVD#AP35
RSVD#AR34
AR35
AT34
AT33
AP35
AR34
DY
CFG6
D1:VREF_DQ CHB
R711
R712
R707 1
M_VREF_CA_DIMM1
R706 1
DY
2 0R2J-2-GP
DY
2 0R2J-2-GP
M_VREF_CA_DIMM0
1KR2F-3-GP
1KR2F-3-GP
20 mils
0629 Modify:
Reserved R710 0ohm to GND to
follow EV board schematic.
R710 1
DY
2 0R2J-2-GP
H_VCCP_SEL
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD#F25
RSVD#F24
RSVD#F23
RSVD#D24
RSVD#G25
RSVD#G24
RSVD#E23
RSVD#D23
RSVD#C30
RSVD#A31
RSVD#B30
RSVD#B29
RSVD#D30
RSVD#B31
RSVD#A30
RSVD#C29
J20
B18
A19
RSVD#J20
RSVD#B18
RSVD#A19
J15
RSVD#J15
CFG7
RSVD#AJ32
RSVD#AK32
AJ32
AK32
RSVD#AH27
AH27
RSVD#AN35
RSVD#AM35
0702 Modify
AN35 TP713
AM35 TP714
R704
DY
RSVD#AT2
RSVD#AT1
RSVD#AR1
CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
DY DY
B34
A33
A34
B35
C35
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1KR2J-1-GP
RSVD#B4
RSVD#D1
0: Enabled; An external Display Port device is

connected to the Embedded Display Port
B4
D1
R701
RSVD#B34
RSVD#A33
RSVD#A34
RSVD#B35
RSVD#C35
1: Disabled; No Physical Display Port

attached to Embedded Display Port
PCIE Port Bifurcation Straps
M_VREF_DQ_DIMM0_C
M_VREF_DQ_DIMM1_C
CFG4
CFG5
1KR2J-1-GP
B4:VREF_DQ CHA
2 0R2J-2-GP
2 0R2J-2-GP
Display Port Presence Strap

R703
3K3R2F-2-GP
PEG DEFER TRAINING
DY
DY
0:Lane Reversed
R705
1KR2J-1-GP
1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training
CFG7
R708 1
R709 1
RESERVED
M3 - Processor Generated SO-DIMM VREF_DQ
1: Normal Operation; Lane #

definition matches socket pin map definition
CFG2
AJ31
AH31
AJ33
AH33
SANDY
0617 Modify:
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1,
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1
from net to power.
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
1KR2J-1-GP
MUXLESS
CFG2
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
L7
AG7
AE7
AK2
W8
CFG0
TP715
PEG Static Lane Reversal

R702
RSVD#L7
RSVD#AG7
RSVD#AE7
RSVD#AK2
RSVD#W8
TPAD14-GP
5 OF 9
CPU1E
0630 Modify:
Reserved TP715 on CFG0.
M_VREF_DQ_DIMM0
M_VREF_DQ_DIMM1
1
1
TP713
TP714
TPAD14-GP
TPAD14-GP
0630 Modify:
Removed CLK_XDP_ITP_P&N
and reserved TP713,TP714.
AT2
AT1
AR1
1D05V_VTT
B
EC701
SCD1U50V3KX-GP
DY
SANDY
SKT-BGA989C470395-1H180
62.10055.421
0719 Modify:
Reserved EC701 0.1uF near
R711(BOTTOM) for EMC NEO suggestion.
2nd = 62.10040.771
3rd = 62.10055.321
<Variant Name>
A
Wistron Corporation
Title
CPU (RESERVED)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
of
108
SSID = CPU
CPU1F
POWER
6 OF 9
VCCIO Output Decoupling Recommendation:

2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
7 x 22 uF & 2 x 0805 no-stuff at Top
SANDY
VCC_CORE
VCC
4 x
8 x
8 x
8 x
C831
SC22U6D3V5MX-2GP
C832
SC10U6D3V5KX-1GP
C833
SC10U6D3V5KX-1GP
1
2
C834
SC10U6D3V5KX-1GP
C835
SC10U6D3V5KX-1GP
0726 Modify:
un-stuff C837.
0819 De-cap
Output Decoupling Recommendation:

470 uF at Bottom Socket Edge
22 uF at Top Socket Cavity
22 uF at Top Socket Edge
22 uF at Bottom Socket Cavity
1
2
1
2
C845
SC10U6D3V5KX-1GP
C844
SC10U6D3V5KX-1GP
1
2
C843
SC10U6D3V5KX-1GP
1
2
C842
SC10U6D3V5KX-1GP
C830
SC10U6D3V5KX-1GP
0617 Modify:
Joseph Removed C812,
C813,C814
H_CPU_SVIDDAT
20100610 V1.0
VIDALERT#
VIDSCLK
VIDSOUT
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R803
2 43R2J-GP
R804
1D05V_VTT
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
For CRB VIDALERT# need to pull high 75 ohm close to CPU
AJ29
AJ30
AJ28
C841
SC10U6D3V5KX-1GP
1
2
C840
SC10U6D3V5KX-1GP
C839
SC10U6D3V5KX-1GP
1
2
C838
SC10U6D3V5KX-1GP
1
2
C809
SC10U6D3V5KX-1GP
2
1
C808
SC10U6D3V3MX-GP
2
1
C805
SC10U6D3V3MX-GP
1D05V_VTT
2 130R2F-1-GP
0705 Modify:
Removed R805,R806, already PH closed PWM side.
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42
B
VCC_CORE
1
0819 De-cap
0721 Modify:
Removed C836.
No-stuff sites outside the socket may be removed.

No-stuff sites inside the socket cavity need to remain.
R801
100R2F-L1-GP-U
2
C827
SC22U6D3V5MX-2GP
C826
SC22U6D3V5MX-L2GP
1
0721 Modify:
Removed C822,C823,C824
C825
SC10U6D3V5KX-1GP
1
2
0726 Modify:
un-stuff C826.
J23
0713 Modify:
Removed C810,C806,C807 10uf 0603 cap
base on layout limitation.
VCC_SENSE
VSS_SENSE
AJ35
AJ34
VCCSENSE 42
VSSSENSE 42
1
0713 Modify:
Removed C818 10uf 0603 cap
base on layout limitation.
VCCIO
VCCIO_SENSE
VSSIO_SENSE
B10
A10
R802
100R2F-L1-GP-U
VCCIO_SENSE 45
VSSIO_SENSE 45
2
2
1
C817
SC10U6D3V3MX-GP
2
1
C819
SC10U6D3V3MX-GP
QC
C821
SC10U6D3V5KX-1GP
1
2
1
2
DY
C837
SC22U6D3V5MX-L2GP
0819 De-cap DY
C816
SC10U6D3V5KX-1GP
2
1
C820
SC10U6D3V3MX-GP
0713 Modify:
Removed C802,C811 10uf 0603
cap base on layout limitation.
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
DY
QC
QC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
PROCESSOR VCCIO: 8.5A
C829
SC10U6D3V5KX-1GP
QC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
QC
2
1
C806
SC10U6D3V3MX-GP
QC
2
1
C804
SC10U6D3V3MX-GP
2
1
C803
SC10U6D3V3MX-GP
QC
SVID
2
1
C802
SC10U6D3V3MX-GP
2
1
C801
SC10U6D3V3MX-GP
QC
X02 1115
53A
2
1
C807
SC10U6D3V3MX-GP
VCC_CORE
SENSE LINES
1115 X02 Modify:

Reserved C802~C804,C806,C807 10uF 0603
for power team fine tune Vcore quality.
PROCESSOR CORE POWER
CORE SUPPLY
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PEG AND DDR
1D05V_VTT
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
<Core Design>
Wistron Corporation
Title
CPU (VCC_CORE)
Size
Custom
SANDY
62.10055.421
2nd = 62.10040.771
5
3rd = 62.10055.321
3

Date:
2
Document Number
Rev
A00
QUEEN 15
Sheet
1
of
108
VAXG Output Decoupling Recommendation:

2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity
0726 Modify:
VCC_GFXCORE
POWER
un-stuff C906.
1D8V_S0
C924
SC1U10V2KX-1GP
VCCPLL
VCCPLL
VCCPLL
2
1
2
SENSE
LINES
20100609 V1.0
+V_SM_VREF_CNT
+V_SM_VREF_CNT 37
0719 Modify:
Add C907,C918,C919,C925 0402 0.1 uF stitching
capacitors between 1D5V_S3 & 1D5V_S0 based on
Intel's review
0D85V_S0
H23
FC_C22
VCCSA_VID1
C22
C24
1
2
DY
EC902
SCD1U50V3KX-GP
1
2
C917
SC10U6D3V5KX-1GP
C915
SC10U6D3V5KX-1GP
1
2
1
VCCSA_SENSE
C916
SC10U6D3V5KX-1GP
2
M27
M26
L26
J26
J25
J24
H26
H25
SCD1U10V2KX-5GP
C925
1
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C919
1
DY
SCD1U10V2KX-5GP
C918
2
1
1
2
DY
1D5V_S3
ST330U2VDM-4-GP
79.33719.20L
2nd = 77.C3371.13L
0617 Modify:
Joseph Removed TC902,TC903 330uF cap.
0719 Modify:
C917 for EMC NEO suggestion.
VCCSA Output Decoupling Recommendation:

1 x 330 uF
2 x 10 uF at Bottom Socket Cavity
0624 Modify:
Removed R902 10ohm closed CPU side.
0713 Modify:
Add R908 100ohm PH to 0D85V_S0.
0714 Modify:
Removed R908 PH.
VCCUSA_SENSE
VCCUSA_SENSE
H_FC_C22
VCCSA_SEL
H_FC_C22
VCCSA_SEL
48
48
48
DCBATOUT
SANDY
62.10055.421
2nd = 62.10040.771
3rd = 62.10055.321
TC901
VDDQ Output Decoupling Recommendation:

1 x 330 uF
6 x 10 uF
PROCESSOR VCCSA: 6A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
C914
SC10U6D3V5KX-1GP
C913
SC10U6D3V5KX-1GP
C912
SC10U6D3V5KX-1GP
SC10U6D3V3MX-GP
1
C911
DY
2
1
C910
2
DY
SC10U6D3V3MX-GP
1
C909
DY
SC10U6D3V3MX-GP
PROCESSOR VDDQ: 10A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1D5V_S0
C907
1
AL1
SM_VREF
VREF
+V_SM_VREF_CNT should have 10 mil trace width
C922
SC1U10V2KX-1GP
1
2
B6
A6
A2
R907
100R2F-L1-GP-U
Refer to the latest Huron River Mainstream PDG

(Doc# 436735) for more details on S3 power
reduction implementation.
RN901
SRN1KJ-7-GP
0714 Modify:
RN901 change to 1K PL from 10K
base on Intel PDDG updated.
VCCPLL Output Decoupling Recommendation:

1 x 330 uF
2 x 1 uF
1 x 10 uF
SCD1U50V3KX-GP
EC901
0617 Modify:
Joseph Removed TC902,
TC903 330uF cap.
C923
SC10U6D3V5KX-1GP
PROCESSOR VCCPLL: 1.2A
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
AK35
AK34
4
3
Disabling Guidelines for External Graphics Designs:

Can connect to GND if motherboard only supports external
graphics and if GFX VR is not stuffed.
Can be left floating (Gfx VR keeps VAXG rail from floating)
if the VR is stuffed
DDR3 -1.5V RAILS
Removed DIS_ONLY Disable Resistor.

R904,R905,R901,R903
VAXG_SENSE
VSSAXG_SENSE
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
SA RAIL
SANDY
MISC
0818
De-cap
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
GRAPHICS
1
C921
2
DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
C920
DY
2
2
0713 Modify:
Removed C907 10uf 0603 cap.
0726 Modify:
stuff C908 10uF.
C908
SC4D7U6D3V3KX-GP
0624 Modify:
Removed C918,C919 10uF 0603 for VCC_GFXCORE.
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.8V RAIL
1
2
DY
C906
SC10U6D3V5KX-1GP
C905
SC10U6D3V5KX-1GP
C904
SC10U6D3V5KX-1GP
PROCESSOR VAXG: 33A
1
2
C902
SC10U6D3V5KX-1GP
1
2
C901
SC10U6D3V5KX-1GP
R906
100R2F-L1-GP-U
7 OF 9
CPU1G
0721 Modify:
Removed C903
VCC_GFXCORE
1
2
SSID = CPU
1122 X02 Modify:

stuff EC901 0.1uF from
EMC Neo suggestion.
<Core Design>
Wistron Corporation
Title
CPU (VCC_GFXCORE)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
of
108
SSID = CPU
8 OF 9
CPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
3rd = 63.10055.321
9 OF 9
CPU1I
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
2nd = 62.10040.771
3rd = 62.10055.321
<Variant Name>
Wistron Corporation
Title
CPU (VSS)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
10
of
108
(Blanking)
<Variant Name>
Wistron Corporation
Title
XDP
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
11
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
12
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
13
of
108
1
2
DY
C1418
SC10U6D3V5KX-1GP
M_B_DQS#[7:0] 6
M_B_DQS[7:0] 6
6 M_B_DIM0_ODT0
6 M_B_DIM0_ODT1
0617 Modify:
from net to power.
RESET#
203
204
VTT1
VTT2
H =5.2mm
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
1
2
1D5V_S3
1D5V_S3
SODIMM A DECOUPLING
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
Layout Note:
Place these Caps near
SO-DIMMA.
DY
DY
2
DY
C1410
SC10U6D3V5KX-1GP
0818
De-cap
DY
DY
C1409
SC10U6D3V5KX-1GP
DY
TC1401
DY
C1408
SC10U10V5ZY-1GP
0617 Modify:
Joseph dummy TC1401 default un-stuff.
0818
De-cap
PART NUMBER
Height
TYPE
62.10017.P61
5.2mm
REVERSED
62.10017.N41(2nd) 5.2mm
REVERSED
62.10017.P41(3rd)
5.2mm
REVERSED
62.10024.E21(4th)
5.2mm
REVERSED
A
<Variant Name>
1110 X02 Modify:

DM2 1st change to 62.10017.P61; 2nd change
to 62.10017.N41 on ST stage from ME updated
connector list.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
DDR3-204P-48-GP
DDR3-SODIMM2
Size
Custom
2nd = 62.10017.N41
3rd = 62.10017.P41
4th = 62.10024.E21
4
2
10KR2J-3-GP
C1402
62.10017.P61
1R1403
DY
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
C1401
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
SA0_DIM1
SA1_DIM1
C1407
SC10U6D3V5KX-1GP
NC#1
NC#2
NC#/TEST
3D3V_S0
TS#_DIMM0_1
197
201
77
122
125
Thermal EVENT
3D3V_S0
TS#_DIMM0_1 15
SA0
SA1
PCH_SMBDATA 15,20,79,82
PCH_SMBCLK 15,20,79,82
C1406
SC10U6D3V5KX-1GP
199
VREF_CA
VREF_DQ
30
0D75V_S0
VDDSPD
ODT0
ODT1
126
1
15,37 DDR3_DRAMRST#
EVENT#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
116
120
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
200
202
198
R1401
10KR2J-3-GP
C1405
SC10U10V5ZY-1GP
12
29
47
64
137
154
171
188
11
28
46
63
136
153
170
187
C1417
SC1U6D3V2KX-GP
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DIM0_CLK_DDR1 6
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
102
104
If SA0 DIM0 = 1, SA1_DIM0 = 0

SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
SA0_DIM1
10
27
45
62
135
152
169
186
CK1
CK1#
SA1_DIM1
C1404
SC22U6D3V5MX-2GP
2
1
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DIM0_CLK_DDR0 6
C1416
SC1U6D3V2KX-GP
2
1
C1422
SC1U6D3V2KX-GP
DY
2
1
2
C1420
SC1U6D3V2KX-GP
DY
2
C1419
SC1U6D3V2KX-GP
1
2
C1421
SC1U6D3V2KX-GP
Place these caps

close to VTT1 and
VTT2.
0D75V_S0
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
101
103
SDA
SCL
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
0825
73
74
CK0
CK0#
0707 Modify:
Change R1404,R1405 to 0ohm 0402 from short pad.
R1402
10KR2J-3-GP
1
C1413
2
C1412
SCD1U10V2KX-5GP
DY
2
2
C
SCD1U10V2KX-5GP
C1411
SC2D2U10V3KX-1GP
M_VREF_DQ_DIMM1
M_B_DIM0_CS#0 6
M_B_DIM0_CS#1 6
C1403
SC10U6D3V5KX-1GP
R1404
0R0402-PAD-2-GP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
114
121
A00
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
CS0#
CS1#
CKE0
CKE1
BA0
BA1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_RAS# 6
M_B_WE# 6
M_B_CAS# 6
0617 Modify:
DDR_VREF_S3 from net to power.
110
113
115
C1415
SC1U6D3V2KX-GP
2
1
109
108
M_B_BS0
M_B_BS1
M_B_DQ[63:0]
RAS#
WE#
CAS#
ST330U2VDM-4-GP
2
1
M_B_BS2
NP1
NP2
6
6
6
3D3V_S0
NP1
NP2
C1414
SCD1U10V2KX-5GP
C1424
2
C1425
SCD1U10V2KX-5GP
DY
2
SCD1U10V2KX-5GP
C1423
SC2D2U10V3KX-1GP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
M_VREF_CA_DIMM1
A00
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
R1405
0R0402-PAD-2-GP
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
SC2D2U10V3KX-1GP
2
0617 Modify:
M_B_A[15:0] 6
from net to power.
0624 Modify:
SWAP DM1 and DM2 location.
SSID = MEMORY
DDR_VREF_S3
DM2
SCD1U10V2KX-5GP
2
Date:
3
Document Number
Rev
A00
QUEEN 15
Sheet
1
14
of
108
1
2
DY
C1521
SC1U6D3V2KX-GP
C1520
SC1U6D3V2KX-GP
1
2
C1518
SC1U6D3V2KX-GP
DY
C1519
SC1U6D3V2KX-GP
M_A_DQS#[7:0] 6
M_A_DQS[7:0] 6
116
120
6 M_A_DIM0_ODT0
6 M_A_DIM0_ODT1
126
1
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
30
14,37 DDR3_DRAMRST#
0617 Modify:
from net to power.
203
204
0D75V_S0
H =9.2mm
3
4
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
2
1
C1502
1D5V_S3
Layout Note:
Place these Caps near
SO-DIMMB.
DY
0818
De-cap
PART NUMBER
Height
TYPE
62.10017.Q41
9.2mm
REVERSED
62.10017.N11(2nd) 9.2mm
REVERSED
62.10017.N61(3rd) 9.2mm
REVERSED
62.10024.D91(4th)
REVERSED
9.2mm
DY
0818
De-cap
DY
DY
<Variant Name>
1110 X02 Modify:

DM1 1st change to 62.10017.Q41; 2nd change
to 62.10017.N11 on ST stage from ME updated
connector list.
Wistron Corporation
Title
DDR3-204P-42-GP
DDR3-SODIMM1
62.10017.Q41
2nd = 62.10017.N11
3rd = 62.10017.N61
4th = 62.10024.D91
5
DY
DY
C1510
SC10U6D3V5KX-1GP
DY
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
C1509
SC10U6D3V5KX-1GP
SODIMM B DECOUPLING
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1D5V_S3
C1501
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
DY
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
SA0_DIM0
SA1_DIM0
C1508
SC10U10V5ZY-1GP
NC#1
NC#2
NC#/TEST
77
122
125
197
201
SA0
SA1
3D3V_S0
TS#_DIMM0_1 14
C1507
SC10U6D3V5KX-1GP
199
C1506
SC10U6D3V5KX-1GP
12
29
47
64
137
154
171
188
VDDSPD
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
EVENT#
198
10
27
45
62
135
152
169
186
200
202
SO-DIMMB is placed farther from

the Processor than SO-DIMMA
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SDA
SCL
C1514
SCD01U50V2KX-1GP
Place these caps

close to VTT1 and
VTT2.
0D75V_S0
11
28
46
63
136
153
170
187
C1505
SC22U6D3V5MX-2GP
2
1
M_A_DIM0_CLK_DDR1 6
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
C1517
SCD1U10V2KX-5GP
C1516
102
104
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
DY
2
SCD1U10V2KX-5GP
C1515
SC2D2U10V3KX-1GP
M_VREF_DQ_DIMM0
M_A_DIM0_CLK_DDR0 6
R1503
0R0402-PAD-2-GP
A00
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6
C1504
SC10U10V5ZY-1GP
0617 Modify:
from net to power.
CK1
CK1#
BA0
BA1
73
74
101
103
C1512
SCD1U10V2KX-5GP
DDR_VREF_S3
CK0
CK0#
A00
C1503
SC10U10V5ZY-1GP
SCD1U10V2KX-5GP
C1522
CKE0
CKE1
RN1501
SRN10KJ-5-GP
C1511
SC1U6D3V2KX-GP
2
1
1
2
SCD1U10V2KX-5GP
C1524
DY
SC2D2U10V3KX-1GP
M_VREF_CA_DIMM0
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_A_DIM0_CS#0 6
M_A_DIM0_CS#1 6
R1501 R1502 for change to parallel resistor
R1504
0R0402-PAD-2-GP
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CS0#
CS1#
114
121
20101220
SC2D2U10V3KX-1GP
0617 Modify:
from net to power.
M_A_RAS# 6
M_A_WE# 6
M_A_CAS# 6
DDR_VREF_S3
109
108
110
113
115
M_A_BS0
M_A_BS1
M_A_DQ[63:0]
RAS#
WE#
CAS#
M_A_BS2
6
6
6
NP1
NP2
NP1
NP2
0707 Modify:
Change R1503,R1504 to 0ohm 0402 from short pad.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
SCD1U10V2KX-5GP
2
M_A_A[15:0] 6
C1523
SA1_DIM0
SA0_DIM0
DM1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
C1513
SCD01U50V2KX-1GP
2
1
SSID = MEMORY
A00
0624 Modify:
SWAP DM1 and DM2 location.
Size
Custom
Date:
3
Document Number
Rev
A00
QUEEN 15
Sheet
1
15
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
16
of
108
3D3V_S0
RN1701
L_CTRL_CLK
L_CTRL_DATA
T45
P39
LVDS_IBG
LVDS_VBG
LVD_VREFH
LVD_VREFL
49 LVDSA_CLK#
49 LVDSA_CLK
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
49 LVDSA_DATA0#
49 LVDSA_DATA1#
49 LVDSA_DATA2#
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
49 LVDSA_DATA0
49 LVDSA_DATA1
49 LVDSA_DATA2
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
TP1701
LVDS_VREFH
4
1
LVDS_VREFL
3
2
0712 Modify:
RN1704
SWAP
RN1704
A00 0R4P2R-PAD
0617 Modify:
Joseph Removed LVDSB related net for
single LVDS channel base on Dell updated spec.
0917 X01 Modify:

Add R1703~R1705 on RGB signal and reserved
EC1701~EC1703 0.1u from EMC Neo suggestion.
Close to PCH side
82
82
82
5
6
7
8
0923 SWAP
CRT_BLUE
CRT_GREEN
CRT_RED
82 CRT_DDC_CLK
82 CRT_DDC_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
82 CRT_HSYNC
82 CRT_VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC
T43
T42
DAC_IREF
CRT_IRTN
4
3
2
1
RN1705
SRN150F-1-GP
CRT_BLUE_N48
2
0R0402-PAD-2-GP
CRT_GREEN_P49
2
0R0402-PAD-2-GP
CRT_RED_T49
2
0R0402-PAD-2-GP
N48
P49
T49
1
R1703
1
R1704
1
R1705
CRT_BLUE
CRT_GREEN
CRT_RED
DAC_IREF_R
R1702
1KR2D-1-GP
1
2
1
2
DY
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
P38
M39
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
DDPC_CTRLCLK
DDPC_CTRLDATA
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
0804 Remove HDMI from PCH.
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
COUGAR-GP-U2-NF
CHIP RES 1K D 1/16W 0402
SCD1U50V3KX-GP
EC1703
DY
SCD1U50V3KX-GP
EC1702
DY
SCD1U50V3KX-GP
EC1701
CRT_BLUE
CRT_GREEN
CRT_RED
SDVO_STALLN
SDVO_STALLP
Notes:
1K 0.5% 0402.
AP43
AP45
SDVO_CTRLCLK
SDVO_CTRLDATA
A00
CRT_RED
CRT_BLUE
CRT_GREEN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_CTRL_CLK
L_CTRL_DATA
AE48
AE47
1
2
Impedance:90 ohm
L_DDC_CLK
L_DDC_DATA
LVD_IBG
LVD_VBG
R1701
2K37R2F-GP
L_BKLTCTL
AF37
AF36
TPAD14-GP
Place near PCH
P45
LVDS_DDC_CLK_R
T40
LVDS_DDC_DATA_R K47
49 LVDS_DDC_CLK_R
49 LVDS_DDC_DATA_R
Cougar
Point
Digital Display Interface
L_BKLT_EN
LVDS_VDD_EN
SRN100KJ-6-GP
0923 SWAP
L_BKLTEN
L_VDD_EN
CRT
RN1702
3
4
49 L_BKLT_CTRL
L_DDC_DATA(PAGE17):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
J47
M45
LVDS
27 L_BKLT_EN
49 LVDS_VDD_EN
SRN2K2J-1-GP
2
1
4 OF 10
PCH1D
L_CTRL_DATA
L_CTRL_CLK
4
3
RN
1
2
<Variant Name>
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
17
of
108
5 OF 10
3D3V_S0
3D3V_S0
INT_PIRQD#
INT_PIRQE#
INT_PIRQC#
INT_PIRQG#
SRN8K2J-2-GP-U
R1801
DY
A16 swap override Strap/Top-Block

Swap Override jumper
PCI_GNT#3
Low = A16 swap

override/Top-Block
Swap Override enabled
High = Default
1
2
4
3
DY
DY
2R1802
1KR2J-1-GP
2R1803
1KR2J-1-GP
BBS_BIT1
BBS_BIT0
BBS_BIT0 21
BOOT BIOS Strap

GNT1#/GPIO51 SATA1GP/GPIO19
LPC
83 DGPU_HOLD_RST#
TPAD14-GP TP1807
93 DGPU_PW R_EN#
Reserved
R1814
8K2R2J-3-GP
BOOT BIOS Location
Reserved
1
1
1
1
79 HDD_FALL_INT1
56 SATA_ODD_DA#
82
USB30_SMI#
69 KB_LED_BL_DET
TPAD14-GP
PCI_PLTRST#
PCI_GNT3#
D47
E42
F46
0R0402-PAD
INT_PIRQE# G42
2
0R0402-PAD
INT_PIRQF# G40
2
0R0402-PAD
INT_PIRQG# C42
2
0R0402-PAD
INT_PIRQH# D44
2
PCI_PME#
K10
C6
H49
H43
J48
K42
H40
DY
R1818
C1801
SC220P50V2KX-3GP
RSVD
RSVD
AT10
BC8
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD
DF_TVS
AV5
AY1
NV_ALE
NV_CLE
RSVD
AV10
NV_RCOMP
RSVD
AT8
RSVD
RSVD
AY5
BA2
RSVD
RSVD
AT12
BF3
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
R1809
NV_CLE
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
10KR2J-3-GP
2 FFS_INT2_R
Set to Vss when LOW

Set to Vcc when HIGH
1D8V_S0
TP1803
Danbury Technology:
Disabled when Low.
Enable when High.
TPAD14-GP
DY
R1810
1KR2J-1-GP
NV_ALE
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
USBRBIAS
B33
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
A14
K20
B17
C16
L16
A16
D14
C14

External debug port use on Huron river platform
USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
USB_PN11
USB_PP11
USB_PN12
USB_PP12
USB_PN13
USB_PP13
USB_RBIAS
Pair
Device
Touch Panel / 3G SIM
Fingerprint
BLUETOOTH
Mini Card2 (WWAN)
CARD READER
USB Ext. port 4 / E-SATA /USB CHARGE
USB Ext. port 2
10
USB Ext. port 3
11
Mini Card1 (WLAN)
12
CAMERA
13
Express Card
82
82
49
49
75
75
1
2
R1811
22D6R2F-L1-GP
USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
FFS_INT2_R
USB Table
49
49
82
82
64
64
63
63
82
82
32
32
USB_PN8 57
USB_PP8 57
USB_OC#0_1 61
1120 X02 Modify:

Reserved USB_OC#0_1 connect from PCH GPIO59.
USB_OC#8_9 61
79
0908
COUGAR-GP-U2-NF
0628 Modify:
Add EC1803 4.7pF 0402 on CLK_PCI_LPC
base on EMC NEO suggestion.
0707 Modify:
Change R1815,R1812,R1813 to 0ohm 0402
from short pad.
0719 Modify:
Reserved TP on CLKOUT_PCI3,4 from vender feedback.
OC[3:0]# for Device 29 (Ports 0-7)

OC[7:4]# for Device 26 (Ports 8-13)
<Variant Name>
RN1802
USB_OC#2_3
USB_OC#6_7
USB_OC#0_1
3D3V_S5
1
2
3
4
5
10
9
8
7
6
USB_OC#12_13
USB_OC#8_9
USB_OC#10_11
USB_OC#4_5
Wistron Corporation
3D3V_S5

Title
PCH (PCI/USB/NVRAM)
SRN8K2J-2-GP-U
H_SNB_IVB#
NV_CLE
Size
A3
Date:
2
1KR2J-1-GP
PME#
PLTRST#
DMI & FDI Termination Voltage
EC1803
DY
0908 X01 Modify:

Add R1818 10K PL on FFS_INT2_R(GPIO14)
1
2
20100625 V1.2
100KR2J-1-GP
2
1
DY
PIRQA#
PIRQB#
PIRQC#
PIRQD#
KBC CLK EMI
R1816
0629 Modify:
Reseved R1816 100K 0402 on PLT_RST#.
TP1802
SC4D7P50V2CN-1GP
2
0R0402-PAD-2-GP
A00
EC1801
DY
SC10P50V2JN-4GP
EC1802
DY
SC4D7P50V2CN-1GP
PLT_RST#
0617 Modify:
Joseph Remove PLT_RST AND
gate logic IC U1801/C1802.
5,27,71,75,82,83
R1812
R1813
R1815
R1817
0709 Modify:
PCI_PLTRST#
Add R1817 0ohm and connect to KB_LED_BL_DET.
(5V Tolerance High Active)
R1804 1
2 22R2J-2-GP CLK_PCI_LPC_R
CLK_PCI_LPC
R1805 1
2 22R2J-2-GP CLK_PCI_FB_R
CLK_PCI_FB
R1806 1
2 22R2J-2-GP CLK_PCI_KBC_R
CLK_PCI_KBC
71
20
27
C46
DGPU_SELECT# C44
E40
1
DGPU_PW R_EN#
1DGPU_PW M_SELECT#
TPAD14-GP TP1801
TPAD14-GP TP1806
R1807
K40
K38
H38
G38
BBS_BIT1
SPI(Default)
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
3D3V_S0
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
RN1803
DGPU_HOLD_RST#
DGPU_PW R_EN#
SRN10KJ-5-GP
B21
M20
AY16
BG46
1 4K7R2J-2-GP PCI_GNT3#
USB
INT_PIRQB#
INT_PIRQF#
INT_PIRQA#
10
9
8
7
6
PCI
1
2
3
4
5
AY7
AV7
AU3
BG4
NVRAM
RN1801
R1808
2K2R2J-2-GP
RSVD
RSVD
RSVD
RSVD
RSVD
0709 Modify:
Removed INT_PIRQH# on RN1801 pin1.
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
Cougar
Point
PCH1E
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
1D8V_S0
SSID = PCH
0719 Modify:
DF_TVS (NV_CLE) connect PROC_SELECT# (H_SNB_IVB#)
with R1808 2.2K5% pull up resistor to PCH VCCPNAND rail
and a R1809 1K5% series resistor base on Intel
feedback.
Document Number
Rev
A00
QUEEN 15
Sheet
1
18
of
108
SSID = PCH
4 DMI_RXN[3:0]
4 DMI_RXP[3:0]
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
4 DMI_TXN[3:0]
4 DMI_TXP[3:0]
3 OF 10
PCH1C
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
4
4
4
4
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
4
4
4
4
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
4
4
4
4
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BJ24
DMI_ZCOMP
FDI_FSYNC0
2 49D9R2F-GP DMI_COMP_R
BG25
DMI_IRCOMP
2 750R2F-GP
BH21
DMI2RBIAS
1D05V_VTT
R1901
R1902
20100628 V1.3
1 DY
2 R1926
10KR2J-3-GP
1
2 R1904
100KR2J-1-GP
SYS_PW ROK
PW ROK
36
3D3V_S0
SYS_PW ROK
1
R1924
2
0R0402-PAD
C12
DY
1 R1907
45,46,47,93 RUNPW ROK
SUSACK#
2
0R0402-PAD
SYS_RESET#
K3
2
0R0402-PAD
2 R1905
10KR2J-3-GP
P12
1R1923
2
0R2J-2-GP
DY
PW ROK
L22
1
R1925
1
XDP_DBRESET#
27,36 S0_PW R_GOOD
DY
1 R1906 2 0R0402-PAD
MEPW ROK
L10
2
0R2J-2-GP
B13
5,37 PM_DRAM_PW RGD
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

PM_RSMRST#
27 SUS_PW R_ACK
27 PM_PW RBTN#
FDI
0628 Modify:
Change R1904 to 100K 0402 from 10K and default stuff.
0629 Modify:
R1926 connect to SYS_PWROK.
0707 Modify:
Change R1903 change to 0ohm 0402 from short pad.
SUS_PW R_ACK
1
0707 Modify:
R1903
stuff R1925 and un-stuff R1905.
5
RBIAS_CPY
Cougar
Point
DMI

DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
27,86 AC_PRESENT
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
System Power Management
4
4
4
4
BATLOW #
E10
PM_RI#
A10
BATLOW#/GPIO72
RI#
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
4
4
4
4
4
4
4
4
FDI_INT
AW16
FDI_INT
AV12
FDI_FSYNC0
FDI_FSYNC1
BC10
FDI_FSYNC1
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
DPWROK
E22
PCH_DPW ROK
SUS_STAT#/GPIO61
G8
PM_SUS_STAT#
SUSCLK/GPIO62
N14
SUS_CLK
SLP_S5#/GPIO63
D10
PM_SLP_S5#
For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as no connect
4.SUSWARN# used as SUSPWRDNACK/GPIO30
1 R1910
R1911
DY1
2 0R0402-PAD PM_RSMRST#
2 10KR2J-3-GP
RTC_AUX_S5
PCH_W AKE# 27
PM_CLKRUN# 27
TP1901 TPAD14-GP
1 R1913
2 0R0402-PAD
PCH_SUSCLK_KBC
27
DSWODVREN - On Die DSW VR Enable
1
TP1902 TPAD14-GP
SLP_S4#
H4
SLP_S3#
F4
PM_SLP_S4# 27,46,75
HIGH
Enabled (DEFAULT)
LOW
Disabled
PM_SLP_S3# 27,36,37,47,75
SLP_A#
G10
PM_SLP_A#
SLP_SUS#
G16
PM_SLP_SUS#
PMSYNCH
AP14
H_PM_SYNC
K14
PM_SLP_LAN#
SLP_LAN#/GPIO29
DSW ODVREN
CLKRUN#/GPIO32
SUSWARN#/SUSPWRDNACK/GPIO30
ACPRESENT/GPIO31
4
4
4
4
4
4
4
4
N3
K16
H20
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
B9
RSMRST#
PWRBTN#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
WAKE#
C21
E20
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
1
1
RTC_AUX_S5
TP1903TPAD14-GP
TP1904TPAD14-GP
H_PM_SYNC
DSW ODVREN
R1917
R1918
2 330KR2J-L1-GP
DY
2 330KR2J-L1-GP
1
TP1905TPAD14-GP
COUGAR-GP-U2-NF
3D3V_S0
3D3V_S5
AC_PRESENT
2
100KR2J-1-GP
1
R1909
2 R1922
2 R1920
PM_CLKRUN#
PCIE_WAKE#
CRB : 1K
CEKLT: 10K
0920 X01 Modify:
move PCH_WAKE# to RN1901 pin4
Add R1909 PH on AC_PRESENT.
110KR2J-3-GP PM_PW RBTN#

110KR2J-3-GP PM_SLP_LAN#
0621 Modify:
Joseph removed Q1901/R1909/R1916 3V_5V_POK
and PM_RSMRST# related control circuit.
DY
<Variant Name>
Wistron Corporation
Title
PM_RSMRST#
PCH (DM I/FDI/PM)

Size
A3
Date:
2 8K2R2J-3-GP
0625 Modify:
Reserved EC1901 on PCH_SUSCLK_KBC for
EC1901 EMC NEO suggestion.
0719 Modify:
Change R1908 to 10K ohm based on Intel review:
8.2K to 10K pull-down is recommended.
2 R1908 1
10KR2J-3-GP
R1919
PCH_SUSCLK_KBC
DY
DY
RSMRST#_KBC 27
SRN10KJ-6-GP
PM_RSMRST# 1 R1912 2
0R0402-PAD
SC4D7P50V2CN-1GP
8
7
6
5
0907 X01 SWAP RN1901

RN1901
BATLOW #
1
PM_RI#
2
PCH_W AKE#
3
SUS_PW R_ACK
4
Document Number
Rev
A00
QUEEN 15
Sheet
1
19
of
108
3D3V_S5
SSID = PCH
3D3V_S50705 Modify:
Add R2004 from RN2001.
R2004
10KR2J-3-GP
DY
75 PCIE_RXN8
75 PCIE_RXP8
75 PCIE_TXN8
75 PCIE_TXP8
::$1&/.
C2004
C2003
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
A00
3
2
4 RN2011 1
0R4P2R-PAD
82 CLK_PCIE_W W AN#
82 CLK_PCIE_W W AN
RN
RN
82 CLK_PCIE_W W AN_REQ#
20100614 V1.1
:/$1&/.
PCIE_TXN8_C
PCIE_TXP8_C
CLK_PCH_SRC0_N
CLK_PCH_SRC0_P
82 CLK_PCIE_W LAN_REQ#
A00
CLK_PCH_SRC3_N
3
2
CLK_PCH_SRC3_P
4 RN2014 1
0R4P2R-PAD
82 CLK_PCIE_LAN#
82 CLK_PCIE_LAN
CLK_PCH_SRC4_N
CLK_PCH_SRC4_P
RN
0623 Modify:
Change PCIE_CLK_RQ2#&CLK_PCIE_WLAN_REQ#
pull high power to 3D3V_S0 from 3D3V_S5.(add RN2018)
1
2
PCIE_CLK_REQ5#
20100614 V1.1
RN2018
4
3
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
PCIE_CLK_RQ2#
CLK_PCIE_W LAN_REQ#
PEG_B_CLKRQ#
A00
3
2
4 RN2015 1
0R4P2R-PAD
75 CLK_PCIE_NEW _REQ#
CLK_PCIE_NEW #
CLK_PCIE_NEW
EC2004
EC2005
DY
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
TPAD14-GP
TPAD14-GP
SML1_CLK
SML1DATA/GPIO75
M16
SML1_DATA
TP2005
TP2006
1
1
CL_CLK
CL_DATA1
T11
CL_DATA 1
CL_RST1#
P10
CRB : 1K
CEKLT: 10K
AB37
AB38
Q2001
TP2002 TPAD14-GP
SMB_CLK
TP2003 TPAD14-GP
X02 1118
CL_RST# 1
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
CLKIN_GND1_N
CLKIN_GND1_P
BJ30
BG30
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
2R2003
0R2J-2-GP
4
1
3 RN2016 2
0R4P2R-PAD
CLKOUT_DMI_N
CLKOUT_DMI_P
PEG_CLKREQ# 83
A00
XTAL25_OUT
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
20100621 V1.2
3D3V_S0 3D3V_S0
R2012
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
2
1
3
4
SRN10KJ-5-GP
G24
E24
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLKIN_SATA_N
CLKIN_SATA_P
AK7
AK5
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
REFCLK14IN
K45
CLK_BUF_REF14
CLKIN_PCILOOPBACK
H45
CLK_PCI_FB
XTAL25_IN
XTAL25_OUT
V47
V49
PL 10K
FOR Integrated CLOCK GEN mode.
0712 Modify:
SWAP RN2020
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
SRN10KJ-5-GP
RN2020
CLK_BUF_DOT96_N 2
3
CLK_BUF_DOT96_P 1
4
CLK_PCI_FB
18
RN2021
CLK_BUF_CKSSCD_N 1
CLK_BUF_CKSSCD_P 2
0712 Modify:
SWAP RN2019
CLK_BUF_EXP_N
CLK_BUF_EXP_P
XTAL25_IN
XTAL25_OUT
PEG_B_CLKRQ#/GPIO56
Y47 XCLK_RCOMP
1
2
R2007
90D9R2F-1-GP
XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIE_CLK_REQ6#
T13
PCIECLKRQ6#/GPIO45
CLK_PCH_SRC7_N
CLK_PCH_SRC7_P
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
82.30020.D41SC12P50V2JN-3GP
2nd = 82.30020.G71
3rd = 82.30020.G61
0630 SWAP RN2010,RN2016
0712 Modify:
SWAP RN2008
UMA
3
4
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
F47
22R2J-2-GP
2
R2001
CLK_48_USB30
1 R2016
CLKOUTFLEX2/GPIO66
H47
CLK_27M_VGA_R
CLKOUTFLEX3/GPIO67
K49 DGPU_PRSNT#
0630 Modify:
COUGAR-GP-U2-NF
Removed XDP CLOCK and reserved TP2005,TP2006.
0913 X01 Modify:
V Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3
Reserved EC2004,EC2005 on CLK_PCIE_NEW
V Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0
&CLK_PCIE_NEW# for EMC suggestion.
and
DY
3D3V_S5
0705 Modify:
Separate RN2009 10K to RN2019,
RN2021,R2008 for layout routing.
222R2J-2-GP
1 R2002
0908
DY
CLK_PCH_48M 32
PCIE_CLK_LAN_REQ#
CLK_PCIE_W W AN_REQ#
USB3_PEGB_CLKREQ#
SRN10KJ-6-GP
RN2002
8 EC_SW I#
7 PCIE_CLK_REQ5#
5 PEG_B_CLKRQ#
<Variant Name>
Wistron Corporation
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
Size
A3
Date:
1
2
3
4
8
7
6
5
SRN10KJ-6-GP
0625 Modify:
Move R2014 to RN2002.
CLK_27M_VGA 83
0R2J-2-GP
0630 Modify:
Removed LAN_XI for LAN 25MHZ and reserved TP2004.
0707 Modify:
Removed R2002 for USB3.0 48MHZ.
0709 Modify:
Add R2002 22ohm for CLK_27M_VGA.
0717 Modify:
default stuff R2002 22ohm for CLK_27M_VGA.
0712 Modify:
SWAP RN2001 PIN6,7,8
RN2001
1
2
3
4
For VGA_ 27M
JTAG_TCK_VGA 86
MUXLESS
10KR2J-3-GP
JTAG_TCK
K43
UMA_DIS# 22
R2011
RN2019
2
1
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
Optimus(Muxless) : 1 0
UMA_DIS#
DGPU_PRSNT#
SRN10KJ-5-GP
4
3
SRN10KJ-5-GP
R2008
1
2
+VCCDIFFCLKN
CLK_BUF_REF14
R2013
R2010
DY
3
C2007
XTAL-25MHZ-155-GP2
1
CLK_EXP_N 5
CLK_EXP_P 5
CLK_BUF_EXP_N
CLK_BUF_EXP_P
SC12P50V2JN-3GP
R2006
1M1R2J-GP2
CLK_PCIE_VGA# 83
CLK_PCIE_VGA 83
4
1
3 RN2010 2
0R4P2R-PAD
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4#/GPIO26
1118 X02 Modify:

Change X2001 to 82.30020.D41 from 82.30020.851
from Sourcer Dick updated.
C2008
2
1
X2001
DY
A00
PCIECLKRQ3#/GPIO25
L12
RN2008
4 RN2006
3 SRN10KJ-5-GP
2N7002KDW -GP
SMB_DATA
SML1_DATA 27,86
M10 PEG_CLKREQ#_R
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
AK14
AK13
1
2
2nd = 84.DM601.03F
84.2N702.A3F
XTAL25_IN
PCIECLKRQ2#/GPIO20
E6
PCIE_CLK_REQ6#
PCH_GPIO74
For DIS_PX mode or MXM mode.
FLEX2
if more than 2 PCI clocks + PCI loopback are routed.
5
3
4
TP2001 TPAD14-GP
CLKOUT_PCIE2N
CLKOUT_PCIE2P
V40
V42
ITPXDP_N
ITPXDP_P
2
1
SML1_CLK 27,86
M7
CL_CLK1
PCIECLKRQ1#/GPIO18
CLK_PCIE_NEW _REQ# K12

RN
NEW CARD
CLKOUT_PCIE1N
CLKOUT_PCIE1P
Y43
Y45
3 RN2005
4 SRN2K2J-1-GP
DRAMRST_CNTRL_PCH 1 R2009 2
1KR2J-1-GP
0719 Modify:
R2009 change to 1K from 10K
base on Intel James feedback list.
3D3V_S0
Dock
PCIECLKRQ0#/GPIO73
SRN10KJ-5-GP
75 CLK_PCIE_NEW #
75 CLK_PCIE_NEW
PCH_GPIO74
E14
PEG_A_CLKRQ#/GPIO47
AB42
AB40
PCIECLKRQ1# and PCIECLKRQ2#

Support S0 power only
1(:&$5'&/.
C13
SML1CLK/GPIO58
CLKOUT_PCIE0N
CLKOUT_PCIE0P
Y37
Y36
2
1
PERN7
PERP7
PETN7
PETP7
RN
82 USB3_PEGB_CLKREQ#
3D3V_S0
BG40
BJ40
AY40
BB40
V10
37
RN2007
SML1ALERT#/PCHHOT#/GPIO74
A00
3
2
4 RN2013 1
0R4P2R-PAD
82 CLK_PCIE_USB3#
82 CLK_PCIE_USB3
Intel GBE LAN
A8
82 PCIE_CLK_LAN_REQ#
86%&/.
PERN6
PERP6
PETN6
PETP6
AA48
AA47
PCIE_CLK_RQ2#
/$1&/.
BJ38
BG38
AU36
AV36
A00
0623 Modify:
SWAP WLAN CLK and LAN CLK routing each other.
0716 Modify:
Rename PCIE_CLK_LAN_RQ1# to PCIE_CLK_LAN_REQ#.
20100614 V1.1
WLAN
USB3.0
J2
2 RN2004
1 SRN2K2J-1-GP
SRN2K2J-1-GP
PERN5
PERP5
PETN5
PETP5
0630 SWAP RN2012

CLK_PCH_SRC1_N AB49
4
1
CLK_PCH_SRC1_P AB47
3 RN2012 2
0R4P2R-PAD
M1
82 CLK_PCIE_W LAN#
82 CLK_PCIE_W LAN
SML0DATA
BG37
BH37
AY36
BB36
Y40
Y39
3
4
SML1_CLK
SML1_DATA
SML0_DATA
SML0_CLK
SML0_DATA
DY
SC4D7P50V2CN-1GP
SML0_CLK
G12
1 RN2003
2 SRN2K2J-1-GP
EC2003
C8
SML0CLK
DRAMRST_CNTRL_PCH
2
10KR2J-3-GP
CLK_PCH_48M
W-WAN
SML0ALERT#/GPIO60
PCIE_TXN5_C
PCIE_TXP5_C
DRAMRST_CNTRL_PCH
4
3
SMB_DATA 75
2
10KR2J-3-GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
A12
R2005
10KR2J-3-GP
SMB_CLK 75
C2009
C2010
PCIE_TXN4_C
PCIE_TXP4_C
PERN4
PERP4
PETN4
PETP4
SMB_DATA
2
10KR2J-3-GP
82 PCIE_RXN5
82 PCIE_RXP5
82 PCIE_TXN5
82 PCIE_TXP5
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
BF36
BE36
AY34
BB34
SMB_CLK
C9
C2005
C2006
PERN3
PERP3
PETN3
PETP3
H14
0915 SWAP
2
10KR2J-3-GP
82 PCIE_RXN4
82 PCIE_RXP4
82 PCIE_TXN4
82 PCIE_TXP4
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
SMBCLK
EC_SW I# 27
LAN
FLEX CLOCKS
C2011
C2012
EC_SW I#
RN
X02 1115
82 PCIE_RXN3
82 PCIE_RXP3
82 PCIE_TXN3
82 PCIE_TXP3
E12
RN
PCIE_TXN3_C
PCIE_TXP3_C
BG36
BJ36
AV34
AU34
Controller
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
CLOCKS
C2001
C2002
SMBALERT#/GPIO11
SMBDATA
Link
PERN2
PERP2
PETN2
PETP2
SMBUS
PCIE_TXN2_C
PCIE_TXP2_C
BE34
BF34
BB32
AY32
PCI-E*
PERN1
PERP1
PETN1
PETP1
Cougar
Point
Card Reader
BG34
BJ34
AV32
AU32
82 PCIE_RXN2
82 PCIE_RXP2
82 PCIE_TXN2
82 PCIE_TXP2
PEG_CLKREQ#_R
2 OF 10
PCH1B
1112 X02 Modify:
Dell required us to disable PCIE port of WWAN slot
,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1
at ST stage.
SMB_CLK
SMB_DATA
Document Number
Rev
A00
QUEEN 15
Sheet
1
20
of
108
SSID = PCH
RTC_X2
2
10MR2J-L-GP
INTVRMEN- Integrated SUS

1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
C2103
SC1U6D3V2KX-GP
0720 Modify:
un-stuff R2122 33ohm.
20101220
HDA_SYNC
3
4
HDA_SDOUT
1 R2102
21KR2J-1-GP
TPAD14-GP
R2106
21KR2J-1-GP HDA_SPKR
Low = Default
HDA_SPKR High = No Reboot
+3VS_+1.5VS_HDA_IO
B
TPAD14-GP
TP2101
INTVRMEN
HDA_BITCLK
N34
HDA_BCLK
HDA_SYNC
L34
HDA_SYNC
T10
SPKR
HDA_RST#
K34
HDA_RST#
TP2105
1PCH_GPIO33
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
PCH_JTAG_TCK_BUF
TPAD14-GP
TP2102
PCH_JTAG_TMS
H7
JTAG_TMS
TPAD14-GP
TP2103
PCH_JTAG_TDI
K5
JTAG_TDI
TPAD14-GP
TP2104
PCH_JTAG_TDO
H1
JTAG_TDO
2 1KR2J-1-GP
HDA_SYNC
27,60 SPI_CS0#_R
This signal has a weak internal pull down.

On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
2 PCH_SPI_CLK
33R2J-2-GP
2 PCH_SPI_CS0#
33R2J-2-GP
1
R2108
1
R2109
27,60 SPI_CLK_R
1 R2103
INTRUDER#
2 PCH_SPI_SI
33R2J-2-GP
1
R2110
27,60 SPI_SI_R
27,60 SPI_SO_R
J3
T3
LPC
C38
A38
B37
C37
FWH4/LFRAME#
D36
LDRQ0#
LDRQ1#/GPIO23
E36
K36
SERIRQ
HDA_SDOUT
No Reboot Strap
DY1
C17
HDA_SDOUT
2 1KR2J-1-GP
1 R2107
27 ME_UNLOCK
Low = Default
High = Enable
NO REBOOT STRAP
3D3V_S0
PCH_INTVRMEN
Notes:
ME_UNLOCK (HDA_SDO) connect to EC.
Make sure EC drive this pin "low" all the time.
Flash Descriptor Security Overide
DY
K22
29 HDA_SDIN0
HDA_SDOUT
HDA_SYNC_R
RN2105 SRN33J-5-GP-U
+3VS_+1.5VS_HDA_IO
SRTCRST#
SM_INTRUDER#
29 HDA_SPKR
A00
2
1
RTCRST#
G22
1R2122 HDA_SYNC
SRN33J-5-GP-U
29 HDA_CODEC_SDOUT
D20
SRTC_RST#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
R2105
330KR2F-L-GP
0707 Modify:
Change RN2101 to R2122,R2123 33ohm 0402.
RN2102
HDA_RST#
1
4
HDA_BITCLK
2
3
29 HDA_CODEC_RST#
29 HDA_CODEC_BITCLK
RTC_RST#
1M1R2J-GP
R2104
2
1
GAP-OPEN
RTC_AUX_S5
Cougar
Point
SATA 6G
DY
RTCX2
SATA
33R2J-2-GP2
29 HDA_CODEC_SYNC
C20
IHDA
82.30001.A81
2nd = 82.30001.691
3rd = 82.30001.861
X-32D768KHZ-67-GP
G2101
RTCX1
RTC_X2
RTC
2
C2104
SC1U6D3V2KX-GP
C2102
SC15P50V2JN-2-GP
0805
A20
JTAG_TCK
JTAG
RTC_X1
LPC_AD[0..3]
27,71
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME# 27,71
0709 Modify:
KB_DET# connect to GPIO23.(inter PH 20K)
KB_DET# 69
V5
INT_SERIRQ
27
20100625 V1.2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AM3
AM1
AP7
AP5
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4
56
56
56
56
ODD
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
SATA_RXN5
SATA_RXP5
SATA_TXN5
SATA_TXP5
57
57
57
57
ESATA
SATAICOMPO
Y11
SATAICOMPI
Y10
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
56
56
56
56
HDD1
HDD2
0629 Modify:
Move All of 0.01uF cap closed to all
connector base on Layout guideline.
1D05V_VTT
SATA_COMP
R2112
2 37D4R2F-GP
1D05V_VTT
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3_COMP R2113
2 49D9R2F-GP
SATA3RBIAS
AH1
RBIAS_SATA3 R2114
2 750R2F-GP
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
SPI
C2101
SC15P50V2JN-2-GP
2
1
LPC_AD[0..3]
1 OF 10
PCH1A
X2101
R2115
20KR2J-L2-GP
2
2
R2116
20KR2J-L2-GP
RTC_X1
0630 modify:
Change RN2104 PH 20K to
R2115,R2216 20K 0402.
RTC_AUX_S5
1
1
R2101
SATALED#
P3
SATA_LED# 68
SATA0GP/GPIO21
V14
SATA_DET#0
SATA1GP/GPIO19
P1
BBS_BIT0
BBS_BIT0 18
COUGAR-GP-U2-NF
PLL ODVR VOLTAGE
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
Low = 1.8V (Default)

HDA_SYNC High = 1.5V
RUN_ENABLE
2N7002K-2-GP
0625 Modify:
Reserved EC2102,EC2103 on HDA_CODEC_BITCLK&HDA_CODEC_SDOUT for
EMC NEO suggestion.
G
D
HDA_CODEC_BITCLK
HDA_CODEC_SDOUT
22
SPI_CS0#_R
S_GPIO
1
2
3
4
0720 Modify:
Add R2117 100K and stuff Q2101,R2124.
2
EC2101
DY
8
7
6
5
0916 X01 Modify:

Add RN2104 instead of R2111 10K.
<Variant Name>
SRN10KJ-6-GP
SC4D7P50V2CN-1GP
0707 Modify:
Reserved Q2101 for isolate CODE and PCH
base on design guide update 1.01.
0712 Modify:
Add R2124 between HDA_SYNC_R and HDA_SYNC.
EC2103
DY
EC2102
DY
1
2ND = 84.2N702.031
SC4D7P50V2CN-1GP
84.2N702.J31
SC4D7P50V2CN-1GP
R2117
100KR2J-1-GP
Q2101
HDA_CODEC_SYNC
3D3V_S0
RN2103
INT_SERIRQ
SATA_DET#0
HDA_SYNC_R
Wistron Corporation
RN2104
22
22
FP_DET#
PSW _CLR#
4
3

1
2
Title
SRN10KJ-5-GP
PCH (SPI/RTC/LPC/SATA/IHDA)
Size
A3
0625 Modify:
Reserved EC2101 on SPI_CSO#_R for
EMC NEO suggestion.
Date:
3
Document Number
Rev
A00
QUEEN 15
Sheet
1
21
of
108
H36
EC_SCI#
E38
ICC_EN#
C10
C4
PCH_GPIO15
G2
0701 Modify:
Separate PCH_TEMP_ALERT# from RN2201
to R2222 10K base on layout limitation.
TPAD14-GP
82
0709 Modify:
Rename PCH_GPIO22 to DBC_EN.
Rename PCH_GPIO24 to 3G_EN.
3D3V_S0
TP2210
DBC_EN
3G_EN
TPAD14-GP
TP2203
PCH_GPIO27
PLL_ODVR_EN
10KR2J-3-GP
RN2201
EC_SMI#
EC_SCI#
DGPU_HPD_INTR#
DBC_EN
0923 SWAP
1
2
3
4
0916
Move
Move
Move
8
7
6
5
X01 Modify:
EC_SCI#,DBC_EN to RN2201.
S_GPIO to RN2103.
PSW_CLR# to RN2104.
PSW _CLR#
21
GAP-OPEN
0701 Modify:
21RN2202 PSW _CLR#
Separate MFG_MODE from
to R2223 10K base on layout limitation.
3D3V_S5
61
TPAD14-GP
TP2206
SCLOCK/GPIO22
E8
GPIO24/MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI#/GPIO34
N2
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
SDATAOUT1/GPIO48
V3
SATA5GP/GPIO49
D6
GPIO57
A4
NCTF_VSS#A4
A44
NCTF_VSS#A44
A45
NCTF_VSS#A45
A46
NCTF_VSS#A46
A5
NCTF_VSS#A5
A6
NCTF_VSS#A6
B3
NCTF_VSS#B3
3G_EN
2
10KR2J-3-GP
B47
NCTF_VSS#B47
20100625 V1.2
0629 Modify:
Add R2221 10K 0402 on PCH_GPIO24(ANNIE updated)
0709 Modify:
Rename PCH_GPIO24 to 3G_EN on R2221.
P4
H_PECI_R
BD1
NCTF_VSS#BD1
BD49
NCTF_VSS#BD49
TPAD14-GP
TP2207
PCH_NCTF_2
BE1
NCTF_VSS#BE1
TPAD14-GP
TP2208
PCH_NCTF_3
BE49
NCTF_VSS#BE49
BF1
NCTF_VSS#BF1
TPAD14-GP
TP2209
PCH_NCTF_4
BF49
NCTF_VSS#BF49
COUGAR-GP-U2-NF
1 R2203
DY
P5
H_RCIN#
AY11
THRMTRIP#
AY10
PCH_THERMTRIP_R
INIT3_3V#
T14
INIT3_3V#
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
AK10 TS_VSS 1
R2219
NC_1
P37
NCTF_VSS#BG2
BG2
NCTF_VSS#BG48
BG48
2
0R2J-2-GP
H_PECI
5,27
DY
27
H_CPUPW RGD
R2204
5,36
2 390R2J-1-GP
GSENSOR_DET
R2206
100KR2J-1-GP
H_THERMTRIP# 5,36
TP2201 TPAD14-GP
2
0R0402-PAD
R2205
10KR2J-3-GP
H_A20GATE 27
AU16
PROCPWRGD
TS_VSS4
USB2_CRT_ON#
2
1KR2J-1-GP
PECI
RCIN#
GPIO35
PCH_TEMP_ALERT#
R2221
B
TACH0/GPIO17
SATA3GP/GPIO37
1
2
1 R2201
SATA4GP/GPIO16
T5
SRN10KJ-5-GP
PCH_GPIO15
A20GATE
SATA2GP/GPIO36
PCH_NCTF_1
DY
GPIO15
V8
0714 Modify:
Add TP2206~TP2209 on PCH NCTF pin.
RN2204
LAN_PHY_PWR_CTRL/GPIO12
M5
PCH_GPIO48
3D3V_S0
GPIO8
FDI_OVRVLTG
MFG_MODE
USB2_CRT_ON#
TP2205 TPAD14-GP
DMI_OVRVLTG
GSENSOR_DET
1118 X02 Modify:

Rename USB3_PWR_ON to PCH_GPIO57.
1120 X02 Modify:
Reserved USB2_CRT_ON# to control
U6102 USB power switch from PCH GPIO57.
1120 X02 Modify:

Rename PCH_GPIO12 to RTC_DET#
on GPIO12.
4
3
G2201
1118 X02 Modify:

Rename GFX_CRB_DET to GSENSOR_DET
on GPIO39.
SRN10KJ-6-GP
RTC_DET#
USB2_CRT_ON#
D40
K4
FP_DET#
R2223
MFG_MODE
U2
10KR2J-3-GP
R2222
PCH_TEMP_ALERT#1
TP2204 TPAD14-GP
DY
DGPU_PW ROK
83,92,93 DGPU_PW ROK
A40 VRAM_SIZE2
0625 Modify:
Change PL 100K 0402 from PH on GFX_CRB_DET.
TS Signal Disable Guideline:

TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
should not float on the motherboard. They should
be tied to GND directly.
0707 Modify:
Change R2219 change to 0ohm 0402 from short pad.
NCTF_VSS#BH3
BH3
NCTF_VSS#BH47
BH47
NCTF_VSS#BJ4
BJ4
NCTF_VSS#BJ44
BJ44
NCTF_VSS#BJ45
BJ45
NCTF_VSS#BJ46
BJ46
NCTF_VSS#BJ5
BJ5
NCTF_VSS#BJ6
BJ6
NCTF_VSS#C2
C2
3D3V_S0
0720 Modify:
Removed DBC_EN on GPIO22.
C41 VRAM_SIZE1
TACH7/GPIO71
FDI TERMINATION VOLTAGE OVERRIDE

R2207
10KR2J-3-GP
DY
2
TACH6/GPIO70
TACH3/GPIO7
10K
FDI_OVRVLTG
GPIO37
(FDI_OVRVLTG)
LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)
10KR2J-3-GP
PCH_GPIO48
2
TACH2/GPIO6
100K
NCTF_VSS#C48
C48
NCTF_VSS#D1
D1
NCTF_VSS#D49
D49
R2208
10KR2J-3-GP
R2220
2 PCH_GPIO16
0R0402-PAD
1
R2213
56 SATA_ODD_PRSNT#
3D3V_S0
UMA_DIS# 20
R2206
GSENSOR_ADI
DMI TERMINATION VOLTAGE OVERRIDE
3D3V_S0
GPIO36
(DMI_OVRVLTG)
LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)
change FFS_INT2_R from PCH GPIO48 to GPIO14

Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220
B41 UMA_DIS#
DY
RTC_DET#
RTC_DET#
SATA_ODD_PW RGT 56
TACH5/GPIO69
R2209
10KR2J-3-GP
DY
NCTF_VSS#E1
E1
NCTF_VSS#E49
E49
60
DGPU_HPD_INTR#
TACH4/GPIO68
Cougar
Point
DMI_OVRVLTG
EC_SCI#
TACH1/GPIO1
BMBUSY#/GPIO0
R2205
NCTF_VSS#F1
F1
NCTF_VSS#F49
F49
Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock
enable.
R2210
10KR2J-3-GP
Integrated Clock Chip Enable

2
27
A42
C40
CPU/MISC
EC_SMI#
T7
GPIO
1120 X02 Modify:

Rename PCH_GPIO12 to RTC_DET#
on GPIO12.
27
PCH1F
GPIO0
2
100R2J-2-GP
EC_SMI#
NCTF
S_GPIO
1 R2218
D1,D49,E1,E49,F1,F49
GPIO27 has a weak[20K] internal pull up.

To enable on-die PLL Voltage regurator,
should not place external pull down.0908 X01 Modify:
21
S_GPIO
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
SRN10KJ-5-GP
V1.2
NCTF TEST PIN:
100KR2J-1-GP
0629 Modify:
20100625
0712 Modify: Stuff R2202 200K 0402 1%(ANNIE updated)
SWAP RN2203
RN2203
H_A20GATE
2
3
H_RCIN#
1
4
6 OF 10
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
3D3V_S0
SATA_ODD_PRSNT#
GSENSOR_ST
Note:
For PCH debug with XDP, need to NO STUFF R2218
R2202
SSID = PCH
0719 Modify:
Change R2202 to 100K from 200K.
3D3V_S0
ICC_EN#
HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)-
ICC_EN#1 R2211
2
1KR2J-1-GP
ENABLED
GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock
enable.
[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G
A
<Variant Name>
PLL ON DIE VR ENABLE

0705 Modify:
Removed R2214~R2217 10K 0402 on VRAM_SIZE1&2.
Wistron Corporation
NOTE:This

signal has a weak internal pull-up
20K
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)

Title
PLL_ODVR_EN
PCH (GPIO/CPU)
DY 1 R2212 2
Size
A3
1KR2J-1-GP
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
22
of
108
SSID = PCH
3D3V_DAC_S0
A00 1228
6A
R2301
2
3D3V_S0
0R0402-PAD-2-GP
0818
De-cap
AM37
0.06A
VCCTX_LVDS
AM38
+1.8VS_VCCTX_LVDS
VCCTX_LVDS
AP36
VCCTX_LVDS
AP37
VCC3_3
V34
VCCIO
AP21
VCCIO
AP23
VCCIO
AP24
VCCIO
AP26
VCCIO
AT24
VCCIO
1
2
3rd = 68.00335.081
3D3V_S0
1 R2304 2
0R0603-PAD
0917 X01 Modify:
Change R2304 to 0R0603
short pad from 0ohm.
C2318
1
2
1D8V_S0
1 R2305 2
0R0805-PAD
3D3V_S0
AT16
VCCDMI
AT20
(0.1uFx1)
0.266A
0.16A
VCCVRM
C2319
SCD1U10V2KX-5GP
1D5V_S0
1119 X02 Modify:

Reserved R2308 on VCCVRM power rail.
1D05V_VTT
0R0402-PAD-2-GP
A00
+1.05VS_VCC_DMI
AB36
A00
R2308
1
VCCVRM
0.042A
VCCCLKDMI
(0.01uF x2)
(22uF x1)
SC10U6D3V5KX-1GP
V33
SC10U6D3V5KX-1GP
VCCTX_LVDS
VCC3_3
SCD1U10V2KX-5GP
AK37
VCCIO
AN27
VSSALVDS
VCCIO
AN26
1
AK36
AN21
VCCALVDS
68.00214.051
2nd = 68.00206.041
C2317
SCD01U16V2KX-3GP
VCCIO
+3VS_VCCA_LVDS
C2314
C2316
SCD01U16V2KX-3GP
AN17
C2313
VCCIO
U47
VCCAPLLEXP
AN16
VSSADAC
1
R2306
(1uF x1)
0R0402-PAD-2-GP
C2320
SC1U6D3V2KX-GP
1
2
C2309
SC1U6D3V2KX-GP
C2308
SC1U6D3V2KX-GP
C2307
SCD1U10V2KX-5GP
C2306
SC1U6D3V2KX-GP
1
2
C2305
SC10U6D3V5KX-1GP
(1uF x4)
BJ22
(10uF x1)
HVCMOS
VCCAPLLEXP
2.925A(Total current of VCCIO)
DMI
TP2301
VCCIO
TPAD14-GP
1D05V_VTT
VCCIO
(0.1uF/0.01uF x1)
(10uF x1_0603)
+VCCA_DAC_1_2
CRT
1D05V_VTT
AN19
VCCADAC
U48
0.001A
LVDS
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
7 OF 10
0.001A
Cougar
Point
VCC CORE
1
2
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
C2304
SC1U6D3V2KX-GP
C2303
SC1U6D3V2KX-GP
1
2
(1uFx3)
(10uFx1_0603)
C2302
SC1U6D3V2KX-GP
C2301
SC10U6D3V5KX-1GP
1.3A(Total current of VCCCORE)
SCD01U16V2KX-3GP
POWER
PCH1G
1D05V_VTT
1111 X02 Modify:

Change VCCADAC power source to
3D3V_DAC_S0 from 3D3V_S0.
L2301
1
DY 2
HCB1608KF-181-GP
C2315
Refer to NPCE795 shared SPI flash architecture
1D05V_VTT
A00
0.02A
+1.05VS_VCC_DMI_CCI
AN33
BH29
VCC3_3
C2310
SCD1U10V2KX-5GP
VccDFTERM
AG16
1
2
R2307
0R0402-PAD-2-GP
C2321
SC1U6D3V2KX-GP
VccDFTERM
AG17
VccDFTERM
AJ16
VccDFTERM
AJ17
0.159A(Totally current of VCCVRM)
AP16
1D5V_S0
TP2302
VCCFDIPLL
BG6
VCCAFDIPLL
1D8V_S0
B
C2322
SCD1U10V2KX-5GP
(0.1uFx1)
TPAD14-GP
(1uFx1)
(10uFx1)
0.19A
1D05V_VTT
+1.05VS_VCC_DMI
0.042A (Totally current of VCCDMI)
AP17
VCCIO
AU20
VCCDMI
VCCSPI
V1
3D3V_S5
0.02A
1
VCCVRM(Internal PLL and VRMs):

A.1.5V for Mobile
B.1.8 V for Desktop
VCCVRM
FDI
(0.1uF x1)
NAND / SPI
VCCIO
VCCIO
AN34
3D3V_S0
0.266A (Totally VCC3_3 current)
(1uFx1)
C2323
SC1U6D3V2KX-GP
COUGAR-GP-U2-NF
3.3V CRT LDO

Current Limit=360mA
5V_S5
3D3V_S0
3D3V_DAC_S0
U2301
1
2
3
VOUT
NC#4
G9091-330T11U-GP
20100621 V1.2
C2312
2nd = 74.09198.G7F
3rd = 74.07716.A7F
1117 X02 Modify:

Add G9091 LDO circuit for CRT DAC power
to avoid monitor noise issue.
1122 X02 Modify:
base on layout condition change 3D3V_DAC_S0
circuit.
SC1U6D3V2KX-GP
74.09091.J3F
SC1U10V2KX-1GP
C2311
VIN
GND
EN
1122 X02 Modify:

Removed U2302 LDO for VCCVRM.
<Variant Name>
Wistron Corporation
Title
PCH (POWER1)
Size
A3
A00 1229 add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
23
of
108
DCPSUSBYP
V12
DCPSUSBYP
+V3.3S_VCC_CLKF33
T38
VCC3_3
TP2405
TPAD14-GP
TP2404
C2402
SC1U10V2KX-1GP
+VCCAPLL_CPY_PCH
1D05V_VTT (10uFx1)
TP2402
+VCCSUS1
VCCSUS3_3
V24
VCCSUS3_3
P24
VCCIO
T26
V5REF_SUS
M26
+5VA_PCH_VCC5REFSUS
DCPSUS
AN23
+VCCA_USBSUS
VCCSUS3_3
AN24
VCCASW
AA29
VCCASW
AA31
VCCASW
AC26
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
3D3V_S0
W26
VCCASW
W29
VCCASW
V5REF
P34
VCCSUS3_3
N20
VCCSUS3_3
N22
VCCSUS3_3
P20
VCCSUS3_3
P22
VCCASW
W33
VCCASW
N16
DCPRTC
Y49
VCCVRM
D2402
CH751H-40PT-GP
VCC3_3
AA16
VCC3_3
W16
VCC3_3
T34
VCC3_3
AJ2
C2428
SC1U6D3V2KX-GP
0.095A
+V1.05S_SSCVCC
SCD1U10V2KX-5GP(1uFx1)
C2415
2
1 +VCCSST
VCCADPLLB
VCCIO
VCCDIFFCLKN
VCCDIFFCLKN
VCCDIFFCLKN
VCCSSC
V16
DCPSST
T17
V19
DCPSUS
DCPSUS
(0.1uFx2)
(1uFx1)
VCCRTC
MISC
CPU
V_PROC_IO
HDA
6uA
A22
COUGAR-GP-U2-NF
1
2
RTC_AUX_S5
BJ8
C2422
SCD1U10V2KX-5GP
C2417
SC4D7U6D3V3KX-GP
(0.1uFx2)
(4.7uFx1_0603)
1D05V_VTT
C2418
SCD1U10V2KX-5GP
C2413
SC1U6D3V2KX-GP
DCPSUS
3D3V_S0
C2430
SCD1U10V2KX-5GP
(0.1uFx2)
C2431
SCD1U10V2KX-5GP
AF13
VCCIO
AH13
VCCIO
AH14
VCCIO
AF14
C2429
SCD1U10V2KX-5GP
(0.1uFx1)
VCCIO
1D05V_VTT
VCCAPLLSATA
(1uFx1)
C2432
SC1U6D3V2KX-GP
1D05V_VTT
AK1
R2411
+V1.05S_VCCAPLL_SATA3
VCCVRM
AF11
VCCIO
AC16
VCCIO
AC17
VCCIO
AD17
1D5V_S0
1D05V_VTT
RTC
TPAD14-GP TP2406
1
0714 Modify:
Removed C2419 1uF base on
Annie updated schematic.
(1uFx1)
C2427
SC1U10V2KX-1GP
3D3V_S0
VCCADPLLA
AG33
10R2J-2-GP
(1uFx1)
1
1
AF17
AF33
AF34
AG34
(1uFx1)
3D3V_S5
C2434
+VCCDIFFCLK
R2407
C2414
SC1U6D3V2KX-GP
BF47
83.R0304.A8F
2nd = 83.R2004.B8F
0.001A
+5VS_PCH_VCC5REF
DY
1 R2406 2
0R0603-PAD
BD47
+1.05VS_VCCA_B_DPL
5V_S0
TPAD14-GP
DYC2437
SC1U10V2KX-1GP
W31
+1.05VS_VCCA_A_DPL
(1uFx1)
0.055A
C2421
SCD1U10V2KX-5GP
3D3V_S5
VCCASW
T21
VCCASW
V21
VCCASW
T19
VCCSUSHDA
P32
C2435
SCD1U10V2KX-5GP
0818
De-cap
DY
(10uFx1)
0R3J-0-U-GP
SC10U6D3V5KX-1GP
+VCCDIFFCLKN
0.001A
TP2403
VCCASW
AA27
0.001A
AA26
(0.1uFx1)
C2426
SCD1U10V2KX-5GP
C2425
SCD1U10V2KX-5GP
1D05V_VTT
VCCASW
+V1.05S_SSCVCC
(0.1uFx1)
10R2J-2-GP
1D05V_VTT
(1uFx1)
R2405
0R0402-PAD-2-GP
VCCASW
2nd = 83.R2004.B8F 83.R0304.A8F

R2408
3D3V_S5
+3VS_+1.5VS_HDA_IO
1 R2409 2
0R0603-PAD
+3VS_+1.5VS_HDA_IO
C2433
SCD1U10V2KX-5GP
3D3V_S5
<Variant Name>
0.01A
1
C2412
SC1U6D3V2KX-GP
1D5V_S0
(0.1uFx1)
2
(0.1uFx1)
C2424
SCD1U10V2KX-5GP
C2408
SCD1U10V2KX-5GP
1
2
C2407
SC1U6D3V2KX-GP
(0.1uFx1)
(1uFx1)
VCCSUS3_3
V23
D2401
CH751H-40PT-GP
(0.1uFx1)
Wistron Corporation
2
A00
T24
VCCASW
AA24
0.16A (Totally current of VCCVRM
1
+VCCDIFFCLK
2
0R0402-PAD-2-GP
1D05V_VTT
+VCCRTCEXT
1D05V_VTT
A00
VCCSUS3_3
5V_S5
D
0.097A (Totally current of VCCSUS3_3)
R2404
C2406
SC1U6D3V2KX-GP
1
2
0617 Modify:
Joseph Rename 1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM.
C2411
SCD1U10V2KX-5GP
1D05V_VTT
VCCSUS3_3
T23
3D3V_S5
3D3V_S5
1
C2410
SC1U6D3V2KX-GP
DY
T29
(1uFx1)
(220uFx1)
C2444
2nd = 68.1001E.10N
0714 Modify:
Reserved C2443,C2444 on +1.05VS_VCCA_A_DPL,
+1.05VS_VCCA_B_DPL same as DG15.
+1.05VS_VCCA_B_DPL
1
2
IND-10UH-218-GP
68.10050.10Y
0818
De-cap
1
2
1
2
SC10U6D3V3MX-GP SC10U6D3V3MX-GP
C2409
SC1U6D3V2KX-GP
0.08A
L2403
DCPSUS
AA21
+1.05VS_VCCA_A_DPL
DY
VCCIO
0818
De-cap
L2402
2nd = 68.1001E.10N
T27
(220uFx1)
C2443
P28
VCCIO
0.08A (1uFx1)
C2404
SC10U6D3V5KX-1GP
1
2
C2403
SC10U6D3V5KX-1GP
(22uFx2_0603)
(1uFx3)
1
2
IND-10UH-218-GP
VCCIO
(1uFx1)
C2423
SCD1U10V2KX-5GP
AA19
1.01A (Total current of VCCASW)
68.10050.10Y
VCCIO
AL24
1D05V_VTT
1D05V_VTT
VCCAPLLDMI2
AL29
P26
TPAD14-GP
BH23
PCI/GPIO/LPC
2nd = 68.1001E.10N
68.10050.10Y
SC10U6D3V5KX-1GP
+V3.3S_VCC_CLKF33
C2401
SATA
L2401
1
2
IND-10UH-218-GP
Clock and Miscellaneous
USB
TPAD14-GP
VCCIO
(0.1uFx1)
(10uFx1)
(1uFx1)
N26
VCCDSW3_3
VCCIO
T16
1D05V_VTT
10 OF 10
Cougar
Point
+VCCPDSW
POWER
VCCACLK
1 R2403 2
0R0603-PAD
AD49
0.002A
3D3V_S5
3D3V_S0
VCCACLK
TP2401
PCH1J
TPAD14-GP
SSID = PCH
Title
PCH (POWER2)
Size
A3
Date:
3
Document Number
Rev
A00
QUEEN 15
Sheet
1
24
of
108
SSID = PCH
8 OF 10
PCH1H
H5
VSS
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
COUGAR-GP-U2-NF
A
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 10
PCH1I
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
<Variant Name>
Wistron Corporation
Title
COUGAR-GP-U2-NF
PCH (VSS)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
25
of
108
(Blanking)
<Variant Name>
Wistron Corporation
Title
Reserved
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
26
of
108
VDD
F_CS0#
F_SCK
F_SDI/F_SDIO1
F_SDIO/F_SDIO0
27
25
11
10
71
72
X01
100.0K
20.0K
2.75V
100.0K
33.0K
2.48V
A00
100.0K
47.0K
2.24V
Reserved
100.0K
64.9K
2.0V
Reserved
100.0K
76.8
1.87V
R2710
33KR2F-GP
64.33025.6DL
AGND
1.358V
Reserved
100.0K
174.0K
1.204V
Reserved
100.0K
215.0K
1.048V
EC_AGND
BLON_OUT 49
AD_IA_HW2 40
PCH_WAKE# 19
TPDATA
TPCLK
69
69
0707 Modify:
KBC_GPIO14 change to PCIE_WAKE#.
0702 Modify:
Rename CHARGE_LED# to CHG_AMBER_LED#
Rename DC_BATFULL# to BATT_WHITE_LED#.
28 FAN_TACH1
19 PM_PWRBTN#
75,82 PCIE_WAKE#
19,36,37,47,75 PM_SLP_S3#
31
117
63
64
68 CHG_AMBER_LED#
29
KBC_BEEP
82 MEDIA_LED1#
69
KB_BL_CTRL
40
AD_IA_HW
82 MEDIA_LED3#
82 MEDIA_LED2#
68
PWRLED#
32
118
62
65
81
66
22
16
<------ TP
<------ BATTERY / CHARGER
<------PCH / eDP
BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 20,86
SML1_DATA 20,86
PM_LAN_ENABLE 82
EC_ENABLE#_1
PROCHOT_EC
0629 Modify:
Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#.
0715 Modify:
Removed PWR_BTN_LED# on KBC GPIO45.
0720 Modify:
Change MEDIA_LED2# to KBC GPIO45.
82
Add AD_IA_HW on KBC GPIO66.
82
LCD_TST_EN 49
EC_SPI_CS#_C
2 R2736
EC_SPI_CLK_C
2 R2719
A00 1 R2737
EC_SPI_DI_C
EC_SPI_DO_C
2 R2722
1 33R2J-2-GP
1 33R2J-2-GP
20R0402-PAD-2-GP
1 33R2J-2-GP
SPI_CS0#_R 21,60
SPI_CLK_R 21,60
SPI_SO_R 21,60
SPI_SI_R 21,60
5,22
1D05V_VTT
ECRST#
113
111
29 AMP_MUTE#
19 PCH_SUSCLK_KBC
30
77
1
1
R2720
H_PECI
C2716
103
EC_SPI_DI_C
NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.
R2773
100KR2J-1-GP
0604 Modify:
Add Pull down 100k ohm at F_SDI for Power consumption concern.
EC_AGND
1.87V
100.0K
1.65V
DN13_UMA
100.0K
143.0K
1.358V
DN13_ATI
100.0K
174.0K
1.204V
100.0K
215.0K
1.048V
1
2
H_PROCHOT#_EC
1
R2733
2
0R0402-PAD
H_PROCHOT#
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
69
3D3V_AUX_KBC
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
USB_DET#
A00
RN2707
MEDIA_BTN2#
MODEL_ID_DET
4
3
PSL_IN2
A00

EC_AGND
KROW[0..7]
KROW0
54
KROW1
55
KROW2
56
KROW3
57
KROW4
58
KROW5
59
KROW6
60
KROW7
61
0714 Modify:
Add USB_DET# on KBC GPIO57/KBSOUT17.
0709 Modify:
Removed R2772 10K PH on EC_GPIO27.
0714 Modify:
Un-stuff D2705 and Add R2760 between EC_SMI# and
ECSMI#_KBC already confirm with NUVOTON and SW.
69
EC_SMI#
DY
ECSMI#_KBC
3
BAS16-6-GP
DY
84.T3906.A11
2nd = 84.03906.F11
5,40,42
USB_DET#
MEDIA_BTN1#
2ND = 84.2N702.031
MEDIA_BTN3#
PCIE_WAKE#
PSL SOLUTION
D2702
40
4
3
1
2KBC_ON#_GATE
G
40
DY
A00 1228
PSL_IN1
BAT_SCL
BAT_SDA
3
4
BAT_IN#
AC_IN#_KBC
4
3
3D3V_AUX_KBC
1 R2767
PSL_OUT
KBC_ON#_R
0R2J-2-GP
EC_ENABLE#_1
10mW
2
1
2ND = 84.2N702.031
KBC_ON#
0702 Modify:
Rename EC_GPIO71 to PSL_OUT
R2766
2 10mW 1
57
84.2N702.J31
8
7
6
5
28
FAN_TACH1
USBDET_CON#
1
2
3
4
1
R2712
KBC_ON#_R
BAT54CPT-GP
USB_DET#
83.R2003.E81
2ND = 83.00054.Q81
KBC_ON#_R
D2707
BAT54CPT-GP
1MEDIA_BTN2#
0628 Modify:
Stuff R2712 and Removed R2805.
82 DATA_RECOVERY#
DATA_RECOVERY#
3
2
10KR2J-3-GP
83.R2003.E81
2ND = 83.00054.Q81
KBC_ON#_R
D2708
E51_RxD
DY
R2708
2
10KR2J-3-GP
A00 1228
<Core Design>
NOTES:
Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.
DY
R2709
Wistron Corporation
2
10KR2J-3-GP
0623 Modify:
Change RN2704 to R2708 10K 0402
Resistor on BLUETOOTH_EN.
0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.

Title
KBC Nuvoton NPCE795

Size
A2
Date:
USBDET_CON#
FAN_TACH1
BLUETOOTH_EN
2
D2706
0723 Modify:
Add R2764,D2708 Base on Dell Peter request, both
13/15 Media BTN 2(Recovery Button) need
support bootable capability.
2ND = 84.2N702.031
2ND = 84.2N702.031
DN15 2ND =83.R2003.E81

83.00054.Q81
84.2N702.J31
Q2706
KBC_ON#_R
0R0402-PAD-2-GP
Q2705
2N7002K-2-GP
1MEDIA_BTN1#
INSTANT_ON#
SRN100KJ-6-GP
3D3V_S0
84.2N702.J31
INSTANT_ON#
1
1
2
SRN10KJ-6-GP
0623 Modify:
Change RN2702 to R2712 10K 0402
Resistor on FAN_TACH1.
KBC_ON#
S
Q2704
D
S5_ENABLE
EC_ENABLE#_1
PSL
G
D
PSL_OUT
D
2
0R2J-2-GP
BAT54CPT-GP
0712 Modify:
Add D2706 connect to MEDIA
BUTTON Instant_on#.
0713 Modify:
Add R2772,D2707 for USBCHARGER
DETECT Function.
RN2705
DY
0630 Modify:
Removed LID_CLOSE#
PH 10K on RN2705.
S5_ENABLE
ECRST#
3D3V_AUX_KBC
2N7002K-2-GP
2
100KR2J-1-GP
2
100KR2J-1-GP
RN2703
PSL_IN1
0R0402-PAD-2-GP
0702 Modify:
Rename EC_GPIO70 to PSL_IN1
2N7002K-2-GP
84.02130.031
2ND = 83.00054.Q81 1
83.R2003.E81
BAT54CPT-GP
0902 X01 Modify:
Add C2722 0.1uF between Q2703 G&S pin for
fixed leakage voltage to 3D3V_AUX_KBC under
DC mode.
0916 X01 Modify:
Add Q2706 2N7002 to avoid leakage loop from
3D3V_S5 to 3D3V_AUX_KBC issue when 10mW
latched fail timing.
PSL
R2769
100KR2J-1-GP
1
AC_IN#
0R2J-2-GP
10mW
C2713
SCD1U10V2KX-5GP
AC_IN#_KBC 2
2ND = 84.03413.A31
PSL_IN1
PSL
Q2703
DMP2130L-7-GP
SRN10KJ-5-GP
D2703
RN2706
AC_IN#_KBC
AC_OK 1 R2768
AC_OK
SCD1U10V2KX-5GP
KBC_ON#_R
82
SRN4K7J-8-GP
R2763
C2722
1
2
KBC_ON#
10mW
DY
3D3V_AUX_S5
1
R2775
1
R2776
3D3V_AUX_KBC
3D3V_AUX_S5
83.R2003.E81
2ND = 83.00054.Q81
2
100KR2J-1-GP
2
100KR2J-1-GP
0722 Modify:
Add R2757 0ohm only for DQ15 stuff,
change D2706 only for DN15 stuff.
RN2701
EC_GPIO72
2
0R2J-2-GP
A00 1228
KBC_PWRBTN#
EC_GPIO72
EC GPIO standard PH/PL
VBACKUP
3D3V_AUX_KBC
R2734
1 R2756
10mW
EC_GPIO72
330KR2J-L1-GP
3D3V_AUX_KBC
1
R2772
1
R2770
R2757
DQ15
1
10mW SOLUTION
0712 Modify:
default stuff R2756, un-stuff R2734.
RTC_AUX_S5
A00 1228
0R0402-PAD-2-GP
2
2ECSMI#_KBC
0709 Modify:
Add R2774,R2775 PH 100K to 3D3V_AUX_KBC
for MEDIA_BTN2#,MEDIA_BTN3#.
Add R2776 100K to 3D3V_AUX_KBC for PCIE_WAKE#
from DEVICE to KBC.
KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.
C2715
MMBT3906-4-GP
Q2701
Q2702
68
R2760
1
EC_SMI#
84.2N702.J31
R2704
D2705
22
83.00016.K11
2ND = 83.00016.F11
1
B
PURE_HW_SHUTDOWN#
0R0402-PAD-2-GP
BAT54CPT-GP
1
2
SRN100KJ-6-GP
83.00016.K11
2ND = 83.00016.F11
0714 Modify:
Un-stuff D2701,D2704 and Add R2758,R2759
ohm confirm with NUVOTON and SW.
R2758
1
2ECSWI#_KBC
20
EC_SWI#
0R0402-PAD-2-GP
A00
1 R2759 2ECSCI#_KBC
22
EC_SCI#
MEDIA BUTTON CONTROL
0621 Modify:
Removed R2723
D
100KR2J-1-GP
ECSCI#_KBC
3
BAS16-6-GP
28,36,86
R2732
D2704
1
DY
76.8K
100.0K
ECRST#
2N7002K-2-GP
PROCHOT_EC
83.00016.K11
2ND = 83.00016.F11
EC_SCI#
100.0K
DQ13_ATI
ECSWI#_KBC
22
2.0V
DQ13_UMA
0R0402-PAD-2-GP
DY
2.24V
64.9K
A00
EC_GPIO47 High Active
3
BAS16-6-GP
47.0K
100.0K
R2705
10KR2J-3-GP
EC_SWI#
100.0K
DN15_ATI
3.0V
3D3V_AUX_S5
D2701
20
DN15_UMA
22
DY
DY
DY
2.48V
NPCE795PA0DX-GP-U
2
0R0402-PAD
20100712 V1.5
2.75V
33.0K
KCOL[0..16]
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
GPIO15/A_PWM
KBSOUT5/TDO
GPIO21/B_PWM
KBSOUT6/RDY#
GPIO13/C_PWM
KBSOUT7
GPIO32/D_PWM
KBSOUT8
GPIO66/G_PWM
KBSOUT9/SDP_VIS#
GPIO33/H_PWM
KBSOUT10/P80_CLK
GPIO45/E_PWM
KBSOUT11/P80_DAT
GPIO40/F_PWM
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
VCC_POR#
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO87/CIRRXM/SIN_CR
GPIO83/SOUT_CR/TRIST#
KBSIN0
KBSIN1
GPIO55/CLKOUT/IOX_DIN_DIO
KBSIN2
GPIO00/EXTCLK
KBSIN3
KBSIN4
KBSIN5
PECI
KBSIN6
VTT
KBSIN7
2 43R2J-GP PECI 13
EC_VTT12
2
0R0402-PAD
Need very close to EC
20.0K
100.0K
2 OF 2
GPIO56/TA1
GPIO20/TA2
GPIO14/TB1
GPIO01/TB2
85
E51_RxD
E51_TxD
R2721
100.0K
DQ15_NVIDIA
20100609 V1.0
U2701B
0709 Modify:
EC_GPIO27 change to PCH_WAKE# to PCH.
0709 Modify:
KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.
DQ15_ATI
215K=64.21535.6DL
NOTES:
The NPCE795P GPIO/PWM outputs that are connected
to LEDs have high drive buffers (20mA) and can be
connected directly to the LEDs.
0707 Modify:
Rename PCH_TEMP_ALERT# for HDMI_IN#
51
H_A20GATE 22
H_RCIN# 22
10.0K
DQ15_Ventura
0707 Modify:
Rename DISCRETE# to MODEL_ID_DET.
Change R2739 to 100K 0402 from 10K.
NOTE:
Locate resistors R2736,R2719 and R2722 close
to the NPCE795P.
EC_AGND
143.0K
21,71
100.0K
0728
HDMI_IN#
ECSWI#_KBC
MEDIA_BTN1#
90
92
86
87
100.0K
INT_SERIRQ 21
PM_CLKRUN# 19
PANEL_BLEN
ECSCI#_KBC
C2718
SCD1U10V2KX-5GP
1.65V
Reserved
PLT_RST# 5,18,71,75,82,83
18
21,71
LPC_AD[0..3]
VOLTAGE
DQ15_UMA
Ventura need to change to 215K(64.21535.6DL)

MODEL_ID_DET
1
2
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
100.0K
100.0K
PULL-LOW RESISTOR
MODEL_ID_DET(GPIO07)
EC_AGND
A00
R2735
PLT_RST#_EC
1
2
0R0402-PAD-2-GPCLK_PCI_KBC
AD_IA_HW2
70
69
67
68
119
120
24
28
1
2
1
R2711
SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
1
2 PANEL_BLEN
0R0402-PAD
0630 Modify:
Removed R2762 100K 0402.
1
R2761
3.0V
SC1U6D3V2KX-GP
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4
NPCE795PA0DX-GP-U
EC_AGND
L_BKLT_EN
10.0K
Reserved
DY
7
2
3
1
128
127
126
125
8
9
29
124
123
121
122
R2726
100KR2F-L1-GP
VCORF
C2712
SC1U10V3ZY-6GP
0719 Modify:
Reserved 0.1uF on all of ADC input pins base on
NUVOTON feedback list.(C2717~C2721)
17
100.0K
44
GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
ROSA Multi GPIO setting

2
C2720
USB3_PWR_ON
2
C2721
SYS_THRM
2
X00
SCD1U16V2KX-3GP
2
0R0402-PAD-2-GP
KBC_VCORF
102
GPIO2
GPIO3/AD6
GPIO4/AD5
GPIO5/AD4
PSL_IN2#_GPIO6
GPIO7/AD7
GPIO16
GPIO24
GPIO30
GPIO34/CIRRXL
GPIO36
GPIO41
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO46/CIRRXM/TRST#
GPIO51
PSL_IN1_GPIO70
PSL_OUT_GPIO71
VBKUP
GPIO75
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST#
GPIO84/IOX_SCLK/XORTR#
GPIO97
C2712 Need very close to EC
CPU_THRM
C2703
SC2D2U10V3KX-1GP
1 PULL-HIGH RESISTOR
3D3V_AUX_KBC
VOLTAGE
2
A00
0706 Modify:
KBC GPIO7 change to DISCRETE#
KBC GPIO97 change to IMVP_PWRGD.
C2719
PULL-HIGH RESISTOR
0629 Modify:
Rename TP_LOCK_LED#&BATT_WHITE_LED#
0702 Modify:
82 WIFI_RF_EN
Rename EC_GPIO71 to PSL_OUT
63,82 BLUETOOTH_EN
19,36 S0_PWR_GOOD
68 TP_LOCK_LED#
61 USB_PWR_EN#
19,86 AC_PRESENT
36,42 IMVP_PWRGD
0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
79
95
96
108
PSL_IN2
93
MODEL_ID_DET
94
114
ECSMI#_KBC
6
109
14
15
80
17
20
21
23
26
PSL_IN1
73
PSL_OUT
74
EC_GPIO72
75
82
83
84
91
110
112
1 R2762 2EC_GPIO97 107
69
CAP_LED
36 S5_ENABLE
82
MEDIA_BTN3#
39
BAT_IN#
70
LID_CLOSE#
19 RSMRST#_KBC
19,46,75 PM_SLP_S4#
21 ME_UNLOCK
82
RCID
101
105
106
USB3_PWR_ON
68 BATT_WHITE_LED#
LRESET#
LCLK
LFRAME#
LAD3
LAD2
LAD1
LAD0
SERIRQ
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GND
GND
GND
GND
GND
GND
0702 Modify:
0707 Modify:
Rename DISCRETE# to MODEL_ID_DET.
Rename EC_GPIO36 for MEDIA_BTN3#.
MEDIA_BTN2#
19 SUS_PWR_ACK
57 USBCHARGER_CB0
82 USB3_PWR_ON
28
SYS_THRM
1
97
98
99
100
PSID_EC
CPU_THRM
FAN1_DAC
LCD_TST
DY
C2711
1
2
SC220P50V2KX-3GP
1 OF 2
18
45
78
89
116
5
28
49
0708 Modify:
Rename EG_EN to MEDIA_BTN2# on GPIO96.
0702 Modify:
VREF
2 SCD1U10V2KX-5GP
AVCC
VCC
VCC
VCC
VCC
VCC
U2701A
104
PCB_VER_AD
82
28
PULL-LOW RESISTOR
X02
PCB_VER_AD
C2717
SCD1U10V2KX-5GP
19
46
76
88
115
1
2
1
2
C2708
SCD1U10V2KX-5GP
1
2
C2707
SCD1U10V2KX-5GP
C2705
SCD1U10V2KX-5GP
1
2
C2704
SCD1U10V2KX-5GP
C2706
SCD1U10V2KX-5GP
C2714
0720 Modify:
Stuff C2714 0.1uF on AD_IA.
C2702
SCD1U10V2KX-5GP
3D3V_AUX_KBC_VCC
EC_AGND
AD_IA
EC_AGND
C2710
SCD1U10V2KX-5GP
C2709
SC2D2U10V3KX-1GP
2
1
2
1
40
R2724
47KR2F-GP
VBAT
1 R2702 2
0R0603-PAD
0628 Modify:
Move R2771 to closed 3D3V_AUX_KBC power
R2771
2D2R3-1-U-GP rail base on layout placement.
SC2D2U10V3KX-1GP
0719 Modify:
Reserved 0.1uF on all of ADC input pins base on
3D3V_S0 NUVOTON feedback list.(C2717~C2721)
0714 Modify:
Change C2709,C2710 to EC_AGND from GND.
DY
PCB VERSION A/D(PIN98)
3D3V_AUX_KBC
C2701
3D3V_AUX_KBC
A00 1222
SSID = KBC
Document Number
Rev
A00
QUEEN 15
Sheet
27
of
108
0705 Modify:
R2802 change to 0ohm 0402 from
short pad and default un-stuff.
Fan controller P2793

1
2
3
4
FAN_VCC
C2802
87.1 Degree
GND
GND
GND
GND
8
7
6
5
5V_S0
G991P11U-GP
74.00991.031
2nd = 74.02793.A31
3rd = 74.05606.A71
A00 1224
P2800A1
R2804
226KR2F-GP
Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
ADJ
FON#
VIN
VO
VSET
*Layout* 10 mil
For linear FAN
3D3V_DAC_S0
R2803
107KR2F-GP
FON#
A00 1227
1227 A00 Modify:

If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
TDR
TDL
GND
ADJ
4
3
2
1
1
R2807
FAN_TACH1
SYS_THRM 27
CPU_THRM 27
FAN_TACH1_C
2
0R0402-PAD
3
2
FAN_VCC
*Layout* 15 mil
ADJ
1
4
P2800_DXN
VCC
DXP
DXN
OTZ
X02 1118
R2805
THERM_SYS_SHDN#_OTZ
1
1117 X02 Modify:
Add R2805 0hm between THERM_SYS_SHDN#_OTZ
and THERM_SYS_SHDN#.
3rd = 83.5R003.08F
R2809
100KR2J-1-GP
THERM_SYS_SHDN#
D
G
1
EMI/ESD
X02 1111
SCD1U10V2KX-5GP
3D3V_S0
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
0709 Modify:
Removed R2811 and connect
3D3V_S0 to Q2802.G directly.
3D3V_DAC_S0
A00 1228 un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805
1111 X02 Modify:
Reserved G709T1UF for T8 solution
sync with DN13. R2801
24K3R2F-1-GP
U2805
R2806
U2805_5
1 SET
5
1 DY
2 U2805_1
2
DY 1
VCC
150R2F-1-GP
C2817
2 GND DY
THERM_SYS_SHDN#
3 OUT#
4
1
DY 2
DY SCD1U10V2KX-5GP
HYST
R2812
0R2J-2-GP
SCD1U16V2KX-3GP
2
C2811
DY
FAN_VCC
DY
1110 X02 Modify:

Add 2nd 20.F1841.003 on FAN1 from
ME updated connector list.
3D3V_S0
A00 1228
2
0R2J-2-GP
EC2801
20.F0772.003
2nd = 20.F1841.003
Q2802
27,36,86 PURE_HW _SHUTDOW N#
SC2200P50V2KX-2GP
1FAN_VCC
83.R5003.C8F
2ND = 83.R5003.H8H
0831
AFTP2802
0724 Modify:
Removed C2808 0.1uF.
1FAN_TACH1_C
DY
AFTP2801
C2810
CH551H-30PT-GP
C2809
74.02800.A71
D2802
FAN1
ACES-CON3-11-GP
T8 Shutdown
2.System Sensor, Put on palm rest
U2801
1117 X02 Modify:

1.H/W
Rename U2801&U2804 pin 8 to
THERM_SYS_SHDN#_OTZ from THERM_SYS_SHDN#.
5
27
1
2
5
C2807
6
SC2200P50V2KX-2GP
7
THERM_SYS_SHDN#_OTZ
8
SC4D7U6D3V3KX-GP
R2808
NTC-100K-8-GP
1
PMBS3904-1-GP
2
DY
C2806
SC470P50V3JN-2GP
C2803 C2804
0628 Modify:
Stuff R2712 and Removed R2805.
P2800EA1-GP
2ND = 84.03904.P11
84.03904.L06
1111 X02 Modify:

ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
P2800A1
P2800_DXP
Q2801
0614 Modify:
Change FAN1 connector part number to
20.D0210.103 base on ME EMN and DXF.
0712 Modify:
Change FAN1 part number to 20.F1639.004
from 20.D0210.103 base on latest EMN and DXF.
C2805
P2800A1
D
FAN1_DAC
27
DY
1
5V_S0
3D3V_DAC_S0
1119 X02 Modify:
Change U2801,U2804,U2805 VCC power to
3D3V_DAC_S0 from 3D3V_S0.
U2802
R2802 0R2J-2-GP
SCD1U10V2KX-5GP
Thermal sensor P2800
SSID = Thermal
SC4D7U6D3V3KX-GP
R2810 3D3V_DAC_S0
U2805_4 2 DY
1
R2811
0R2J-2-GP
A00 1224
2 DY
1
Hysterisis:
0R2J-2-GP
10C for HYST= VCC
2C for HYST=GND
G709T1UF-GP
74.00709.A7F
20101019 X01:
Reserve U2804 for PURE_HW_SHUTDOWN# test.
20101020 X01:
Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST.
A00 1228 Cancel VGA Thermal sensor P2800 circuit
<Core Design>
1111 X02 Modify:

ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
Wistron Corporation
Title
Thermal P2800/Fan Controllor P2793

Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
28
of
108
HDA_CODEC_SYNC
HDA_CODEC_RST#
AUD_PC_BEEP
21 HDA_CODEC_SYNC
21 HDA_CODEC_RST#
C2902
SCD1U10V2KX-5GP
2
1
C2904
SCD1U10V2KX-5GP
C2903
SC1U6D3V2KX-GP
1R2901
33R2J-2-GP
0707 Modify:
updated U2901 part number from data base.
92HD87B1A5NDGXTBX8-GP
2010/06/30 Change to 92HD87 (71.92H87.A03)
A00
C2910
SC10U6D3V5MX-3GP
C2909
SC1U10V2KX-1GP
C2908
SCD1U10V2KX-5GP
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVSS
PORTD_-L
PORTD_+L
PVDD
AVDD2
VREG/+2_5V
DVDD_LV
DMIC_CLK/GPIO_1
DMIC_0/GPIO_2
SDATA_OUT
BITCLK
SDATA_IN
DVDD
71.92H87.A03
SYNC
RESET#
PCBEEP
1 R2904 2
0R0603-PAD
PUMP_CAPP
CAP+
CAPVAVSS2
PORTB_R
PORTB_L
AVSS2
PORTA_R
PORTA_L
AVDD1
30
29
28
27
26
25
24
23
22
21
PUMP_CAPN
AUD_V_B
AUD_HP1_JACK_R
AUD_HP1_JACK_L
AUD_EXT_MIC_R
AUD_EXT_MIC_L
CLOSE TO CODEC
C2914
SC2D2U10V3KX-1GP
R2906
R2905
C2922
C2921
2 60D4R2F-GP
2 60D4R2F-GP
1
1
AUD_HP1_JACK_R2
AUD_HP1_JACK_L2
1 SC1U10V3KX-3GP
1 SC1U10V3KX-3GP
2
2
82
82
MIC_IN_R 82
MIC_IN_L 82
+AVDD
SENSE_A
SENSE_B
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP2
VREFOUT_A
VREFOUT_C
3D3V_S0
21 HDA_CODEC_SDOUT
21 HDA_CODEC_BITCLK
21 HDA_SDIN0
1
2
3
4
5
6
7
8
9
10
AUD_DMIC_CLK_R
AUD_DMIC_IN0_R
HDA_CODEC_SDOUT
HDA_CODEC_BITCLK
2HDA_CODEC_SDIN0
5V_S0
1 R2903 2
0R0603-PAD
1 R2902 2
0R0603-PAD
Put C2921 and C2922 close to codec

AUD_CAP2
AUD_VREFFLT
11
12
13
14
15
16
17
18
19
20
1
2
1122 X02 Modify:

change R2920,R2921 to 22ohm from 0ohm and
stuff EC2901,EC2902 22p from EMC Neo updated.
Close to codec
U2901
C2901
SC10U6D3V5MX-3GP
C2905
SCD1U10V2KX-5GP
AUD_DVDDCORE
SC22P50V2JN-4GP
SC22P50V2JN-4GP
41
40
39
38
37
36
35
34
33
32
31
Close to codec
EC2902
+PVDD
+AVDD
+AVDD
1
2
EC2901
+PVDD
AMP_MUTE#
AMP_MUTE#
58
58
58
58
AUD_VREG
27
AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+
5V_S0
For EMI
AUD_DMIC_CLK
AUD_DMIC_IN0
AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+
SSID = AUDIO
C2906
SC1U10V2KX-1GP
AUD_V_B
1
2
C2916
SC1U6D3V2KX-GP
1
2
C2915
SC10U6D3V5MX-3GP
AUD_VREFOUT_B
R2908
10KR2J-3-GP
C2918
SC10U6D3V5MX-3GP
0707 Modify:
Change R2911,R2914,R2917 change
to 0ohm 0603 from short pad.
0726 Modify:
Removed all of AUD_AGND and R2911,R2914,R2917.
20101220
SRN22J-7-GP
3D3V_S0
AUD_VREG
C2917
SC4D7U6D3V3KX-GP
AUD_DMIC_IN0_R
AUD_DMIC_CLK_R
AUD_PC_BEEP
4
3
AUD_SENSE_A
AUD_SENSE_B
1
2
49 AUD_DMIC_IN0
49 AUD_DMIC_CLK
AUD_VREFFLT
AUD_CAP2
AUD_VREFOUT_B
RN2902
Close to codec
AMP_MUTE#
AUD_VREFOUT_B
HDA_CODEC_BITCLK
AUD_PC_BEEP
Trace width>15 mils
120KR2J-L-GP
R2909
1
2
C2912
1 SCD1U10V2KX-5GP SB_SPKR_R
C2913
1 SCD1U10V2KX-5GP KBC_BEEP_R 1
R2910
1
C2907
SC4D7P50V2CN-1GP
DY
2
C2923
SC1U10V2KX-1GP
AUD_PC_BEEP
From SB
HDA_SPKR 21
2
470KR2J-2-GP
0719 Modify:
Move RN2901 to closed AUDIO CODEC from speaker connector.
KBC_BEEP 27
0,&,1
From EC
G2901
DUMMY-C2
2
1
AUD_VREFOUT_B
3
4
RN2901
SRN4K7J-8-GP
$]DOLD,)(0,
HDA_CODEC_SDOUT
82
MIC_IN_L
82
MIC_IN_R
+AVDD
+AVDD
R2913
R2916
2K49R2F-GP
AUD_SENSE_B
<Core Design>

Wistron Corporation
R2919
EXT_MIC_JD# 82
Title
39K2R2F-L-GP
C2920
SCD1U10V2KX-5GP
Close to Pin13
Size
A3
Close to Pin14
Date:
5
R2918
20KR2F-L-GP
C2919
SC1000P50V3JN-GP-U
1
2
DY
82
AUD_SENSE_A
AUD_HP1_JD#
20KR2F-L-GP
R2915
2K49R2F-GP
PCH_AZ_CODEC_SDOUT1
DY
R2912
47R2J-2-GP
Audio Codec 92HD87B1

Document Number
Rev
A00
QUEEN 15
Sheet
1
29
of
108
(Blanking)
C
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
30
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
31
of
108
SSID = SDIO
48MHz clock input trace of characteristic impedance (Zo) must be 50
15%.
3D3V_CARD_S0
3D3V_CARD_S0
3D3V_S0
1 R3201 2
6K2R2F-GP
USB_PN5_R
USB_PP5_R
V18
1
2
3
4
5
6
C3202
SC1U10V2KX-1GP
25
RREF
DM
DP
3V3_IN
CARD_3V3
V18
GND
74
74
74
74
74
C3206
SCD1U10V2KX-4GP
C3207
SC4D7U6D3V3KX-GP
Close to chip
U3201
RTS5138-GR-GP
SP10
GPIO0
SP9
SP8
SP7
SP6
18
17
16
15
14
13
SP10
SP10
74
SP9
SP8
SP7
SP6
SP9
SP8
SP7
SP6
74
74
74
74
7
8
9
10
11
12
C3204
SC4D7U6D3V3KX-GP
DY
2
3D3V_CARD_S0
CLK_IN
XD_D7
SP14
SP13
SP12
SP11
SC100P50V2JN-3GP
MAX 0.4A
C3203
SCD1U10V2KX-4GP
RREF
24
23
22
21
20
19
DY2
XD_CD#
SP1
SP2
SP3
SP4
SP5
C3201
1
XD_D7
SP14
SP13
SP12
SP11
XD_D7
SP14
SP13
SP12
SP11
PCH GPIO67(48M) confirm with SW
20 CLK_PCH_48M
The maximum range of the PMOS output current

1. xD-Picture Card: 250mA
2. SD/MMC Card: 250mA
3. MS/MSPRO/Duo-HG: 250mA
71.05138.003
SP5
SP4
SP3
SP2
SP1
XD_CD#
SP5
SP4
SP3
SP2
SP1
XD_CD#
74
74
74
74
74
74
The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout

with differential characteristic impedance (Zdiff) is 90[
10%
POWER TRACE
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).
Keep the trace routing lengths as short as possible.
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
8.Via size: Pad>=32 mils, Finished hole>=16 mils.
R3211
18
USB_PP5
USB_PP5_R
0R0402-PAD-2-GP
A00 1229
0917 X01 Modify:
stuff TR3201 and un-stuff R3211,R3210
at X01 stage from EMC Neo suggestion.
R3210
18
USB_PN5
USB_PN5_R
0R0402-PAD-2-GP
<Core Design>
A
Wistron Corporation
Title
Size
A3
Date:
5
Card Reader-RTS5138
Document Number
Rev
A00
QUEEN 15
Sheet
1
32
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
A
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
E
33
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
34
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
35
of
108
0628 Modify:
Removed R3609,R3610,R3613,C3613 and Stuff R3614.
A00
1 R3614
27,42 IMVP_PW RGD
Q3603
PS_S3CNTRL
SYS_PW ROK
0R0402-PAD-2-GP
R3622
1D05V_VTT
C3612 DY
SCD01U50V2KX-1GP
0723 Modify:
Default stuff R3622 PH Resistor to fix Annie
demo board abnormal issue from Annie team
updated.
H_THERMTRIP# 5,22
56R2J-4-GP
SSID = Reset.Suspend
2 H_PW RGD_R
1KR2J-1-GP
Power Sequence
BAS16-6-GP
83.00016.K11
2ND = 83.00016.F11
1
2
0621 Modify:
Change R3603 to 1K from 2K 0402.
+5V_RUN Comsumption
Peak current 7.73A
4
3
2
1
U3601
C3603
SC10U10V5ZY-1GP
5V_RUN_ENABLE
2
10KR2J-3-GP
C3608
SCD01U50V2KX-1GP
PS_S3CNTRL 37
S5_ENABLE 27
D
D
D
D
S
S
S
G
5
6
7
8
2
1KR2J-1-GP
5V_S0
AO4468-GP
R3604
100KR2J-1-GP
1
R3603
5V_S0
84.04468.037
5V_S5
27,28,86
D3601
R3602
200KR2J-L1-GP
AO4468 MAX 9A
Rds(on) = 18.5mOhm
2nd = 84.08882.037
15V_S5
PURE_HW _SHUTDOW N#
3V_5V_EN
ROSA Run Power
1 R3606
3
41
DY
1 R3605
CHT2222APT-GP
0628 Modify:
Utilize D3602 Diode instead of U3603 AND GATE
for SYS_PWROK sequnece control.
3D3V_AUX_S5
DY
2ND = 83.00016.F11
83.00016.K11
SYS_PW ROK 19
D3602
BAS16-6-GP
DY Q3601
B
C3602
DY
2nd = 84.2N702.031
19,27 S0_PW R_GOOD
1 R3601
5,22 H_CPUPW RGD
84.2N702.J31
2N7002K-2-GP
2
SCD1U10V2KX-5GP
S
A00 1228 stuff Q3603
PS_S3CNTRL
2
100KR2J-1-GP
19,27,37,47,75 PM_SLP_S3#
U3602
3.3V_RUN_ENABLE
2
10KR2J-3-GP
1 R3607
+3.3V_RUN Comsumption
Peak current 8.14A
DY
4
3
2
1
C3604
SC10U6D3V5KX-1GP
0719 Modify:
C3604 for EMC NEO suggestion.
B
RUN_ENABLE
3D3V_S0
EC3601
SCD1U50V3KX-GP
5
6
7
8
3D3V_S0
3D3V_S0
AO4468-GP
S G D
84.04468.037
3D3V_S5
84.2N702.A3F
2nd = 84.DM601.03F
D
D
D
D
Rds(on) = 18.5mOhm
AO4468 MAX 11.6A
2nd = 84.08882.037
Q3602
2N7002KDW -GP
S
S
S
G
D G S
C3605
SCD01U50V2KX-1GP
0615 Modify:
Removed R3626,R3628 0ohm 0805 Resistor,
they are unnecessary for this power rail.
Removed R3627,R3629 0ohm 0805 Resistor for 1D5V_DDR_S0.
1D5V_S3
1.5V_RUN for VGA Comsumption

Peak current 7.39A
1D5V_S0
TPCA8062-H-GP MAX 28A

Rds(on) = 4.1~5.4m OHM
8
7
6
5
+1.5V_RUN for Mini-Card Comsumption

Peak current 1A
D
D
D
D
U3606
S
S
S
G
MAX Current ? mA
Design Current ? mA
Total= 11.39A
1
2
3
4
+1.5V_RUN_CPU Comsumption
Peak current 3A
1.5V_RUN_ENABLE
2
10KR2J-3-GP
C3609
SC10U6D3V5KX-1GP
<Core Design>
A
84.08062.037
Wistron Corporation
C3610
SCD01U50V2KX-1GP
1 R3630
TPCA8062-H-GP
1D5V_S0

2nd = 84.00460.037
3rd = 84.00312.037
Title
0713 Modify:
Change U3606 part number to 84.08062.037
from 84.04468.037.
0827 Add 2nd and 3rd.
Power Plane Enable

Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
1
36
of
108
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
Q3702_D2
0629 Modify
D
R3705
100KR2J-1-GP
Q3702
2N7002K-2-GP
Q3701
2N7002K-2-GP
DY
84.2N702.J31
2N7002K-2-GP
36
PS_S3CNTRL
PS_S3CNTRL
RUN_ENABLE
2ND = 84.2N702.031
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
84.2N702.J31
0706 Modify:
Removed Q3707,R3717 and connect
RUN_ENABLE to Q3708.G directly
same as EV board.
0629 Modify
D
G
R3704
220R2J-L2-GP
+V_SM_VREF_CNT 9
2 +V_SM_VREF
0R0402-PAD
DY
2
Q3701_D
Q3708
1
R3708
R3703
22R2J-2-GP
R3707
0R2J-2-GP
1
DY 2
M_VREF_DQ_DIMM0
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
1D5V_S0
0D75V_S0
Close to CPU
S3 Power Reduction X01 20091111
1D5V_S3
R3706
1KR2J-1-GP
2N7002K-2-GP
36 PS_S3CNTRL
1.05VTT_PW RGD 45,48

0D75V_EN
0908 X01 Modify:
Stuff Q3704,R3710; un-stuff R3716.
R3710
0R0402-PAD-2-GP U3701 pin2 change to 1.05VTT_PWRGD from
RUNPWROK.
S
Q3704
A00
2ND = 84.2N702.031
84.2N702.J31
1
R3716
2
DY 22R2J-2-GP
R3709 2
0R2J-2-GP
Q3703
2N7002K-2-GP
DY1
0730
S3 Power Reduction Circuit

SM_DRAMRST#
SM_DRAMRST#
SM_DRAMRST#_D
1 R3718 2
1KR2J-1-GP
DDR3_DRAMRST#
14,15
19,27,36,47,75 PM_SLP_S3#
0D75V_EN 46
84.2N702.J31
C3702
SC100P50V2JN-3GP
2ND = 84.2N702.031
C3705
SCD1U10V2KX-5GP
DRAMRST_CNTRL_PCH
20
DY
B
C3703
1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
0709 Modify:
Change U3701 pin1,5 to 3D3V_S0 from 3D3V_S5.
Close to CPU
3D3V_S0
1D5V_S0
X02 1111
R3713
200R2F-L-GP
PUSH PULL
DY
U3701
R3702
200R2F-L-GP
5,19 PM_DRAM_PW RGD
CEKLT V1.0: PCH to 1K,CUP to 200R
3D3V_S0
5
0D75V_EN
R3719
2
VDDPW RGOOD_R 1
0920
VDDPW RGOOD 5
3
910R2F-GP
TC7SZ08FU-2-GP
R3720
750R2F-GP
2nd = 73.01G08.L04
3rd = 73.7SZ08.DAH
DN15ATI
0709 Modify:
U3701 change to OD type 73.01G09.AAH.
0723 Modify:
Change U3701 to push pull type 73.01G08.L04.
R3720 change to 910ohm 0402.
R3719 change to 750ohm 0402.
default un-stuff R3702.
R3717
5,19 PM_DRAM_PW RGD
1110 X02 Modify:

Change U3701 1st to 73.7SZ08.EAH;2nd to
73.01G08.L04;3rd to 73.7SZ08.DAH from
Sourcer Eason updated.
73.7SZ08.EAH
VDDPW RGOOD_R
2
DY 0R2J-2-GP
0827
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55 200mV and the edge must be monotonic
Wistron Corporation
Title
ADAPTER
Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
1
37
of
108
SSID = PWR.Support
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
DCIN
Document Number
Rev
A00
QUEEN 15
Sheet
1
38
of
108
BATT_SENSE
1
C3902
SCD1U50V3KX-GP
27,40
27,40
27
BAT_SCL
BAT_SDA
BAT_IN#
A00 1224
PN3901
1
2
3
4
8
7
6
5
BATT1
10
1
2
3
4
5
6
7
8
9
11
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
SRN33J-7-GP
AFTP3901
BAT_ALERT
ALP-CON9-2-GP-U
DY
20.81316.009
2nd = 20.81440.009
3rd = 20.81328.009
DCBATOUT
SCD1U50V3KX-GP
EC3903
0701 Modify:
Removed D3904 ESD Diode on BAT_IN#.
2
1
SC10P50V2JN-4GP
2
1
SC10P50V2JN-4GP
EC3901 EC3902
DY
1
1
1
1
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+
AFTP3902
AFTP3903
AFTP3904
AFTP3905
Batt Connecter
DY
A
GAP-CLOSE-PW R-3-GP
0714 Modify:
Merge R3902~R3904 to PRN3901 33ohm.
C3901
SC2200P50V2KX-2GP
40
G3901
BT+
D
PD3902
1SMA18AT3G-GP
1122 X02 Modify:

EMC Neo suggestion.
For actual location, need to be swap all pin

Close to Batt Connector
BAT_SCL
BAT_SDA
BAT_IN#
D3901
BAV99-5-GP-U
1
A
D3903
BAV99-5-GP-U
D3902
BAV99-5-GP-U
83.00099.T11
83.00099.T11
2nd = 83.00099.K11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
3rd = 83.BAV99.D11
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
3D3V_AUX_KBC
<Core Design>
0930 X01 Modify:

Change D3901~D3903 main source to 83.00099.T11
for 83.BAV99.D11 shortage issue.
Wistron Corporation
Title
Size
A3
Date:
Document Number
BATT CONN
Rev
QUEEN 15
A00
Sheet
1
39
of
108
1
2
PC4019
SCD1U50V3KX-GP
PC4018
SC10U25V6KX-1GP
2
1
PC4017
SC10U25V6KX-1GP
2
1
PG4009
GAP-CLOSE-PWR-3-GP
1
2
1
1
PR4030
1K8R6J-GP
0603 Modify:
Add PC4034 to 78.10622.52L.
CHG_AGND
CHG_AGND
A00 1222
Q4001
AC_IN# to KBC
27
PC4033
SCD1U10V2KX-5GP
PW R_CHG_REF
AC_IN#
AC_OK
AC_OK
0701 Modify:
Change PQ4002 to single 2N7002.
2PQ4004_G
2 PR4011 1
BT+
CHG_AGND
ICREF
2ND = 84.2N702.031
DY
AC_OK
<Core Design>
Wistron Corporation
2N7002K-2-GP
84.2N702.J31

2ND = 84.2N702.031
27
Title
10KR2F-2-GP
CHARGER BQ24745
Size
A3
PG4010
GAP-CLOSE-PWR-3-GP
1
2
DY
Date:
5
1
4
3
2
1
0721 Modify:
Change PU4005 to 84.00412.037
from power team Brian updated.
1 PR4020 2
0R0402-PAD
1
2
DY
2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
2
1
DY
SCD1U50V3KX-GP
EC4008
DY
PR4024
0R0402-PAD
0707 Modify:
Change PR4023 change to 0ohm 0402 from short pad.
BATT_SENSE 39
DY
0629 Modify
PG4009_1
PW R_CHG_CSOP_1
1
CHG_AGND
0916 X01 Modify:

Reserved PQ4004,PR4036,PR4037 for
AD_IA_HW2 function.
CHG_AGND
EC4003
SCD1U50V3KX-GP
EC4005
EC4004
1 PR4023 2
0R0402-PAD
1
2
CHG_AGND
PR4036
76K8R2F-GP
0R0402-PAD-2-GP
A
PC4032
DY
SCD1U25V2KX-GP
84.2N702.J31
1PR4037
PC4023
1
GND
PW R_CHG_VFB1 PR4028 2
0R0402-PAD
84.00412.037
Id=12A
Qg=3.8nC
Rdson=24~30mohm
15
2
VFB
CHG_AGND
A00 1222
PQ4004
2N7002K-2-GP
AD_IA_HW 2
16
PQ4004_D
A00 1222
27
BT+
AD+
NC#16
1 PR4029 2
0R0402-PAD
0917 X01 Modify:

Change PR4027 to 0R0402
EMI/ESD
PW R_CHG_ACOK
PU4001
BQ24745RHDR-GP
SCD01U50V2KX-1GP
FBO
EAI
EAO
VREF
CE
GND
PR4019
1
2
D01R2512F-4-GP
2nd = 68.5R610.10U
68.5R610.10X
Id=5.5A
DCR=39~42mohm
Size=6.6X7.3X3
PU4005
SIS412DN-T1-GE3-GP
VICM
84.00412.037
2nd = 84.08061.A37
4
3
2
1
PW R_CHG_CSON
29
PC4028
DY
DY
PC4030
SCD1U10V2KX-5GP
PC4029
DY
0625 Modify:
Reserved EC4003,EC4004 on DC_IN_D&PWR_CHG_ACOK for
EMC NEO suggestion.
0719 Modify:
Reserved EC4005 0.1uF near PR4004 for EMC NEO suggestion.
Reserved EC4008 0.1uF near PC4017 for EMC NEO suggestion.
DC_IN_D
PW R_CHG_CSOP
SCD1U50V3KX-GP
PW R_CHG_VICM
PW R_CHG_FBO
PC4020
SCD1U50V3KX-GP
1
2
17
SC56P50V2JN-2GP
SCD1U50V3KX-GP
2
PC4027
PC4025
1
2
SC1U6D3V2KX-GP
DY
This Resistor
must be 1%
tolerance.
PC4022
PR4026
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
2
1PR4526_01
2
1
PC4021
SC150P50V2JN-3GP
PC4026
18
CSON
6
PW R_CHG_EAI
5
PW R_CHG_EAO
4
PW R_CHG_REF
3
PW R_CHG_CE
7
12
1 PR4027 2
0R0402-PAD
CSOP
PR4022
200KR2F-L-GP
1
2
SCD01U50V2KX-1GP
2
1
PC4024
1
SC220P50V2JN-3GP
8K45R2F-2-GP
DY
NC#14
CHG_AGND
2
IND-5D6UH-48-GP-U1
68.5R610.10X
S
S
S
G
PR4025
1
20KR2J-L2-GP
0720 Modify:
Change PR4001 to 20K from 0ohm
base on power team Brian updated.
1
PR4021
4K7R2J-2-GP
1PWR_CHG_FBO1
2
AD_IA
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4005
1
2
GAP-CLOSE-PWR-3-GP
PG4004
1
2
GAP-CLOSE-PWR-3-GP
PG4006
1
2
5
6
7
8
DY
D
D
D
D
14
PR4001
27
BT+
BT+_R
2
1
PC4034
SC10U25V6KX-1GP
19
1
2
PC4014
SC220P50V2JN-3GP
PW R_CHG_LGATE
0603 Modify:
change PL4001 to 68.5R610.10X.
84.00412.037
2nd = 84.08061.A37 PL4001
SC3300P50V3KX-1GP
PW R_CHG_LX1
SCD1U25V2KX-GP
PGND
DY
Charger Current=1.4~3.6A
PC4016
SC10U25V6KX-1GP
2
1
20
1 PR4018 2
0R0603-PAD
EC4002
DY
2
1
PC4015
SC10U25V6KX-1GP
2
1
LGATE
SDA
CHG_AGND
PW R_CHG_PHASE
2nd = 84.04835.H37
PC4031
SCD1U50V3KX-GP
23
1
2
PC4012
SCD1U50V3KX-GP
8
7
6
5
Id=-12A
Qg=-25nC
Rdson=10~38mohm
EC4001
SC2200P50V2KX-2GP
PHASE
83.1R504.A8F
2nd = 83.1R504.B8F
PC4013
PC4009
SCD1U50V3KX-GP
PW R_CHG_UGATE
CHG_AGND
1
2
PC4011
SCD1U50V3KX-GP
PC4008
SC10U25V6KX-1GP
2
1
24
PD4001
UGATE
PR4006
470KR2J-2-GP
PC4007
SC10U25V6KX-1GP
2
1
PW R_CHG_BOOT
1 PR4017 2PW R_CHG_BST1
K
A
PW R_CHG_VDDP 0R0603-PAD
SD103AWS-1-GP
PU4004
SIS412DN-T1-GE3-GP
25
21
PC4006
SC1U6D3V2KX-GP
BOOT
VDDP
DY
DY
D
D
D
D
PW R_DCBATOUT_CHG
5
6
7
8
CHG_AGND
27
26
PW R_CHG_SDA
1
GAP-CLOSE-PW R-3-GP
2
PG4008
27,39 BAT_SDA
PG4001
1
2
SCD1U50V3KX-GP
PW R_CHG_CSSN
PW R_CHG_ICOUT
CSSN
ICOUT
BT+
PU4003
S
S
S
G
84.04407.F37
PW R_DCBATOUT_CHG
ACIN
3D3V_AUX_KBC
PC4005
PW R_CHG_CSSP 1
2
1PR4533_02
1
2
PC4004
SCD1U50V3KX-GP
DCIN
ICREF
22
PC4003
PW R_CHG_ACIN
SCD47U50V5KX-1GP
CHG_AGND
CSSP 28
PU4004
Id=12A
Qg=3.8nC
Rdson=24~30mohm
PR4032
0R0402-PAD-2-GP
2
PW R_CHG_DCIN
1
1
2
PR4010
0R0402-PAD A00 1222
1
2
PC4002
SCD1U50V3KX-GP
PC4010
SCD01U50V2KX-1GP
1
2
5,27,42 H_PROCHOT#
CHG_AGND
CHG_AGND
0723 Modify:
Removed PR4038 PH.
S
S
S
G
PR4007
0R2J-2-GP
1
2
3
4
AO4407A-GP
0R0402-PAD-2-GP
AD+
D
D
D
D
27,39
PR4031
PR4008
0917 X01 Modify:
150KR2F-L-GP
0R0402-PAD
Change PR4008,PR4010 to 0R0402
11 VDDSMB
0707 Modify:
Change PR4012 change to 0ohm 0402 from short pad.
PC4001
SCD1U10V2KX-5GP
PW R_CHG_ACOK
13 ACOK
1 PR4012 2
0R0402-PAD
CHG_AGND
PW R_CHG_SCL
10 SCL
2
1
BAT_SCL
PG4007
GAP-CLOSE-PW R-3-GP
AC_OK
DY
1
2
1
1 PR4034 2PQ4003_G
AD_IA_HW
20R5F-1GP
0827
A00 1222
PR4047
174KR2F-GP
ICREF
84.2N702.A3F
2nd = 84.DM601.03F
27
PG4003
GAP-CLOSE-PW R-3-GP
2N7002KDW -GP
0702 Modify:
Change PR4014 from 48.7K to 49.9K
0402 base on power team suggest.
A00 1222
PR4035
A00 1222
84.2N702.J31
2ND = 84.2N702.031
S
PG4002
PQ4003
2N7002K-2-GP
1
5
GAP-CLOSE-PW R-3-GP
A00 1222
300KR2F-L-GPPW R_CHG_REF
A00 1222
PR4005
10KR2F-2-GP
0818
PR4014
49K9R2F-L-GP
1
0720 Modify:
Add AD_IA_HW related circuit
from TOM suggestion.
PQ4003_D
PR4004
1
2
10KR2J-3-GP
316KR3F-2-GP
PR4009
PW R_CHG_ACOK
AD+_G_1
DC_IN_D
PQ4001
PR4033
1
AD+_G_2
1
2
D01R2512F-4-GP
PR4524_03
AD+
PR4002
PR4003
100KR2J-1-GP
84.04407.F37
2nd = 84.04835.H37
AO4407A-GP
D
AD+_TO_SYS
1
2
3
4
SCD1U50V3KX-GP
EC4007
PU4002
S
S
S
G
D
D
D
D
SCD1U50V3KX-GP
EC4006
8
7
6
5
AD+
Id=-12A
Qg=-25nC
Rdson=10~38mohm
0719 Modify:
Reserved EC4006 0.1uF near PR4002
for EMC NEO suggestion.
0719 Modify:
Reserved EC4007 0.1uF near PG4006
DCBATOUT
for EMC NEO suggestion.
SSID = Charger
PR4013
33R3J-2-GP
2
1
Document Number
Rev
A00
QUEEN 15
Sheet
1
40
of
108
SSID = PWR.Plane.Regulator_5v3p3v
PWR_3D3V_LGATE2_1
TONSEL
GND
SKIPSEL
ENC
SI7716ADN-T1-GE3-GP
PWR_5V3D3V_ENC
2
1
1
3
A
1
PT4104
A00 1224
0804
EC4107
SCD1U50V3KX-GP
2
2
PG4109
1
GAP-CLOSE-PWR
2
PG4111
1
GAP-CLOSE-PWR
2
PG4115
1
GAP-CLOSE-PWR
2
PG4117
1
GAP-CLOSE-PWR
2
PG4119
1
GAP-CLOSE-PWR
2
PG4121
1
GAP-CLOSE-PWR
2
PG4123
1
GAP-CLOSE-PWR
2
PR4113
0R0402-PAD
1
2
EC4101
SCD1U50V3KX-GP
DY
EC4102
SCD1U50V3KX-GP
2
1
PC4128
SC18P50V2JN-1-GP
PC4127
0701 Modify:
PC4127 Default un-stuff.
DY
DY
PR4115
33KR2F-GP
PWR_5V_FB1_R
PC4126
5V_S5
DY
0719 Modify:
Reserved EC4101~EC4106 0.1uF near
PTC4101,PC4119 for EMC NEO suggestion.
PR4119
21K5R2F-GP
Close to VFB Pin (pin2)
DY
GAP-CLOSE-PWR
2
EC4103
SCD1U50V3KX-GP
5V_AUX_S5
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37
1 PR4121 2
0R0402-PAD
2
GAP-CLOSE-PWR
2
PC4123
SC560P50V-GP
PR4114
0R2J-2-GP
SC4D7U25V5KX-GP
2
PR4120
1
0R2J-2-GP
PC4120
2nd = 84.08065.B37
SC22U6D3V5MX-2GP
1 PR4118 2
0R0402-PAD
DY
84.07716.037
1 2
PC4125
3D3V_AUX_S5
PU4105
3V_5V_EN 36
PR4117
1
DY0R2J-2-GP
DY
PR4110
100KR2J-1-GP
25
2nd = 77.93371.011
PG4114
PWR_5V_ENTRIP1
15
18
PG4128
1
PG4107
1
8
2
1
PR4116
10KR2F-2-GP
PR4108
2D2R5F-2-GP
23
1
GAP-CLOSE-PWR
2
77.53371.04L
SE330U6D3VM-15-GP
GND
PG4125
1
K
TRIP1
VREF
GAP-CLOSE-PWR-3-GP
PWR_5V3D3V_VREF
2
IND-2D2UH-46-GP-U
1PWR_5V_SNUB
PGOOD
TRIP2
74.51123.073
PWR_3D3V_FB2_R
PC4124
Close to VFB Pin (pin5)
DY
3V_5V_POK
PWR_5V3D3V_SKIPSEL
14
3D3V_AUX_S5
PWR_5V3D3V_VREF
PWR_5V_FB1
5
6
7
8
PWR_5V3D3V_TONSEL
4
EN0
TPS51123RGER-GP
PR4112
0R2J-2-GP
1
2
PWR_5V_VOUT1
4
3
2
1
PWR_3D3V_ENTRIP26
3
3D3V_AUX_S5
5
6
7
8
24
2
PWR_5V3D3V_EN0 13
2
DY820KR2F-GP
PWR_5V3D3V_VREF
4
3
2
1
1
2
2
VIN
68.2R210.20B
2nd = 68.2R21B.10J
D 8
D 7
D 6
D 5
S
S
S
G
1
PR4109
1
2
3
4
VFB1
GAP-CLOSE-PWR
2
PG4127
1
S
S
S
G
1
2
3
4
1
2
16
1
2
D 8
D 7
D 6
D 5
1
2
1PWR_3D3V_SNUB
SE330U6D3VM-15-GP
1 2
DY
PR4123
1
0R2J-2-GP
DCBATOUT
PU4101_5
DY
PWR_5V3D3V_EN0
PU4101_2
0629 Modify
2N7002KDW-GP
PD4105
MMPZ5231BPT-GP
83.5R103.E3F
2nd = 83.PDZ51.AVF
TONSEL
PR4101
DY100KR2F-L1-GP
CH1
CH2
GND
200kHz
250kHz
VREF
300kHz
375kHz
400kHz
500kHz
VREG3 or VREG5
PR4125
750KR2F-GP
4
5
SKIPSEL
VREG3 or VREG5
VREF(2V)
Operating
Mode
OOA Auto Skip
Auto Skip
GND
PWM only
84.2N702.A3F
DY
1
Vz=5.1V DY
PU4101
PR4124
40K2R2F-GP
DY
DCBATOUT
PWR_5V_LGATE1
GAP-CLOSE-PWR-3-GP
PC4119
SCD1U10V2KX-4GP
VO1
VFB2
DYSC18P50V2JN-1-GP
0914 X01 Modify:

Un-stuff PU4101,PD4105,PR4124,
PR4125,PR4101 at X01 stage.
19
0719 Modify:
Reserved EC417 0.1uF for
EMC NEO suggestion.
5V_PWR
PL4102
3D3V_S5
2nd = 84.08065.B37
84.07716.037
Id=16A
Qg=7.3nC
Rdson=13.5~16.5mohm
VO2
PG4106
1
GAP-CLOSE-PWR
2
PG4126
1
PWR_5V_PHASE1
PR4111
6K65R2F-GP
PWR_5V_UGATE1
20
VREG5
GAP-CLOSE-PWR
2
SCD1U25V3KX-GP
PC4118
1 PR4106 2PWR_5V_VBST1_1 1
2
0R0603-PAD
22
SC10U6D3V5KX-1GP
PG4124
1
PWR_3D3V_FB2
VREG3
GAP-CLOSE-PWR
2
DRVL1
GAP-CLOSE-PWR
2
5V_S5
5V_PWR
Design Current = 8A
12.6A<OCP< 14.6A
21
17
PG4122
1
Mag. 2.20uH 6.5*6.9*3

DCR=18~20mohm
Idc=8A, Isat=14A
LL1
DRVL2
84.00412.037
2nd = 84.08061.A37
PWR_5V_BOOT1
PWR_5V3D3V_VREG3
GAP-CLOSE-PWR
2
LL2
PG4120
1
PC4121
SC330P50V3KX-GP DY
PWR_3D3V_VOUT2 7
84.07716.037
GAP-CLOSE-PWR
2
PU4106
SI7716ADN-T1-GE3-GP
PG4118
1
0804
DRVH1
PG4105
1
PC4117
SCD1U10V2KX-4GP
GAP-CLOSE-PWR
2
2D2R5F-2-GP
VBST1
DRVH2
PC4114 PC4116
GAP-CLOSE-PWR-3-GP
PG4116
1
PT4102
PWR_3D3V_LGATE2
12
VBST2
PU4104
SIS412DN-T1-GE3-GP
SCD1U50V3KX-GP
GAP-CLOSE-PWR
2
2nd = 68.2R21B.10J
DY
PG4113
PR4107
0721 Modify:
Change PR4106 to 0ohm 0603 from
2.2ohm from power team Brian updated.
SC10U25V6KX-1GP
PG4112
1
A00 1224
PWR_3D3V_PHASE2
11
2
IND-2D2UH-46-GP-U
PC4109
SCD1U25V3KX-GP
0804 Change MOS follow Brian.

0901 PU4104 and PU 4105 horizontally mirror.
S
S
S
G
GAP-CLOSE-PWR
2
PWR_3D3V_UGATE2
2D2R3-1-U-GP
10
SCD1U25V3KX-GP
68.2R210.20B
77.53371.04L
PL4101
= 77.93371.011
PC4108
SCD1U25V3KX-GP
0721 Modify:
Add PG4127,PG4128 from
power team Brian updated.
D
D
D
D
PG4110
1
PC4115
PR4105
2
1PWR_3D3V_BOOT1
1
2PWR_3D3V_BOOT2 9
PC4122
3D3V_PWR
3D3V_PWR
GAP-CLOSE-PWR
2nd
2
2nd = 84.08061.A37
SCD22U10V2KX-1GP
PG4108
1
PU4103
84.00412.037
PC4107
SC1U25V3KX-1-GP
PWR_5V_DCBATOUT
PWR_5V_DCBATOUT
S
S
S
G
0909 X01 Modify:

Change PL4101,PL4102 to 68.2R210.20B
from 68.2R210.20Q base on Brian updated.
Add 2nd source 68.2R21B.10J on PL4101,
PL4102 base on updated 2nd excel file.
PU4102
SIS412DN-T1-GE3-GP
DY
0721 Modify:
Change PU4104 to 84.04800.D37
from power team Brian updated.
PC4113
SC10U25V6KX-1GP
SCD1U50V3KX-GP
2
PC4112
PC4101
D
D
D
D
3D3V_S5
PC4111
DCBATOUT
0810
PC4108_1
0629 Modify
DCBATOUT
SCD01U50V2KX-1GP
Design Current = 9.2A

14.5A<OCP< 17A
PC4110
0604 Modify:
Change PU4103 to 74.8223.A73.
0714 Modify:
Change PU4103 to TPS51123 from RT8223MGQW.
0720 Modify:
Change PR4105 to 2.2ohm from 0ohm from
0913 X01 Modify:
Add 2nd source 84.08061.A37 on PU4102,
PU4104 base on Brian updated 2nd soruce excel file.
SC10U25V6KX-1GP
GAP-CLOSE-PWR
2
SC10U25V6KX-1GP
GAP-CLOSE-PWR
2
PG4104
1
SC10U25V6KX-1GP
PG4103
1
84.00412.037
Id=12A
Qg=3.8nC
Rdson=24~30mohm
PWR_3D3V_DCBATOUT
5V_S5
83.00054.Y81
2nd = 83.0R203.081
83.15R03.C3F
2nd = 83.15R03.E3F
PWR_3D3V_DCBATOUT
PD4101
BAT54S-7F-GP
15V_PWR
PG4101
GAP-CLOSE-PWR-3-GP
PD4104
BZT52C15S-GP
GAP-CLOSE-PWR
2
83.00054.Y81
2nd = 83.0R203.081
15V_S5
PG4102
1
1
3
PD4103
BAT54S-7F-GP
0603 Modify:
Change PR4103 to 187K from 100K.
DCBATOUT
PD4102
BAT54-7-F-GP
DY
PD4101_3
0629 Modify
DY
2
1
187KR2F-GP
PR4103
PC4106
SC18P50V2JN-1-GP
ROSA team
PD4103_3
0629 Modify
DY
PR4104
147KR2F-GP
PC4105
SC18P50V2JN-1-GP
PWR_3D3V_ENTRIP2
PWR_5V_ENTRIP1
PC4103
SCD1U25V3KX-GP
PC4104
SC1KP50V2KX-1GP
PC4102
SCD1U25V3KX-GP
1 PR4102 2
0R0402-PAD
1
PWR_3D3V_LGATE2
<Variant Name>
Wistron Corporation
Title
5V/3D3V(TPS51123RGER)
Size
A2
Date:
A
Document Number
Rev
A00
QUEEN 15
Sheet
E
41
of
108
PR4216
0629 Modify
95831_VW G
PR4216_1
ISPG
ISNG
PR4236
NTCG
95831_PROG2
VCCSENSE
VSSSENSE
43
ISEN1
ISEN1
43
ISEN2
ISEN2
43
ISEN3
ISEN3
1
2
43
PC4219
1
2
DY
PC4223
1
2
SC1000P50V3JN-GP-U
A00 1227
0629 Modify
PR4242_2
Place near choke of Phase1
PR4245
NTC-10K-27-GP
69.60013.131
2nd = 69.60011.201
VSUM-
845R2F-GP DC&QC
PG4201
PR4242
2K61R2F-1-GP
PR4218
2
DUMMY-C2
<Variant Name>
43
Wistron Corporation
PC4218
SCD1U10V2KX-4GP
Title
DUMMY-R2
0629 Modify
ISL95831_CPU_CORE(1/3)
Size
A3
0721 Modify:
Change PR4217 to 1K from 698ohm from
Date:
5
EC4209
SCD1U50V3KX-GP
0921
1R2F-GP
Change PU4201 VDD power source to 5V_S5 from
5V_S0 to avoid abnormal MVP_PWRGD waveform.
1
PR4217
1
SC330P50V2KX-3GP
0920 X01 Modify:

Change PR4213 to 3.6K from 3.16K
from Brian updated.
1
1
2
A00 1230
Only for Dual-core,
Qual-core stuff 3K6R(64.36015.6DL)
0721 Modify:
Only for Dual-core,
Change PR4213 to 3.16K from 2.32K from
2K37R2F-GP
Qual-core stuff 1K27R
DC&QC
(64.12715.6DL)
PR4218_2
VSUM+
A00 1227 PR4213

1
2
PC4210_2
SCD22U10V2KX-1GP
PC4213
1
2PC4213_1 1
2
0629 Modify
499R2F-2-GP
SC470P50V-2-GP
SC150P50V2KX-GP
316KR2F-GP
DUMMY-C2
0629 Modify
PC4230
PR4214
1
2PR4214_1 1
2
2KR2F-3-GP
SC560P50V-GP 0921 X01 Modify:
Add PR4214,PC4230 from vender suggestion.
PR4224
1 PR4225 2
0R0402-PAD
PR4209
DY
0719 Modify:
C1403(TOP),C1507,C1509,C1406,
TP_LOCK_LED1 for EMC NEO suggestion.
VCC_GFXCORE
33uF from 47uF from

updated.
0.033uF from 0.068uF from
updated.
PC4227
2
1
0629 Modify
0721 Modify:
Change PC4227 to
power team Brian
Change PC4225 to
power team Brian
PC4217
1
2
ISEN3
PC4216
1
2
PR4212
SC39P50V2JN-1GP
PC4210
1
2
0629 Modify
0629 Modify
PR4226
SCD22U10V2KX-1GP
0629 Modify
95831_COMP
95831_VDDP
PW R_VCCCORE1_DCBATOUT
95831_ISUMN
2
1
8K06R2F-GP
VSUM-
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
COMPG
FBG
VSENG
RTNG
ISPG
ISNG
NTCG
PROG2
BOOTG
UGG
PHG
LGG
SCD22U10V2KX-1GP
PC4209
1
2
DUMMY-R2
PC4207
PHASE1 43
UGATE1 43
BOOT1 43
PR4243
0R0402-PAD
5V_S5
1
2
1
LGATE1 43
PHASE1
UGATE1
BOOT1
0629 Modify
95831_VDD
PC4215
1
2
PC4206
SC1000P50V3JN-GP-U
DY
5K62R2F-GP
95831_FB
PR4206
LGATE1
0629 Modify
95831_VIN
0707 Modify:
Stuff PR4247 NTC Resistor.
27K4R2F-GP
PR4205
5V_S0
PR4223
2
0R2J-2-GP
95831_PW M3
PR4241
11KR2F-L-GP
PR4228
1
43
0901
69.60013.141
2nd = 69.60037.021
0629 Modify
LGATE2 43
PC4201
SCD22U25V3KX-GP
3K83R2F-GP
Place near high side MOSFET of Phase1
LGATE2
1
2
NTC-470K-9-GP
PC4224
SC330P50V2KX-3GP
0707 Modify:
Change all of 9531_AGND to GND for vender suggest.
PR4228_1
PR4247
BOOT2 43
UGATE2 43
PHASE2 43
0629 Modify
95831_PROG1
DUMMY-C2
PR4229
1
BOOT2
UGATE2
PHASE2
95831_NTC
0629 Modify
27K4R2F-GP
NTC place near high side MOSFET of Phase1
1
36
35
34
33
32
31
30
29
28
27
26
25
BOOT2
UG2
PH2
VSSP2
LG2
VDDP
PWM3
LG1
VSSP1
PH1
UG1
BOOT1
ISL95831HRTZ-T-GP
0629 Modify
PW M3
PG4203
PC4204
SC47P50V2JN-3GP
1
3K83R2F-GP
PR4222
0R0402-PAD
1 PR4215 2
0R0402-PAD
5,27,40 H_PROCHOT#
COMP
FB
ISEN3/FB2
ISEN2
ISEN1
VSEN
RTN
ISUMN
ISUMP
VDD
VIN
PROG1
75R2F-2-GP
0629 Modify
13
14
15
16
17
18
19
20
21
22
23
24
DY
1D05V_VTT
PR4220
BOOTG 44
UGATEG 44
PHASEG 44
LGATEG 44
ISEN3
ISEN2
ISEN1
VSSSENSE
PR42351
3D3V_S0
27,36 IMVP_PW RGD
VWG
IMONG
PGOODG
SDA
ALERT#
SCLK
VR_ON
PGOOD
IMON
VR_HOT#
NTC
VW
PR4207
22KR2F-GP
1 PR4204 2
0R0402-PAD
A00 1227
Only for Dual-core,

DC&QC
Qual-core stuff 18K2R
(64.18225.LDL)
PC4203
SCD01U50V2KX-1GP
1 PR4203 2
0R0402-PAD
95831_IMON
PU4201
PR4230
1K91R2F-1-GP
1
0629 Modify
2
95831_PGOODG 3
95831_SDA
4
5
95831_SCLK
6
IMVP_VR_ON
7
8
2 1K91R2F-1-GP
9
H_PROCHOT#_C
10
11
PR4201
95831_VW
12
0629 Modify
1
2
8 VR_SVID_ALERT#
8 H_CPU_SVIDCLK
48 D85V_PW RGD
3D3V_S0
1 PR4231 2
0R0402-PAD
0707 Modify:
Removed PR4233.
PR4234
54D9R2F-L1-GP
0707 Modify:
Removed PR4240 GND to 95831_AGND.
PR4244
75R2F-2-GP
2
1
Close to CPU
PR4219
69.60013.141
2nd = 69.60037.021
16K5R2F-2-GP
SCD1U10V2KX-4GP
0707 Modify:
Updated IMONG and IMON circuit
from power team Brian.
PC4214
1D05V_VTT
PR4232
130R2F-1-GP
2
1
1
2
PC4205
SCD047U25V2KX-GP
VSS_AXG_SENSE
8 H_CPU_SVIDDAT
PR4246
1
2
NTC-470K-9-GP
TP4202 TPAD14-GP
1
PR4239
1
PR4202
22KR2F-GP
DUMMY-C2
0920 X01 Modify:

3K01R2F-3-GP Change PR4236 to 3.01K from 3.32K
from Brian updated.
95831_IMONG
Only for Dual-core,

Qual-core stuff 22KR
(64.22025.6DL)
PG4202
44
44
0719 Modify:
Stuff PR4246 NTC resistor.
475KR2F-GP
SC150P50V2KX-GP
SC1000P50V3JN-GP-U
0629 Modify
PR4210
2PC4211_2 1
VSS_AXG_SENSE 9
PC4221
PC4221_1 1
2
0629 Modify
422R2F-2-GP
SC680P50V2KX-2GP
SC39P50V2JN-1GP
PC4211
PC4222
1
2
PR4211
PC4208
1
2
VCC_AXG_SENSE 9
PC4225
SCD033U16V2KX-GP
DUMMY-R2
PR4237
SCD33U6D3V2KX-1-GP
DY
SC330P50V2KX-3GP
PC4212
SCD068U10V2KX-1GP
PC4226
SC1U10V2KX-1GP
0629 Modify
95831_COMPG
95831_FBG
PC4228
SC1U10V2KX-1GP
PC4220
1
2
PC4202
SC1000P50V3JN-GP-U
PR4208
8K06R2F-GP
0719 Modify:
PR4246(TOP) for EMC NEO suggestion.
0721 Modify:
Removed EC4201~EC4203.
SC330P50V2KX-3GP
2KR2F-3-GP
PC4229
SC1U10V2KX-1GP
SSID = CPU.Regulator
0921 X01 Modify:

Add PR4216,PC4231 from vender suggestion.
PC4231
1
2
PR4220_1
Document Number
Rev
A00
QUEEN 15
Sheet
1
42
of
108
42
VSUM+
1
2
SC4D7U25V5KX-GP
1
2
ST330U2VDM-4-GP
1
2
2
PWR_VCCCORE_VSUM-_1
1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
79.33719.20L
2nd = 77.C3371.13L
ST330U2VDM-4-GP
2
1
5
6
7
8
1
PG4318
PG4317
PT4302
79.33719.20L
PR4315
2nd = 77.C3371.13L
1
2
DY
1R2F-GP
ISEN2
42
PR4316
1
DY
2
1R2F-GP
PR4317
1
2
1R2F-GP
ISEN3
42
VSUM-
42
PR4318
2
ISEN1
42
10KR2F-2-GP
PR4319
2
1
VSUM+
42
3K65R2F-1-GP
42
0705 Modify
DCBATOUT_IMVP7
FOR NVIDIA VENTURA

0705 Modify
PWR_VCCCORE1_DCBATOUT
PG4305
2
0705 Modify
DCBATOUT
GAP-CLOSE-PWR
PG4306
1
2
DCBATOUT_IMVP7
VCC_CORE
1
PR4321
10R2F-L-GP
PR4322
10R2F-L-GP
VENTURA
VENTURA
PC4319
1
2
VENTURA
SCD1U25V2KX-GP
ISEN3
42
42
DY
42
VSUM+
42
R4346
3K3R2J-3-GP
DY
DN15ATI
0728
Wistron Corporation
3K65R2F-1-GP
SMBC_INA219 85,92
SMBD_INA219 85,92
Title
ISL95831_CPU_CORE ( 2 of Rev
3)
Size
Document Number
Custom
Would be instead of INA219 by HPA00900
QUEEN 15
Date: Tuesday, January 04, 2011

4
R4347
3K3R2J-3-GP
1R2F-GP
ISEN2
0712 Modify:
Change VENTURA solution part number to
74.00900.079 from 74.00219.079.
INA_A0
INA_A1
1
VSUM-
2nd = 79.47612.60L
VENTURA
HPA00900AIDCNR-GP
74.00900.079
10KR2F-2-GP
PR4313
2
1
3K3R2J-3-GP
R4344
A00 1224
PT4306
SE47U25VM-11-GP
79.47612.3FL
R4345
3K3R2J-3-GP
VENTURA
DCBATOUT
0719 Modify:
Reserved PTC4307 47uF.
0721 Modify:
Removed PTC4307.
VENTURA
SCD1U10V2KX-5GP
PR4311
0702 Modify:
Change U4306 power source to
3D3V_VGA_S0 from 3D3V_S0.
VIN+
VINGND
VS
U4306
3D3V_VGA_S0
VENTURA
PR4310
1
2
DY
1R2F-GP
GAP-CLOSE-PWR
42
GAP-CLOSE-PWR
PG4310
1
2
C4301
A1
A0
SDA
SCL
ISEN1
GAP-CLOSE-PWR
PG4309
1
2
0705 Modify:
Add PR4321,PR4322,PC4319.
1
2
3
4
79.33719.20L
2nd = 77.C3371.13L
2nd = 77.C3371.13L
1
2
DY
1R2F-GP
GAP-CLOSE-PWR
PG4308
1
2
A00 1224
0705 Modify:
Removed R4347 sense Resistor base on VENTURA SPEC.
1
2
D004R3720F-GP
79.33719.20L
PR4309
PR4312
2
PT4304
ST330U2VDM-4-GP
PG4304
ST330U2VDM-4-GP
1
2
2
1
PG4303
0708 Modify:
PR4320 change to BIG SIZE footprint for CPU VENTURA.
0705 Modify:
R4346 change to PR4320 4m ohm sense
Resistor from 3m ohm.
0705 Modify
PT4303
A00 1223 no co-lay

PR4320
1
2
SC4D7U25V5KX-GP
1
2
SC4D7U25V5KX-GP
1
2
SC4D7U25V5KX-GP
PC4311
0809
2nd = 84.08059.037
0719 Modify:
Change PU4305 part number to 84.00172.037 from
84.07686.037 base on power team Brian suggestion.
0726 Modify:
Brian updatede PU4305 change to 84.00462.037.
1
2
5
6
7
8
84.00460.037
PC4310
8
7
6
5
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
GAP-CLOSE-PWR
SC4D7U25V5KX-GP
1
2
SC4D7U25V5KX-GP
1
2
SC4D7U25V5KX-GP
1
2
SC4D7U25V5KX-GP
4
3
2
1
84.00460.037
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
Vcc_core
Iomax=53A
OCP>97.5A
42
A00 1224
PT4301
0809
PWR_VCCCORE_VSUM+_1
ISEN3
4
3
2
1
1
2
ST330U2VDM-4-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
ST330U2VDM-4-GP
5
6
7
8
2
2
1
4
3
2
1
PWR_VCCCORE_VSUM-_3
1
VSUM-
2
L-D36UH-1-GP
GAP-CLOSE-PWR
PG4316
1
2
LGATE1
GAP-CLOSE-PWR
PG4315
1
2
A
2
1R2F-GP
VCC_CORE
PU4310
84.00460.037
42
0705 Modify
PL4303
68.R3610.20A
2nd = 68.R3610.20C
2nd = 84.08059.037
42
ISEN2
PC4317
3K65R2F-1-GP
PWR_VCCCORE_VSUM-_2
GAP-CLOSE-PWR
PG4314INS43029
1
2
84.00460.037
42
2
L-D36UH-1-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR
PG4313
1
2
QC
PR4305
1
68.R3610.20A
2nd = 68.R3610.20C
PWR_VCCCORE_VSUM+_2
4
3
2
1
GAP-CLOSE-PWR
PG4312
1
2
SIR460DP-T1-GE3-GP
S
S
S
G
84.00460.037
PWR_VCCCORE2_DCBATOUT 2nd = 84.08059.037

PG4311
2
84.00460.037
PU4307
SIR460DP-T1-GE3-GP
S
S
S
G
QC
1
PU4309
2nd = 84.08059.037
79.33719.20L
2nd = 77.C3371.13L
PL4302
1
D
D
D
D
D
D
D
D
PU4306
4
3
2
1
LGATE2
0705 Modify
DCBATOUT_IMVP7
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
PT4309
PR4304
1
2
DY
1R2F-GP
PC4309
GAP-CLOSE-PWR-3-GP
4
3
2
1
84.00462.037
2nd = 84.08064.A37
PHASE2
5
6
7
8
LGATE2
PC4308
SC4D7U25V5KX-GP
1
42
ISEN1
U4306_VIN-
PHASE2
PR4303
1
2
DY
1R2F-GP
PT4308
U4306_VIN+
UGATE2
42
S
S
S
G
42
UGATE2
SC4D7U25V5KX-GP
2PWR_VCCCORE_BOOT2_1
QCPC4307
2D2R3-1-U-GP
PC4312
SCD22U25V3KX-GP
UGATE1
PHASE1
PC4316
QC
GAP-CLOSE-PWR
PG4307
1
2
D
D
D
D
PR4308
1
42
42
PC4315
PU4305
SIR462DP-T1-GE3-GP
79.33719.20L
2nd = 77.C3371.13L
PR4306
0719 Modify:
0726 Modify:
5
6
7
8
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
GAP-CLOSE-PWR
BOOT2
0809
10KR2F-2-GP
PR4307
2
1
GAP-CLOSE-PWR
PG4324
1
2
42
A00 1224
PG4302
GAP-CLOSE-PWR
PG4322
1
2
GAP-CLOSE-PWR
PG4323
1
2
VCC_CORE
PC4314
84.00462.037
2nd = 84.08064.A37
5
6
7
8
1
2
84.00460.037
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
PWR_VCCCORE_VSUM+_3
84.00460.037
0705 Modify
SIR462DP-T1-GE3-GP
PC4318
SCD22U25V3KX-GP
2
L-D36UH-1-GP
PG4301
2nd = 84.08059.037
GAP-CLOSE-PWR
PG4321
1
2
68.R3610.20A
0.36uH, Idc=20A,
Isat=25A
DCR=1.4 +/-7% mohm
68.R3610.20A
2nd = 68.R3610.20C
5
6
7
8
5
6
7
8
PWR_VCCCORE_LG3
GAP-CLOSE-PWR
PG4320
1
2
SC4D7U25V5KX-GP
4
3
2
1
BOOT
GND
GND
9
3
4
3
2
1
1
PG4319
2
SC4D7U25V5KX-GP
1
5
6
7
8
1
2
5
VCC
1
DCBATOUT_IMVP7
SIR460DP-T1-GE3-GP
S
S
S
G
84.00460.037
2nd = 84.08059.037
0705 Modify
SIR460DP-T1-GE3-GP
S
S
S
G
QC
80.3371V.A2L
330uF, 2.5V, B2
ESR=9m[, Iripple=3.073A
PL4301
D
D
D
D
PU4303
PU4304
2D2R3-1-U-GP
PC4306
SC4D7U25V5KX-GP
PC4313
SIR460DP-T1-GE3-GP
S
S
S
G
PWR_VCCCORE_PH3
PWR_VCCCORE_HG3
7
8
4
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
D
D
D
D
ISL6208CRZ-TGP-U
PHASE
UGATE
LGATE
PC4305
PU4308
D
D
D
D
PWM
PWR_FCCM
6 FCCM
SC4D7U25V5KX-GP
1
2
2
PC4302
SCD22U25V3KX-GP
PC4304
PR4314
1
BOOT1
SIR460DP-T1-GE3-GP
S
S
S
G
PWM3
PC4303
42
D
D
D
D
42
PU4302
2D2R3-1-U-GP
S
S
S
G
PR4301 PU4301
0R0402-PAD
PR4302
1
D
D
D
D
S
S
S
G
SC1U10V2KX-1GP
PC4301
D
D
D
D
PWR_VCCCORE_BOOT3
5V_S0
0719 Modify:
0726 Modify:
4
3
2
1
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
A00
Sheet
1
43
of
108
0705 Modify
DCBATOUT_IMVP7
0719 Modify:
0720 Modify:
84.00172.037 base on power team Brian suggestionl.
SC4D7U25V5KX-GP
1
2
GAP-CLOSE-PW R
2
79.33719.20L
A00 1224
1
2
80.3371V.A2L
330uF, 2.5V, B2
79.33719.20L
2nd = 77.C3371.13L
DY
0629 Modify
PC4408_1
PR4402
1 DY
SCD068U16V2KX-GP
PR4404
1
2
2
2
1
PT4403
ST330U2VDM-4-GP
ST330U2VDM-4-GP
1
2
ST330U2VDM-4-GP
VCC_GFXCORE
Iomax=33A
OCP>50A
2nd = 77.C3371.13L
PT4402
PC4411
ISNG
42
0721 Modify:
768R2F-1-GP
Change PR4404 to 768ohm from 549ohm from
SCD068U16V2KX-GP
ISPG
42
DY
PW R_GFXCORE_DCBATOUT
1
2
VCC_GFXCORE
1
2
DY
2
1
2
1
2
PG4409
1
SCD1U50V3KX-GP
EC4410
GAP-CLOSE-PW R
2
0920 X01 Modify:

Change PC4410 to 0.01u from 0.022uF
from Brian updated.
SCD1U50V3KX-GP
EC4409
SCD1U50V3KX-GP
EC4407
PC4410
SCD01U16V2KX-3GP
11KR2F-L-GP
PR4405_2
1 2
PR4406
7K5R2F-1-GP
SCD1U50V3KX-GP
EC4408
PG4408
1
0715 Modify:
Add EC4401~EC4410 for EMC NEO suggestion.
SCD1U50V3KX-GP
EC4405
SCD1U50V3KX-GP
EC4403
DY
SCD1U50V3KX-GP
EC4402
SCD1U50V3KX-GP
EC4401
DY
GAP-CLOSE-PW R
2
549R2F-GP
1R2F-GP
PR4405
NTC-10K-27-GP
10KR2F-2-GP
PG4407
1
PR4408
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
PR4403
VCC_CORE
GAP-CLOSE-PW R
2
PT4401
PC4409
SCD1U10V2KX-4GP
0629 Modify
PR4403_2
PR4407
VCC_CORE
PG4406
1
PC4408
69.60013.131
EMI/ESD
GAP-CLOSE-PW R
2
VCC_GFXCORE
0809
2nd = 69.60011.201
0629 Modify
PG4405
1
79.33719.20L
PG4402
GAP-CLOSE-PWR-3-GP
PWR_GFXCORE_ISP_R
84.03503.037
BSZ035N03MS
Id=18A,Qg=27~35nC,
Rdson=3.4~4.3mohm
GAP-CLOSE-PW R
2
PC4406
68.R3610.20A
0.36uH, Idc=20A, Isat=25A
DCR=1.4 +/-7% mohm
PG4401
84.00460.037
2nd = 84.08059.037
PG4404
1
2nd = 77.C3371.13L
68.R3610.20A
2nd = 68.R3610.20C
2
SIR460DP-T1-GE3-GP
S
S
S
G
PU4404
PC4405
PL4401
1
2
L-D36UH-1-GP
D
D
D
D
SIR460DP-T1-GE3-GP
S
S
S
G
84.00460.037
2nd = 84.08059.037
D
D
D
D
PU4403
5
6
7
8
LGATEG
4
3
2
1
42
4
3
2
1
UGATEG
PHASEG
5
6
7
8
84.00462.037
2nd = 84.08064.A37
42
42
1
PWR_GFXCORE_ISN_R
4
3
2
1
PU4401
SIR462DP-T1-GE3-GP
SC4D7U25V5KX-GP
2
0721 Modify:
Removed PC4401
S
S
S
G
PC4407
SCD22U25V3KX-GP
PC4403 PC4404
0624 Modify:
Removed PU4402
MOSFET.
PW R_GFXCORE_BOOT_1
GAP-CLOSE-PWR-3-GP
1R3J-L1-GP
SC4D7U25V5KX-GP
5
6
7
8
PR4401
1
BOOTG
D
D
D
D
42
PC4402
GAP-CLOSE-PW R
2
84.00462.037
SIR462DP-T1-GE3-GP
Id=30A, Qg=8.8nC,
Rdson=7.9 mohm
PG4403
1
DN15ATI
Wistron Corporation
Title
ISL95831_CPU_CORE(3/3)
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
44
of
108
DCBATOUT
PW R_1D05V_DCBATOUT
PG4501
1
GAP-CLOSE-PW R
2
PG4502
1
GAP-CLOSE-PW R
2
PG4503
1
GAP-CLOSE-PW R
2
0719 Modify:
PW R_1D05V_DCBATOUT
1122 X02 Modify:
EMC Neo suggestion.
1
2
EC4501
SCD1U50V3KX-GP
1
2
1
2
1
2
5
6
7
8
4
3
2
1
1
2
DY
PW R_1D05V_VFB
PC4509
SC560P50V-GP
PR4507
20KR2F-L-GP
0921
DY
PTC4509
PC4511
79.3971V.30L
2nd = 77.93971.02L
0920 X01 Modify:

Change PR4507 to 20K from 20.5K
from Brian updated.
1D05V_VTT
PG4505
1
GAP-CLOSE-PW R
2
PG4506
1
GAP-CLOSE-PW R
2
PG4507
1
GAP-CLOSE-PW R
2
PG4508
1
GAP-CLOSE-PW R
2
PG4509
1
GAP-CLOSE-PW R
2
PG4510
1
GAP-CLOSE-PW R
2
PG4511
1
GAP-CLOSE-PW R
2
PG4512
1
GAP-CLOSE-PW R
2
PG4513
1
GAP-CLOSE-PW R
2
PG4514
1
GAP-CLOSE-PW R
2
PG4515
1
GAP-CLOSE-PW R
2
PG4516
1
GAP-CLOSE-PW R
2
VSS_SENSE_L
2nd = 84.08059.037
1
2
1
PR4506
9K76R2F-1-GP
PC4508
1
2
100R2F-L1-GP-U
VTT_SENSE_L
DY
84.00460.037
A00 1224
COIL-2D2UH-11-GP
68.2R210.20C
2nd = 68.2R21B.10I PR4505
1PWR_1D05V_SNUB 2
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
SCD1U10V2KX-4GP
A00 1224
DY
2D2R5F-2-GP
4
3
2
1
2
PC4501
PR4514
PU4503
PL4501
SCD1U25V3KX-GP
PC4503
5
6
7
8
0809
1
PW R_1D05V_DRVL
1D05V_PW R
SCD1U10V2KX-4GP
5V_S5
TPS51218DSCR-GP-U1
DY
2
PW R_1D05V_VBST 1
2PW R_1D05V_VBST_R
2
PW R_1D05V_DRVH
2D2R3-1-U-GP
PW R_1D05V_SW

15.6A<OCP< 18.3A
Mag. 2.20uH 10*11.5*4

DCR=6.7~7mohm
Idc=12A, Isat=27A
0909 X01 Modify:

Change PL4501 to 68.2R210.20C
from IND-D56UH-27-GP base on
Brian updated.
SIR460DP-T1-GE3-GP
S
S
S
G
SC1KP50V2KX-1GP
11
10
9
8
7
6
SC1U10V2KX-1GP
GND
VBST
DRVH
SW
V5IN
DRVL
PC4502
SCD1U25V3KX-GP
1
D
D
D
D
PR4503
470KR2F-GP
PGOOD
TRIP
EN
VFB
CCM
PR4504
1D05V_PW R
SE390U2D5VM-7GP
PT4502
1
PR4502
PW R_1D05V_TRIP 2
1
2
PW R_1D05V_EN
3
1
2
PW R_1D05V_VFB 4
75KR2F-GP
0R0402-PAD-2-GP
PW R_1D05V_CCM 5
A00 1224
84.00172.037
2nd = 84.08065.037
PU4501
10KR2J-3-GP
37,48 1.05VTT_PW RGD
PR4501
19,46,47,93 RUNPW ROK
0721 Modify:
Change PR4504 to 2.2ohm from 0ohm from
PC4507
SCD1U25V3KX-GP
S
S
S
G
PR4516
3D3V_S0
1123 X02 Modify:

Change PR4501 to 75K from 45.3K
for 1.05V OCP set to 20A from Brian.
PC4506
SC4D7U25V5KX-GP
PU4502
SIR172DP-T1-GE3-GP
PC4505
SC4D7U25V5KX-GP
TPS51218 for 1D05V
PC4504
SC4D7U25V5KX-GP
GAP-CLOSE-PW R
2
D
D
D
D
PG4504
1
84.00172.037
BSZ115N03MSC
Id=20A, Qg=9.8nC,
Rdson=8.9 mohm
0721 Modify:
Brian suggest change PU4503 to 84.00460.037.
Change PR4506 to 9.76K from 10K from
PR4508
100R2F-L1-GP-U
1 PR4509 2
0R0402-PAD
VCCIO_SENSE
DY
VSS_SENSE_L
PC4510
SC1000P50V3JN-GP-U
1 PR4510 2
0R0402-PAD
0617 Modify:
Joseph Change PTC4502 to 330uF from 390uF
base on layout placement status.
0721 Modify:
0719 Modify:
Brian Add PC4511 1uF.
Change PTC4502 to 330u 79.33719.L01. Reserved EC4502,EC4503 0.1uF near
0901 X01 Modify:
Change PTC4502 to 79.3971V.30L from
79.33719.L01 from power team Brian updated.
0913 X01 Modify:
Add 2nd source 77.93971.02L on PTC4502
base on Brian updated 2nd soruce excel file.
DN15ATI
Wistron Corporation
Title
TPS51218_+1.05V_VTT
Size
A3
Date:
5
PG4516(TOP) for EMC NEO suggestion.
VSSIO_SENSE 8
0727 Modify:
PR4505,PR4508 change to 100ohm from 10ohm.
stuff PR4509,PR4510 0ohm from Brian updated.
EC4502
SCD1U50V3KX-GP
DY
Vout=0.704V*(R1+R2)/R2
VTT_SENSE_L
Document Number
Rev
A00
QUEEN 15
Sheet
1
45
of
108
SSID = PWR.Plane.Regulator_1p5v0p75v
1D5V_PW R
DCBATOUT
0719 Modify:
VTTGND
GND
TPS51216RUKR-GP
74.51216.073
State
S3
VTTREF
VTT
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
Off(Hi-Z)
S4/S5
Lo
Lo
Off
Off
Off
400kHz
100k ohm
300kHz
1
2
2
1
1
2
PG4613
GAP-CLOSE-PW R
1D5V_PW R
1
2
PG4614
GAP-CLOSE-PW R
1
2
PG4615
GAP-CLOSE-PW R
DY
EC4601
SCD1U50V3KX-GP
A00 1224
PT4602
PC4613
SCD1U50V3KX-GP
1
2
1
2
PG4616
GAP-CLOSE-PW R
1
2
PG4617
GAP-CLOSE-PW R
1
2
PG4618
GAP-CLOSE-PW R
1
2
PG4619
GAP-CLOSE-PW R
1
2
PG4620
GAP-CLOSE-PW R
1
2
PG4621
GAP-CLOSE-PW R
1
2
PG4622
GAP-CLOSE-PW R
0721 Modify:
Removed PR4615,PR4616 and connect
0D75V_EN to VTTEN directly.
1
2
PG4623
GAP-CLOSE-PW R
On
1
2
PG4624
GAP-CLOSE-PW R
DDR_VREF_S3
PW R_1D5V_VTTREF 1 PR4611 2
0R0603-PAD
19,27,75 PM_SLP_S4#
0702 Modify:
Add PR4611 0ohm 0603 pad
on PWR_1D5V_VTTREF.
Discharge Mode
PR4607
1
A00 1224
PW R_1D5V_EN
0R0402-PAD-2-GP
DY
1
2
PG4625
GAP-CLOSE-PW R
PC4606
SCD1U10V2KX-5GP
Frequency
1
2
PG4612
GAP-CLOSE-PW R
GAP-CLOSE-PW R
MODE
200k ohm
GAP-CLOSE-PW R
79.3971V.30L
390uF, 2.5V,6.3X5.7
0630 Modify:
ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.
GAP-CLOSE-PW R
PG4602
1
2
VDDR
1
2
PG4611
GAP-CLOSE-PW R
79.3971V.30L
2nd = 77.93971.02L
1D5V_PW R
0721 Modify:
un-stuff PC4617 from
GAP-CLOSE-PW R
PG4606
2
1
0902 X01 Modify:

Change PTC4602 to 79.3971V.30L from
79.22719.20L sync with DQ15-NV
Add 2nd source 77.93971.02L on PTC4602.
2nd = 84.08059.037
+0D75V_DDR_P
0D75V_S0
PG4601
1
2
S5
PR5003
5
6
7
8
84.00460.037
0630 Modify:
Change 1D5V power soluiton to TPS51216 from
TPS51116 follow power team Brian suggest.
0630 Modify:
Change PC4610 to 0.22u 0402
from 0603 from Brian.
PC4622
SC330P50V2KX-3GP
7
0920 X01 Modify:
Change PR4602 to 110K from 68K
from Brian updated.
DY
1
2
PG4610
GAP-CLOSE-PW R
SE390U2D5VM-7GP
GAP-CLOSE-PW R
PG4605
2
1
PC4621
SCD1U10V2KX-4GP
VTTS
PC4610
SCD22U6D3V2KX-1GP
21 GND
DY
PC4620
SC4D7U6D3V5KX-3GP
VTT
+0D75V_DDR_P
68.R6810.20G
2nd = 68.R681A.10Q
DY
68.R6810.20G
Id=22~39A
DCR=2.4~2.7mohm
TPS51216_PHS_SET
Size=10X11.5X4
2
VTTREF
VTTIN
VDDQS
1
2
PG4609
GAP-CLOSE-PW R
2
IND-D68UH-51-GP-U
PR4612
2D2R5F-2-GP
4
3
2
1
TRIP
PW R_1D5V_VTTREF5
PW R_1D5V_VDDQS
PU4603
PC4604
SC1U10V3KX-3GP
10
84.00460.037
SiR460DP-T1-GE3
Id=40A, Qg=16.8nC,
Rdson=4.7~6.1 mohm
SC10U6D3V5MX-3GP
PGND
PC4614
SC4D7U25V5KX-GP
TPS51216_DRVL
1
2
PG4608
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4604
2
1
0913 X01 Modify:

Add 2nd source 68.R681A.10Q on PL4601
base on Brian updated 2nd soruce excel file.
PG4607
GAP-CLOSE-PWR-3-GP
11
DRVL
PC4612
SC10U25V6KX-1GP
PW R_1D5V_SW
+PW R_SRC_1D5V
PG4603
1

22.71A<OCP< 26.84A
4
3
2
1
13
MODE
PW R_1D5V_TRIP 18
SW
PC4616
2
1
SC10U6D3V5MX-3GP
200KR2F-L-GP
1
PR4602
110KR2F-GP
1
14
PL4601
REFIN
PW R_1D5V_MODE 19
2
1
PR4601
47KR2F-GP
PR4606
PR4608
1
2
PW R_1D5V_REFIN 8
4K02R2F-GP
2
1
2
1
DRVH
PW R_1D5V_DRVH
84.00172.037
2nd = 84.08065.037
PWR_1D5V_VDDQS
VREF
0721 Modify:
PR4603
10KR2F-2-GP Change PR4602 to 68K from 6.2K from
0928
Change PR4606 to 4.02K from
240ohm for fine tune 1.5V output
Voltage.
15
VBST
SIR172DP-T1-GE3-GP
PC4619
SCD1U25V3KX-GP
SIR460DP-T1-GE3-GP
S
S
S
G
PC4602
SCD01U16V2KX-3GP
2
1
EN/PSV
PR4605
PW R_1D5V_VBST1
2
2D2R3J-2-GP
D
D
D
D
PC4603
SCD1U25V3KX-GP
VTTEN
16
PW R_1D5V_VREF 6
PR4601_1
17
12
PC4615
2
1
SCD1U10V2KX-4GP
PW R_1D5V_EN
0D75V_EN
V5IN
S
S
S
G
37
PGOOD
PC4617
2
1
PU4601
20
19,45,47,93 RUNPW ROK

0721 Modify:
Removed PR4615,PR4616 and connect
0D75V_EN to VTTEN directly.
PR4605_2
PU4602
0630 modify
PC4611
SC10U25V6KX-1GP
D
D
D
D
PR4604
20KR2J-L2-GP
84.00172.037
BSZ115N03MSC
Id=20A, Qg=9.8nC,
Rdson=8.9 mohm
PC4609
SC10U25V6KX-1GP
+PW R_SRC_1D5V
5
6
7
8
3D3V_S0
PC4601
SC1U10V3KX-3GP
5V_S5
1D5V_S3
Tracking Discharge
68k ohm
300kHz
47k ohm
400kHz
Non-tracking Discharge
<Variant Name>
A
Wistron Corporation
Title
TPS51116_+1.5V_SUS
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
46
of
108
SSID = PWR.Plane.Regulator_1D8V_S0
3D3V_S5
PC4709
SCD1U25V3KX-GP
TPS51311 PWM for 1D8V_S0

3D3V_S5
+1.8V_RUN
Design current = 2.7985A
51331_VBST
1 PR4710 251331_VBST_1
0R0603-PAD
PC4711
SCD1U25V3KX-GP
GAP-CLOSE-PW R
1D8V_RUN_PW R
2
1
PR4712
51331_EN
PC4717
SC1U6D3V2KX-GP
1 2
0629 Modify
PC4712_1
0920 X01 Modify:

stuff PC4714 22uF
from Brian updated.
PR4701
20KR2F-L-GP
1
2
PG4702
GAP-CLOSE-PW R
51331_FB
51331_FB_1
GAP-CLOSE-PW R
PR4713
40D2R2F-GP
GAP-CLOSE-PW R
PG4709
1
2
PC4712
SC2200P50V2KX-2GP
PG4710_1
0902 X01 Modify:

Change PR4712 to 10K from 0ohm and stuff
PC4717 for fine tune 1D8V_S0 ramp up sequence.
10KR2J-3-GP
B
68.2R210.20B
2nd = 68.2R21B.10J
74.51311.073
19,27,36,37,75 PM_SLP_S3#
GAP-CLOSE-PW R
PG4708
1
2
IND-2D2UH-46-GP-U
TPS51311RGTR-GP
PG4707
2
SW#5
SW#6
SW#7
PL4701
PC4714
PGOOD
EN
51331_SW
SC22U6D3V5MX-2GP
PR4708
57K6R2F-GP
5
6
7
1D8V_RUN_PW R
1D8V_S0
PG4706
1
2
PC4715
SC10U6D3V5MX-3GP
RES
MODE
3
1
19,45,46,93 RUNPW ROK
DY
2
8
VBST
PG4710
GAP-CLOSE-PWR-3-GP
51331_PS
1
DY 2
100KR2J-1-GP PR4714
3D3V_S0
COMP
PC4713
SCD1U25V3KX-GP
PC4718
SC10U6D3V5MX-3GP
FB
15
16
10
PGND
PGND
PC4716
SC10U6D3V5MX-3GP
2
1
AGND
PGND
13
14
PC4710
51331_FB_1
1
2 PR4709_1 2
1
SC2200P50V2KX-2GP
5K9R2F-GP 0629 Modify
51331_COMP
11
17
PR4709
VIN
VIN
SC100P50V2JN-3GP
2
VDD
PC4701
1
12
PU4702
PR4711
10KR2F-2-GP
DN15ATI W histler
Wistron Corporation
Title
TPS51311 for 1D8V_S0

Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
47
of
108
3D3V_S0
TPS51461 for VCCSA
VCCSA_PWM
PWR_VCCSA_V5DRV
DY
VCCSA_PWM
PWR_VCCSA_VID1
1 PR4804 2
0R0402-PAD
1 PR4805 2
0R0402-PAD
PWR_VCCSA_VID0
PWR_VCCSA_EN
VCCSA_SEL
H_FC_C22
VCCSA_PWM
1 PR4801 2
0R0402-PAD
1.05VTT_PWRGD
VCCSA_PWM
1
2
D85V_PWRGD 42
PR4812
1
2
1KR2F-3-GP
VCCSA_PWM
PWR_VCCSA_PGOOD
PC4816
SC2D2U10V3KX-1GP
1 PR4808 2
0R0402-PAD
VCCSA_PWM
PC4814
PR4806
1R2F-GP
VCCSA_PWM
PR4809
4K7R2J-2-GP
SC1U10V2KX-1GP
1112 X02 Modify:

set TPS51461 PWM solution dummy field for
VCCSA_PWM and APL5916 LDO solution dummy
field for VCCSA_LDO. defualt stuff VCCSA_LDO at
ST stage.
VCCSA_PWM
5V_S5
37,45
DY
PC4810
SC1U6D3V2KX-GP
0D85V_S0
100R2F-L1-GP-U
2nd = 68.R4710.10V
0.9V
0.8V
0.725V
0.675V
PC4801
SCD01U50V2KX-1GP
VCCUSA_SENSE 9
VCCSA_PWM
VCCSA_PWM
PR4802
VCCSA_PWM
DY
4K99R2F-L-GP
VCCSA_PWM
1
2
DYPC4808
VCCSA_PWM VCCSA_PWM
VCCSA_PWM VCCSA_PWM
PC4809
SC560P50V-GP
0D85V_S0
PC4817
SC3300P50V3KX-1GP
PC4802
SCD22U10V2KX-1GP
EC4801
SCD1U50V3KX-GP
DY
VCCSA_PWM
PWR_VCCSA_COMP_1
1PWR_VCCSA_SNUB
2
1 PR4810 2
0R0402-PAD
1
2
1
2
GND
VREF
COMP
SLEW
VOUT
MODE
PWR_VCCSA_VOUT
PWR_VCCSA_SLEW
68.R4710.10M
SCD1U25V3KX-GP
1
2
3
4
5
6
DY
SC22U6D3V5MX-2GP
VCCSA
1
2
IND-D47UH-22-GP
VCCSA_PWM
PR4803
2D2R5F-2-GP
SC22U6D3V5MX-2GP
PWR_VCCSA_SW
VCCSA_PWM
PR4811
74.51461.043
0D85V_S0
PL4801
SC22U6D3V5MX-2GP
TPS51461RGER-GP
PWR_VCCSA_COMP
PWR_VCCSA_VREF
VID1
VCCSA_PWM
SC22U6D3V5MX-2GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SCD1U25V3KX-GP
VID0
C
PC4812
VCCSA_PWM
VCCSA_PWM
VCCSA_PWM

6.6A<OCP< 7.8A
PC4806
PC4813
BST
SW#11
SW#10
SW#9
SW#8
SW#7
PC4805
PC4815
68.R4710.10M
Id=17.5~26A
DCR=4~4.2mohm
Size=6.5X6.9X3
PC4811
SCD1U25V3KX-GP
PWR_VCCSA_BST
1 PR4807 2PWR_VCCSA_BST_R
1
0R0603-PAD
12
11
10
9
8
7
PC4804
PC4807
VCCSA_PWM
VCCSA_PWM
PGND
PGND
PGND
VIN
VIN
VIN
GND
PC4803
19
20
21
22
23
24
25
PCB Footprint = QFN24-G2D25H40

5V_S5
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
18
17
16
15
14
13
PU4801
1D05V_VTT
PG4801
PWR_VCCSA_VIN
2
VCCSA_LDO
GAP-CLOSE-PWR
PG4802
1
2
VCCSA_LDO
VCCSA_PWM
GAP-CLOSE-PWR
PG4809
1
2
VCCSA_LDO
GAP-CLOSE-PWR
PG4810
1
2
VCCSA_LDO
APL5916 for VCCSA

1112 X02 Modify:
CO-LAY APL5916 related circuit for VCCSA LDO
solution.
GAP-CLOSE-PWR
PG4811
1
2
VCCSA_LDO
20100614 V1.1
for CRB board
GAP-CLOSE-PWR
PG4812
1
2
5V_S5
VCCSA_LDO
3D3V_S0
GAP-CLOSE-PWR
1
0.9V
0.8V
PTC4801
DY
2
2
2
VCCSA_PWR
DY
VCCSA_LDO
GAP-CLOSE-PWR
PG4808
1
2
VCCSA_LDO
DY
VCCSA_SEL
10KR2J-3-GP
PC4826
SCD1U10V2KX-4GP
A
DY
PR4818
10KR2F-2-GP
DY
DY
2
84.2N702.A3F
2nd = 84.DM601.03F
PQ4801
2N7002KDW-GP
VCCSA_LDO
GAP-CLOSE-PWR
PG4807
1
2
PR4813
PQ4801_5
3D3V_S0
GAP-CLOSE-PWR
PG4806
1
2
GAP-CLOSE-PWR
VCCSA_LDO
PQ4801_D
VCCSA_SEL
VCCSA_LDO
Vout=0.8*(1+R1/R2)
PR4816
80K6R2F-GP
SC10U6D3V5MX-3GP
PR4815
80K6R2F-GP
SC10U6D3V5MX-3GP
R2
74.05916.031
VCCSA_LDO
PC4819
ST100U6D3VBM-7GP
VCCSA_LDO
VCCSA_LDO PC4825
PWR_VCCSA_FB
PU4802
APL5916KAI-TRL-GP
VCCSA_LDO
GAP-CLOSE-PWR
PG4805
1
2
PC4818
PR4814
10KR2F-2-GP
2
VCCSA_LDO
GAP-CLOSE-PWR
PG4804
1
2
VCCSA_PWR
0D85V_S0
PG4803
VCCSA_LDO
GND
FB
R1
Iomax=6A
OCP>9A
VCCSA=0.85V
1
SC100P50V2JN-3GP
DY
PC4821
SC1U6D3V2KX-GP
VCCSA_LDO
3
4
SC10U6D3V5MX-3GP
2
VIN
VIN
VOUT
VOUT
SC10U6D3V5MX-3GP
EN
5
9
VCCSA_LDO
VCCSA_LDO
POK
VCCSA_LDO
APL5916_EN 8
2
0R2J-2-GP
VCNTL
42 D85V_PWRGD
1
PR4817
PC4820
VCCSA_LDO
37,45 1.05VTT_PWRGD
PC4822
VCCSA_LDO
PC4824
SC1U6D3V2KX-GP
PR4819
4K7R2J-2-GP
<Core Design>
PQ4801_G
Wistron Corporation
1118 X02 Modify:

Change PTC4801 to 100u(77.21071.07L)
from 150u from power team Brian updated.
1122 X02 Modify:
Updated VCCSA_LDO circuit from Power
team Brian updated.

Title
TPS51461_VCCSA
Size
A2
Date:
Document Number
Rev
QUEEN&NIRVANA 15
Sheet
1
48
of
A00
108
SSID = VIDEO
3D3V_S0
SRN2K2J-1-GP
RN9403
LCD POWER for ROSA

4
3
LVDS CONNECTOR
17 LVDS_DDC_CLK_R
17 LVDS_DDC_DATA_R
DCBATOUT_LCD
LCD1
SSID = VIDEO
1
2
0909 X01 Modify:

Change LCD1 to 20.F1816.030 for 30pin
Re-assign LCD1 pin define base on Roy updated
cable pin define list.
31
NP1
1
0902 X01 Modify:

Add 2nd source 74.09724.09F on
U4901 sync with Annie.
LCDVDD
L_BKLT_CTRL 17
U4901
LCD_TST_C
C4901
SCD1U10V2KX-5GP
DY
1 R4907
C4907
74.05285.07F
2nd = 74.09724.09F
1122 X02 Modify:
EMC Neo suggestion.
RN4901
BLON_OUT_C
LCD_TST_C
1
2
4
3
BLON_OUT 27
LCD_TST 27
C4902
SC1U6D3V2KX-GP
69.10103.041
USB_PN12
2
100KR2J-1-GP
SRN100J-3-GP
1122 X02 Modify:
Change RN4901 to 100ohm 4p from 8p
for improve layout place.
PS-CON30-GP
IN#4
TP4904TPAD14-GP
LCDVDD
20.F1816.030
2nd = 20.F1860.030
IN#5
LVDSA_DATA1 17
LVDSA_DATA1# 17
LVDSA_DATA0 17
LVDSA_DATA0# 17
LVDS_DDC_DATA_R 17
LVDS_DDC_CLK_R 17
1
3D3V_S0
EN
GND
OUT
G5285T11U-GP
C4908
SCD1U50V3KX-GP
EC4907
83.R2003.E81
2ND = 83.00054.Q81
LVDSA_DATA2 17
LVDSA_DATA2# 17
1
2
3
SC4D7U6D3V3KX-GP
D4901
27 LCD_TST_EN
Layout 40 mil
LCDVDD_EN
17 LVDS_VDD_EN
AUD_DMIC_CLK 29
AUD_DMIC_IN0 29
LVDSA_CLK 17
LVDSA_CLK# 17
BLON_OUT_C
3D3V_S0
BAT54CPT-GP
A00 0103 not co-lay
R4905
49K9R2F-L-GP
1 33R2J-2-GP
3D3V_CAMERA_S0
NP2
32
18
R4902 2
USB_CAMERA#
USB_CAMERA
LCD_BRIGHTNESS
SC4D7U6D3V3KX-GP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
USB_CAMERA#
USB_CAMERA
2nd = 69.10084.071
FILTER-4P-6-GP
TPNL
6
DCBATOUT_LCD
1122 X02 Modify:

stuff C4908 0.1uF from
EMC Neo suggestion.
DCBATOUT
ACES-CON4-17-GP-U
F4901
1
2
69.50007.A31 DY
2nd = 69.50007.A41
0R0402-PAD-2-GP
A00 1230
USB_PN0_C
USB_PN0
USB_PP0_C
TR4901
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
TPNL
A00 1229
FILTER-4P-6-GP
69.10103.041
2nd = 69.10084.071
USB_PP0
DY DY DY DY
SC33P50V2JN-3GP
1
2
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
DY DY
EC4911EC4913EC4914EC4915
DY
DY
18
EC4901EC4902EC4910 EC4912
SC33P50V2JN-3GP
DY DY
C4903
SC10U6D3V5KX-1GP
SC5D6P50V2CN-1GP
2
SCD1U10V2KX-5GP
2
DY
EC4903
EC4904 EC4905
SC33P50V2JN-3GP
1 F4902 2
0R0603-PAD
LCD_BRIGHTNESS
LCD_TST_C
LVDSA_CLK#
LVDSA_CLK
3D3V_CAMERA_S0
LVDSA_DATA0
LVDSA_DATA0#
LVDSA_DATA1
LVDSA_DATA1#
LVDSA_DATA2
LVDSA_DATA2#
Camera Power
TPNL2
0916 X01 Modify:

Change TPNL1 to 20.F1621.004 from
Double updated EMN&DXF.
0917 X01 Modify:
Add 2nd source 20.F1561.004;3rd source
20.F1686.004 on TPNL1 from updated
connector list.
0913 X01 Modify:

Reserved EC4910~EC4915 on LVDS signal
for EMC suggestion.
For EMI request

Close to LVDS connector
3D3V_S0
18
5V_S0
R4904
2nd = 20.F1561.004
3rd = 20.F1686.004
SC5D6P50V2CN-1GP
2
2
1
POLYSW -1D1A24V-GP-U
C4905
SCD1U50V3KX-GP
2
1
C4904
SC1KP50V2KX-1GP
1
2
20.F1621.004
SCD1U50V3KX-GP
EC4906
DY
USB_PN0_C
USB_PP0_C
SCD1U50V3KX-GP
EC4908
2
3
4
C4911
SC10U6D3V5KX-1GP
TPNL
TPNL
C4910
SCD1U10V2KX-4GP
TPNL_5V
USB_PP12
1122 X02 Modify:

Change TR4902 CM choke to 69.10103.041
and un-stuff R4908,R4909 from EMC Neo Suggestion.
EC4909
SCD1U50V3KX-GP
TOUCH PANEL
18
CLOSED TO LVDS CONN LCD1
TPNL1
4
TR4902
DN15ATI W histler
1122 X02 Modify:

Swap TR4901 pin4,3 and pin2,1 each other
base on Connie swap report.
Change R4911,R4912 to 0603 from 0402.
Wistron Corporation
Title
LCD Connector
Size
A3
Date:
Document Number
Rev
QUEEN 15
Sheet
A00
49
of
108
(Blanking)
<Variant Name>
Wistron Corporation
Title
CRT Connector
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
50
of
108
HDMI_CLK_R_C_CON
HDMI_DATA1_R_C_CON
HDMI_PLL_GND
0913 X01 Modify:

0R0402-PAD-2-GP
Add R5101~R5108and reserved TR5101~TR5104
on all of HDMI differential pair for EMC suggestion.
0R0402-PAD-2-GP
0831 X01 Modify:

Change HDMI1 part
22.10296.271 base
0910 X01 Modify:
Change HDMI1 part
22.10296.311 base
HDMI CONN
HDMI1
R5106
HDMI_DATA1_R_C 1
0721 Modify:
Change HDMI1 part number to 22.10296.271 from
22.10296.211 base on ME latest EMN and DXF.
A00 1229
22
20
1
R5123
DY 0R2J-2-GP
HDMI_CLK_R_C
HDMI Level Shifter & CONNECTOR
SSID = VIDEO
R5101
1
number to 22.10296.311 from

on ME Double updated.
number to 22.10296.331 from
on ME Double updated.
HDMI_DATA2_R_C_CON
5V_CRT_S0_R
DDC_CLK_HDMI
DDC_DATA_HDMI
A00 1223 HDMI leakage
C5102
SKT-HDMI23-2-GP-U1
HDMI_DATA0_R_C#_CON
R5107
HDMI_DATA2_R_C# 1
0R0402-PAD-2-GP
HDMI_DATA2_R_C#_CON
2nd = 22.10296.311
0R0402-PAD-2-GP
R5112
10KR2J-3-GP
HDMI_IN#
27
HDMI_DATA0#
HDMI_DATA0
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_CLK_R_C#
HDMI_CLK_R_C
HDMI_DATA0#
HDMI_DATA0
C5105
C5106
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA0_R_C#
HDMI_DATA0_R_C
Q5105
2N7002KDW -GP
HDMI_CLK#
HDMI_CLK
85
85
C5103
C5104
HPD_HDMI_CON
85
85
HDMI_CLK#
HDMI_CLK
X02 10.28
R5103
HDMI_DATA0_R_C# 1
22.10296.331
3D3V_S0
R5113
100KR2J-1-GP
DY
HDMI_DATA2_R_C_CON
0R0402-PAD-2-GP
0716 Modify:
Add F5101 1A FUSE for DELL suggesiton.
0720 Modify:
Stuff F5101 FUSE from DELL suggestion.
HDMI_CLK_R_C#_CON
HDMI_DATA2_R_C 1R5108
HDMI_DATA0_R_C#_CON
HDMI_CLK_R_C_CON
HDMI_DATA0_R_C_CON
0R0402-PAD-2-GP
GPU_HDMI_HPD
HDMI_DATA1_R_C#
HDMI_DATA1_R_C
HDMI_DATA2#
HDMI_DATA2
C5108
C5109
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA2_R_C#
HDMI_DATA2_R_C
DY
1
1KR2F-L-GP
1
R5111
3D3V_VGA_S0
RN5107
SRN470J-5-GP
0927
R5114
0R0402-PAD-2-GP
A00
A00 1228
3
4
3D3V_VGA_S0
Optimus
27
RN5101
SRN2K2J-1-GP
Q5104
85 GPU_HDMI_CLK
85
0810
GPU_HDMI_CLK
84.2N702.J31
2ND = 84.2N702.031
2
1
HDMI_IN#
HDMI_HPD_DET
3
4
2
0R0402-PAD
Q5101
2N7002K-2-GP
0923 SWAP
DDC_CLK_HDMI
2
0R2F-N1-GP
0629 Modify:
Utilize Q5104 2N7002 instead of PCA9509 Level
shifter base on Intel DG recommand on HDMI DDC.
RN5116
SRN2K2J-1-GP
1
R5127
0707 Modify:
Add Q5101,R5109,R5127 for HDMI_IN# to KBC.
DY
DY
5V_CRT_S0_R
0714 Modify:
Stuff R5109 20K PH to 3D3V_S0.
2
HDMI_OE#
1
R5125
R5117
10KR2J-3-GP
0R2J-2-GP
2
1
R5109
20KR2J-L2-GP
DY
HDMI_HPD_E
DY
R5115
2
1
0726 For NV
84.03904.L06
DY
HDMI_PLL_GND
1
2
3
4
X02 1110
3D3V_S0
1
2
3
4
0630 SWAP RN5107
Q5102
PMBS3904-1-GP
0629 Modify
2nd = 84.03904.P11
3rd = 84.03904.T11
83,85,86
RN5106
SRN470J-5-GP
0630 SWAP RN5106
R5110
1MR2F-GP
5V_S0
8
7
6
5
8
7
6
5
Close to HDMI Connector
2HDMI_HPD_B
1KR2F-L-GP
PEX_RST#
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
2
1
1
HDMI_DATA2#
HDMI_DATA2
C5110
C5107
85
85
HDMI_DATA1#
HDMI_DATA1
1
2
HDMI_DATA1#
HDMI_DATA1
85
3D3V_S0
R5116
85
85
DDC_DATA_HDMI
HDMI_DATA1_R_C#_CON
HDMI_DATA0_R_C_CON
HDMI_DATA0_R_C 1R5104
R5105
HDMI_DATA1_R_C# 1
HDMI_DATA1_R_C#_CON
2
0R0402-PAD-2-GP
HDMI_CLK_R_C#_CON
R5102
1
2
0R0402-PAD-2-GP
HDMI_CLK_R_C#
2ND = 84.2N702.031
TPAD14-GP AFTP5101
84.2N702.J31
0806
3D3V_VGA_S0
HDMI_DATA2_R_C#_CON
HDMI_DATA1_R_C_CON
Q5103
2N7002K-2-GP
SCD1U10V2KX-5GP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
HPD_HDMI_CON
85 GPU_HDMI_DATA
GPU_HDMI_DATA
2N7002KDW -GP
84.2N702.A3F
DDC_DATA_HDMI
2nd = 84.DM601.03F
Routing Guidelines:
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK.
<Variant Name>
A
Wistron Corporation
Title
HDMI Level Shifter/Connector

Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
51
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
52
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
LVDS_Switch
Rev
QUEEN 15
A00
Sheet
1
53
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
54
of
108
SSID = User.Interface
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
ITP/Fan Connector
Document Number
Rev
QUEEN 15
A00
Sheet
1
55
of
108
SATA HDD Connector
SSID = SATA
HDD1
20100625 V1.2
21
21
0629 Modify:
Move All of 0.01uF cap closed to HDD
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SATA_TXP0
SATA_TXN0
C5616
C5615
21 SATA_RXN0
21 SATA_RXP0
1
1
23
NP1
1
1 C5614
1 C5613
SATA_TXP0_C
SATA_TXN0_C
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
SATA_RXN0_C
SATA_RXP0_C
2
2
8
9
10
11
12
13
14
15
16
17
18
19
1HDD1_20 20
1HDD1_21 21
HDD1_22
1
22
NP2
24
3D3V_S0
SCD1U10V2KX-5GP
2
EC5601
SC180P50V2JN-1GP
3D3V_S0
5V_S0
SC10U10V5ZY-1GP
2
1123 X02 Modify:

stuff EC5601 180pF from RF
fine tune result.
DY
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
C5604 C5601
DY
C5605 C5606
79
FFS_INT2
TPAD14-GP
TPAD14-GP
TPAD14-GP
2
3
4
5
6
7
TP5601
TP5602
TP5603
TYCO-CON22-1-GP-U2
20.F1011.022
2nd = 62.10065.081
0810
0901 Add 2nd.
0906 Add 3rd.
A00 delete 62.10065.121
SATA Zero Power ODD

0629 Modify:
Move R5601 PH 10K to RN5601 PH.
U5601
G547F1P81U-GP
SATA_RX- and SATA_RX+ Trace

Length match within 20 mil
ODD1
8
NP1
S1
4
3
2
1
2nd = 62.10065.D01
3rd = 62.10065.D61
SATA_RXN4
SATA_RXP4
OC#
OUT#6
OUT#7
OUT#8
ODD_PW R_5V
C5610
SC10U6D3V5KX-1GP
74.00547.C79
2ND = 74.02191.079
100 mil
5V_S0
SATA_ODD_DA#_C
ODD_PW R_5V
0R2J-2-GP

,
SATA_ODD_PRSNT# 22
DY 1
R5602
R5605
100KR2J-1-GP
SATA_ODD_DA# 18
1
0629 Modify:
Move R5601 PH 10K to RN5601 PH.
3D3V_S0
20100625 V1.2
RN5601
SATA_ODD_PW RGT
SATA_ODD_DA#
4
3
1
2
SATA_ODD_DA#_C
R5604
DY 10KR2J-3-GP
<Variant Name>
Q5601
2N7002KDW -GP
SRN10KJ-5-GP
0614 Modify:
Change ODD1 connector part number to
22.10300.421 base on ME EMN and DXF.
0707 Modify:
Change ODD1 connector part number to
62.10065.E01 base on latest EMN and DXF.
C5609
SC10U6D3V5KX-1GP
5
6
7
8
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
21
21
62.10065.E01
2SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP
21
21
SKT-SATA7P-6P-40-GP-U
C5607 1
C5608 1
SATA_TXP4
SATA_TXN4
ODD_PWRGT#
P1
P2
P3
P4
P5
P6
NP2
9
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
EN/EN#
IN#3
IN#2
GND
SATA_RX4-_C
SATA_RX4+_C
Mars:
Exchange ODD and ESATA differential pair each other.
SATA_TXP4_C C5612 1
SATA_TXN4_C C5611 1
ODD_PW R_5V
5V_S0
S2
S3
S4
S5
S6
S7
22 SATA_ODD_PW RGT
20100625 V1.2
ODD Connector
0629 Modify:
Move All of 0.01uF cap closed to ODD
84.2N702.A3F
2nd = 84.DM601.03F
Wistron Corporation
SUPPORT ZERO SATA ODD

Title
SATA_ODD_PW RGT
HDD/ODD
SATA_ODD_DA#
0707 Modify:
Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD.
Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
56
of
108
SSID = ESATA
USB CHARGER
D
0803 Modify:
Change U5702 USB CHARGER circuit to
PI5USB14550 from MAX14556.
0629 Modify
U5702
1
2
3
4
5
USB_PP8_R
USB_PN8_R
0806
1122 X02 Modify:

Change TR5701CM choke to 69.10103.041
1123 X02 Modify:
Change R5718,R5719 to 0603 from 0402.
S0
D+
DGND
A+
GND
S1
Y+
YVDD
A-
11
10
9
8
7
6
PI5USB14550AZEE-GP
1
R5721
0R0402-PAD
2
USB_PP8 18
USB_PN8 18
5V_S5
USBCHARGER_CB0
Switch Control Bit:

CB=0 (AM):auto detection charger identification active.
CB=1 (PM):connect DP/DM to TDP/TDM.
Auto
D+/- connects to Y+/-
A00 1229
SCD1U10V2KX-4GP
1
S1
0
1
0
1
ESATA CONN
USB_PN8_C
TR5701
0831
5V_USB1_S3
FILTER-4P-6-GP
USB_PP8_R
27
0809
C5701
S0
0
0
1
1
USB_PN8_R
CB
0809
ESATA1
69.10103.041 USB_PP8_C
2nd = 69.10084.071
21 SATA_TXP5
21 SATA_TXN5
21 SATA_RXP5
21 SATA_RXN5
C5707 1
C5708 1
SCD01U16V2KX-3GP
2
SCD01U16V2KX-3GP
2
SATA_TXP5_C
SATA_TXN5_C
C5705 1
C5702 1
SCD01U16V2KX-3GP
2
SCD01U16V2KX-3GP
2
SATA_RXP5_C
SATA_RXN5_C
VBUS
6
7
A+
A-
10
9
B+
B-
3
2
D+
D-
USB_PP8_C
USB_PN8_C
close to ESATA1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
DT1
DT2
12
13
GND
GND
GND
GND
GND
GND
GND
GND
4
5
8
11
14
15
16
17
R5722
ESATA1_D1 1
1
AFTP5717
AFTE14P-GP
0629 Modify:
SKT-ESATA-USB-11P-6-GP-U
Move All of 0.01uF cap closed to ESATA
0706 Modify:
2nd = 22.10339.261
Change ESATA1 part number to 22.10321.F71
base on latest EMN and DXF.
0713 Modify:
E-SATA USB 2.0 Combo
Add USBDET_CON# on ESATA1 pin15 for
USB temporary detect solution ESATA1 CONN
should be searched for detect type connector.CE/H=-0.16/2.83mm with detect
0719 Modify:
ME Double provide temporary foxconn ESATA conn
22.10290.141 for SSI stage function test.
5V_USB1_S3
USB_PN8_C
USB_PP8_C
0R0402-PAD
2
USBDET_CON# 27
22.10321.W11
AFTP5716
AFTP5715
AFTP5703
function
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
ESATA
Document Number
Rev
QUEEN 15
Sheet
1
A00
57
of
108
SSID = AUDIO
D
6SHDNHU&RQQHFWRU
ACES-CON4-7-GP-U
29
29
29
AUD_SPK_LAUD_SPK_L+
AUD_SPK_R-
R5801 0R0402-PAD-2-GP
1
2
1R5802 0R0402-PAD-2-GP
2
1R5803 0R0402-PAD-2-GP
2
29
AUD_SPK_R+
1R5804 0R0402-PAD-2-GP
2
AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
4
3
2
AUD_SPK_R+_C
2
1
SPK1
EC5804
SC470P50V-2-GP
2
1
EC5803
SC470P50V-2-GP
2
1
EC5802
SC470P50V-2-GP
2
1
EC5801
SC470P50V-2-GP
A00
20.F0772.004
2nd = 20.F1804.004
1110 X02 Modify:
Add 2nd 20.F1804.004 on SPK1 from
1122 X02 Modify:

stuff EC5801~EC5804 470pF from EMC
Neo suggestion.
0913 X01 Modify:

Change SPK1 to 20.F0772.004 from
20.F1647.004 from Double updated.
0914 X01 Modify:
Re-assign SPK1 pin define base on
Roy updated excel file for 20.F0772.004
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
AFTP5801
AFTP5802
AFTP5803
AFTP5804
1
1
1
1
AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C
<Core Design>
Wistron Corporation

Title
Size
A4
Document Number
SPEAKER CONN
Date: Tuesday, January 04, 2011

5
Rev
QUEEN 15
2
A00
Sheet
58
of
1
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
59
of
108
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH

3D3V_S5
SPI_HOLD_0#
2
SCD1U10V2KX-5GP
DY
SC10U6D3V5KX-1GP
R6005
4K7R2J-2-GP
R6004
4K7R2J-2-GP
R6003
4K7R2J-2-GP
C6002
C6001
0701 Modify:
Change RN6001 4.7K to R6003,R6004,R6005
4.7K 0402 for layout routing.
3D3V_S5
3D3V_S5
U6001
21,27 SPI_CS0#_R
21,27 SPI_SO_R
SPI_SO
SPI_W P#
2
33R2J-2-GP
1
2
3
4
CS#
DO
WP#
VSS
VCC
HOLD#
CLK
DI
8
7
6
5
SPI_CLK_R 21,27
SPI_SI_R 21,27
EC6003
2nd = 72.25320.C01
3rd = 72.25P32.C01
0629 Modify:
Change U6001 part number to 72.25320.C01
base on Sourcer provide recommand ROM list.
DY DY
SC4D7P50V2CN-1GP
2
72.25Q32.A01
W 25Q32BVSSIG-1-GP
DY
2
EC6002
SC4D7P50V2CN-1GP
1
R6001
EC6001
SC10P50V2JN-4GP
0917 X01 Modify:

EC6001 change to 10p from 4.7p and
default stuff from Neo suggestion.
X02
X02
SSID = RBATT
3D3V_AUX_S5
B
RTC_AUX_S5
Q6001
A00 1224 Update RTC1
+RTC_VCC
RTC1
3
2
R6002
2
1KR2J-1-GP
1
2
NP1
NP2
CH715FPT-GP
C6003
SC1U6D3V2KX-GP
RTC_PW R
TPAD14-GP
83.R0304.B81
2nd = 83.00040.E81
TP6001
PWR
GND
NP1
NP2
BAT-330DG02PSS0301CE-GP-U
Width=20mils
62.70001.051
1111 X02 Modify:
Add Q6002,R6007 fo FACTORY RTC detect function
TPAD14-GP
TP6002
2nd = 62.70014.001
3rd = 62.70001.061
+RTC_VCC
R6006
2
DY
100R2J-2-GP
2N7002K-2-GP
1
G
0615 Modify:
Change RTC1 connector part number to 62.70001.051
base on ME EMN and DXF.
RTC_PW R
X02 1111
D
R6007
10MR2J-L-GP
RTC_DET# 22
VccRTC is now connected to VccDSW3_3

through the Schottky diode instead of the 3.3V Sus well.
Q6002
84.2N702.J31
2ND = 84.2N702.031
<Variant Name>
Wistron Corporation
Title
Flash/RTC
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
60
of
108
CRT Board and COMBO USB Power

Support 2A
USB_OC#8_9 18
U6101
5V_USB1_S3
AP2182SG-13-GP
74.02182.071
2nd = 74.00546.A7D
3rd = 74.02062.079
1122 X02 Modify:
Change U6101 to dual USB power switch from single
for Layout limitation and placement.
1123 X02 Modify:
Change U6101 1st(74.02182.071);2nd(74.00546.A7D)
;3rd(74.02062.079) from Sourcer Harrison suggestion.
1
C6102
SC1U10V2KX-1GP
at least 80 mil
8
7
6
5
2nd = 77.C1071.20L
at least 80 mil
USB_OC#0_1 18
C6104
SC1U10V2KX-1GP
A00 1221
TC6101
ST100U6D3VAM-3-GP
80.10715.B1L
5V_USB2_S3
FLG1
OUT1
OUT2
FLG2
GND
IN
EN1#
EN2#
27 USB_PW R_EN#
22 USB2_CRT_ON#
1
2
3
4
1
2
C6101
SCD1U10V2KX-5GP
1123 X02 Modify:

Removed C6105,C6103.
SCD1U10V2KX-5GP
C6103
at least 160 mil
5V_S5
TC6102
SC10U6D3V5KX-1GP
SSID = USB
<Core Design>
A
Wistron Corporation
Title
Size
Document Number
USB Power SW
Rev
QUEEN&NIRVANA 15
Date:
5
Sheet
1
61
A00
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
62
of
108
R6303
DY
0R2J-2-GP
Q6301
D
BT_LED
Bluetooth Module conn.
DY
A00 1224 Update BT1
W LAN_W W AN_LED#
BT1
84.2N702.J31
2ND = 84.2N702.031
AFTP6302
AFTP6304
AFTP6305
AFTP6307
1
1
1
BLUETOOTH_DET#
W LAN_ACT
BDC_ON
BLUETOOTH_EN
BT_LED
BLUETOOTH_GPIO3
BLUETOOTH_GPIO5
3
5
7
9
11
13
15
NP1
2
DY
4
6
8
10
12
14
NP2
16
x01 change tolerant 20091118
USB_PP3
USB_PN3
0722 Modify:
Add Q6301 and combine BT_LED to
WLAN_WWAN_LED#.
3D3V_S0
BT_ACT
AFTP6301
2N7002K-2-GP
C6301
SC2D2U6D3V3MX-1-GP
AFTP6306
DY
HRS-CONN14D-GP-U1
20.F0987.014
0721 Modify:
Change C6301 to 78.22510.5BL follow
common parts data base.
2nd = 20.F1500.014
68,82 W LAN_W W AN_LED#
18
USB_PP3
18
USB_PN3
82
BT_ACT
27,82 BLUETOOTH_EN
82 W LAN_ACT
BT_ACT
BLUETOOTH_EN
W LAN_ACT
AFTP6309
AFTP6310
AFTP6308
AFTP6311
AFTP6312
AFTP6313
1
1
1
1
1
1
W LAN_ACT
BLUETOOTH_EN
BT_ACT
3D3V_S0
USB_PP3
USB_PN3
DY
DY
R6302
10KR2J-3-GP
EC6301
SC220P50V2KX-3GP
2
1
DY
R6301
100KR2J-1-GP
0709 Modify:
PM confirmed there is no stand-alone BT module,
so DY BT1 connector, add BT enable signal
and 5V_S5 power option on WLAN connector pin 51.
0712 Modify:
Stuff BT relatek component to verify function.
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Bluetooth
Rev
QUEEN 15
A00
Sheet
1
63
of
108
Finger Printer Connector
FP1
1123 X02 Modify:

Add C6402 0.1uF,C6403 180pF and stuff C6401
47pF from RF fine tune result.
1
2
3
4
5
6
EC6403
SC180P50V2JN-1GP
Biometric_USBPN
Biometric_USBPP
1
2
C
EC6401
SC47P50V2JN-3GP
3D3V_S0
EC6402
SCD1U10V2KX-4GP
2
1
0707 Modify:
Add FP_DET# signal on FP1 pin1.
0715 Modify:
Add FP_DET# signal on FP1 pin1.
0806 Swap pin.
0810 Change to 4 pin.
0827 Change to 6 pin.
8
ACES-CON6-13-GP
20.K0320.006
1 R6403
USB_PN2
Biometric_USBPN
2
0R2J-2-GP
AFTP42
AFTP43
AFTP44
A00 1229
R6404
18
USB_PP2
DN15
DY
DY
DY
1
1
1
3D3V_S0
Biometric_USBPN
Biometric_USBPP
0615 Modify:
Change FP1 connector part number to 20.K0320.004
0630 Modify:
Change FP1 connector part number to 20.K0320.006
0707 Modify:
Reassign Figer print pin define base on EXCEL FILE.
0713 Modify:
Reassign Figer print pin define base on EXCEL FILE.
Removed FP_DET# on FP1.
0917 X01 Modify:

stuff TR6401 and un-stuff R6403,R6404
at X01 stage from EMC Neo suggestion.
2nd = 20.K0382.006
DN15
18
DN15
Biometric_USBPP
2
0R2J-2-GP
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
RESERVED
Document Number
Rev
QUEEN 15
A00
Sheet
1
64
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
RESERVED
Rev
QUEEN 15
A00
Sheet
1
65
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
66
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
67
of
108
3
1
27
21
PW RLED#
SATA_LED#
DYSC220P50V2KX-3GP
3rd = 84.00143.N11
4
3
1A
2 FPOW ER_LED_A
390R2J-1-GP
K2
1
R6808
2 POW ER_SW _LED_B

1KR2J-1-GP
1
R6811
2 POW ER_SW _LED_C

1KR2J-1-GP
83.01221.R70
0706 Modify:
Change HDD_LED part number to
83.01221.R70 base on latest EMN and DXF.
3
SATA_LED_R
PDTA143ET-GP
DY
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
HDD_LED_A
2
390R2J-1-GP
1
R6812
EC6810
SC220P50V2KX-3GP
R1
SATA HDD LED(White)
E
1A
3rd = 84.00143.N11
A00 1223
HDLED1
R2
84.00143.M11
2nd = 84.02143.011
NEED confirm with ME actual

HDD_LED part number.
Q6805
K2
LED-W -27-GP
83.01221.R70
0923 X01 Modify:

Add 2nd source 83.00110.J70 on FPOWERLED1
HDDLED1,WLANLED1 from Sourcer Anya suggestion.
A00 1223
W LED1
2K
2nd = 83.00110.R70
A1
W LAN_LED_A
LED-W -27-GP
1
2
R6815
390R2J-1-GP
83.01221.R70
A00 1229 delete Liteon for package
2nd = 83.00110.R70
Q6807
1
SRN15KJ-3-GP
5V_S5
Q6808
Battery LED1(AMBER_LED)
R2
2
1
AMBER_LED_BAT
R1
BAT_AMBER
2
390R2J-1-GP
1
R6803
EC6809
SC220P50V2KX-3GP

5V_S0
Q6804
PDTA143ET-GP
DY
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
Need change to LOW actived from KBC GPIO
R6813
1
TP_LOCK_LED_R
R1
0706 Modify:
Add PWRBTN2 for DQ15,PWRBTN1 FOR DN15.
A00 20110103
EC6803
SC220P50V2KX-3GP
R2
2
15KR2J-1-GP
2nd = 83.00327.D70
0706 Modify:
Change TP_LOCK_LED part number to
83.19217.J70 base on latest EMN and DXF.
TPLOCK LED
R6807
1
ORANGE
A00 delete 83.01108.070

0923 X01 Modify:
Add 2nd source 83.00327.D70 on
CHARGERLED1from Sourcer Anya suggestion.
DY
84.00143.M11
2nd = 84.02143.011
27 TP_LOCK_LED#
83.01222.X80
3rd = 84.00143.N11
0629 Modify
Q6804_B
WHITE
LED-OW -8-GP
PDTA143ET-GP
EC6807
SC220P50V2KX-3GP
3rd = 84.00143.N11
CHLED1
DY
84.00143.M11
2nd = 84.02143.011
W HITE_LED_BAT#
AMBER_LED_BAT#
0923 X01 Modify:

Add 2nd source 83.00110.J70 on FPOWERLED1
HDDLED1,WLANLED1 from Sourcer Anya suggestion.
BAT_W HITE
2
390R2J-1-GP
1
R6801
4
3
DY
WHITE
RN6801
0706 Modify:
Change WLAN_LED part number to
W LAN_LED_R
A00 1223
W HITE_LED_BAT
PDTA143ET-GP
1
2
27 BATT_W HITE_LED#
27 CHG_AMBER_LED#
R1
0702 Modify:
ORANGE
Battery LED2(WHITE_LED)

5V_S5
R2
PDTA143ET-GP
5V_S0
SATA_LED#_C
2 Q6806_B B
15KR2J-1-GP
2nd = 83.00110.R70
X02 1116
SRN15KJ-3-GP
R6814
1
63,82 W LAN_W W AN_LED#
5V_S0
0629 Modify Q6806
LED-W -27-GP
84.00143.M11
2nd = 84.02143.011
RN6802
1
R6806
EC6801
R1
PDTA143ET-GP
LED_PW R
1
2
WLAN_LED
0706 Modify:
WLAN__LED# rename to WLAN_WWAN_LED#.
R1
A00 1223
FPLED1
R2
PW RLED#_C
5V_S5
Q6801
R2
0706 Modify:
Change FPOWER_LED part number to

FPOWER_LED part number.
SC220P50V2KX-3GP
EC6811
FRONT POWER LED
A00 20110103
TPLED2
2TP_LOCK_LED_A
390R2J-1-GP
DN15
A00 1223
LED-Y-57-GP
0923 X01 Modify:

Add 2nd source 83.00190.Z70 on TPLOCKLED1
TPLOCKLED2 from Sourcer Anya suggestion.
83.01921.P70
PW RBT2
2nd = 83.00190.S7A
TPLED1
0706 Modify:
Change TP_LOCK_LED1 part number to
83.19217.J70 base on latest EMN and DXF.
DQ15
A00 20110103
KBC_PW RBTN#_C
POW ER_SW _LED_C
POW ER_SW _LED_B
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A
2
3
4
DN15
6
ACES-CON4-10-GP-U
27 KBC_PW RBTN#
1
R6802
PW RBT1
2
100R2J-2-GP
A00 1223
20.K0320.004
2nd = 20.K0382.004
5
1
KBC_PW RBTN#_C
POW ER_SW _LED_C
POW ER_SW _LED_B
2
3
4
0715 Modify:
Removed PWR_BTN_LED# control circuit
base on Dell feedback.
DQ15
<Core Design>
A
Wistron Corporation
6
ACES-CON4-10-GP-U
20.K0320.004
KBC_PW RBTN#_C
1
POW ER_SW _LED_C 1
POW ER_SW _LED_B 1
AFTP6801
AFTP6802
AFTP6803

Title
LED Bard/Power Button
2nd = 20.K0382.004
Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
1
68
of
108
SSID = KBC
SSID = Touch.Pad
0715 Modify:
Add R6908,R6909 for TPAD1 co-lay power option.
Internal KeyBoard Connector

D
0630 Modify:
Change KB1 part number to 20.K0565.030
base on ME updated EMN and DXF.
KROW [0..7]
27
KCOL[0..16]
27
0624 Modify:
Removed TP LOCKED CONTROL combin
with KEYBOARD Function KEY.
TP_VDD
5V_S0
R6908
1
AFTP45
AFTP46
AFTP47
AFTP48
AFTP49
AFTP50
AFTP51
AFTP52
AFTP53
AFTP54
AFTP55
AFTP56
AFTP57
AFTP58
AFTP59
AFTP60
AFTP61
AFTP62
AFTP63
AFTP64
AFTP65
AFTP66
AFTP68
AFTP67
AFTP69
AFTP70
TouchPad Connector
TP_VDD
1
2
TPAD1
4
3
2
TPCLK
TPDATA
SC33P50V2JN-3GP
CAP_LED_R
1
C6903
SC33P50V2JN-3GPAFTP71
20.K0320.004
2nd = 20.K0382.004
0927
CAP LED CONTROL

R2
R1
Q6902_B
B
AFTP73
AFTP74
AFTP75
5V_S5
Q6902
ACES-CON4-10-GP-U
CAP_LED_R
R6905
1
1
1
TP_VDD
TPCLK
TPDATA
0707 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
0713 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
X02 1116
CAP_LED_R
CAP_LED_R
2
1KR2J-1-GP
CAP_LED_Q
1
R6906
15KR2J-1-GP
PDTA143ET-GP
0915 X01 Modify:

un-stuff R6907 and stuff R6905,Q6902,R6906
for 5V drive CAP LED.
0R2J-2-GP
C6902 DY DY
High Active from KBC GPIO.
CAP_LED
C6901
SCD1U10V2KX-5GP
4
3
27
27
JAE-CON30-7-GP
27
3D3V_S0
R6909
1
2
RN6901
SRN10KJ-5-GP
AFTP72
2nd = 20.K0592.030
0R2J-2-GP
0721 Modify:
SWAP RN6901
20.K0565.030
DY
TP_VDD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
KB_DET# 21
KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
0630 Modify:
Change TPAD1 part number to 20.K0320.006
base on ME updated EMN&DXF.
0712 Modify:
Change TPAD1 part number to 20.K0320.004
from 20.K0320.006.
0713 Modify:
Change TPAD1 power source to 3D3V_S0 from
5V_S0 base on DELL latest spec A02.
1
31
1
KB1
84.00143.M11
2nd = 84.02143.011
1
2
3rd = 84.00143.N11
R6907 DY100R2J-2-GP
CAP_LED:(Default HIGH actived)

Connect to KB driving internal LED directly.(MAX 25mA)
KB Backlight Connector
5V_S0
+5V_KB_BL
F6901
DY
MAX 260mA
1
FUSE-D5A6V-2-GP
2 R6902
0R2J-2-GP
DN15
C6905
SCD1U10V2KX-5GP
KBLIT1
DN15
5
1
R6904
KB_LED_DET_C
100KR2J-1-GP
DY
2
DN15
C6906
KB_BL_CTRL#
51KR2J-1-GP
R6903
DN15
SCD1U10V2KX-5GP
18 KB_LED_BL_DET
0624 Modify:
Change KB Backlight control all of related
circuit component column to VOSTRO from DY.
0708 Modify:
R6904 change to 51K 0402 from 100ohm for
KB_LED_BL_DET to PCH GPIO.
updated KBLIT1 pin define base on KB DATA SHEET.
2
3
4
6
DN15
ACES-CON4-34-GP
20.K0589.004
1
2nd = 20.K0613.004
AFTP82
0901 X01 Modify:

Change KBLIT1 to 20.K0320.004 from
20.K0218.004 base on ME updated X01 DXF&EMN.
Re-assign KBLIT1 pin define sync with DQ15_NV.
0914 X01 Modify:
Add 2nd source 20.K0382.004 on KBLIT1
base on updated connector list.
0923 X01 Modify:
Change KBLIT1 part number to 20.K0589.004
and re-assign pin define base on Roy updated.
Q6901
P8503BMG-GP
KB_BL_CTRL
DN15
R6901
100KR2J-1-GP
DN15
27
84.P8503.031
2nd = 84.03404.C31
+5V_KB_BL
KB_LED_DET_C
KB_BL_CTRL#
1
1
1
<Core Design>
Wistron Corporation
Title
AFTP76
AFTP77
AFTP78
Key Board/Touch Pad

Size
A3
Date:
Document Number
Rev
A00
QUEEN 15
Sheet
1
69
of
108
12
HALL1
NP1
0729
13
11
10
9
8
7
6
2
3
4
5
16
14
LID_CLOSE# 27
3D3V_S5
0804 swap
15
AFTP83 AFTE14P-GP
1 3D3V_S5
1 LID_CLOSE#
C
AFTP84 AFTE14P-GP
NP2
AFTP85
TCN-CONN10C-GP
1
AFTE14P-GP
20.F1655.010
2nd = 20.F0962.010
1110 X02 Modify:
Add 2nd 20.F0962.010 on HALL1 from
<Core Design>
A
Wistron Corporation
Title
Hall Sensor
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
70
of
108
3D3V_S0
DB1
11
1
2
3
4
5
6
7
8
9
10
12
21,27 LPC_AD0
21,27 LPC_AD1
21,27 LPC_AD2
21,27 LPC_AD3
21,27 LPC_FRAME#
5,18,27,75,82,83 PLT_RST#
18
CLK_PCI_LPC
DY
PAD-10P-177042-GP
ZZ.00PAD.Y41
A00 1229 DB1 change to ZZ.00PAD.Y41(solder kmask type)
and keep un-stuffat X-Build stage
<Core Design>
A
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Dubug connector
QUEEN 15
Rev
A00
Sheet
1
71
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
72
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
73
of
108
SSID = SDIO
C7405
1
2
DY
SC10U6D3V5MX-3GP
C7404
SC2D2U6D3V3MX-1-GP
1
2
C7403
SCD01U16V2KX-3GP
DY
2
DY
Close to CARD1
C7402
SCD1U10V2KX-5GP
C7401
SCD1U10V2KX-5GP
3D3V_CARD_S0
SD/XD/MS/MMC+ Card Reader

0906 X01 Modify:
Change CARD1 to 20.I0129.001 from 62.10051.931
from ME double updated latest DXF&EMN on X01.
3D3V_CARD_S0
CARD1
P13
SD_VCC
P22
MS_VCC
18
XD_VCC
XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP_IN
32
32
32
32
SP4
SP3
SP13
SP12
P4
P3
P25
P23
SD_DAT0
SD_DAT1
SD_DAT2
SD_DATA3
32
32
32
32
SP8
SP6
SP1
SP10
P10
P1
P2
P19
SD_CLK
SD_CD
SD_WP
SD_CMD
32
32
32
SP14
SP2
SP1
P9
P16
P20
MS_BS
MS_INS
MS_SCLK
32
32
32
32
SP9
SP12
SP8
SP5
P12
P11
P14
P18
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
32
32
32
32
SP11
SP9
SP7
SP5
P21
P17
P8
P5
MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
1
2
3
4
5
6
7
8
XD_CD#
SP1
SP2
SP3
SP4
SP5
SP6
SP7
32
32
32
32
32
32
32
32
10
11
12
13
14
15
16
17
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
32
32
32
32
32
32
32
32
SD_WP_COM/SDIO_GND
SD_CD_COM/SDIO_GND
SD_GND
SD_GND
P26
P27
P7
P15
MS_GND
MS_GND
P6
P24
XD_GND
XD_GND
9
19
NP1
NP2
NP1
NP2
CARD-PUSH-46P-1-GP-U
20.I0129.001
1119 X02 Modify:

Add 2nd 20.I0135.001 on HALL1 from
2nd = 20.I0135.001
For EMI Reserved
EC7417
SC220P50V2KX-3GP
DY
2
DY
2
DY
EC7416
SC220P50V2KX-3GP
EC7415
SC220P50V2KX-3GP
DY
2
DY
EC7414
SC220P50V2KX-3GP
EC7413
SC220P50V2KX-3GP
DY
2
DY
EC7412
SC220P50V2KX-3GP
EC7411
SC220P50V2KX-3GP
DY
2
DY
EC7410
SC220P50V2KX-3GP
EC7409
SC220P50V2KX-3GP
DY
2
DY
EC7408
SC220P50V2KX-3GP
EC7407
SC220P50V2KX-3GP
DY
2
DY
EC7406
SC220P50V2KX-3GP
EC7405
SC220P50V2KX-3GP
DY
2
EC7404
SC220P50V2KX-3GP
DY
2
DY
EC7403
SC220P50V2KX-3GP
EC7402
SC220P50V2KX-3GP
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
XD_CD#
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
SD/XD/MS/MMC Card CONN
Document Number
QUEEN 15
Sheet
1
Rev
A00
74
of
108
0824 X01 Modify:

Due to our NEW1 change to Express card to
bottom side so re-assign NEW1 pin define same
as DQ15-NV.
0906 X01 Modify:
Add 2nd source 20.K0382.026 on NEW1 base on
updated connector list.
1D5V_S0_CARD Max. 650mA, Average 500mA.

3D3V_S0_CARD Max. 1300mA, Average 1000mA
3D3V_S5_CARDAUX Max. 275mA
SB-25
NEW 1
27
20
PCIE_TXP8
20
PCIE_TXN8
20
20
1122 X02 Modify:
Change R7501,R7502 to 0603 from 0402.
PCIE_RXP8
PCIE_RXN8
20 CLK_PCIE_NEW
20 CLK_PCIE_NEW #
3D3V_S0
18
USB_PP13
3D3V_S5
27,82 PCIE_W AKE#
1D5V_S0
USB_PP13_R
69.10103.041
2nd = 69.10084.071
FILTER-4P-6-GP
DN15
A00 1229
20
SMB_DATA
20
SMB_CLK
19,27,46 PM_SLP_S4#
19,27,36,37,47 PM_SLP_S3#
5,18,27,71,82,83 PLT_RST#
TR7501
1
2
0R2J-2-GPPCIE_TXP8_CON
2
PCIE_TXN8_CON
2
3
0R2J-2-GP
4
PCIE_RXP8_CON
2
5
20R2J-2-GPPCIE_RXN8_CON 6
0R2J-2-GP
7
CLK_PCIE_NEW _C 8
2
20R2J-2-GPCLK_PCIE_NEW #_C 9
0R2J-2-GP
10
2 CLK_PCIE_NEW _REQ#_CON
11
0R2J-2-GP
12
13
14
15
1 DN15 2 PCIE_W AKE#_CON
16
R7510
0R2J-2-GP
17
18
SMB_DATA
19
SMB_CLK
20
PM_SLP_S4#
21
PM_SLP_S3#
22
PLT_RST#
23
USB_PP13_R
24
USB_PN13_R
25
26
1 DN15
R7505
1 DN15
R7506
1 DN15
R7508
1 DN15
R7507
1 DN15
R7503
1 DN15
R7504
1 DN15
R7509
0913 X01 Modify:

Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R.
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C
DN15
28
ACES-CON26-6GP-U
18
USB_PN13_R
USB_PN13
20.K0320.026
2nd = 20.K0382.026
For EMI
EC7505
SC4D7P50V2CN-1GP
EC7508
DY
DY
SC4D7P50V2CN-1GP
EC7504
SC4D7P50V2CN-1GP
2
EC7507
2
EC7503
DY
DY
DY
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1
SC4D7P50V2CN-1GP
EC7506
EC7502
EC7501
DY
DY
SC4D7P50V2CN-1GP
CLK_PCIE_NEW _REQ#
PCIE_W AKE#
PCIE_TXP8_CON
PCIE_TXN8_CON
PCIE_RXP8
PCIE_RXN8
CLK_PCIE_NEW #_C
CLK_PCIE_NEW _C
3D3V_S5
3D3V_S0
1D5V_S0
USB_PN13_R
USB_PP13_R
CLK_PCIE_NEW _REQ#_CON
SMB_CLK
SMB_DATA
PM_SLP_S3#
PM_SLP_S4#
PLT_RST#
CLK_PCIE_NEW #_C
CLK_PCIE_NEW_C
PCIE_TXN8_CON
PCIE_TXP8_CON
PCIE_RXN8_CON
PCIE_RXP8_CON
PCIE_W AKE#_CON
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AFTP107
AFTP108
AFTP109
AFTP110
AFTP111
AFTP112
AFTP113
AFTP114
AFTP115
AFTP116
AFTP117
AFTP118
AFTP119
AFTP120
AFTP121
AFTP122
AFTP123
AFTP124
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
SC4D7P50V2CN-1GP
0913 X01 Modify:

Add R7503,R7504 and reserved EC7501,EC7502 on
CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
0921 X01 Modify:
Add R7505~R7508 0ohm and reserved EC7503~EC7506
on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508
on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
<Core Design>
A
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Express Card
Rev
QUEEN 15
A00
Sheet
1
75
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
76
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
77
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
78
of
108
Free Fall Sensor
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
C7902
SCD1U10V2KX-4GP
DY
2
DY
3D3V_S0
2
INT2
12
SDO
HDD_FALL_INT1
DY
2
4
5
10
3D3V_S0
DE351DLTR8-GP
5V_S0
Q7901
2N7002KDW -GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
1
GND
GND
GND
GND
DYR7904
100KR2J-1-GP
DY
74.00351.0B3
0701 Modify:
Change G-SENSOR U7901 back to DE351DLTR8.
0705 Modify:
Change DUMMY column to:MAIN source->ADI solution.
second source->ST solution.
R7906
10KR2J-3-GP
RESERVED#3
RESERVED#11
FALL_INT2
CS
3
11
R7903
100KR2J-1-GP
DY
09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b
18
INT1
SDA/SDI/SDO
DY
SCL/SPC
13
3D3V_S0
HDD_FALL_INT1
PCH_SMBDATA
R7901
2 HDD_FALL_SDO
100KR2J-1-GP
3D3V_S0
14
PCH_SMBCLK
R7902
100KR2J-1-GP
DY
VDD_IO
VDD
U7901
14,15,20,82 PCH_SMBCLK
14,15,20,82 PCH_SMBDATA
C7901
SC10U6D3V5MX-3GP
3D3V_S0
0802
FFS_INT2_R
0706 Modify:
R2220 and R7904 double PH.
FFS_INT2 56
R7905
2
0R2J-2-GP
DY
FFS_INT2_R 18
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Free Fall Sensor
QUEEN 15
Rev
A00
Sheet
1
79
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
80
of
108
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
QUEEN 15
A00
Sheet
1
81
of
108
IO Board CONN 80 pin
:/$13&,(
:/$13&,(
20
20
PCIE_TXN2
PCIE_TXP2
20
20
PCIE_RXP2
PCIE_RXN2
20
20
PCIE_RXN4
PCIE_RXP4
20
20
86%3&,(
86%3&,(
PCIE_RXN3
PCIE_RXP3
PCIE_TXP4
PCIE_TXN4
20
20
PCIE_RXN5
PCIE_RXP5
20
20
PCIE_TXP5
PCIE_TXN5
A00 1229
0916 X01 Modify:

Keep original X00 IOBD1 pin define.
0917 X01 Modify:
Change IOBD1 part number to 20.F1849.080
1D5V_S0
base on Double updated latest DXF&EMN.
5V_S5
0920 X01 Modify:
Re-assign IOBD1 pin define due to updated
connector pin define is different as before.
Add R8206,R8207 to isolated AGND and DGND.
CLK_PCIE_W LAN_REQ# 20
E51_TXD 27
E51_RXD 27
W IFI_RF_EN 27
W LAN_W W AN_LED# 63,68
PM_LAN_ENABLE 27
PLT_RST# 5,18,27,71,75,83
1122 X02 Modify:
PCIE_W AKE# 27,75
stuff EC8201,EC8202 0.1u(closed H3)
BLUETOOTH_EN 27,63 between GND and GND from EMC Neo suggestion.
BT_ACT 63
stuff EC8206 between 3D3V_S5 and GND from
1R8206
2
EMC Neo suggestion.
0R0603-PAD-2-GP
AUD_HP1_JD# 29
EXT_MIC_JD# 29
MIC_IN_L 29
3D3V_S5
MIC_IN_R 29
AUD_HP1_JACK_L2 29
AUD_HP1_JACK_R2
29
1R8207
2
0R0603-PAD-2-GP
3D3V_S0
A00
A00
IOBD1
X02 1122
AUD_AGND
0913 X01 Modify:
Change R8201~R8203 to 470ohm from 100ohm.
Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for
PWM OD mode.
ACES-CONN80D-1-GP
20.F1849.080
2nd = 20.F1908.080
86%3&,(
86%3&,(
CRT Board Connector

CRTBD1
5V_CRT_S0_R
3D3V_S0
CRT_HSYNC_CON
CRT_VSYNC_CON
AD+
27
27
PSID_EC
RCID
USB_PN1
USB_PP1
41
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
46
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
44
ACES-CONN40D-GP
20.F1121.040
2nd = 20.F0085.040
3rd = 20.F1932.040
0625 Modify:
Change CRTBD1 part number to 20.F0957.030
from 20.F1521.030 base on EMN updated part number.
0720 Modify:
Change CRTBD1 connector to 20.F1121.040 from
30pin base on ME Double provide final solution.
0721 Modify:
re-assign CRTBD1 pin define to follow Joseph
release PIN define.
1
1
1
1
1
1
1
43
2
45
NP2
18
18
AFTP8201
AFTP8202
AFTP8203
AFTP8204
AFTP8205
AFTP8206
AFTP8207
MEDIA1
42
NP1
0906 X01 Modify:

Add 2nd source 20.F0085.040 on CRTBD1
base on updated connector list.
0915 X01 Modify:
Re-assign CRTBD1 pin define base on
EMC suggestion.
22
CRT_GREEN
CRT_RED
5V_S5
MEDIA_LED1#
1
MEDIA_LED2#R8204
1
MEDIA_LED3#R8205
1
R8208
2
210KR2J-3-GP
210KR2J-3-GP
10KR2J-3-GP
DY
DY
DY
MEDIA1_1
MEDIA1_2
MEDIA1_3
1119 X02 Modify:
5V_S5
Reserved EC8203~EC8205 470p on all of
INSTANT_ON#
DATA_RECOVERY# MEDIA_LED# signal from EMC Neo suggestion.
MEDIA_BTN3#
MEDIA_LED1#
1
2
MEDIA_LED2#EC82031
2SC470P50V-2-GP
MEDIA_LED3#EC82041
2SC470P50V-2-GP
EC8205
SC470P50V-2-GP
5V_S5
CRT_BLUE
A00
MEDIA1_1 1 R8201 2
MEDIA1_2 1KR2J-1-GP
1
MEDIA1_3
2
2
3
4
5
6
7
8
SCD1U50V3KX-GP
EC8206
::$1:/$160%86
SCD1U50V3KX-GP
EC8202
3D3V_S5
18
USB30_SMI#
63
W LAN_ACT
20 USB3_PEGB_CLKREQ#
14,15,20,79 PCH_SMBDATA
14,15,20,79 PCH_SMBCLK
27 USB3_PW R_ON
3G_EN
:/$1&/.
86%&/.
/$13&,(
20
20
PCIE_TXP3
PCIE_TXN3
::$1&/.
/$13&,(
20
20
CLK_PCIE_W LAN 20
CLK_PCIE_W LAN# 20
CLK_PCIE_USB3 20
CLK_PCIE_USB3# 20
/$1&/.
::$13&,(
X02 1116
::$13&,(
CLK_PCIE_LAN 20
CLK_PCIE_LAN# 20
CLK_PCIE_W W AN 20
CLK_PCIE_W W AN# 20
::$186%
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
NP2
81
SCD1U50V3KX-GP
EC8201
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
18
USB_PN11
20 PCIE_CLK_LAN_REQ#
18 USB_PP4
18 USB_PN4
20 CLK_PCIE_W W AN_REQ#
:/$186%
18
USB_PP11
82
NP1
1
1112 X02 Modify:

Dell required us to disable PCIE port of WWAN slot
,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1
at ST stage.
High active
MEDIA_LED1# 27
MEDIA_LED2# 27
MEDIA_LED3# 27
INSTANT_ON# 27
DATA_RECOVERY#
MEDIA_BTN3# 27
4
3
RN8201
SRN1KJ-7-GP
20101220
27
10
AD+
ACES-CON8-19-GP
CRT_DDC_CLK
CRT_DDC_DATA
20.K0320.008
2nd = 20.K0465.008
5V_S5
3D3V_S5
5V_USB2_S3
1110 X02 Modify:

Add 2nd 20.K0465.008 on MEDIA1 from
1112 X02 Modify:
change Media resistor from 430 ohm to 1K on
both DQ/DN15(R8201, R8202, R8203)
for Media button LED light spot issue
A00 1224
5V_CRT_S0_R R8211
1123 X02 Modify:
Removed R8211,R8212 and connect
1
2
DY
5V_USB2_S3 to CRTBD1 pin 37 directly.
0R3J-0-U-GP
1120 X02 Modify:
Reserved R8211,R8212 0ohm 0805 on CRTBD1
pin37,39 to separate EATA and CRT USB power in
ST build.
5V_CRT_S0
F8201
FUSE-1D1A6V-4GP-U
A00 0103 add 3rd T-conn(20.F1932.040) at XBuild batch run
5V_S0
D8201
69.50007.691
2nd = 69.50007.771
0814
CH551H-30PT-GP
2ND = 83.R5003.H8H
83.R5003.C8F RN8205
0810
17 CRT_DDC_DATA
17 CRT_DDC_CLK
17
17
17
CRT_DDC_DATA
CRT_DDC_CLK
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_RED
CRT_GREEN
CRT_BLUE
17 CRT_VSYNC
17 CRT_HSYNC
<Core Design>
1
2
SRN22-3-GP
1122 X02 Modify:
Swap RN8205 pin4,3 and pin2,1 each other
base on Connie swap report.
Wistron Corporation
4 CRT_VSYNC_CON
3 CRT_HSYNC_CON
A00 1224
1120 X02 Modify:

Add RN8205
base on HSYNC&VSYNC report.

Title
Size
A3
Date:
3rd = 83.5R003.08F
IO Board Connector
Document Number
Rev
QUEEN 15
A00
Sheet
1
82
of
108
Optimus
Optiums
Optumus
PEG_RXP13Optimus
PEG_RXN13Optimus
1
1
2 C8303 SCD1U10V2KX-5GP PEG_C_RXP15AN32

2 C8301 SCD1U10V2KX-5GP PEG_C_RXN15AP32
PEG_TXP14
PEG_TXN14
PEG_RXP15Optimus
PEG_RXN15Optimus
2
1
1
1
2
2
1
2
1
2
HDCP_CLK
G6
HDCP_SDA
4
3
F6
RN8301
SRN4K7J-8-GP
GND
GND
OPTIMUS
PEX_RX14
PEX_RX14#
NC#AG20
PEX_TERMP
A4
C5
AK14
K9
N12P-GE-A1-GP
Optimus
STRAPPING MODE TABLE

MULTI-LEVEL
BINARY PRODUCTION
BINARY BRINGUP
MULTI_STRAP_REF1_GND
40.2K TO GND
40.2K TO GND
NC
40.2K TO GND
NC
NC
GPU_ROM_SI
for Hynix VRAM
(128Mx16) (0x6)
RAM_CFG[0]=0
RAM_CFG[1]=1
RAM_CFG[2]=1
RAM_CFG[3]=0
for Samsung VRAM

(128Mx16) (0x7)
RAM_CFG[0]=1
RAM_CFG[1]=1
RAM_CFG[2]=1
RAM_CFG[3]=0
1V_VGA_S0
STRAP1
GPU_ROM_SO
3GIO_PADCFG[0]=0
3GIO_PADCFG[1]=1
3GIO_PADCFG[2]=1
3GIO_PADCFG[3]=0
EBMS160808A121-GP
C8358
for Samsung VRAM

(64Mx16) (0x3)
RAM_CFG[0]=1
RAM_CFG[1]=1
RAM_CFG[2]=0
RAM_CFG[3]=0
for Hynix VRAM

(64Mx16) (0x2)
RAM_CFG[0]=0
RAM_CFG[1]=1
RAM_CFG[2]=0
RAM_CFG[3]=0
Need check panel resolution

1366x768
68.00375.101
2ND = 68.00119.101
VGA_DEVICE
SMB_ALT_ADDR
FB_0_BAR_SIZE
XCLK_417
Notebook configure.
=1
=0
=0
=0
Optimus
STRAP2
PCI_DEVID[0]=0
PCI_DEVID[1]=0
PCI_DEVID[2]=1
PCI_DEVID[3]=0
[0]
[1]
[2]
[3]
N12P-GE
1
0
1
0
N12P-GV1
1
1
1
0
N12M-GE
TBD
N11P-GE
1
0
0
0
GPU_ROM_SCLK
N11P-GS
0
0
0
0
PEX_PLL_EN_TERM
SLOT_CLK_CFG
SUB_VENDOR
PCI_DEVID[4]
=0
=1
=0
=1
[4]
N12P-GE
1
N12P-GV1
1
N12M-GE
TBD
N11P-GE
1
N11P-GS
1
AG20
PEX_RX15
PEX_RX15#
STRAP0
STRAP1
STRAP2
AG21 PEX_TERMP
PEX_TX15
PEX_TX15#
Logical Strap Bit Mapping

Resistor Pull-up Pull-down
5Kohms
1000
0000
10Kohms
1001
0001
15Kohms
1010
0010
20Kohms
1011
0011
25Kohms
1100
0100
30Kohms
1101
0101
35Kohms
1110
0110
45Kohms
1111
0111
R8301
2K49R2F-GP
TESTMODE
OPTIMUS
AP35 PEX_TESTMODE
Optimus
R8313
10KR2J-3-GP
GPU_ROM_SI
GPU_ROM_SO
GPU_ROM_SCLK
0901
3D3V_VGA_S0
DY
2 R8309
10KR2F-2-GP
DIS_DID_L
DY
1
Optimus
2 R8326
34K8R2F-1-GP
Optimus
2 R8307
45K3R2F-L-GP
DY
1
1
2 R8305
30KR2F-GP
3D3V_VGA_S0
DIS_DID_H
2 R8308
34K8R2F-1-GP
2 R8311
15KR2F-GP
2 R8316
10KR2F-2-GP
DY
2 R8317
10KR2F-2-GP
Optimus
2 R8327
2KR2J-1-GP
DIS_SAM_HYX 15KR2F-GP
DY
2 R8325
2KR2J-1-GP
2 R8310
15KR2F-GP
DY
2 R8312
NV_PEG_CLKREQ#
0R2J-2-GP
<Variant Name>
PEG_CLKREQ#
20
0xDF5
84.2N702.J31
2ND = 84.2N702.031
STRAP 2: DIS_DID_L
N12P-GE
PH = NC, PL = 30K(64.30025.6DL)
N12P-GV1
PH = NC, PL = 15K(64.15025.6DL)
N12M-GE
PH = TBD, PL = TBD
N11P-GE-A1 PH = TBD, PL = 10K
N11P-GS-A1 PH= NC, PL = 4.99K
GPU_ROM_SCLK: DIS_DID_H
N12P-GE
PH = 15K(64.15025.6DL),
N12P-GV1
PH = 15K(64.15025.6DL),
N12M-GE
PH = TBD, PL = TBD
N11P-GE-A1 PH = 15K(64.15025.6DL),
N11P-GS-A1 PH = 15K(64.15025.6DL),
PL = NC
PL = NC
GPU_ROM_SI
Hynix
64x16 = PL 15K
Samsung 64x16 = PL 20K
Wistron Corporation
Title
PL = NC
PL = NC
0728
N12P(1/6)_PEG
Size
A2
Date:
Optimus
1
2
HDCP_CLK
HDCP_SDA
A5
BUFRST#
NC#C5
1009
DY
STRAP0
STRAP1
STRAP2
W5
W7
V7
CEC
PIN NAME
DY
G
2
1
2
Optimus
DGPU_PWROK
GPU_ROM_SI
GPU_ROM_SO
GPU_ROM_SCLK
PEX_TX14
PEX_TX14#
22,92,93
N9
M9
R8304
40K2R2F-GP
Optimus
92
Near BALLS Near BGA
N12P-GE-A1-GP
1 R8322
2
1
1
2
1
2
C8357S
Optimus
PEX_RX13
PEX_RX13#
GPU_ROM_CS#
D3
C4
D4
Optimus
PEX_TX13
PEX_TX13#
AR34
AP34
PQ8309
2N7002K-2-GP
1
2
1
2
2
C8340S
PEX_RX12
PEX_RX12#
AR31
AR32
PEG_TXP15
PEG_TXN15
AM31
2 C8304 SCD1U10V2KX-5GP PEG_C_RXP14
AM32
2 C8302 SCD1U10V2KX-5GP PEG_C_RXN14
R8303
40K2R2F-GP
C8359
L8303
PEX_PLLVDD
AG14
PEX_TX12
PEX_TX12#
AN31
AP31
1
1
AB5
STRAP0
Optimus
120mA
PEX_PLLVDD
PEX_RX11
PEX_RX11#
AP29
AN29
PEG_TXP13
PEG_TXN13
PEG_RXP14Optimus
PEG_RXN14Optimus
1
1
AM29
AM30
I2CH_SCL
I2CH_SDA
USER[0]=1
USER[1]=1
USER[2]=1
USER[3]=1
SC4D7U6D3V3KX-GP
1
1
PEG_TXP12
PEG_TXN12
C8352S
GND_SENSE
PEX_RX10
PEX_RX10#
PEX_TX11
PEX_TX11#
C3
Optimus
VGA_SENSE 92
C1U6D3V2KX-GP
2 C8308 SCD1U10V2KX-5GP PEG_C_RXP12AK29

2 C8306 SCD1U10V2KX-5GP PEG_C_RXN12AL29
STRAP0
STRAP1
STRAP2
STRAP_3V3
STRAP_MIOB
PEX_TX10
PEX_TX10#
AR28
AR29
1
1
D35
P7
AD20
AD19
R7
E35
CD1U10V2KX-5GP
PEG_RXP12Optimus
PEG_RXN12Optimus
2
PEX_RX9
PEX_RX9#
AN28
AP28
PEG_TXP11
PEG_TXN11
C8351S
2 C8311 SCD1U10V2KX-5GP PEG_C_RXP11AL28

2 C8309 SCD1U10V2KX-5GP PEG_C_RXN11AK28
C8344S
DY
PEG_RXP11Optimus
PEG_RXN11Optimus
VDD_SENSE#D35
VDD_SENSE#P7
VDD_SENSE#AD20
GND_SENSE#AD19
GND_SENSE#R7
GND_SENSE#E35
R8324
3D3V_VGA_S0
3D3V_VGA_S0
Optimus
C8341S
1
1
PEG_TXP10
PEG_TXN10
Optimus
J10
J11
J12
J13
J9
AM27
AM28
ROM_CS#
ROM_SI
ROM_SO
ROM_SCLK
3D3V_VGA_S0
C1U6D3V2KX-GP
AP26
AN26
1
1
NC#J26
NC#J25
PEX_RX8
PEX_RX8#
PEG_RXP10Optimus
PEG_RXN10Optimus
13 OF 16
MISC2
J26
J25
OptimusOptimus
PEX_TX9
PEX_TX9#
3D3V_VGA_S0
XTALOUT_R
VGA2M
SC4D7U6D3V3KX-GP
PEG_TXP9
PEG_TXN9
Optimus
SC15P50V2JN-2-GP
NC#A5
PEX_TX8
PEX_TX8#
2 C8314 SCD1U10V2KX-5GP PEG_C_RXP9 AL26

2 C8313 SCD1U10V2KX-5GP PEG_C_RXN9AM26
1MR2F-GP
R8320
Optimus
C8364
Near BALLS
PEX_RX7
PEX_RX7#
AR25
AR26
1
1
VDD33
VDD33
VDD33
VDD33
VDD33
PEX_TX7
PEX_TX7#

2 C8315 SCD1U10V2KX-5GP PEG_C_RXN8 AK25
Stuff PD on XTAL_SSIN and

XTAL_OUTBUFF when EXT_SS is not
used.
R8321
0R2J-2-GP
X8301
XTAL-27MHZ-85-GP
MUXLESS
0723
PEX_RX6
PEX_RX6#
AN25
AP25
1
1
82.30034.641
CEC
PEX_TX6
PEX_TX6#
AP23
AN23
PEG_TXP8
PEG_TXN8
PEG_RXP9 Optimus
PEG_RXN9 Optimus
PEX_RX5
PEX_RX5#
C8363S
CD1U10V2KX-5GP
2 C8319 SCD1U10V2KX-5GP PEG_C_RXP7AM24

XTALOUT
Optimus
Optimus
CD1U10V2KX-5GP
1
1
XTALIN
R8306
10KR2J-3-GP
CD1U10V2KX-5GP

PEG_TXP7
PEG_TXN7
PEG_RXP8 Optimus
PEG_RXN8 Optimus
PEX_TX5
PEX_TX5#
AR22
AR23
1
1
R8319
10KR2J-3-GP
OPTIMUS
Optimus
Optimus
1
1
PEX_RX4
PEX_RX4#

PEG_TXP6
PEG_TXN6
PEG_RXP7 Optimus
PEG_RXN7 Optimus
PEX_TX4
PEX_TX4#
AN22
AP22
XTALOUTBUFF
B2
C8353
2
Optimus

PEG_TXP5
PEG_TXN5
PEG_RXP6 Optimus
PEG_RXN6 Optimus
PEX_RX3
PEX_RX3#
PEG_RXP5 Optimus
PEG_RXN5 Optimus
PEX_TX3
PEX_TX3#
A2
A7
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AJ5
AK15
AL7
B7
C7
D5
D6
D7
E5
E7
F4
G5
H32
P6
U7
V6
Y4
1
1
NC#A2
NC#A7
NC#AA4
NC#AB4
NC#AB7
NC#AC5
NC#AD6
NC#AF6
NC#AG6
NC#AJ5
NC#AK15
NC#AL7
NC#B7
NC#C7
NC#D5
NC#D6
NC#D7
NC#E5
NC#E7
NC#F4
NC#G5
NC#H32
NC#P6
NC#U7
NC#V6
NC#Y4
PEX_RX2
PEX_RX2#
AP20
AN20
PEG_TXP4
PEG_TXN4
DY
PEX_TX2
PEX_TX2#

D1
Optimus
C8354
SC15P50V2JN-2-GP
2
1
0728
C8330S
1
1
XTAL_OUT
N12P-GE-A1-GP
DY
X02 11/29 0R2J-2-GP
AG19
F7
PEX_RX1
PEX_RX1#
AR19
AR20
PEG_TXP3
PEG_TXN3
PEG_RXP4 Optimus
PEG_RXN4 Optimus
PEX_SVDD_3V3
NC#F7
PEG_RXP3 Optimus
PEG_RXN3 Optimus
SC4D7U6D3V3KX-GP
Near BALLS
PEX_TX1
PEX_TX1#

XTAL_OUTBUFF
XTAL_IN
Optimus
2nd = 82.30034.651
3rd = 82.30034.681
C1U6D3V2KX-GP
1
1
C8361 20 CLK_27M_VGA
0818
De-cap
0728
R8318
10KR2J-3-GP
3D3V_VGA_S0
PEX_RX0
PEX_RX0#
AN19
AP19
PEG_TXP2
PEG_TXN2
Optimus
XTAL_SSIN
B1
R8302
C8317
0818
De-cap
CD1U10V2KX-5GP
PEG_RXP2 Optimus
PEG_RXN2 Optimus
OptimusOptimus
PLLVDD
VID_PLLVDD
SP_PLLVDD
XTALSSIN D2
C8345S
PEX_TX0
PEX_TX0#
AP17
AN17
PEG_TXP1
PEG_TXN1
C8350
DY
XTAL_PLL
AE9
AD9
AF9
10KR2J-3-GP

C8349S
14 OF 16
VGA2N
C8343
Optimus
C8360S
DY
SC10U6D3V5KX-1GP
1
1
Optimus
C8321S
SC4D7U6D3V3KX-GP
PEG_RXP1 Optimus
PEG_RXN1 Optimus
0723
Optimus
SC4D7U6D3V3KX-GP
PEG_TXP0
PEG_TXN0

C8334S
DY
C1U6D3V2KX-GP
4 PEG_TXP[0..15]
4 PEG_TXN[0..15]
1
1
PEX_REFCLK
PEX_REFCLK#
C8326S
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16
CD1U10V2KX-5GP
PEG_RXP0 Optimus
PEG_RXN0 Optimus
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
AR16
AR17
20 CLK_PCIE_VGA
20 CLK_PCIE_VGA#
4 PEG_RXP[0..15]
4 PEG_RXN[0..15]
AJ17
AJ18
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
CD1U10V2KX-5GP
200R2F-L-GP
PEXTSTCLK_OUT
2
PEXTSTCLK_OUT#
PEX_CLKREQ#
CD1U10V2KX-5GP
DY
R8315
1
PEX_RST#
AR13
AM16
NV_PEG_CLKREQ#
Optimus Optimus
C8356
DY
1V_VGA_S0
PEX_RST#
Optimus Optimus
2 100KR2J-1-GP
DY
R8314 1
C8348
C8346
CD1U10V2KX-4GP
2nd = 73.7SZ08.DAH
D
0818
De-cap
AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
C8362
C8347
CD1U10V2KX-4GP
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
0927
73.01G08.L04
C8338
DY
74LVC1G08GW-1-GP
C8339
1
2
PEX_RST# 51,85,86
C8342
C8355
SCD1U10V2KX-4GP
PEX_RST#
GND
AK16
AK17
AK21
AK24
AK27
SC22U6D3V5MX-2GP
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
SC10U6D3V3MX-GP
DY
SC4D7U6D3V3KX-GP
VCC
Near BGA
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
PLT_RST#
SC1U6D3V2KX-GP
PLT_RST#
A00
SCD1U10V2KX-4GP
3D3V_S5
U8301
1
18 DGPU_HOLD_RST#
0818
De-cap
150mA
VIO_PLLVDD
0R0603-PAD-2-GP
1V_VGA_S0
Near BALLS
PCI_EXPRESS
5,18,27,71,75,82
1 L8301
1V_VGA_S0
1 OF 16
VGA2A
2
0R0402-PAD-2-GP
SC10U6D3V3MX-GP
1
R8323
A00
OptimusOptimus
1
Document Number
Rev
QUEEN 15
A00
Sheet

1
83
of
108
2 OF 16
VGA2B
FBA
3 OF 16
VGA2C
FBB
1
1
1
2
89
89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88
88,89
88,89
89
FB_PLLAVDD0
1
FB_PLLAVDD1
OPTIMUS
1
2
1
FBA_CMD_20
88
88
89
89
L8401
C8412
C8413
90
90
90
90
91
91
91
91
FBBDQM0
FBBDQM1
FBBDQM2
FBBDQM3
FBBDQM4
FBBDQM5
FBBDQM6
FBBDQM7
90
90
90
90
91
91
91
91
FBBDQSP0
FBBDQSP1
FBBDQSP2
FBBDQSP3
FBBDQSP4
FBBDQSP5
FBBDQSP6
FBBDQSP7
90
90
90
90
91
91
91
91
FBBDQSN0
FBBDQSN1
FBBDQSN2
FBBDQSN3
FBBDQSN4
FBBDQSN5
FBBDQSN6
FBBDQSN7
C8416
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
C8415
FBBD0
FBBD1
FBBD2
FBBD3
FBBD4
FBBD5
FBBD6
FBBD7
FBBD8
FBBD9
FBBD10
FBBD11
FBBD12
FBBD13
FBBD14
FBBD15
FBBD16
FBBD17
FBBD18
FBBD19
FBBD20
FBBD21
FBBD22
FBBD23
FBBD24
FBBD25
FBBD26
FBBD27
FBBD28
FBBD29
FBBD30
FBBD31
FBBD32
FBBD33
FBBD34
FBBD35
FBBD36
FBBD37
FBBD38
FBBD39
FBBD40
FBBD41
FBBD42
FBBD43
FBBD44
FBBD45
FBBD46
FBBD47
FBBD48
FBBD49
FBBD50
FBBD51
FBBD52
FBBD53
FBBD54
FBBD55
FBBD56
FBBD57
FBBD58
FBBD59
FBBD60
FBBD61
FBBD62
FBBD63
B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25
A16
D10
F11
D15
D27
D34
A34
D28
C14
A10
E10
D14
E26
D32
A32
B26
B14
B10
D9
E14
F26
D31
A31
A26
1V_VGA_S0
G14
G15
G11
G12
G27
G28
G24
G25
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27
0810
ODTx & CKEx & RST termination.
RN8402
FBB_CMD_16
FBB_CMD_19
FBB_CMD_20
FBB_CMD_0
4
3
2
1
FBB_CMD_3
SRN10KJ-6-GP
R8403
2
10KR2J-3-GP
Optimus
C
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_CLK0
FBB_CLK0#
FBB_CLK1
FBB_CLK1#
FBB_WCK0
FBB_WCK0#
FBB_WCK1
FBB_WCK1#
FBB_WCK2
FBB_WCK2#
FBB_WCK3
FBB_WCK3#
FBB_DEBUG0
FBB_DEBUG1
F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20
FBB_CMD_0 90
E17
D17
D23
E23
FBB_CLK0
FBB_CLK0#
FBB_CLK1
FBB_CLK1#
G19
G16
FBC_DEBUG0
FBC_DEBUG1
K27
FBCAL_PD_VDDQ
FBB_CMD_2
FBB_CMD_3
FBB_CMD_4
FBB_CMD_5
FBB_CMD_6
FBB_CMD_7
FBB_CMD_8
FBB_CMD_9
FBB_CMD_10
FBB_CMD_11
FBB_CMD_12
FBB_CMD_13
FBB_CMD_14
FBB_CMD_15
FBB_CMD_16
90
90
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90
90,91
91
90,91
91
FBB_CMD_18
FBB_CMD_19
FBB_CMD_20
FBB_CMD_21
FBB_CMD_22
FBB_CMD_23
FBB_CMD_24
FBB_CMD_25
FBB_CMD_26
FBB_CMD_27
FBB_CMD_28
FBB_CMD_29
FBB_CMD_30
91
91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90
90,91
90,91
91
FBB_CLK0
FBB_CLK0#
FBB_CLK1
FBB_CLK1#
TP8413
TP8414
1
1
90
90
91
91
TPAD14-GP
TPAD14-GP
Optimus
A00
1D5V_VGA_S0
1009
FB_CAL_PD_VDDQ
L8402
1V_VGA_S0
Optimus
L27
M27
N12P-GE-A1-GP
2
0R0603-PAD-2-GP
FB_CAL_PU_GND
FB_CAL_TERM_GND
2Optimus
40D2R2F-GP
2Optimus
40D2R2F-GP
2Optimus
60D4R2F-GP
1
R8404
FBCAL_PU_GND
1
R8405
FB_CAL_TERM_GND
1
R8402
<Variant Name>
A00
OPTIMUS
Wistron Corporation
Title
N12P(2/6)_MEMORY
Size
Custom
GB1-128 do not need.
Date:
5
Optimus
5
6
7
8
2
0R0603-PAD-2-GP
1
C8418
Optimus
Optimus Optimus Optimus
10KR2J-3-GP
N12P-GE-A1-GP
5
6
7
8
R8401
NC#J27
Optimus
4
3
2
1
TPAD14-GP
TPAD14-GP
C8417
J19
J18
FBBD[32..63]
SRN10KJ-6-GP
SC4D7U6D3V3KX-GP
J27
FBA_CMD_18
FBA_CMD_19
FBA_CMD_20
FBA_CMD_21
FBA_CMD_22
FBA_CMD_23
FBA_CMD_24
FBA_CMD_25
FBA_CMD_26
FBA_CMD_27
FBA_CMD_28
FBA_CMD_29
FBA_CMD_30
TP8411
TP8412
91
0802 swap
SC1U6D3V2KX-GP
FB_VREF
1
88
88
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88
88,89
89
88,89
89
FBA_DEBUG0
FBA_DEBUG1
FBA_CMD_2
FBA_CMD_3
FBA_CMD_4
FBA_CMD_5
FBA_CMD_6
FBA_CMD_7
FBA_CMD_8
FBA_CMD_9
FBA_CMD_10
FBA_CMD_11
FBA_CMD_12
FBA_CMD_13
FBA_CMD_14
FBA_CMD_15
FBA_CMD_16
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
Optimus
RN8401
T30
T29
AG27
AF27
C8411
FBA_CMD_16
FBA_CMD_19
FBA_CMD_3
FBA_CMD_0
T32
T31
AC31
AC30
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
Near BGA
ODTx & CKEx & RST termination.
FBA_DEBUG0
FBA_DEBUG1
C8414
FBA_CMD_0 88
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
SCD1U10V2KX-5GP
2
1
2
Mode E is necessary for DDR3

that require compatibility
with previous generation
GPUs (GB1-128) and only
applies to GB2-128 package.
FB_DLLAVDD
FB_PLLAVDD
TP8415
TPAD14-GP
0818
De-cap
FB_DLLAVDD
FB_PLLAVDD
1
2
1
1
2
1
2
C8410
DY
FBA_WCK0
FBA_WCK0#
FBA_WCK1
FBA_WCK1#
FBA_WCK2
FBA_WCK2#
FBA_WCK3
FBA_WCK3#
0723
P29
R29
L29
M29
AG29
AH29
AD29
AE29
C8426
SC4D7U6D3V3KX-GP
Differential write clocks

for GDDR5 for Frame Buffers.
Reference for read and write
data.
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
C8409
0818
De-cap
0818
De-cap
Optimus Optimus
SCD1U10V2KX-4GP
L35
G35
H31
N32
AD32
AJ31
AJ35
AC34
FBADQSN0
FBADQSN1
FBADQSN2
FBADQSN3
FBADQSN4
FBADQSN5
FBADQSN6
FBADQSN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
C8419
Near BALLS
C8420
1D5V_VGA_S0
FBBD[0..31]
SCD1U10V2KX-5GP
88
88
88
88
89
89
89
89
L34
H35
J32
N31
AE31
AJ32
AJ34
AC33
Optimus
SC4D7U6D3V3KX-GP
FBADQSP0
FBADQSP1
FBADQSP2
FBADQSP3
FBADQSP4
FBADQSP5
FBADQSP6
FBADQSP7
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
C8422 C8421
DY
SC1U6D3V2KX-GP
88
88
88
88
89
89
89
89
P32
H34
J30
P30
AF32
AL32
AL34
AF35
Optimus
C8423
SCD1U10V2KX-5GP
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
C8424
SCD01U50V2KX-1GP
88
88
88
88
89
89
89
89
C8425
90
OptimusOptimus
SCD01U50V2KX-1GP
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
J23
J24
J29
SCD1U10V2KX-4GP
FBAD[32..63]
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
SCD1U10V2KX-5GP
89
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
SCD01U50V2KX-1GP
OptimusOptimusOptimus
L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35
SC1U6D3V2KX-GP
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
1D5V_VGA_S0
FBAD[0..31]
88
0818
De-cap
Document Number
Rev
QUEEN 15
A00
Sheet

1
84
of
108
2
R8514
2K2R2J-2-GP
I2CA_SCL
I2CA_SDA
Optimus
R8503
10KR2J-3-GP
NV_I2CA_SCL
NV_I2CA_SDA
DACB_VDD
DACA_RSET
DACA_HSYNC
DACA_VSYNC
AM13
AL13
DACA_RED
DACA_GREEN
DACA_BLUE
In Optimus mode the GPU does not drive certain

interfaces. These interfaces should be treated as
unused and appropriate terminations per the GPU design
guide should be applied th the signal or the power
supply block.
NV_I2CA_SDA
NV_I2CA_SCL
AM15
1
2
R8507
10KR2J-3-GP
Optimus
3D3V_VGA_S0
RN8501
AG7
AK6
AK13
G1
G4
DACA_VREF
DACB_VDD
AH7
G3
G2
I2CB_SCL
I2CB_SDA
2 0R0402-PAD-2-GP
2 0R0402-PAD-2-GP
VENTURA
SMBC_INA219
SMBD_INA219
43,92
43,92
AM1
AM2
DACB_HSYNC
DACB_VSYNC
AK4
DACB_RED
AL4
DACB_GREEN
AJ4
DACB_BLUE
Optimus
0723
NV suggest un-used I2C pull-up.
0804 swap
Ventura I2C must connect to I2CB_SCL & I2CB_SDA.
SRN2K2J-1-GP
N12P-GE-A1-GP
VENTURA
1R8511
1R8512
A00
4
3
AM14
AL14
SMBC_INA219_C
SMBD_INA219_C
DACB_VREF
DACB_RSET
R8515
2K2R2J-2-GP
AK12
DACA_VDD
AJ12
DACB
DACA
10.28
VENTURA
VENTURA
6 OF 16
VGA2F
4 OF 16
VGA2D
DACA_VDD
3D3V_VGA_S0
If a DAC interface is not required, it should be disabled by:

1. Adding a pull-down to the DACx_VDD with a 10 kilohm resistor to GND.
2. All other DAC I/O pins can be left floating.
N12P-GE-A1-GP
OPTIMUS
OPTIMUS
The following guidelines only apply to a fully unused IFP macro:

1. Pull down IFPxy_IOVDD with 10 kilohm resistor.
2. Pull down IFPxy_PLLVDD with 10 kilohm resistor.
3. The other IO pins can be NC; this includes unused data lines.
7 OF 16
VGA2G
IFPEF
AL8
AM8
IFPA_TXD0#
IFPA_TXD0
IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL
AM9
AM10
IFPA_TXD1#
IFPA_TXD1
IFPEF_PLLVDD
IFPEF_PLLVDD
AJ6
AL1
IFPAB_PLLVDD
AK9
AJ11
IFPAB_PLLVDD
AL10
AK10
IFPA_TXD2#
IFPA_TXD2
IFPAB_IOVDD
AL11
AK11
IFPA_TXD3#
IFPA_TXD3
4
3
AF5
AF4
IFPE_L0#
IFPE_L0
AG4
AH4
GPIO15
AH5
AH6
L1
1
2
A00
AP8
AN8
1
2
IFPB_TXD4#
IFPB_TXD4
IFPAB_IOVDD
IFPAB_IOVDD
20101220
IFPE_L1#
IFPE_L1
AM12
AM11
IFPA_TXC#
IFPA_TXC
RN8503
SRN10KJ-5-GP
IFPE_L2#
IFPE_L2
RN8502
SRN10KJ-5-GP
Optimus
Optimus
IFPEF_RSET
IFPEF_IOVDD
A00
IFPAB_RSET
IFPE_L3#
IFPE_L3
IFPEF_PLLVDD
AD4
AE4
AE5
AE6
4
3
IFPAB_PLLVDD
9 OF 16
VGA2I
IFPAB
AG9
AG10
IFPA_IOVDD
AN10
AP10
IFPB_TXD5#
IFPB_TXD5
20101220
IFPEF_IOVDD
AE7
IFPEF_IOVDD
AD7
IFPE_IOVDD
IFPF_AUX_I2CZ_SDA#
IFPF_AUX_I2CZ_SCL
IFPF_IOVDD
IFPF_L3#
IFPF_L3
IFPB_IOVDD
AR10
AR11
IFPB_TXD6#
IFPB_TXD6
IFPF_L2#
IFPF_L2
IFPF_L1#
IFPF_L1
AP11
AN11
IFPB_TXD7#
IFPB_TXD7
IFPF_L0#
IFPF_L0
AN13
AP13
IFPB_TXC#
IFPB_TXC
GPIO21
AF2
AF3
AH3
AH2
AH1
AJ1
AJ2
AJ3
AL3
AL2
K6
N12P-GE-A1-GP
OPTIMUS
K1
GPIO0
N12P-GE-A1-GP
OPTIMUS
B
IFPC_PLLVDD
IFPC_RSET
IFPC_AUX_I2CW_SDA#
IFPC_AUX_I2CW_SCL
R8509
1KR2F-3-GP
Optimus
IFPC_L3#
IFPC_L3
IFPC_L2#
IFPC_L2
AJ8
IFPC_L1#
IFPC_L1
IFPC_IOVDD
IFPCD_IOVDD
C4D7U6D3V3KX-GP
1009
AN3
AP2
GPU_HDMI_DATA 51
GPU_HDMI_CLK 51
IFPC_L0#
IFPC_L0
GPIO1
IFPCD_PLLVDD
AC6
IFPD_RSET
AB6
IFPD_PLLVDD
IFPD_RSET
IFPD_AUX_I2CX_SDA#
IFPD_AUX_I2CX_SCL
R8508
1KR2F-3-GP
Optimus
C8511S
C8505S
C1U6D3V2KX-GP
CD1U10V2KX-5GP
220ohm@100MHz ESR=0.05
C8512S
Optimus 0R0603-PAD-2-GP
AK7

2
1
A00
C4D7U6D3V3KX-GP
C1U6D3V2KX-GP
L8502
AJ9
IFPC_RSET
C8516S
280mA
1V_VGA_S0
IFPCD_PLLVDD
C8506S
DY
Optimus
C8507S
CD1U10V2KX-5GP
300ohm@100MHz ESR=0.25
CD1U10V2KX-5GP
C8508S
IFPD
NEED CHECK PAGE 51.
AR2
AP1
HDMI_CLK# 51
HDMI_CLK 51
AM4
AM3
HDMI_DATA0# 51
HDMI_DATA0 51
IFPD_L2#
IFPD_L2
AM5
AL5
HDMI_DATA1# 51
HDMI_DATA1 51
IFPD_L1#
IFPD_L1
AM6
AM7
HDMI_DATA2# 51
HDMI_DATA2 51
IFPD_L3#
IFPD_L3
Optimus Optimus
2
0R0603-PAD-2-GP
Optimus
5 OF 16
VGA2E
IFPC
L8503
A00
8 OF 16
VGA2H
220mA
3D3V_VGA_S0
IFPCD_IOVDD
AK8
IFPD_IOVDD
IFPD_L0#
IFPD_L0
GPIO19
K2
GPU_HDMI_HPD
AN4
AP4
AR4
AR5
AP5
AN5
AN7
AP7
AR7
AR8
L7
51
N12P-GE-A1-GP
N12P-GE-A1-GP
OPTIMUS
If either IFPC or IFPD is used, then the whole IFPCD interface is
OPTIMUS
considered as being used. This is because IFPC and IFPD share one
macro design so one IO interface cannot be independently disabled.
X02 1110
DY
3D3V_S0
U8501
51,83,86 PEX_RST#
2
2
U8501_2
1
DYR8510
0R2J-2-GP
R8513
1
0R2J-2-GP
2
3
DY0927
B
VCC
A
Y
<Variant Name>
5
4
GPU_HDMI_HPD
GND
Optimus systems with HDMI connected to GPU.

(Option A).

R8505
100KR2J-1-GP
74LVC1G08GW-1-GP
73.01G08.L04
2ND = 73.7SZ08.DAH
Wistron Corporation
51 HDMI_HPD_DET
93 9025_PGOOD_1V
0927
DY
Title
N12P(3/6)_DAC
Size
A2
Date:
Document Number
Rev
QUEEN 15
A00
Sheet

1
85
of
108
RN8601
VGA2J
MIOA_VDDQ
0R2J-2-GP
C8602
DY
2
R8603
10KR2J-3-GP
Optimus
SCD1U10V2KX-4GP
R8601
DY
P9
R9
T9
U9
NC#P9
NC#R9
NC#T9
NC#U9
U5
NC#U5
T5
NC#T5
0728 Reserve for N12M.
N5
NV_OVERTEMP# 1
NV_GPIO9
2
10 OF 16
NC#N1
NC#P4
NC#P1
NC#P2
NC#P3
NC#T3
NC#T2
NC#T1
NC#U4
NC#U1
NC#U2
NC#U3
NC#R6
NC#T6
NC#N6
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
OPTIMUS
NC#R4
NC#T4
NC#N4
R4
T4
N4
Optimus
D
12 OF 16
VGA2L
MISC1
1P2800_VGA_DXN B4
TP8611
TPAD14-GP
THERMDN
A00 1231 add probe point
20 JTAG_TCK_VGA
MIOA_CLKIN_NC
TPAD14-GP
TPAD14-GP
TPAD14-GP
1TP8608
1TP8609
1TP8610
MIOA_CLKIN_NC
3D3V_VGA_S0
AP14
AR14
AN14
AN16
AP16
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#
C8601
R8605
10KR2J-3-GP
Optimus
0728 Reserve for N12M.
SCD1U10V2KX-4GP
DY
3
4
NC#AA9
NC#AB9
NC#W9
NC#Y9
AA7
NC#AA7
AA6
NC#AA6
AF1
NC#Y1
NC#Y2
NC#Y3
NC#AB3
NC#AB2
NC#AB1
NC#AC4
NC#AC1
NC#AC2
NC#AC3
NC#AE3
NC#AE2
NC#U6
NC#W6
NC#Y6
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
GPIO16
GPIO17
GPIO18
L2
L4
M4
GPIO20
L5
GPIO22
GPIO23
GPIO24
L6
M6
M7
PW RCNTL_0
PW RCNTL_1
NV_GPIO7
1
NV_OVERTEMP#
NV_GPIO9
3D3V_VGA_S0
1
2
PW RCNTL_0 92
PW RCNTL_1 92
TP8601 TPAD14-GP
0915
C
0728
RN8606
SRN10KJ-5-GP
OPTIMUS
Optimus
GPU_GPIO23
TP8606 TPAD14-GP
N12P-GE-A1-GP
MIOx_CLKIN signals should

have 10K pull-down
resistors.
3D3V_VGA_S0
R8604
10KR2J-3-GP
NC#AF1
PW R_LEVEL
Optimus
D8601
3
BAS16-6-GP
3D3V_VGA_S0
0723
AC_PRESENT 19,27
83.00016.K11
2ND = 83.00016.F11
3
4
W3
W1
W2
Y5
GPIO12
1 - > AC mode.
0 -> Battery mode.
NC#W3
NC#W1
NC#W2
NC#Y5
RN8605
4
3
PW R_LEVEL
0R2J-2-GP
AA9
AB9
W9
Y9
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
2
1
MIOB_VDDQ
I2CC_SCL
I2CC_SDA
E3
E4
3
4
DY
R8602
11 OF 16
VGA2K
SMBC_THERM_NV
SMBD_THERM_NV
Optimus
RN8602
SRN10KJ-5-GP
Optimus
MIOB_CLKIN_NC
E2
E1
THERMDP
2
1
N12P-GE-A1-GP
JTAG_TCK_VGA
NV_TMS
NV_TDI
NV_TDO
JTAG_TRST#
I2CS_SCL
I2CS_SDA
SRN2K2J-1-GP
1P2800_VGA_DXP B5
TP8612
TPAD14-GP
P5
N3
L3
N2
3D3V_VGA_S0
SRN10KJ-5-GP
0915
NC#N5
NC#P5
NC#N3
NC#L3
NC#N2
4
3
3D3V_VGA_S0
RN8603
SRN2K2J-1-GP
Optimus
OPTIMUS
V4
W4
AE1 MIOB_CLKIN_NC
Q8601
2
1
NC#V4
NC#W4
NC#AE1
SMBC_THERM_NV
Optimus
6
SML1_CLK 20,27
N12P-GE-A1-GP
SML1_DATA 20,27
SMBD_THERM_NV
2N7002KDW -GP
84.2N702.A3F
2nd = 84.DM601.03F
2ND = 84.2N702.031
84.2N702.J31
MIOA/B Support
2N7002K-2-GP
MIOA
MIOB
GB1-192
15-bit, available
TBD
27,28,36 PURE_HW _SHUTDOW N#
C8603
DY
DY
Package
R8606
2
Q8602_G
DY
1
PEX_RST#
51,83,85
A
<Variant Name>
G
A
0R2J-2-GP
SCD1U10V2KX-4GP
Wistron Corporation
Q8602
Not available
GB2-128
Not available
0915
Title
NV_OVERTEMP#
N12P(5/6)_MIO/ GPIO
Size
A3
Date:
Document Number
Rev
QUEEN 15
Sheet
1
A00
86
of
108
VGA_CORE
VGA_CORE
Under GPU
2
1
2
Optimus
0728
1
2
C8702
SCD1U10V2KX-4GP
1
2
1
C8706
SC1U6D3V2KX-GP
OPTIMUS
C8701
SCD1U10V2KX-5GP
N12P-GE-A1-GP
C8710
Optimus Optimus
C8718
DY
C8703
SCD1U10V2KX-5GP
C8707
C8725
OptimusOptimus
Optimus Optimus
DY
C8724
SCD1U10V2KX-5GP
C8712
C8717
SC4D7U10V3KX-GP
C8711
SCD1U10V2KX-5GP
Optimus
1
2
1
DY
1
2
1
2
1
2
1
2
1
2
SCD1U10V2KX-5GP
C8721
SC22U6D3V5MX-2GP
C8720
SC22U6D3V5MX-2GP
C8714
SCD1U10V2KX-5GP
DY
C8719
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
C8715
SCD1U10V2KX-5GP
C8709
C8723
SC4D7U6D3V3KX-GP
Optimus
C8705
C8722
SC10U6D3V3MX-GP
Optimus
C8708
0818
De-cap
C8716
SCD1U10V2KX-5GP
Optimus
Near GPU
VGA_CORE
C8704
OptimusOptimus
SCD1U10V2KX-5GP
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
SCD1U10V2KX-5GP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SCD047U25V2KX-GP
0818
De-cap
Optimus
C8713
SCD1U10V2KX-5GP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SCD1U10V2KX-5GP
VGA_CORE
16 OF 16
VGA2P
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
SC1U6D3V2KX-GP
NVVDD
E15
E18
E24
E27
E30
E6
E9
F2
F31
F34
F5
J2
J31
J34
J5
L9
M11
M13
M15
M17
M19
M2
M21
M23
M25
M31
M34
M5
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R31
R34
R5
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V12
V14
V16
V18
V2
V20
V22
V24
V31
V5
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
SCD1U10V2KX-5GP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
15 OF 16
VGA2O
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AA5
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD11
AD13
AD15
AD17
AD2
AD21
AD23
AD25
AD31
AD34
AD5
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG31
AG34
AG5
AK2
AK31
AK34
AK5
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AL6
AL9
AN2
AN34
AP12
AP15
AP18
AP21
AP24
AP27
AP3
AP30
AP33
AP6
AP9
B12
B15
B21
B24
B27
B3
B30
B33
B6
B9
C2
C34
E12
0728
<Variant Name>
N12P-GE-A1-GP
Wistron Corporation
OPTIMUS

Title
N12P(6/6)_POWER
Size
A3
Date:
5
Document Number
Rev
QUEEN 15
A00
Sheet
1
87
of
108
Frame Buffer Patition A Lower 32 bits.
RST
A7
A4
A11
A2
A10
A5
BA2
WE*
BA0
A15
32..63
1
2
1
2
1
2
2
2
0818
De-cap
C8840
DY
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
0818
De-cap
C8830
1
2
C8837 C8838
C8836
C8835
1
2
C8833 C8834
1
2
C8832
0818
De-cap
1D5V_VGA_S0
RAS*
A14
A3
A13
CAS*
CKE
CS1*
CS0*
ODT
RST
A6
A5
A9
A1
WE*
A4
A15
A10
BA0
BA2
FBA_VREF12
R8802
1K05R2F-GP
Optimus
R8801
1K05R2F-GP
Optimus
A11
A7
BA1
A12
A8
A0
A2
TC8802
ST100U6D3VBM-16GP
DY
TC8801
ST100U6D3VBM-16GP
DY
Optimus
C8839
SCD01U50V2KX-1GP
<Variant Name>
Wistron Corporation
Title
VRAM(1/4)
Size
A3
Date:
1
2
1
2
1
2
2
C8831
1D5V_VGA_S0
ODT
CS1*
CS0*
CKE
A9
A6
A3
A0
A8
A12
A1
RAS*
A13
BA1
A14
CAS*
OptimusOptimus
C8828
Modified in SB
1D5V_VGA_S0
0..31
C8827
1112 X02 Modify:

All of VRAM PCB footprint change to CO-LAY type
(DUMMY-BGA96D075133H48) from BGA96D0913H48
DRAM Function
Mode E
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
DY
C8826
0818
De-cap
C8822
DY
2nd = 72.41164.I0U
PCB Footprint = BGA96D0913H48
CMD25
CMD23
CMD2
CMD0
CMD10
CMD26
CMD14
CMD7
CMD1
CMD22
CMD20
CMD24
CMD18
CMD9
CMD29
CMD8
CMD27
CMD15
CMD11
CMD16
CMD28
CMD3
CMD17
CMD5
CMD4
CMD21
CMD6
CMD13
CMD19
CMD12
CMD30
72.52G63.A0U
OptimusOptimus
C8825
C8820
OptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimus
1
72.52G63.A0U
DY
C8824
C8819
GB2-128
Single Rank
0818
De-cap
Optimus
C8823
C8818
SCD01U16V2KX-3GP
H5TQ2G63BFR-11C-GP
1112 X02 Modify:

GB1-128 Mode C
Optimus
H5TQ2G63BFR-11C-GP
2nd = 72.41164.I0U
DY
C8829
0818
De-cap
C8817
SCD1U10V2KX-5GP
WE#
CAS#
RAS#
G1
F9
E8
E2
D8
D1
B9
B1
G9
SC1U6D3V2KX-GP
L3
K3
J3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
Optimus
C8821
C8816
SCD1U10V2KX-4GP
DMU
DML
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
0818
De-cap
C8815
SC10U6D3V3MX-GP
FBA_CMD_28
FBA_CMD_15
FBA_CMD_11
84,89 FBA_CMD_28
84,89 FBA_CMD_15
84,89 FBA_CMD_11
D3
E7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0729
C8814
SC4D7U6D3V3KX-GP
Optimus
FBADQM0
FBADQM3
CKE
T7
L9
L1
J9
J1
C8813
SC4D7U6D3V3KX-GP
WE#
CAS#
RAS#
84
84
K9
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
C8812
SC10U6D3V3MX-GP
L3
K3
J3
FBA_CMD_3
FBA_CMD_3
FBA_CMD_2 84
FBA_CMD_20 84,89
SC10U6D3V3MX-GP
DMU
DML
84
FBA_CMD_2
FBA_CMD_20
SC4D7U6D3V3KX-GP
FBA_CMD_28
FBA_CMD_15
FBA_CMD_11
84,89 FBA_CMD_28
84,89 FBA_CMD_15
84,89 FBA_CMD_11
D3
E7
G1
F9
E8
E2
D8
D1
B9
B1
G9
CK
CK#
L2
T2
SC4D7U6D3V3KX-GP
FBADQM1
FBADQM2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
J7
K7
CS#
RESET#
C8811
OptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimus
SC1U6D3V2KX-GP
CKE
FBA_CLK0
FBA_CLK0#
BA0
BA1
BA2
FBA_CMD_0 84
C8810
SC1U6D3V2KX-GP
K9
84
84
M2
N8
M3
FBA_CMD_0
SCD01U50V2KX-1GP
FBA_CMD_3
FBA_CMD_29
FBA_CMD_13
FBA_CMD_27
84,89 FBA_CMD_29
84,89 FBA_CMD_13
84
FBA_CMD_27
K1
SC10U6D3V3MX-GP
84
84
FBA_CMD_3
0729
ODT
SCD1U10V2KX-5GP
84
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
C8809
SC1U6D3V2KX-GP
CK
CK#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0729
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
C8808
SCD1U10V2KX-4GP
J7
K7
T7
L9
L1
J9
J1
FBA_CMD_2 84
FBA_CMD_20 84,89
FBA_CMD_7
FBA_CMD_10
FBA_CMD_24
FBA_CMD_6
FBA_CMD_22
FBA_CMD_26
FBA_CMD_5
FBA_CMD_21
FBA_CMD_8
FBA_CMD_4
FBA_CMD_25
FBA_CMD_23
FBA_CMD_9
FBA_CMD_12
FBA_CMD_7
FBA_CMD_10
FBA_CMD_24
FBA_CMD_6
FBA_CMD_22
FBA_CMD_26
FBA_CMD_5
FBA_CMD_21
FBA_CMD_8
FBA_CMD_4
FBA_CMD_25
FBA_CMD_23
FBA_CMD_9
FBA_CMD_12
C8807
SC1U6D3V2KX-GP
84
84
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
FBA_CMD_2
FBA_CMD_20
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84
FBADQSP3 84
FBADQSN3 84
C8806
SC1U6D3V2KX-GP
BA0
BA1
BA2
L2
T2
FBA_CMD_0 84
DQSL
DQSL#
C8805
SC1U6D3V2KX-GP
M2
N8
M3
CS#
RESET#
FBA_CMD_0
FBADQSP0 84
FBADQSN0 84
F3
G3
DY
SC1U6D3V2KX-GP
FBA_CMD_29
FBA_CMD_13
FBA_CMD_27
160R3F-1-GP
R8807
1
2
Optimus
FBA_CLK0
FBA_CLK0#
84,89 FBA_CMD_29
84,89 FBA_CMD_13
84
FBA_CMD_27
K1
C7
B7
OptimusOptimusOptimusOptimusOptimusOptimusOptimus
C8804
SC1U6D3V2KX-GP
0729
ODT
1FBA_ZQ1
243R2F-2-GP
DQSU
DQSU#
C8803
SC1U6D3V2KX-GP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
R8803 2
VREFDQ
VREFCA
ZQ
C8802
SCD1U10V2KX-5GP
FBA_CMD_7
FBA_CMD_10
FBA_CMD_24
FBA_CMD_6
FBA_CMD_22
FBA_CMD_26
FBA_CMD_5
FBA_CMD_21
FBA_CMD_8
FBA_CMD_4
FBA_CMD_25
FBA_CMD_23
FBA_CMD_9
FBA_CMD_12
Optimus
FBADQSP2 84
FBADQSN2 84
H1
M8
L8
OptimusOptimus
SC1U6D3V2KX-GP
FBA_CMD_7
FBA_CMD_10
FBA_CMD_24
FBA_CMD_6
FBA_CMD_22
FBA_CMD_26
FBA_CMD_5
FBA_CMD_21
FBA_CMD_8
FBA_CMD_4
FBA_CMD_25
FBA_CMD_23
FBA_CMD_9
FBA_CMD_12
FBA_VREF12
1D5V_VGA_S0
SC1U6D3V2KX-GP
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
243R2F-2-GP
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84
DQSL
DQSL#
F3
G3
FBADQSP1 84
FBADQSN1 84
FBAD4
FBAD3
FBAD7
FBAD0
FBAD5
FBAD2
FBAD6
FBAD1
SC1U6D3V2KX-GP
C7
B7
D7
C3
C8
C2
A7
A2
B8
A3
SC1U6D3V2KX-GP
DQSU
DQSU#
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
SC1U6D3V2KX-GP
VREFDQ
VREFCA
ZQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FBAD26
FBAD29
FBAD24
FBAD30
FBAD25
FBAD31
FBAD28
FBAD27
SC4D7U6D3V3KX-GP
H1
M8
L8
0730 swap pin
A8
A1
C1
C9
D2
E9
F1
H9
H2
84
E3
F7
F2
F8
H3
H8
G2
H7
SCD1U10V2KX-5GP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1D5V_VGA_S0
FBAD[0..31]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC1U6D3V2KX-GP
FBA_ZQ0
FBAD13
FBAD11
FBAD14
FBAD8
FBAD12
FBAD10
FBAD15
FBAD9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC1U6D3V2KX-GP
D7
C3
C8
C2
A7
A2
B8
A3
FBRAM2
K8
K2
N1
R9
B2
D9
G7
R1
N9
SC1U6D3V2KX-GP
R8804
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
1D5V_VGA_S0
SC1U6D3V2KX-GP
Optimus
SCD01U50V2KX-1GP
1 FBA_VREF12
A8
A1
C1
C9
D2
E9
F1
H9
H2
84
SC1U6D3V2KX-GP
FBAD22
FBAD18
FBAD23
FBAD17
FBAD21
FBAD19
FBAD20
FBAD16
SC1U6D3V2KX-GP
C8801
E3
F7
F2
F8
H3
H8
G2
H7
1D5V_VGA_S0
FBAD[0..31]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Optimus
FBRAM1
K8
K2
N1
R9
B2
D9
G7
R1
N9
1D5V_VGA_S0
Document Number
Rev
QUEEN 15
A00
Sheet
1
88
of
108
Frame Buffer Patition A Upper 32 bits.

1D5V_VGA_S0
K8
K2
N1
R9
B2
D9
G7
R1
1D5V_VGA_S0 N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
Optimus
C8901
2
1 FBA_VREF34
SCD01U50V2KX-1GP
R8903
2
1FBA_ZQ2
FBA_CMD_9
FBA_CMD_24
FBA_CMD_10
FBA_CMD_13
FBA_CMD_26
FBA_CMD_22
FBA_CMD_21
FBA_CMD_5
FBA_CMD_8
FBA_CMD_23
FBA_CMD_28
FBA_CMD_4
FBA_CMD_7
FBA_CMD_14
243R2F-2-GP
FBA_CMD_9
FBA_CMD_24
FBA_CMD_10
FBA_CMD_13
FBA_CMD_26
FBA_CMD_22
FBA_CMD_21
FBA_CMD_5
FBA_CMD_8
FBA_CMD_23
FBA_CMD_28
FBA_CMD_4
FBA_CMD_7
FBA_CMD_14
0729
FBA_CMD_29
FBA_CMD_6
FBA_CMD_30
160R3F-1-GP
2
OptimusR8904 1
FBA_CLK1
FBA_CLK1#
84,88 FBA_CMD_29
84,88 FBA_CMD_6
84 FBA_CMD_30
84
84
84
0730 swap pin
FBA_CMD_16
84
84
FBA_CMD_16
FBADQM6
FBADQM4
84,88 FBA_CMD_25
84,88 FBA_CMD_15
84,88 FBA_CMD_11
FBA_CMD_25
FBA_CMD_15
FBA_CMD_11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
FBAD[32..63]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBAD33
FBAD35
FBAD32
FBAD39
FBAD34
FBAD37
FBAD36
FBAD38
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD48
FBAD52
FBAD50
FBAD55
FBAD51
FBAD54
FBAD49
FBAD53
DQSU
DQSU#
C7
B7
DQSL
DQSL#
F3
G3
ODT
K1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
H1
M8
L8
Optimus
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84
FBRAM3
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS# Optimus
1D5V_VGA_S0
84
K8
K2
N1
R9
B2
D9
G7
R1
1D5V_VGA_S0 N9
0730 swap pin

0802 swap pin
FBADQSP6 84
0730 swap pin
FBADQSN6 84
FBA_VREF34
2 R8905 1FBA_ZQ3
243R2F-2-GP
FBADQSP4 84
FBADQSN4 84
FBA_CMD_19
FBA_CMD_19 84
FBA_CMD_18
FBA_CMD_20
FBA_CMD_18 84
FBA_CMD_20 84,88
0729
Optimus
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84
FBA_CMD_9
FBA_CMD_24
FBA_CMD_10
FBA_CMD_13
FBA_CMD_26
FBA_CMD_22
FBA_CMD_21
FBA_CMD_5
FBA_CMD_8
FBA_CMD_23
FBA_CMD_28
FBA_CMD_4
FBA_CMD_7
FBA_CMD_14
FBA_CMD_9
FBA_CMD_24
FBA_CMD_10
FBA_CMD_13
FBA_CMD_26
FBA_CMD_22
FBA_CMD_21
FBA_CMD_5
FBA_CMD_8
FBA_CMD_23
FBA_CMD_28
FBA_CMD_4
FBA_CMD_7
FBA_CMD_14
0729
84,88 FBA_CMD_29
84,88 FBA_CMD_6
84 FBA_CMD_30
84
84
84
0730 swap pin
FBA_CMD_29
FBA_CMD_6
FBA_CMD_30
FBA_CLK1
FBA_CLK1#
FBA_CMD_16
84
84
FBA_CMD_16
FBADQM7
FBADQM5
84,88 FBA_CMD_25
84,88 FBA_CMD_15
84,88 FBA_CMD_11
FBA_CMD_25
FBA_CMD_15
FBA_CMD_11
FBRAM4
FBAD[32..63]
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS# Optimus
84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBAD43
FBAD45
FBAD46
FBAD40
FBAD44
FBAD41
FBAD47
FBAD42
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD56
FBAD63
FBAD57
FBAD62
FBAD58
FBAD59
FBAD61
FBAD60
DQSU
DQSU#
C7
B7
FBADQSP7 84
0730 swap pin
FBADQSN7 84
DQSL
DQSL#
F3
G3
FBADQSP5 84
FBADQSN5 84
ODT
K1
FBA_CMD_19
FBA_CMD_19 84
CS#
RESET#
L2
T2
FBA_CMD_18
FBA_CMD_20
FBA_CMD_18 84
FBA_CMD_20 84,88
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
0730 swap pin
0729
C
H5TQ2G63BFR-11C-GP
H5TQ2G63BFR-11C-GP
72.52G63.A0U
72.52G63.A0U
2nd = 72.41164.I0U
2nd = 72.41164.I0U
1112 X02 Modify:

1112 X02 Modify:

1D5V_VGA_S0
R8901
1K05R2F-GP
FBA_VREF34
R8902
1K05R2F-GP
Optimus
C8902
SCD01U50V2KX-1GP
Optimus
Optimus
<Variant Name>
Wistron Corporation
Title
VRAM(2/4)
Size
A3
Date:
5
Document Number
Rev
QUEEN 15
A00
Sheet
1
89
of
108
Frame Buffer Patition B Lower 32 bits.

1D5V_VGA_S0
1D5V_VGA_S0
Optimus
C9001
1 FBB_VREF12
SCD01U50V2KX-1GP
2 R9002 1FBB_ZQ0
243R2F-2-GP
Optimus
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84
FBB_CMD_7
FBB_CMD_10
FBB_CMD_24
FBB_CMD_6
FBB_CMD_22
FBB_CMD_26
FBB_CMD_5
FBB_CMD_21
FBB_CMD_8
FBB_CMD_4
FBB_CMD_25
FBB_CMD_23
FBB_CMD_9
FBB_CMD_12
FBB_CMD_7
FBB_CMD_10
FBB_CMD_24
FBB_CMD_6
FBB_CMD_22
FBB_CMD_26
FBB_CMD_5
FBB_CMD_21
FBB_CMD_8
FBB_CMD_4
FBB_CMD_25
FBB_CMD_23
FBB_CMD_9
FBB_CMD_12
0729
84
84
FBB_CMD_29
FBB_CMD_13
FBB_CMD_27
160R3F-1-GP
2
OptimusR9005 1
FBB_CLK0
FBB_CLK0#
84
FBB_CMD_3
84
84
FBBDQM0
FBBDQM2
84,91 FBB_CMD_29
84,91 FBB_CMD_13
84
FBB_CMD_27
0730 swap pin
84,91 FBB_CMD_28
84,91 FBB_CMD_15
84,91 FBB_CMD_11
FBB_CMD_3
FBB_CMD_28
FBB_CMD_15
FBB_CMD_11
FBRAM5
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
FBBD[0..31]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBBD21
FBBD18
FBBD17
FBBD20
FBBD16
FBBD23
FBBD19
FBBD22
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBBD6
FBBD1
FBBD5
FBBD7
FBBD3
FBBD2
FBBD4
FBBD0
DQSU
DQSU#
C7
B7
84
1D5V_VGA_S0
FBBDQSP0 84
FBBDQSN0 84
0730 swap pin

FBB_VREF12
DQSL
DQSL#
F3
G3
ODT
K1
FBB_CMD_0
FBB_CMD_0 84
CS#
RESET#
L2
T2
FBB_CMD_2
FBB_CMD_20
FBB_CMD_2 84
FBB_CMD_20 84,91
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
Optimus
1D5V_VGA_S0
FBBDQSP2 84
FBBDQSN2 84
2 R9001 1FBB_ZQ1
243R2F-2-GP
Optimus
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84
0729
FBB_CMD_7
FBB_CMD_10
FBB_CMD_24
FBB_CMD_6
FBB_CMD_22
FBB_CMD_26
FBB_CMD_5
FBB_CMD_21
FBB_CMD_8
FBB_CMD_4
FBB_CMD_25
FBB_CMD_23
FBB_CMD_9
FBB_CMD_12
FBB_CMD_7
FBB_CMD_10
FBB_CMD_24
FBB_CMD_6
FBB_CMD_22
FBB_CMD_26
FBB_CMD_5
FBB_CMD_21
FBB_CMD_8
FBB_CMD_4
FBB_CMD_25
FBB_CMD_23
FBB_CMD_9
FBB_CMD_12
0729
84,91 FBB_CMD_29
84,91 FBB_CMD_13
84
FBB_CMD_27
84
84
FBB_CLK0
FBB_CLK0#
84
FBB_CMD_3
84
84
0730 swap pin
FBBDQM1
FBBDQM3
FBB_CMD_29
FBB_CMD_13
FBB_CMD_27
FBB_CMD_3
84,91 FBB_CMD_28
84,91 FBB_CMD_15
84,91 FBB_CMD_11
H5TQ2G63BFR-11C-GP
FBB_CMD_28
FBB_CMD_15
FBB_CMD_11
FBRAM6
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS# Optimus
FBBD[0..31]
84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBBD26
FBBD25
FBBD30
FBBD28
FBBD29
FBBD27
FBBD31
FBBD24
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBBD14
FBBD11
FBBD15
FBBD8
FBBD13
FBBD10
FBBD12
FBBD9
DQSU
DQSU#
C7
B7
DQSL
DQSL#
F3
G3
ODT
K1
FBB_CMD_0
FBB_CMD_0 84
CS#
RESET#
L2
T2
FBB_CMD_2
FBB_CMD_20
FBB_CMD_2 84
FBB_CMD_20 84,91
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
0802 swap
FBBDQSP1 84
0730 swap pin
FBBDQSN1 84
FBBDQSP3 84
FBBDQSN3 84
0729
H5TQ2G63BFR-11C-GP
72.52G63.A0U
72.52G63.A0U
2nd = 72.41164.I0U
2nd = 72.41164.I0U
1112 X02 Modify:

1112 X02 Modify:

1D5V_VGA_S0
R9003
1K05R2F-GP
Optimus
C9002
SCD01U50V2KX-1GP
A
<Variant Name>
R9004
1K05R2F-GP
Optimus
A
FBB_VREF12
Optimus
Wistron Corporation
Title
VRAM(3/4)
Size
A3
Date:
5
Document Number
Rev
QUEEN 15
A00
Sheet
1
90
of
108
Frame Buffer Patition B Upper 32 bits.

1D5V_VGA_S0
K8
K2
N1
R9
B2
D9
G7
R1
1D5V_VGA_S0 N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
Optimus
C9101
1 FBB_VREF34
SCD01U50V2KX-1GP
2 R9105 1FBB_ZQ2
243R2F-2-GP
Optimus
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84
FBB_CMD_9
FBB_CMD_24
FBB_CMD_10
FBB_CMD_13
FBB_CMD_26
FBB_CMD_22
FBB_CMD_21
FBB_CMD_5
FBB_CMD_8
FBB_CMD_23
FBB_CMD_28
FBB_CMD_4
FBB_CMD_7
FBB_CMD_14
FBB_CMD_9
FBB_CMD_24
FBB_CMD_10
FBB_CMD_13
FBB_CMD_26
FBB_CMD_22
FBB_CMD_21
FBB_CMD_5
FBB_CMD_8
FBB_CMD_23
FBB_CMD_28
FBB_CMD_4
FBB_CMD_7
FBB_CMD_14
0729
FBB_CMD_29
FBB_CMD_6
FBB_CMD_30
160R3F-1-GP
R9103
1
2
Optimus
FBB_CLK1
FBB_CLK1#
84,90 FBB_CMD_29
84,90 FBB_CMD_6
84 FBB_CMD_30
84
84
84
0730 swap pin
84
84
FBB_CMD_16
FBB_CMD_16
FBBDQM6
FBBDQM4
84,90 FBB_CMD_25
84,90 FBB_CMD_15
84,90 FBB_CMD_11
FBB_CMD_25
FBB_CMD_15
FBB_CMD_11
H1
M8
L8
FBRAM7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBBD48
FBBD53
FBBD50
FBBD54
FBBD51
FBBD52
FBBD49
FBBD55
DQSU
DQSU#
C7
B7
FBBDQSP6 84
0730 swap pin
FBBDQSN6 84
DQSL
DQSL#
F3
G3
FBBDQSP4 84
FBBDQSN4 84
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS# Optimus
RAS#
K8
K2
N1
R9
B2
D9
G7
R1
1D5V_VGA_S0 N9
E3
F7
F2
F8
H3
H8
G2
H7
VREFDQ
VREFCA
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
1D5V_VGA_S0
84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
K9
FBBD[32..63]
FBBD35
FBBD37
FBBD34
FBBD36
FBBD33
FBBD38
FBBD32
FBBD39
0730 swap pin

0802 swap pin
FBB_CMD_19
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84
FBB_CMD_18 84
FBB_CMD_20 84,90
0729
FBB_CMD_9
FBB_CMD_24
FBB_CMD_10
FBB_CMD_13
FBB_CMD_26
FBB_CMD_22
FBB_CMD_21
FBB_CMD_5
FBB_CMD_8
FBB_CMD_23
FBB_CMD_28
FBB_CMD_4
FBB_CMD_7
FBB_CMD_14
FBB_VREF34
1FBB_ZQ3
243R2F-2-GP
Optimus
FBB_CMD_19 84
FBB_CMD_18
FBB_CMD_20
R9101
FBB_CMD_9
FBB_CMD_24
FBB_CMD_10
FBB_CMD_13
FBB_CMD_26
FBB_CMD_22
FBB_CMD_21
FBB_CMD_5
FBB_CMD_8
FBB_CMD_23
FBB_CMD_28
FBB_CMD_4
FBB_CMD_7
FBB_CMD_14
0729
84,90 FBB_CMD_29
84,90 FBB_CMD_6
84 FBB_CMD_30
84
84
0730 swap pin
FBB_CMD_29
FBB_CMD_6
FBB_CMD_30
FBB_CLK1
FBB_CLK1#
84
FBB_CMD_16
84
84
FBBDQM7
FBBDQM5
84,90 FBB_CMD_25
84,90 FBB_CMD_15
84,90 FBB_CMD_11
FBB_CMD_16
FBB_CMD_25
FBB_CMD_15
FBB_CMD_11
FBRAM8
FBBD[32..63]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBBD44
FBBD40
FBBD43
FBBD42
FBBD45
FBBD41
FBBD46
FBBD47
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBBD59
FBBD58
FBBD61
FBBD62
FBBD57
FBBD63
FBBD56
FBBD60
DQSU
DQSU#
C7
B7
DQSL
DQSL#
F3
G3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS# Optimus
84
D
0730 swap pin
FBBDQSP7 84
0730 swap pin
FBBDQSN7 84
FBBDQSP5 84
FBBDQSN5 84
ODT
K1
FBB_CMD_19
CS#
RESET#
L2
T2
FBB_CMD_18
FBB_CMD_20
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBB_CMD_19 84
FBB_CMD_18 84
FBB_CMD_20 84,90
C
0729
H5TQ2G63BFR-11C-GP
H5TQ2G63BFR-11C-GP
72.52G63.A0U
72.52G63.A0U
2nd = 72.41164.I0U
2nd = 72.41164.I0U
1112 X02 Modify:

1D5V_VGA_S0
1112 X02 Modify:

R9104
1K05R2F-GP
FBB_VREF34
R9102
1K05R2F-GP
Optimus
C9102
SCD01U50V2KX-1GP
Optimus
1 2
Optimus
<Variant Name>
Wistron Corporation
Title
VRAM(4/4)
Size
A3
Date:
5
Document Number
Rev
QUEEN 15
A00
Sheet
1
91
of
108
10
SSID = PWR.Plane.Regulator_GFX
J
DCBATOUT_GPU
MUXLESS
0809
RT8208B
MUXLESS
P0(Hot)
R9210//PR9209
0.975V
0.954V
(default boot up)
0.878V
0.853V
0923 update table
PR9227
10KR2J-3-GP
2
0805
DY
ST470U2VDM-6-GP-U
ST470U2VDM-6-GP-U
0923
Update value of PR9210, PR9209 and PR9213
for N12P.
PR9216
1
GND_SENSE
83
0R0402-PAD
PR9207
10R2J-2-GP
PR9226
10KR2J-3-GP
2
0728
MUXLESS
MUXLESS
DY
PWRCNTL_0
PWRCNTL_1
ST470U2VDM-6-GP-U
R9213
75KR2F-GP
MUXLESS
PR9224
10KR2J-3-GP
MUXLESS
PR9210
82KR2F-1-GP
MUXLESS
1
2
PR9225
10KR2J-3-GP
PR9209
300KR2F-GP
3D3V_VGA_S0
P8 & P12
PR9210
77.24771.15L
2nd = 79.47719.9BL
PWR_VGA_CORE_D1
PWR_VGA_CORE_D0
ES
77.24771.15L
2nd = 79.47719.9BL
PWR_VGA_CORE_FB
PR9210//PR9213
MUXLESS
PR9210//R9209//PR9213
MUXLESS
VGA_CORE_PWR
1
P0(Cold)
PC9211
SCD1U10V2KX-4GP
MUXLESS
(GPIO5)
DY
8209A_EN/DEM_VGA
DY
CH551H-30PT-GP
PWRCNTL_0
(GPIO6)
1GND_SENSE_1
93 DGPU_PWR_EN
PWRCNTL_1
P-State
PD9201
1
1
DY
210KR2J-3-GP
PT9204
0928
Follow Brian suggestion.
PC9209 PC9210
VGA_SENSE
PR9208
10KR2F-2-GP
MUXLESS
MUXLESS
77.24771.15L
2nd = 79.47719.9BL
VGA_SENSE_R
1 PR9211 2
0R0402-PAD
PR9206 1
PT9203
MUXLESS
PC9218
DY SC330P50V3KX-GP
83
3D3V_VGA_S0
PT9202
MUXLESS
MUXLESS
PWR_VGA_CORE_VOUT
2nd = 84.17N03.030
A00 1224
MUXLESS
2
Modify to PCMC135T-R36MF
PC9208
SCD1U10V2KX-4GP
PR9230
2D2R5F-2-GP
DY
SC10P50V2JN-4GP
2nd = 84.17N03.030
MUXLESS
RT8208BGQW-GP
84.06725.030
PG9205
SC10P50V2JN-4GP
PWR_VGA_CORE_VOUT
7
6
2
1
7
6
2
1
84.06725.030
PU9205
IRF6725MTRPBF-GP-U
86
PU9204
IRF6725MTRPBF-GP-U
PL9201
2
L-D36UH-1-GP
GAP-CLOSE-PWR-3-GP
PWRCNTL_1
68.R3610.20A
2nd = 68.R3610.20C
86
MUXLESS
Design Current = 32A
VOUT
PWR_VGA_CORE_D1
PWR_VGA_CORE_D0
PWRCNTL_0
MUXLESS
PR9203
10R2J-2-GP
GND
PWR_VGA_CORE_FB
1PWR_VGA_SNUB
EM/DEM
7
3
14
5
6
PC9206
2PWR_VGA_CORE_BOOT_C 1
SCD1U25V3KX-GP
2D2R3-1-U-GP
VGA_CORE_UGATE
1 PR9218 2
0R0402-PAD
VGA_CORE_LGATE
1 PR9219 2
0R0402-PAD
5
4
3
17
G0
FB
G1
D1
D0
PR9205
S
S
G
20100702_PWR
15
PGOOD
CS
PWR_VGA_CORE_UGATE
PWR_VGA_CORE_PHASE
PWR_VGA_CORE_LGATE
5
4
3
8209A_EN/DEM_VGA
VDD
PWR_VGA_CORE_BOOT 1
1
2
1
2
6
5
2
1
6
5
2
1
1
MUXLESS
UGATE
PHASE
LGATE
MUXLESS
13
12
11
8
S
S
G
PC9207
SC1U10V2KX-1GP
MUXLESS
4
10
BOOT
D
D
D
D
8209A_PGOOD_VGA
PWR_VGA_CORE_CS
2
6K2R2F-GP
TON
VDDP
D
D
D
D
1
PR9204
16
9
Vout=0.75V*(R1+R2)/R2
45<OCP<50A
0927
PL9201 change
VGA_CORE
like CPU core
power choke.
PU9201
2 PR9201 1
10R2F-L-GP
PWR_VGA_CORE_VDD
MUXLESS
MUXLESS
SC1U10V2KX-1GP
MUXLESS
PC9203
SC4D7U25V5KX-GP
MUXLESS
MUXLESS
PC9202 PC9205
SC4D7U25V5KX-GP
2nd = 84.45N03.A30
MUXLESS
PC9213 PC9214
SC4D7U25V5KX-GP
84.06721.030
2nd = 84.45N03.A30
MUXLESS
PC9215
SC4D7U25V5KX-GP
2249KR2F-GP
PR9202 1
MUXLESS
PWR_VGA_CORE_TON
MUXLESS
PC9201
PC9204
SC4D7U25V5KX-GP
84.06721.030
I
PU9203
IRF6721SPBF-GP-U
SC4D7U25V5KX-GP
PU9202
IRF6721SPBF-GP-U
SCD1U25V3KX-GP
D
D
D
D
D
D
D
D
5V_S5
MUXLESS
1
MUXLESS
FOR NVIDIA VENTURA

DCBATOUT
MUXLESS
DCBATOUT_GPU
Frequency setting
470K -->165KHz
200K -->323KHz
100K -->500KHz
0705 Modify
0705 Modify
A00 1223 not co-lay
0705 Modify:
2
D004R3720F-GP Removed PR9222 sense Resistor.
Add PR9215,PR9216,PC9201
2
1
PR9217
PR9221
10R2F-L-GP
VENTURA
VENTURA
0702 Modify:
Change U4306 power source to
3D3V_VGA_S0 from 3D3V_S0.
0915
3D3V_VGA_S0
3D3V_S5
PU9205_VIN+
VENTURA
SCD1U25V2KX-GP
PU9205_VIN-
PC9217
1
2
PR9215
10R2F-L-GP
DY
DY
22,83,93
1
R9226
3K3R2J-3-GP
VENTURA
VENTURA
2
R9228
3K3R2J-3-GP
PR9229
100R2J-2-GP
PU9205_A1
PU9205_A0
DY
MUXLESS
A1
A0
SDA
SCL
DY
VGA_CORE
PQ9206
DMN66D0LDW-7-GP
8
7
6
5
DY
PU9206
PWR_VGA_CORE_EN_R#
SMBC_INA219
43,85
SMBD_INA219
43,85
8209A_EN/DEM_VGA
PQ9206_3
0607
DGPU_PWROK
1
R9225
3K3R2J-3-GP
1
PC9212
SC100P50V2JN-3GP
1 PR9214 2
0R0402-PAD
R9227
3K3R2J-3-GP
2
MUXLESS
VENTURA
0728
PR9212
10KR2J-3-GP
100KR2J-1-GP
0712 Modify:
Change VENTURA solution part number to
74.00900.079 from 74.00219.079.
3D3V_VGA_S0
DY PR9228
PC9216
SCD1U10V2KX-5GP
VIN+
VINGND
VS
3D3V_VGA_S0
8209A_PGOOD_VGA
VENTURA
2
74.00900.079
1
2
3
4
HPA00900AIDCNR-GP
JV10-CS
Wistron Corporation
A
Title
Size
Date:
10
DC/DC_VGA CORE_RT8208A
Document Number
2
Rev
QUEEN 15
Sheet
A00
92
of
1
108
3D3V_S0 to 3D3V_VGA_S0 Transfer

3D3V_VGA_S0
DY
PR9301
2
0R2J-2-GP
DMP2130L-7-GP
PQ9302
S
D
1
3D3V_S0
PR9316
10KR2F-2-GP
PC9324
84.02130.031
2ND = 84.03413.A31
MUXLESS
SCD1U10V2KX-5GP
MUXLESS
3D3V_VGA discharge
D
MUXLESS
PR9319
1
PQ9302_G
2
10KR2F-2-GP
MUXLESS
PR9319_1
PR9314
470R2J-2-GP
PQ9303
2N7002KDW-GP
RUNPWROK
PR9321
1
3.3V_RUN_VGA_1
DY
3D3V_S0
10KR2J-3-GP
2N7002K-2-GP
G
18 DGPU_PWR_EN#
PR9337
2
100KR2J-1-GP
MUXLESS
19,45,46,47
MUXLESS
D
DGPU_PWR_EN
A00
MUXLESS
MUXLESS
1
84.2N702.A3F
2nd = 84.DM601.03F
NV do not need 1.8V

DGPU_PWR_EN
92
S
PQ9304
84.2N702.J31
2ND = 84.2N702.031
C
DGPU_PWR_EN#
0628 Modify:
Change PU9305 part number to 84.04468.037 same as U3601&U3602.
2
1
1
2
3
4
DY 2
SC100P50V2JN-3GP
PR9313
1MUXLESS
2
5V_S5
PWR_1V_VDD
0R0402-PAD-2-GP
PC9313
1V_VGA_S0
PG9306
2
GAP-CLOSE-PWR
PC9316
MUXLESS
1D5V_S3
PC9314
SC10U6D3V5MX-3GP
MUXLESS
PR9318
0915
3D3V_S5
PG9305
2
DY
MUXLESS
PQ9307
PC9317
Vo(cal.)=1.05V
74.G9731.03D
2nd = 74.05930.03D
0R0402-PAD-2-GP
GAP-CLOSE-PWR
MUXLESS
A00 1224
1V_PWR
GND
ADJ
VO#3
VO#4
G9731F11U-GP
PWR_1V_PGOOD
1MUXLESS
2
GND
VEN
POK
VPP
VIN
PG9307
2
GAP-CLOSE-PWR
1
1
9025_PGOOD_1V
1D5V_VGA_EN#
SC1U6D3V2KX-GP
0628 Modify:
Simplify 1D5V_ENABLE control circuit.
Rmoved PQ9305,PR9327,PR9328 PQ9306.
85 9025_PGOOD_1V
G
PWR_1V_ADJ
PU9303
MUXLESS
PR9311
2N7002K-2-GP
MUXLESS
1D5V_ENABLE
0630 Modify:
Rename PWR_1D8V_EN to 1D8V_VGA_EN.
Rename PWR_1D5V_EN to 1D5V_VGA_EN.
DY
PR9324
2K2R2J-2-GP
A00 1224
84.2N702.J31
1
4K7R2F-GP
2
PC9315
9
8
7
6
5
PG9308
2
A00 1224
0R0402-PAD-2-GP
MUXLESS
CH551H-30PT-GP
2ND = 84.2N702.031
MUXLESS
PR9322
1
2
PR9331
100KR2J-1-GP
MUXLESS
1D5V_VGA_EN
DY 1
92 DGPU_PWR_EN
MUXLESS
S G D
3D3V_VGA_S0
PD9302
PR9336
470R2J-2-GP
15V_S5
0714 Modify:
Change LDO to Max 4A.
PWR_1V_EN
0629 Modify:
Reserved PD9302 connect DGPU_PWR_EN to
PWR_1V_EN for power down sequence.
1D5V_VGA_S0
1 PR9326 2
DGPU_PWROK
20KR2F-L-GP
A00 1224
0R0402-PAD-2-GP
GAP-CLOSE-PWR
MUXLESS
SC10U6D3V5MX-3GP
22,83,92
PR9312
Discharge Circuit
PR9315
15KR2F-GP
0630 Modify
Change PR9312 to 10K 0402 from
0ohm and stuff PC9318.
1MUXLESS
2
3D3V_VGA_S0
MUXLESS
CH551H-30PT-GP
Iomax<4A
0806
SC10U6D3V5MX-3GP
DY 1
84.2N702.A3F
2nd = 84.DM601.03F
MUXLESS
ramp-up before 1V_VGA_S0
so 1V_VGA_S0 EN have to fine tune RC delay

after VGA_Core
0927
D G S
PQ9305
2N7002KDW-GP
1V_VGA_S0 should ramp up before 1D8V_VGA_S0
MUXLESS
higih-side R + low-side
low-side R
Vout = 0.8 x
VGA_Core
VGA_Core should
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
PC9318
0629 Modify:
Reserved PD9301 connect DGPU_PWR_EN to
PWR_1D5V_EN for power down sequence.
3D3V_VGA_S0 should ramp-up before
PC9332
PR9330
1
PC9326
SCD01U50V2KX-1GP
MUXLESS
PD9301
2nd = 84.08882.037
2 1D5V_VGA_EN#
100KR2J-1-GP
1
PR9332
84.04468.037
MUXLESS
3D3V_AUX_S5
92 DGPU_PWR_EN
AO4468-GP
Park_Madison Does Not Support BACO, So follow Old Sequence

Seymour_Whistler_Robson Support BACO, So Change Sequence
SC10U6D3V3MX-GP
MUXLESS
PC9327
0629 Modify:
Add PC9332 10uF 0603.
1
2
3
4
S
S
S
G
G9731F11U-GP for 1V_S0
1D5V_VGA_S0
MUXLESS
PU9305
8 D
7 D
6 D
5 D
AO4468, SO-8
Id=?A, Qg=9~12nC
Rdson=17.4~22m ohm
1D5V_S3
change low Rds(on) MOSFET
1D5V_VGA_S0
IGPU with BACO
DIS_1D5V_VGA_S02
IGPU
1D5V_ENABLE_RC
dGPU mode
2 PWR_1V_EN#
0728
DY
100KR2J-1-GP
PQ9311
2N7002KDW-GP
Wistron Corporation
<Core Design>
1
84.2N702.A3F
2nd = 84.DM601.03F
DY

PR9317
PWR_1V_EN
PQ9308_3 2
Title
1
1V_VGA_S0
Size
A2
470R2J-2-GP
DY
Date:
5
DISCRETE VGA POWER

Document Number
Rev
QUEEN 15
A00
Sheet

1
93
of
108
(Blanking)
<Variant Name>
A
Wistron Corporation
Title
LVDS_Switch
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
94
of
108
(Blanking)
<Variant Name>
A
Wistron Corporation
Title
CRT_Switch
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
95
of
108
SSID = SDIO
(Blanking)
<Variant Name>
Wistron Corporation
Title
TOUCH PANEL
Size
A3
Date:
5
Document Number
Rev
A00
QUEEN 15
Sheet
1
96
of
108
H6
HOLE237R95-GP
DY
DY
D
H12
HOLE256R126-GP
HTML2
HOLE197R166-GP
HTML3
HOLE197R166-GP
0721 Modify:
Removed SPR1
0915 X01 Modify:

Reserved EC9701~EC9723 0.1uF for
RF suggestion.
1D8V_S0
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1D5V_S3
1D5V_S0
DY
EC9713
EC9714
DY
EC9715
DY
2
DY
EC9712
SCD1U50V3KX-GP
EC9711
DY
1D5V_S3
EC9710
DY
EC9709
DY
EC9708
DY
EC9707
DY
EC9706
DY
EC9705
DY
SCD1U50V3KX-GP
1
2
1
2
EC9704
1
2
1
2
1
2
2
1
2
1
2
1
2
1
1
2
1
2
DY
DY
SC47P50V3JN-GP
EC9739
EC9703
DY
DY
3D3V_S0
SCD1U50V3KX-GP
EC9726
EC9702
DY
3D3V_S5 3D3V_S5
SCD1U50V3KX-GP
EC9725
EC9701
SCD1U50V3KX-GP
EC9733
DY
DY
DY
DCBATOUT
1D5V_S3
SCD1U50V3KX-GP
EC9732
SC470P50V-2-GP
EC9730
DY
5V_S0
DY
5V_S5
SCD1U50V3KX-GP
EC9721
5V_S0
DCBATOUT
SCD1U50V3KX-GP
EC9722
DY
3D3V_S0
SC470P50V-2-GP
EC9729
DCBATOUT
DY
SCD1U50V3KX-GP
EC9724
DY
DY
DCBATOUT 3D3V_S0
SCD1U50V3KX-GP
EC9731
DCBATOUT
DY
SCD1U50V3KX-GP
EC9727
1D8V_S0
DY
SCD1U50V3KX-GP
EC9723
3D3V_S0
SCD1U50V3KX-GP
EC9728
DY
0901
DCBATOUT 1D05V_VTT 1D5V_S3
DY
SCD22U50V3ZY-1GP
EC9738
5V_S5
DY
3D3V_S0
SC47P50V3JN-GP
EC9737
ZZ.00PAD.J91
DY
3D3V_S0
SCD1U50V3KX-GP
EC9717
ZZ.00PAD.J91
DY
5V_S5
SC47P50V3JN-GP
EC9735
ZZ.00PAD.J91
DY
DY
SCD1U50V3KX-GP
EC9720
ZZ.00PAD.J91
DY
3D3V_S5 3D3V_S5 3D3V_S5

SCD1U50V3KX-GP
EC9736
ZZ.00PAD.J91
DY
H15
HT10X10BE10R32-D-5-GP
5V_S0
SCD1U50V3KX-GP
EC9719
DY
H7
SCD1U50V3KX-GP
EC9718
DY
H13
5V_S0
SCD1U50V3KX-GP
EC9734
H5
SCD1U50V3KX-GP
EC9716
H1
1D5V_S3
1D5V_S3
RF CAP
DY
DY
DY
ZZ.00PAD.J01
1
ZZ.00PAD.J01
ZZ.00PAD.J01
ZZ.00PAD.J01
stand off
CPU Thermal module hole

HTML1
HOLE197R166-GP
0624 Modify:
Removed AFTP1,AFTP7~AFTP13.
H11
HOLE256R126-GP
ZZ.00PAD.D01
DY
H4
HOLE256R126-GP
Check test point
ZZ.00PAD.D01
DY
D
H10
HOLE335R115-GP
H9
HOLE335R115-GP
ZZ.00PAD.921
ZZ.00PAD.D01
H2
HOLE335R115-GP
H3
HOLE256R126-GP
3D3V_S0
SCD1U10V2KX-4GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GPSCD1U10V2KX-4GP
0802 For EMI/ESD.
GPU Thermal module hole

HGPU1
STF237R117H83-1-GP
HGPU2
STF237R117H83-1-GP
HHD4
STF237R117H83-1-GP
34.4CK01.001
3rd = 34.4CK01.501
34.4CK01.001 34.4CK01.001
2nd = 34.4CK01.401
34.4CK01.001
2nd = 34.4CK01.401
2nd = 34.4CK01.401 2nd = 34.4CK01.4013rd = 34.4CK01.501
3rd = 34.4CK01.501
3rd = 34.4CK01.501
HBT1
STF237R117H123-GP
DY
Wistron Corporation
34.4DM11.001
2nd = 34.4A902.001
0818
A00 0103 add 3rd LIDON(34.4CK01.501) on HDD1,HDD4,HGPU1,HGPU2 at XBuild batch run

Title
UNUSED PARTS/EMI Capacitors

Size
A3
Date:
<Variant Name>
HHD1
STF237R117H83-1-GP
Document Number
Rev
A00
QUEEN 15
Sheet
1
97
of
108
Huron River Platform Power Sequence

(AC mode)
(DC mode)
red word: KBC GPIO
+RTC_VCC
+RTC_VCC
T1
>9ms
DCBATOUT
DCBATOUT
T2
T2
3D3V_AUX_S5
3D3V_AUX_S5
KBC GPIO34 control power on by 3V_5V_EN

S5_ENABLE
Sense the power button status
Press Power button
KBC_PWRBTN#
Platform to KBC PSL_IN2
T3
5V_S5
V5REF_Sus must be powered up before
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
T1 >9ms
RTC_RST#
RTC_RST#
Within logic high level and disable if

it is less than the logic low level.
red word: KBC GPIO
EC_ENABLE#_1(GPIO31) keep low

T4
3D3V_S5
+5VA_PCH_VCC5REFSUS
3D3V_AUX_KBC
T5
T3
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE
KBC GPIO43 to PCH

T6
PM_RSMRST#(EC Delay 40ms)
>10ms
PCH to KBC GPIO00

PCH_SUSCLK_KBC
V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
T7 >5ms
KBC GPO84 to PCH

Not floating.
AC_PRESENT
Sense the power button status
AC KBC_PWRBTN#
0ms<T8 <90ms
5V_S5
T4
3D3V_S5
T5
+5V_ALW & +3.3V_ALW need meet 0.7V difference

+5V_ALW & +3.3V_ALW need meet 0.7V difference
+5VA_PCH_VCC5REFSUS
T6
T7 >16ms
Press Power button
3D3V_AUX_KBC
KBC GPIO20 to PCH
PM_PWRBTN#
Platform to KBC PSL_IN2

This signal has an internal
pull-up resistor and has an
internal 16 ms de-bounce on the
input.
KBC GPIO43 to PCH

T9
>16ms
PM_RSMRST#
KBC GPIO20 to PCH
T8
>10ms
PCH to KBC GPIO00
AC PM_PWRBTN#
PCH_SUSCLK_KBC
AC PM_PWRBTN#
T9 >5ms
DC PCH_RSMRST#
T10
T10
PCH to KBC GPIO44

PM_SLP_S4#
T11
PCH to KBC GPIO01
>30us
PM_SLP_S3#
PCH to KBC GPIO44

PM_SLP_S4#
T11
KBC GPIO23 to LAN
PM_LAN_ENABLE
PCH to KBC GPIO01
>30us
PM_SLP_S3#
KBC GPIO23 to LAN
PM_LAN_ENABLE
Enable by PM_SLP_S4#
1D5V_S3
T12
DDR_VREF_S3(0.75V)
T13
+5V_RUN & +3.3V_RUN need meet 0.7V difference
V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
5V_S0
T14
3D3V_S0
T15
Enable by PM_SLP_S4#
+5VS_PCH_VCC5REF
V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
T16
1D5V_S0
T17
1D8V_S0
T18
0D75V_S0
T19
1D5V_S3
T12
DDR_VREF_S3(0.75V)
T13
5V_S0
T14
3D3V_S0
T15
+5VS_PCH_VCC5REF
+5V_RUN & +3.3V_RUN need meet 0.7V difference
T16
1D5V_S0
T17
1D8V_S0
T18
0D75V_S0
T19
1D8V_S0 & 1D5V_S3 power ready
1D8V_S0 & 1D5V_S3 power ready

RUNPWROK
RUNPWROK
T20
1D05V_VTT
T21
T20
1D05V_VTT
T21
VT357FCX PGOOD
VT357FCX PGOOD
T22
1.05VTT_PWRGD
0D85V_S0
0D85V_S0
T24
T24
TPS51461RGER PGOOD
TPS51461RGER PGOOD
D85V_PWRGD
SetVID
CPU SVID BUS
ACK
50us< T25 <2000us
SetVID
CPU SVID BUS
VCC_CORE
ACK
50us< T25 <2000us
VCC_CORE
VCC_GFXCORE
VCC_GFXCORE
T26
<5ms
IMVP_PWRGD
T26
ISL95831 PGOOD to system
<5ms
IMVP_PWRGD
CLK_EXP_P
This signal represents the Power
Good for all the non-CORE and
non-graphics power rails.
T23
0D85V_S0
D85V_PWRGD
T22
1.05VTT_PWRGD
T23
0D85V_S0
ISL95831 PGOOD to system
CLK_EXP_P
ALL_SYS_PWRGD=D85V_PWRGD
T27 >99ms
PWROK
D85V_PWRGD
KBC GPIO77 to PCH

T28 >0us
2ms<
This signal represents the Power

Good for all the non-CORE and
non-graphics power rails.
ALL_SYS_PWRGD=D85V_PWRGD
T27 >99ms
PWROK
D85V_PWRGD
T29 <650ms
PCH to CPU
VDDPWRGOOD
2ms<
KBC GPIO77 to PCH
T28 >0us
T29 <650ms
PCH to CPU
VDDPWRGOOD
T30 >1ms
T31 >2ms
5ms< T32 <650ms
1D8V_S0
1D8V_S0
PCH to CPU
H_CPUPWRGD
5ms<
T30 >1ms
T31 >2ms
T32 <650ms
PCH to CPU
H_CPUPWRGD
T33 >0ms
SYS_PWROK
1ms<
T35 <100ms
PLT_RST#
T33 >0ms
SYS_PWROK
T34 >1ms+60us
PCH to all system
1ms<
PLT_RST#
T36 <200us
DMI
T35 <100ms
T34 >1ms+60us
PCH to all system
T36 <200us
DMI
N12P-GE Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output

DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
8209A_EN/DEM_VGA(Discrete only)
tNVVDD >0ms
VGA_CORE(NVVDD)
RT8208 PGOOD
DGPU_PWROK(Discrete only)
A
1D5V_VGA_S0(FBVDDQ)
tNV-FBVDDQ
>0ms
VGA_CORE,1V_VGA_S0
1D5V_VGA_S0,3D3V_VGA_S0
First rail to power down

Last rail to power down
tPOWER-OFF
<10ms
<Core Design>
Wistron Corporation
For power-down, reversing the ramp-up sequence is recommended.

Title
Power Sequence
Size
A1
Date:
5
Document Number
Rev
QUEEN 15
1
A00
Sheet
98
of
108
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5
DCBATOUT
-6
AC
Adapter in
AD+
-3.1
Page38
-3.1
-3.1
VDDP
PWR_5V3D3V_ENC
3V_5V_EN
VIN
1D5V_S3
VOUT
S5_ENABLE
3
PM_SLP_S4#
-3.2
EN
-3.3
DDR_VREF_S3
REF
PWR_CHG_ACOK
ENC
SWITCH
LL1
Page40
LL2
VREG5
RT8223MGQW
DC/DC
(3V/5V)
-6.1
DCBATOUT
VREG3
VIN
5V_S5
PUMP
15V_S5
TPS51116RGER
3D3V_S5
0D75V_S0
VTT
5V_AUX_S5
3D3V_AUX_S5
-5
3V_5V_POK
-2
RUNPWROK
PGOOD
PGD
PM_SLP_S4#
Page46
Page41
DC
Battery
5V_S5
4
BQ24745
Charger
BT+
3D3V_S5
5V_S0
PM_SLP_S3#
SWITCH
-3
Page39
Page37
BJT
3D3V_AUX_KBC
VDD
-3.1
SWITCH
S5_ENABLE
-4
VIN
VOUT
3D3V_S0
Page40 ACOK
PM_SLP_S3#
Page37
1D8V_S0
TPS53311RGTR
EN
RUNPWROK
GPIO34
AC_IN#
GPIO70
Page47
SWITCH
Page37
1
-1
PGD
1D5V_S0
SLP_S4#
KBC
NPCE795P
KBC_PWRBTN#
GPIO6
SLP_S3#
-2.1
Power Button
11
PM_RSMRST#
GPIO43
PM_SLP_S4#
GPIO44
GPIO20
PM_SLP_S3#
GPIO01
AND GATE
0D75V_EN
RSMRST#
PWRBTN#
SM_DRAMPWROK
DRAMPWRGD
H_CPUPWRGD
VDDPWRGOOD
Y
PM_DRAM_PWRGD
PM_PWRBTN#
H_CPUPWRGD_R
UNCOREPWRGOOD
PROCPWRGD
Cougar Point
PCH
Page27
GPIO77
12
Sandy Bridge
CPU
13
S0_PWR_GOOD
APWROK
PWROK
PLT_RST#
BUF_CPU_RST#
PLTRST#
RSTIN#
SVID
SYS_PWROK
SYS_PWROK
SVID
10
5V_S5
V5IN
VIN
VOUT
5
RUNPWROK
EN
S0_PWR_GOOD
SYS_PWROK
Y
PGOOD
5a
5V_S5 DCBATOUT
VIN
VOUT
5a
10
AND GATE
IMVP_PWRGD
1.05VTT_PWRGD
Page45
1.05VTT_PWRGD
1D05_VTT
TPS51218DSCR
VDDP
DCBATOUT
-5
0D85_S0
-7
RT8208BGQW
EN
RTC_AUX_S5
D85V_PWRGD
Page48
3D3V_AUX_S5
-8
PGOOD
+RTC_VCC
6
DCBATOUT
RTC battery
VIN
OUTPUT
VCC_CORE
SVID
A
D85V_PWRGD
SVID
VCC_GFXCORE
VR_ON
IMVP_PWRGD
VR OUTPUT
ISL95831HRTZ
IMVP_VR_ON
<Core Design>
Page42 & 43 & 44 PGOOD
Wistron Corporation
Power Up Sequence: -8 ~ 13
Title
Size
A2
Date:
Power Sequence Diagram
Document Number
Rev
QUEEN 15
A00
Sheet

1
99
of
108
VGA_CORE
RT8208B
1V_VGA_S0
For Discrete
RT9025
Adapter
DCBATOUT
TPS51216RUKR
ISL95831HRTZ
TPS51218DSCR
DDR_VREF_S3
AO4407A
0D75V_S0
1D5V_S3
Charger
VCC_CORE
BQ24745
Battery
VCC_GFXCORE
1D05V_VTT
For UMA
+PBATT
TPCA8062
AO4468
1D5V_S0
1D5V_DDR_S0
APL5916KAI
0D85V_S0
TPS51123RGER
For Discrete
15V_S5
3D3V_AUX_S5
3D3V_S5
5V_S5
5V_AUX_S5
DMP2130L
3D3V_AUX_KBC
B
AO4468
G547F2P81U
AO4468
5V_S0
5V_USB1_S3
3D3V_S0
PA102FMG
TPS51311RGTR
3D3V_LAN_S5
1D8V_S0
CRT Board USB Power
AO4468
G5285T11U
1D8V_VGA_S0
LCDVDD
For Discrete
RTS5138
DMP2130L
3D3V_CARD_S0
RTL8111E
+1.2V_LOM
3D3V_VGA_S0
For Discrete
Power Shape
Regulator
LDO
Switch
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Power Block Diagram
Document Number
QUEEN 15
Rev
A00
Sheet
1
100
of
108
3D3V_S5
3D3V_S0
KBC SMBus Block Diagram
PCH SMBus Block Diagram
3D3V_S0
3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP
SMBCLK
SMB_CLK
SMBDATA
SMB_DATA
DIMM 1
EPCH_SMBCLK
E PCH_SMBDATA
E
E
SRN10KJ-5-GP
TouchPad Conn.
SCL
SDA
3D3V_S5
SMBus Address:A0
PSDAT1
TPDATA
PSCLK1
TPCLK
E
E
TPDATA
TPDATA
TPCLK
TPCLK
2N7002SPT
3D3V_AUX_KBC
3D3V_S5
SRN2K2J-8-GP
E
SML1CLK
SML1_CLK
SML1DATA
SML1_DATA
To KBC
EPCH_SMBCLK
E PCH_SMBDATA
SML0CLK
SML0_CLK
SML0DATA
SML0_DATA
SRN4K7J-8-GP
DIMM 2
SRN2K2J-1-GP
SCL
Battery Conn.
SRN100J-3-GP
SDA
GPIO17/SCL1
BAT_SCL
BATA_SCL_1
CLK_SMB
GPIO22/SDA1
BAT_SDA
BATA_SDA_1
DAT_SMB
SMBus address:16
SMBus Address:A4
G-Sensor
3D3V_S0
PCH
EPCH_SMBCLK
E PCH_SMBDATA
BQ24745
KBC
NPCE795P
SCLK
SDATA
SCL
SDA
SMBus address:12
SRN2K2J-1-GP
SMBus address:xx
UMA
2
SDVO_CTRLCLK
SDVO_CTRLDATA
Level
Shift
PCH_HDMI_CLK
PCH_HDMI_DATA
DDC_CLK_HDMI
DDC_DATA_HDMI
UMA
EPCH_SMBCLK
E PCH_SMBDATA
3D3V_S0
Minicard
WLAN
SMB_CLK
SMB_DATA
E
SRN2K2J-1-GP
UMA
SRN0J-6-GP
PCH_SMBCLK
L_DDC_CLK
LVDS_DDC_CLK_R
PCH_SMBDATA
L_DDC_DATA
LVDS_DDC_DATA_R
Minicard
W-WAN
GPIO73/SCL2
SML1_CLK
SCL
GPIO74/SDA2
SML1_DATA
SDA
PCH
SMB_CLK
SMB_DATA
UMA
CRT_DDC_CLK
CRT_DDC_DATA
3D3V_VGA_S0
CRT_DDC_CLK
CRT_DDC_DATA
E
SRN2K2J-1-GP
DIS
SRN0J-6-GP
3
DDC1CLK
GPU_LVDS_CLK
LVDS_DDC_CLK
CLK
DDC1DATA
GPU_LVDS_DATA
LVDS_DDC_DATA
DATA
DDC2CLK
VGA_CRT_DDCCLK
DDC2DATA
VGA_CRT_DDCDATA
LCD CONN
DIS
SRN0J-6-GP
3D3V_S0
VGA
5V_S0
DIS
E
3D3V_S0
UMA
SRN0J-6-GP
SRN2K2J-1-GP
SRN10KJ-6-GP
UMA
E
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT CONN
5V_HDMI
3D3V_VGA_S0
UMA
2N7002DW-1-GP
E
3D3V_S0
SRN1K5J-GP
SRN2K2J-1-GP
4
DIS
DDC2CLK
GPU_HDMI_CLK
DDC2DATA
GPU_HDMI_DATA
Level
Shift
DDC_CLK_HDMI
HDMI CONN
DDC_DATA_HDMI
<Core Design>
Wistron Corporation
SRN0J-6-GP

Title
DIS
Size
A2
Date:
SMBUS Block Diagram
Document Number
QUEEN 15
Rev
A00
Sheet
101
of
108
Thermal Block Diagram
Audio Block Diagram
SPKR_PORT_D_LPAGE28
DXP
P2800_DXP
SPEAKER
SPKR_PORT_D_R+
MMBT3904-3-GP
SC2200P50V2KX-2GP
UMA
Thermal
P2800
DXN
P2800_DXN
Codec
92HD79B1
Place near CPU

PWM CORE
HP
OUT
HP1_PORT_B_L
MMBT3904-3-GP
PAGE27
GPIO5
KBC
NPCE795P
GPIO92
SYS_THRM
TDR
CPU_THRM
TDL
HP1_PORT_B_R
T8
OTZ
THERM_SYS_SHDN#
2N7002
PURE_HW_SHUTDOWN#
IMVP_PWRGD
Put under CPU(T8 HW shutdown)
GPIO4
GPIO94
GPIO56
VGA_THRM
EN
VR
TDR
MIC
IN
HP0_PORT_A_L
PAGE28
P2800_VGA_DXP
DXP
HP0_PORT_A_R
THRMDA
VREFOUT_A_OR_F
FAN_TACH1
FAN1_DAC
3V/5V
PGOD
TACH
FAN
SC2200P50V2KX-2GP
VGA
Thermal
P2800
SC2200P50V2KX-2GP
VGA
P2800_VGA_DXN
DXN
THRMDC
Place near GPU(DISCRETE only).
MMBT3904-3-GP
Digital
MIC
DMIC_CLK/GPIO1
VIN
5V
DMIC0/GPIO2
PH
VIN
OTZ
VSET
VOUT
FAN CONTROL
P2793
PORTC_L
PAGE28
Analog
MIC
PORTC_R
VREFOUT_C
<Core Design>
Wistron Corporation
Title
Thermal/Audio Block Diagram
Size
Document Number
Custom
Date:
A
Rev
A00
QUEEN 15
Sheet
E
102
of
108
VERSION DATA
PAGE
Change Iteam
VERSION DATA
PAGE
Change Iteam
08/25
14
SWAP SA0_DM1 and SA1_DIM1 each other for DM2 can't boot up issue.
09/06
15
DM1 2nd=62.10017.Q31, 3rd=62.10017.K01.
08/29
28
Change U2802 Main source to 74.00991.031, 2nd 74.02793.A31,3rd 74.05606.071
09/06
14
DM2 2nd=62.10017.P31, 3rd=62.10017.K11.
08/29
61
Add 2nd 77.C1071.20L on TC6101.
09/07
68
Add 2nd source 20.K0343.004 on PWRBTN1& PWRBTN2 base on updated connector list.
08/29
64
Re-assign FP1 pin define.
09/07
69
Add 2nd source 20.K0343.004 on KBLIT1 base on updated connector list.
08/29
71
Un-stuff Debug port connector(DB1) on X01.
09/07
82
Add 2nd source 20.F0085.040 on CRTBD1 base on updated connector list.
08/29
37
Change U3701 pin2 to RUNPWROK from 0D75V_EN. Reserved R3717 0ohm between
PM_DRAM_PWRGD and VDDPWRGOOD_R.
09/07
64
Add 2nd source 20.K0382.006 on FP1 base on updated connector list.
08/29
37
Change R2724 to 20K 0402 from 10K for X01 stage.
09/07
75
Add 2nd source 20.K0382.026 on NEW1 base on updated connector list.
08/29
40
Change 3D3V_AUX_S5 to 3D3V_AUX_KBC to avoid leakage Voltage to 3D3V_AUX_KBC under DC mode.
09/07
4~10
08/31
51
HDMI1 change to 22.10296.311 from 22.10296.271
Updated CPU1 footprint to SKT-BGA989C470395-1H180 from SKT-BGA989C470395-1H186 base on data

base updated.
Add 2nd source 62.10040.771 on CPU1 base on updated connector list.
08/31
28
FAN1 change to 20.F0772.003 from 20.F1639.004
09/07
75
Change CARD1 to 20.I0129.001 from 62.10051.931 from ME double updated latest DXF&EMN on X01.
08/31
57
E-SATA1 change to 22.10321.W11 from 22.10290.141
09/07
93
PQ9308 change name to PQ9311.
09/01
41
PU4104 and PU 4105 horizontally mirror.
09/07
ALL
Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.
09/01
83
R8305 Change to 30K ohm.
09/07
28
Change U2801,U2803 to 74.02800.A71 from 74.02800.071 from vender updated parts.

Change R2803&R2817 to 107K from 499K,R2804&R2818 to 226K from 102K base on updated ADJ Table.
09/01
97
H1, H5, H13, H7 and H15 change to ZZ.00PAD.J91 from ZZ.00PAD.D01.

09/08
18, 22
09/01
56
HDD1 add 2nd=62.10065.121.
Change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220.
Add R1818.
09/01
79
U7901 change main source to 74.00351.0B3.
09/08
82
1.Rename IOBD1 pin20,22,26,28 to IOBD1_20,22,26,28 from PCIE_TXN5,PCIE_TXP5,PCIE_RXP5,PCIE_RXN5.

2.Add RN8207,RN8208 for optional USB3.0 PCIE or USB2.0 signal.
09/01
42
PR4226 change to 5.62K ohm.
09/01
45
PTC4502 change to 79.3971V.30L.
09/08
18
Reserved USBP9~USBP10 to IOBD1 pin20,22,26,28.
09/03
61
U6101 add 2nd=74.00547.079.
09/08
37
Stuff Q3704,R3710; un-stuff R3716. U3701 pin2 change to 1.05VTT_PWRGD from RUNPWROK.
09/03
49
U4901 add 2nd=74.09724.09F.
09/08
20
DY R2002.
09/03
40
PU4002 and PU4003 add 2nd=84.P1403.B37.
09/08
47
Mount PC4710.
09/03
24
L2401,L2402,L2403 add 2nd=68.10090.10B.
09/08
98
Update N12P power sequence.
09/03
27
DY C2713. Add C2722.
09/09
82
R8201, R8202 and R8203 change to 62 ohm.
09/03
47
Add PR4702
09/10
45
Change PL4501 to 68.2R210.20C from IND-D56UH-27-GP base on Brian updated.
09/03
22
Change FFS_INT2_R from PCH GPIO48 to GPIO15

Removed R2220 and change R2201 default pull up to pull down.
09/10
41
Change PL4101,PL4102 to 68.2R210.20B from 68.2R210.20Q base on Brian updated.
09/10
82
Rename IOBD1 pin14 to IOBD1_14 from USB30_SMI#.

Add R8207 for USB20 USB_OC#10_11
Add R8206 for USB30 USB30_SMI#
Add R8208 for USB20 USB signal.
Add R8207 for USB30 PCIE signal.
09/10
49
Add TPNL1 for touch panel solution 4pin connector.

Change LCD1 to 20.F1816.030 for 30pin
Re-assign LCD1 pin define base on Roy updated cable pin define list.
09/10
51
Change HDMI1 part number to 22.10296.331 from 22.10296.311 base on ME Double updated.
X01
X01
X2001 add 3rd=82.30020.A31.
09/06
20
09/06
56
U5601 add 2nd=74.02191.079.
09/06
93
PU9303 add 2nd=74.05930.03D.
09/06
37
U3701 add 2nd=73.7SZ08.DAH.
09/06
23
Add 2nd and 3rd for L2301.
09/06
23
R434 change name to PR9321. Add PC9324 and PR9319 for soft start.
09/06
61
TC6101=80.10715.B1L, 2nd=77.C1071.21L, 3rd=77.C1071.20L.
09/06
56
ODD1 add 2nd and 3rd source. HDD1 add 3rd source.
09/06
49
LCD1 add 2nd source.
Title
09/06
69
TPAD1 add 2nd.
Size
A3
<Core Design>
Wistron Corporation
Date:
5
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
1
103
of
108
VERSION DATA
PAGE
Change Iteam
VERSION DATA
PAGE
Change Iteam
09/17
40,41
Stuff EC4002 0.1uF from EMC Neo suggestion.

Stuff EC4102,EC4103 0.1uF from EMC Neo suggestion.
Stuff PC4119,PC4120 0.1uF from EMC Neo suggestion.
Stuff EC4006,EC4007 0.1uF from EMC Neo suggestion.
Change R8201~R8203 to 470ohm from 100ohm.

Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for PWM OD mode.
09/17
60,18
EC6001 change to 10p from 4.7p and default stuff from Neo suggestion.
EC1801 change to 10p from 4.7p and default stuff from Neo suggestion.
40
Add 2nd source 84.04835.H37 on PU4002,PU4003 base on Brian updated 2nd source excel file.
09/17
44
default stuff EC4407,EC4405,EC4403,EC4410 base on EMC Neo suggestion.
09/14
58
Change SPK1 to 20.F0772.004 from 20.F1647.004 from Double updated.
09/17
49
Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
09/14
51
Add R5101~R5108and reserved TR5101~TR5104 on all of HDMI differential pair for EMC suggestion.
Rename HDMI1 CONN NET name.
09/17
49
Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
09/17
82
Change R8201~R8203 to 430ohm.
09/14
29
Add R2920,R2921 and reserved EC2901,EC2902 on AUD_DMIC_CLK &AUD_DMIC_IN0 for EMC suggestion.
09/17
48
Change PR4809 to 4.7K from 100K PH power source change to 3D3V_S0 from S5.
09/13
83
Change X8501 to 82.30034.641;2nd 82.30034.651;3rd 82.30034.681 from sourcer suggestion.
09/13
47
Change 1.8V power solution.
09/14
82
09/14
09/13
Change KBLIT1, PWRBTN2 and TPAD1 2nd source from 20.K0343.004 to 20.K0382.004.
09/14
75
Add R7503,R7504 and reserved EC7501,EC7502 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R.
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C
09/17
40,27,83
Rename PCIE_RST# to AD_IA_HW2 on KBC GPIO50 for power Tom suggest.

Reserved PQ4004,PR4036,PR4037 for AD_IA_HW2 function.
09/17
68
Rename CHARGER_LED1 to CHARGERLED1.

Rename FPOWER_LED1 to FPOWERLED1.
Rename HDD_LED1 to HDDLED1.
Rename TP_LOCK_LED1 to TPLOCKLED1.
Rename TP_LOCK_LED2 to TPLOCKLED2.
Rename WLAN_LED1 to WLANLED1
09/14
20
Reserved EC2004,EC2005 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
09/14
49
Reserved EC4910~EC4915 on LVDS signal for EMC suggestion.
09/15
58
Re-assign SPK1 pin define base on Roy updated excel file for 20.F0772.004
09/15
51
Add 2nd source 22.10296.311 on HDMI1 from updated connector list.
09/15
68
Add 2nd source 20.K0382.004 on PWRBTN1& PWRBTN2 base on updated connector list.
09/15
82
Re-assign CRTBD1 pin define base on EMC suggestion.
09/15
49
Change BLON_OUT_C to pin 15 and pin 4 to NC on LCD1.
X01
X01
09/15
28, 51,82
09/17
21,22
09/17
56
09/17
56
09/17
ALL
Add test point for WKS AFTE request.
Base on layout routing,Add RN2104 10K instead of R2111 10K.

Move EC_SCI#,DBC_EN to RN2201. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104.
Change R5605 to 100K from 10K and PH to 5V_S0 from 3D3V_S0 to meet Vgs>2V turn on.
Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing.
Change all of 0402 0ohm to 0R0402 short pad.
PR4008,PR4010,PR4012,PR4020,PR4023,PR4024,PR4027,PR4028,PR4029,PR4225PR4102,PR4113,PR4118,
PR4121,PR4203,PR4204,PR4215,PR4222,PR4231,PR4243,PR4301,PR4509,PR4510,PR4801,PR4804,PR4805,
PR4808,PR4810,PR9211
09/15
All
ADD 2nd source follow Power team suggestion.
09/15
92, 93
Modify PR9318 and PR9228 power source from 3D3V_AUX_S5 to 3D3V_S5.
09/15
86
Reserve Q8602, C8603 and R8606 for VGA over temp.
09/20
Add 2nd for TC901.
09/15
20
RN2005 swap net.
09/20
83
Add 2nd for L8303.
09/15
19
RN2005 swap net.
09/20
82
Add 2nd for LD8201.
F4902,PR4017,PR4018,PR4106,PR4611,PR4710,PR4807,R2304,R2403,R2406,R2409,R2702,R2902,R2903,R2904
R2305
09/15
48
Change PR4809 to 10K from 100K PH power source change to 3D3V_S0 from S5.
09/20
86
Add 2nd for Q8601.
09/15
82
Re-assign CRTBD1 pin define base on EMC suggestion.
09/20
83
Add R8321. C8353 and C8354 change to 12pF.
09/15
97
Reserved EC9701~EC9723 0.1uF for RF suggestion.
09/20
82
Redefine IOBD1.
09/15
41
Un-stuff PU4101,PD4105,PR4124, PR4125,PR4101 at X01 stage for 5mW issue.
09/20
75
AFTP111 and AFTP110 connect to USB_PP13_R and USB_PN13_R.
09/15
69
un-stuff R6907 and stuff R6905,Q6902,R6906 for 5V drive CAP LED.
09/20
51
Change P/N of Q5102.
09/17
82
Change IOBD1 part number to 20.F1849.080 base on Double updated latest DXF&EMN.
09/21
42
Change PU4201 VDD power source to 5V_S5 from 5V_S0 to avoid abnormal MVP_PWRGD waveform.
09/17
49,57
32,64
stuff TR4901 and un-stuff R4911,R4912 at X01 stage from EMC Neo suggestion.
09/21
47
stuff PC4714 22uF from Brian updated.
09/17
20
Change RN2010~RN2016 to 33ohm from 0ohm from EMC Neo suggestion.
09/17
37
Change R3710 to 100K from 0ohm to avoid impact 1.05VTT_PWRGD turn off sequence directly.
09/17
17
Add R1703~R1705 on RGB signal and reserved EC1701~EC1703 0.1u from EMC Neo suggestion.
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
1
104
of
108
VERSION
DATA
PAGE
Change Iteam
VERSION
DATA
PAGE
Change Iteam
09/21
45
Change PR4507 to 20K from 20.5K from Brian updated.
09/27
09/21
46
Change PR4602 to 110K from 68K from Brian updated.
09/27
69
AFTP73 connect to TP_VDD.
09/21
42
Change PR4217 to 1.27K from 1K from Brian updated.

Change PR4213 to 3.6K from 3.16K from Brian updated.
Change PR4236 to 3.01K from 3.32K from Brian updated.
09/27
85
U8501 power change to 3D3V_S0.
09/27
92
PL9201 change like CPU core power choke.
Change PC4410 to 0.01u from 0.022uF from Brian updated.
09/28
83, 84
L8303, L8401, L8402, L8502 and L8503 follow NV DG spec.
09/21
44
TR4901, TR4902, TR5701, TR3201 and TR6401 DY. Stuff 0 ohm.
09/21
39
Add 2nd 83.00099.K11;3rd 83.00099.T11 on D3901,D3902,D3903 from Sourcer Eden suggestion.
09/28
46
Change PR4606 to 4.02K from 240ohm for fine tune 1.5V output Voltage.
09/21
39
Add 2nd 84.02143.011;3rd 84.00143.N11 on 6801,Q6804,Q6805,Q6806,Q6807,Q6808

from Sourcer Eden suggestion.
09/28
92
PTC9202, PTC9203 and PTC9204 2nd=79.47719.9BL
09/28
22
Change R2220 to 10K from 100K.
09/21
43
Change PU4303,PU4306,PU4309 dummy field only for QC CPU stuff.

Change PC4307,PC4316 dummy field only for QC CPU stuff.
Add 2nd for PTC4306.
09/28
60
EC6001 change to 10p from 4.7p and default un-stuff from Neo suggestion.
EC1801 change to 10p from 4.7p and default un-stuff from Neo suggestion
09/21
41
PD4101, PD4103, PD4104 and PD4105 add 2nd source.
09/21
69
Q6902 add 2nd source.
09/28
27
Change R2710, R2739, R2724 and R2726 change to 1%.
09/21
40
PD4001 add 2nd source.
09/29
27
Default mount R2756, Dummy R2734.
09/21
19
move PCH_WAKE# to RN1901 pin4;Add R1909 PH 100K on AC_PRESENT.
10/04
24
Add 2nd source 68.1001E.10N on L2401,L2402,L2403 from sourcer Renee Lee updated.
09/21
37
R3710 change to 0ohm. Remove R3701 and C3701.
10/07
43
PTC4306 cahnge second source to 79.47612.60L.
09/21
42
Add PR4214, PC4230, PR4216 and PC4231 from Brian updated.
10/09
85
Change L8503 to 68.00375.091,and add second source 68.00206.171
09/23
20
RN2016, RN2010, RN2011, RN2012, RN2014 and RN 2013 keep 0ohm.
10/09
85
09/23
ALL
PR9216, R504, R1812,R1813,R1815,R1817, R1903, R1906,R1910,R1912,R1913,R1924,R1925, R2213,R2219,

R2711,R2720,R2733,R2761, R2807,R2814, R3708, R5125, R5127, R5721, R5722.
10/09
84
Change L8401 and L8402 to 68.00115.181,and add second source 68.00206.341
10/09
83
09/23
75
Add R7505~R7508 0ohm and reserved EC7503~EC7506 on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508 on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
10/09
83
09/23
ALL
RN5101, RN2201, RN1702, RN1901, RN1705 swap pin.
10/09
42
Change PR4217 to 64.84505.6DL for Dual-core OCP
09/23
79
DUMMY G-SENSOR.
10/09
42
Change PR4213 to 64.23715.6DL for Dual-core loadline
09/23
92
Update value of PR9210, PR9209 and PR9213 for N12P.
10/09
42
Change PR4207 to 64.22025.6DL for CPU(35W) Turbo setting
09/23
43
PR4320 change to 4 m ohm.
10/09
42
Change PR4202 to 64.22025.6DL for GFX Turbo setting
09/23
68
Add 2nd source 83.00110.J70 on FPOWERLED1,HDDLED1,WLANLED1 from Sourcer Anya suggestion.

Add 2nd source 83.00326.G70 on CHARGERLED1from Sourcer Anya suggestion.
Add 2nd source 83.00190.Z70 on TPLOCKLED1,TPLOCKLED2 from Sourcer Anya suggestion.
10/09
20,83
10/19
28
Change R2817 from 107K to 124K (64.12435.6DL) for VGA temperature setting change
Change R8402 from 40D2R to 60D4R (64.60R45.6DL) for meeting the spec
X01
49, 57
32, 64
X01
Dummy R2004 R2003 and PQ8309, stuff R2005
09/23
69
Change KBLIT1 part number to 20.K0589.004 and re-assign pin define base on Roy updated.
10/25
84
09/23
42, 44
Add 2nd source 69.60011.201 on PR4405,PR4245 from Sourcer Kitty suggestion.
10/25
14 15
09/23
42
Add 2nd source 69.60037.021 on PR4246,PR4247 from Sourcer Kitty suggestion.
10/25
85
09/24
23
Add 2nd source 68.00214.211 on L2301 updated from DN13ATI.
11/01
51 85
09/24
68, 69
Change R6806,R6808,R6811~R6813,R6801,R6803,R6815,R6906 to 390ohm from 1K to fine tune all of MB LED

for 5mA spec.
11/10
27
Change R2724 to 64.33025.6DL for PCB version change
11/10
83
X02
Add DM1 and DM2 second source:62.10017.Q41 and 62.10017.P61

Ventura SMBC_INA219_C and SMBD_INA219_C add 3.3V pull high schematic
Change HDMI HPD schematic for cost down
09/27
51
Reserve R5114 and R5115.
09/27
85
Reserve R8510 and R8513.
09/27
83
DY U8301, mount R8323.
09/27
92
R9206 change to 10K, PC9211 mount 0.1u.
Title
09/27
93
R9312 change to 1K.
Size
A3
<Core Design>
Wistron Corporation
Date:
5
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
1
105
of
108
VERSION
DATA
PAGE
Change Iteam
VERSION
DATA
PAGE
Change Iteam
11/11
14
DM2 1st change to 62.10017.P61; 2nd change to 62.10017.N41 on ST stage from ME updated connector list.
11/18
28
Rename U2801&U2804 pin 8 to THERM_SYS_SHDN#_OTZ from HERM_SYS_SHDN#.
11/11
15
DM1 1st change to 62.10017.Q41; 2nd change to 62.10017.N11 on ST stage from ME updated connector list.
11/18
20
Change X2001 to 82.30020.D41 from 82.30020.851 from Sourcer Dick updated.
11/18
23
Reserved R2308,R2309 on VCCVRM power rail.Reserved U2302 LDO circuit on VCCVRM power rail
11/11
60
U6001 1st change to 72.25Q32.A01; 2nd change to 72.25320.C01; 3rd change to 72.25P32.C01 on ST stage
11/18
22 82
Rename USB3_PWR_ON to PCH_GPIO57.

Add R8209,R8210 for PM_SLP_S4# and VGA_THRM to control USB3_PWR_ON
11/11
68
Change CHARGERLED1 2nd to 83.00327.D70 from Sourcer updated.
11/11
37
Change U3701 1st to 73.7SZ08.EAH;2nd to 73.01G08.L04;3rd to 73.7SZ08.DAH from

Sourcer Eason updated.
11/18
48
Change PTC4801 to 100u(77.21071.07L) from 150u from power team Brian updated
11/19
74
Add 2nd 20.I0135.001 on CARD1 from ME updated connector list.
11/11
69
Add 2nd 20.K0592.030 on KB1 from ME updated connector list.

11/19
82
Add 2nd 20.F1908.080 on IOBD1 from ME updated connector list.
11/20
Updated PCIE ROUTING
11/20
28
Change U2801,U2804,U2805 VCC power to 3D3V_DAC_S0 from 3D3V_S0.

Stuff R2812, un-stuff R2805
11/20
23
Reserved R2308 on VCCVRM power rail.

Reserved U2302 LDO circuit on VCCVRM power rail.
11/20
48
Set TPS51461 PWM solution dummy field for VCCSA_PWM and APL5916 LDO solution dummy field for
VCCSA_LDO. defualt stuff VCCSA_LDO at ST stage
11/20
22
Rename GFX_CRB_DET to GSENSOR_DET on GPIO39.
11/20
60
Un-stuff R6007 10M.
11/20
82
Reserved EC8201,EC8202 0.1u(closed H3) between AGND and GND from EMC Neo suggestion.
11/20
82
Reserved EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
11/11
82
Add 2nd 20.K0465.008 on MEDIA1 from ME updated connector list.
11/11
58
Add 2nd 20.F1804.004 on SPK1 from ME updated connector list.
11/11
28
Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.
11/11
70
Add 2nd 20.F0962.010 on HALL1 from ME updated connector list.
11/11
23
X02
Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.
X02
11/11
60
Add Q6002,R6007 fo FACTORY RTC detect function
11/11
28
ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.
11/11
28
Reserved G709T1UF for T8 solution sync with DN13.
11/12
82
Change R8201, R8202, R8203 from 430 ohm to 1K ohm (63.10234.1DL) for soluting media board LED
brightness is too light issue
11/15
49
Add 2nd 20.F1860.030 on LCD1 from ME updated connector list.
11/20
82
Add RN8205 base on HSYNC&VSYNC report
11/15
Reserved C802~C804,C806,C807 10uF 0603 for power team fine tune Vcore quality
11/20
61
Removed R6101 and connect USB_PWR_EN# to U6101 pin4 directly.
11/20
22
Rename PCH_GPIO12 to RTC_DET# on GPIO12.
11/15
88 89
90 91
All of VRAM(VRAM1~VRAM8) PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from

BGA96D0913H48 same as DW30.
11/20
61 22
18
Reserved U6102 USB POWER related circuit to separate EATA and CRT USB power in ST build.
Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
11/20
82
Reserved R8211,R8212 0ohm 0805 on CRTBD1 pin37,39 to separate EATA and CRT USB power in ST build.
11/22
82
Swap RN8205 pin4,3 and pin2,1 each other base on Connie swap report.
11/22
82
stuff EC8201,EC8202 0.1u(closed H3) between GND and GND from EMC Neo suggestion.
stuff EC8206 between 3D3V_S5 and GND from EMC Neo suggestion.
11/22
23
base on layout condition change 3D3V_DAC_S0 circuit. Stuff R2301 and un-stuff L2301.
11/22
82
stuff EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
11/22
23
Removed U2302 LDO for VCCVRM.
68
69
Change R6813, R6906 from 390 ohm to 1K ohm (63.10234.1DL) for soluting LED
11/15
20
Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1 at ST stage.
11/16
97
Change HHD1 HDD4 HGPU1 HGPU2 2nd from 34.4CK01.201 to 34.4CK01.401 from ME update connector list
11/16
68
Change R6808, R6811 from 390 ohm to 1K ohm (64.10234.1DL) for soluting LED
11/15
11/16
28
stuff both G709T1UF and P2800 related circuit, add R2805 0ohm default un-stuff at ST stage.
11/17
48
CO-LAY APL5916 related circuit for VCCSA LDO solution.
23
Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.
Stuff R2301 and un-stuff L2301.
<Core Design>
A
11/18
Wistron Corporation
Title
11/18
28
Add R2805 0hm between THERM_SYS_SHDN#_OTZ and THERM_SYS_SHDN#.

Add R2812 0ohm between THERM_SYS_SHDN# and U2805 pin3.
Size
A3
Date:
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
106
1
of
108
VERSION
DATA
PAGE
11/22
Change Iteam
VERSION
DATA
PAGE
Change Iteam
29
change R2920,R2921 to 22ohm from 0ohm and stuff EC2901,EC2902 22p from EMC Neo updated.
11/24
57
Add 2nd(22.10339.261)on ESATA1 from Karl updated.
11/24
28
un-stuff VGA P2800 related circuit from Niki confirmed.
11/22
61
Change U6101 to dual USB power switch from single for Layout limitation and placement.
Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
11/24
64
rename C6401,C6402,C6403 to EC6401,EC6402,EC6403
11/22
49
stuff C4908 0.1uF from EMC Neo suggestion.

11/24
22
Dummy R2206
11/25
28
Dummy R2817 R2818 C2816
11/25
69
Add 3rd(83.00110.R70) on FPOWERLED1,HDDLED1,WLANLED1 from Anya provide
11/25
69
Add 3rd(83.00192.J70) on TPLOCKLED1 and TPLOCKLED2 from Anya provide.
11/25
69
Add 3rd(83.01108.070) on CHARGERLED1 from Anya provide.
11/26
43 92
11/29
83
X02
11/22
57
Change TR5701 to 69.10103.041 and un-stuff R5718,R5719 from EMC Neo Suggestion.
11/22
49
Change TR4902 CM choke to 69.10103.041 and un-stuff R4908,R4909 from EMC Neo Suggestion.
11/22
49
Swap TR4901 pin4,3 and pin2,1 each other base on Connie swap report.
11/22
75
11/22
58
stuff EC5801~EC5804 470pF from EMC Neo suggestion.
11/22
9 39
45 49
stuff EC901, EC3903, EC4501, EC4909, EC4907 0.1uF from EMC Neo suggestion.
11/22
49
Change RN4901 to 100ohm 4p from 8p for improve layout place.
11/22
48
Updated VCCSA_LDO circuit from Power team Brian updated.
83 84 85
11/22
60
11/23
49 57 75
Change C8353 C8354 to 15PF ,R8320 stuff from vendor suggestion.

C
11/29
36
Stuff D3602
Change L8301 L8401 L8402 to 0 ohm resistor (63.00000.00L)
11/30
68
Change 2nd source to 83.00322.070 from 83.00110.J70
stuff R6007 10M.
11/30
85
Change L8502 L8503 to 0 ohm
11/30
92
Stuff PR9237 DY PR9321
X02
11/22
Change PC9217 PC4319 to 0.1u 50V
SWAPTR4901 TR4902 TR5701 TR7501 pin1&4 and pin2&3 each other base on Connie swap report.
12/01
Change C837,C826 to 22uF from 10uF and default stuff from Power Brian updated.
11/23
60
Change U6101 1st(74.02182.071);2nd(74.00546.A7D);3rd(74.02062.079) from Sourcer Harrison suggestion.
12/01
Change C801~C807 and C817 10uF stuff at QC CONFIG from power Brian updated.
11/23
64
Add C6402 0.1uF,C6403 180pF and stuff C6401 47pF from RF fine tune result.
12/21
ALL
11/23
57 49 75
Change R5718,R5719,R4908,R4909,4911,R4912,R7501,R7502 to 0ohm 0603 from 0402.
11/23
56 97
11/23
97
stuff EC9739,EC9737,EC9735 47pF from RF fine tune result.

stuff EC5601 180pF from RF fine tune result.
Stuff EC9738 0.22uF closed EC9739 from RF fine tune result.
45
82
12/21
17 20
Change resistor pad(ZZ.0R04P.ZZZ): RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2015 RN2016
12/21
83 84 85
Change L8301, L8401,L8402,L8502,L8503 to 0R0603 pad(ZZ.00PAD.M21)
12/21
ALL
Change to Parallel resistor

R1501 ,R1502; R2739 ,R2774;R8202 ,R8203;R8501 ,R8502;R8506 ,R8507;R2123 ,R2124
12/21
82
RN8205 change to R8201, R8202
12/21
93
PR9237 rename to PR9337
stuff ECEC9729,EC9730 470pF from EMC Neo suggestion.
Change PR4501 to 75K from 45.3K for 1.05V OCP set to 20A from Brian.
11/23
82
Removed R8211,R8212 and connect 5V_USB2_S3 to CRTBD1 pin 37 directly.
11/23
61
Removed C6105,C6103.
11/23
69 70
12/21
A00
11/23
Change 0402 pad(ZZ.00PAD.M11): R1404 R1405 R1503 R1504 R1703 R1704 R1705 R1807 R2301 R2306
R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R2762 R3614 R3710 R5114 R5801
R5802 R5803 R5804 R8210 R8323 R8511 R8512
12/21
56 61 68
Change 0603 pad(ZZ.00PAD.M21): R8206 R8207
Delete 77.C1071.21L(TC6101), delete 83.01108.070(CHARGERLED) , delete 62.10065.121(HDD1)
Change AFTP 80 81 to AFTP 83 84; change AFTP 83 to AFTP82; change AFTP 82 to AFTP85.
<Core Design>
11/24
20
Add 2nd(82.30020.G71);3rd(82.30020.G61) on X2001 from Sourcer Dick updated.
11/24
69
Add 2nd(20.K0613.004)on KBLIT1 from Karl updated.
Wistron Corporation
Title
Size
A3
Date:
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
1
107
of
108
VERSION
DATA
PAGE
Change Iteam
12/22
27
R2724 change to 47K resistor for XBulid
12/28
27
Change R2756, R2763, R2766 to short pad
12/22
27
R2301 change to 0 resistor for CRT debug
12/28
36
Stuff Q3603
28 86
Cancel VGA Thermal sensor P2800 ciruit
40
1.Change PR4032,PR4034,PR4037 to ZZ.00PAD.M11

2.Stuff PQ4003,PQ4004
3.Change PR4047 to 174K(64.17435.6DL)
4.Change PR4035 to 300K(64.30035.6DL)
5.Change PR4036 t0 76.8K(64.76825.6DL)
6.Change PR4031 to 150K(64.15035.6DL)
12/28
12/22
12/28
27 28 82
12/23
VERSION
PAGE
Change Iteam
1.FPOWERLED1 rename to FPLED1

2.HDDLED1 rename to HDLED1
3.CHARGERLED1 renamtpe to CHLED1
4.WLANLED1 rename to WLED1
5.TPLOCKLED2 rename to TPLED2
6.TPLOCKLED1 rename to TPLED1
7.PWRBTN1 rename to PWRBT1
8.PWRBTN2 rename to PWRBT2
68
DATA
Change to VGA_THRM to USB3_PWR_ON
12/28
23
Change R2301 to short pad
12/29
51
Change HDMI resistor to short pad
12/29
49,57,75
Delete USB DUMMY resistor for no-lay
12/29
32
Change USB 0 resistor to short pad for no-lay
12/29
Reserve EC502 ,EC504 for EMI suggestion,add DUMMY EC505 for EMI
12/29
82
Delete PM_SLP_S4# line, directly link to USB3_PWR_ON
12/23
43
Delete PR4323,PR4324,PR4325;
Stuff PR4320 for all BOM ,not co-lay Ventura
12/23
92
Delete PR9220,PR9222,PR9223;
Stuff PR9217 for all BOM ,not co-lay Ventura
12/23
51
Change 5V_HDMI to 5V_CRT_S0_R for HDMI power leakage
12/29
23
Add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config
12/29
68
Not use Liteon LED(83.00322.070) for package
12/30
Add DUMMY diode EC506 for BUF_CPU_RST# as EMI suggestion
All
PRN3901 rename to PN3901

PTC9202~04 rename to PT9202~04
PTC4306 rename to PT4306
12/30
42
PC4227 change to 78.33420.5FL as 78.33423.5FL obsoleted
12/30
49
Change R4904 to short pad
12/31
86
Add probe point for P2800_VGA_DXN/P2800_VGA_DXP
01/03
68
Change TPLED1,2 1st to 83.01921.P70 ,2nd to 83.00190.S7A,3rd to 83.00191.H70;

R6813 change to 390R from 1K same as DN13 LED part.
01/03
49
Delete R4908, R4909 for USB_Camera not co-lay
01/03
4~10
Add 3rd foxconn(62.10055.321) on CPU1 at X-Build batch run config
01/03
82
Add 3rd T-conn(20.F1932.040) on CRTDB1at X-Build batch run config
01/03
97
Add 3rd LIDON(34.4CK01.501) on HHD1,HHD4,HGPU1,HGPU2 at X-Build batch run config
01/04
68
Delete 83.00191.H70 for TPLED1,2 as cost high
12/24
A00
A00
12/24
28
Change U2802 3rdto 74.05606.A71 at X-Build batch run
12/24
82
Change RN8205 to 66.22036.04L from 66.22036.040at X-Build stage
12/24
82
Reserved R8211 0603 0ohm on F8201
12/24
36
Reserved Q3603 2N702 on IMVP_PWRGD to fine tune glitch waveform when AC lose and DC lose.
12/24
28
Change 3D3V_S0 to 3D3V_DAC_S0
12/24
45 46 93
Change to short pad:

PR4502,PR4607,PR9311,PR9312,PR9326.
DUMMY PC4501
12/27
28
If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
12/27
42
PR4207,PR4213,PR4217 DUMMY field set to DC&QC option
01/04
49,57,75
Add 2nd TAI-TECH(69.10084.071) on TR4901,TR4902,TR5701,TR7501 at X-Build batch run config
<Core Design>
Wistron Corporation
12/28
51

Change 5V_HDMI to 5V_CRT_S0_R on RN5101

Title
12/28
28
Size
A3
Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at XBuild
Date:
Change History
Document Number
Rev
QUEEN 15
A00
Sheet
of
108
108

Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge Rev A00 SCH

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Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge Rev A00 SCH

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5

Discrete/UMA Schematics Document

Tuesday, January 04, 2011

DDRIII 1066/1333 Channel B

14 USB 2.0/1.1 ports

USB 2.0 x 1BPCIE X 1

VOSTRO Express Card

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

PCIE ports (8)

High Definition Audio

Internal Digital MIC

SATA ports (6)

ATI : Co-layout HDMI coming from UMA(default) &

NVidia : Co-layout HDMI coming from dGPU(Default) &

Project code : 91.4IE01.001

Huron River Schematic Checklist Rev.0_7

Reboot option at power-up

Weak internal pull-up. Leave as "No Connect".

GNT[3:0]# functionality is not available on Mobile.

Configuration (Default value for each bit is

PEG DEFER TRAINING

1: PEG Train immediately following xxRESETB de assertion

ON for supporting Deep Sleep states

Powered by Li Coin Cell in G3

Disable Danbury:Leave floating (internal pull-down)

Low (0) - Flash Descriptor Security will be overridden. Also,

DMI termination voltage. Weak internal pull-up. Do not pull low.

11 : x16 - Device 1 functions 1 and 2 disabled

Disable Danbury:Left floating, no pull-down required.

15 -> 0, 14 -> 1, ...

Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Disabled - No Physical Display Port attached to

Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm

AC Brick Mode only

Mini Card1(WLAN) SATA

Intel GBE LAN

Touch Panel / 3G SIM

USB Ext. port 1 (HS)

Mini Card2 (WWAN)

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2

USB Ext. port 3

Mini Card1 (WLAN)

HURON RIVER ORB

Tuesday, January 04, 2011

Signal Routing Guideline:

Signal Routing Guideline:

PCI EXPRESS* - GRAPHICS

PEG Static Lane Reversal

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

Tuesday, January 04, 2011

A00 1229 EMI

22,36 H_CPUPW RGD

Connect EC to PROCHOT# through inverting OD buffer.

A16 CLK_DP_P_R 1 R512

Signal Routing Guideline:

JTAG & BPM

A00 1230 EMI

A00 0103 add 3rd foxcon CPU1 at XBuild batch run

A00 1229 EMI

Buffered reset to CPU

Tuesday, January 04, 2011

DDR SYSTEM MEMORY A