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  • Self-Assessment Problem 6-6: Answer Time (NS) Routine

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    Richard Mcdaniel
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    The CPU executes the main program from 0-10 nanoseconds. From 10-30 nanoseconds it handles the highest priority interrupt IRQ5. From 30-50 nanoseconds it handles the next highest priority interrupt IRQ3. From 50-60 nanoseconds it handles the lowest priority interrupt IRQ1, since it had to wait for the other interrupts to complete first.

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    Self Test

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    Self-Assessment+6-6

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    The CPU executes the main program from 0-10 nanoseconds. From 10-30 nanoseconds it handles the highest priority interrupt IRQ5. From 30-50 nanoseconds it handles the next highest priority interrupt IRQ3. From 50-60 nanoseconds it handles the lowest priority interrupt IRQ1, since it had to wait for the other interrupts to complete first.

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    © All Rights Reserved
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    11 visualizações1 página

    Self-Assessment Problem 6-6: Answer Time (NS) Routine

    Enviado por

    Richard Mcdaniel
    The CPU executes the main program from 0-10 nanoseconds. From 10-30 nanoseconds it handles the highest priority interrupt IRQ5. From 30-50 nanoseconds it handles the next highest priority interrupt IRQ3. From 50-60 nanoseconds it handles the lowest priority interrupt IRQ1, since it had to wait for the other interrupts to complete first.

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato DOCX, PDF, TXT ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    de 1

    Self-Assessment problem 6-6

    For the following set of events, show which routine the CPU is executing for times 0 to 100
    nanoseconds (ns). Each handler routine (with its interrupt request) takes 20 ns to complete. The
    priority of the interrupts ranges from IRQ6 as the highest priority interrupt to IRQ1 as the lowest
    priority interrupt.
    Time

    Action

    0 ns

    start of main program

    10 ns

    IRQ5

    20 ns

    IRQ3

    45 ns

    IRQ1

    60 ns

    IRQ4

    Answer
    Time
    (ns)

    Routine

    1 to
    10

    main

    10 to 30

    IRQ5

    30 to 50

    IRQ3

    50 to 60

    IRQ1, because IRQ1 has to wait until 50 ns for the higher


    priority interrupt to complete

    60 to 80

    IRQ4, because IRQ4 is higher priority than IRQ1 at 60 ns

    80 to 90

    IRQ1

    90 to 100 main

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