`timescale 1ns/1ps

module dataroute (clk,Dadd,Write,Aadd,Badd,ConsIn,MB,FS,MD,DataIn,DataOut,AddOut

,V,C,N,Z); // creacion modulo dataroute( Ruta de Datos)
input [15:0] DataIn, ConsIn;
input [3:0] FS;
input MB,MD,Write,clk;
input [2:0] Aadd, Badd, Dadd; // Aadd -> Direccion A registro
output V,C,N,Z;
output [15:0] DataOut, AddOut;
wire [15:0] WD,WA,WB1,WB2,WF;
assign DataOut = WB2;
assign AddOut = WA;
regbank BANK (clk,WD,Dadd,Write,Aadd,Badd,WA,WB1);
MUX MUX_B (WB1,ConsIn,MB,WB2); // Multiplexor B
MUX MUX_D (WF,DataIn,MD,WD); // Multiplexor D
//ALU_unit ALU (WF,V,C,N,Z,WA,WB2,FS);
fuction_unit ALU (WF,V,C,N,Z,FS,WA,WB2);

endmodule
/*module tb;
dataroute ROUTE (clk,Dadd,Write,Aadd,Badd,ConsIn,MB,FS,MD,DataIn,DataOut,AddOut,
V,C,N,Z);
reg [15:0] DataIn, ConsIn; // Registros de 16 bits de palabra
reg [3:0] FS;
reg MB,MD,Write,clk;
reg [2:0] Aadd, Badd, Dadd;
wire V,C,N,Z;
wire [15:0] DataOut, AddOut;
initial clk = 0; // Inicializamos la seal de reloj a 0
always #20 clk = ~clk; // Seal de reloj de T=40 ns (20 ns de subida)
initial Write = 0;
initial begin // Test bench
#0 ConsIn = 16'd0; // #0 -> Retardo = 0, 16' -> 16 bits, d0 -> d (bas
e decimal) = 0
MB = 0;
MD = 1;
DataIn = 16'd0;
Write = 1;
Dadd = 3'd0;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0; // Retardo 40 ( =40ns)
MB = 0;
MD = 1;
DataIn = 16'd1;
Write = 1;
Dadd = 3'd1;
Aadd = 0;

Badd = 0;
#40 ConsIn = 16'd0; // Retardo 40 ( =80ns)
MB = 0
MD = 1;
DataIn = 16'd2;
Write = 1;
Dadd = 3'd2;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0;
MB = 0;
MD = 1;
DataIn = 16'd3;
Write = 1;
Dadd = 3'd3;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0;
MB = 0;
MD = 1;
DataIn = 16'd4;
Write = 1;
Dadd = 3'd4;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0;
MB = 0;
MD = 1;
DataIn = 16'd5;
Write = 1;
Dadd = 3'd5;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0;
MB = 0;
MD = 1;
DataIn = 16'd6;
Write = 1;
Dadd = 3'd6;
Aadd = 0;
Badd = 0;
#40 ConsIn = 16'd0;
MB = 0;
MD = 1;
DataIn = 16'd7;
Write = 1;
Dadd = 3'd7;
Aadd = 0;
Badd = 0;
// Hasta aqu inicializamos los registros con su valor R0=0,...
#105 Aadd = 7;
Badd = 0;
Write = 1;
Dadd = 7;
ConsIn = 0;
MB = 0;
FS = 1;
DataIn = 0;
MD = 0;
#40 Aadd = 1;

Badd = 2;
Write = 1;
Dadd = 6;
ConsIn = 0;
MB = 0;
FS = 2;
DataIn = 0;
MD = 0;
#40 Aadd = 3;
Badd = 7;
Write = 1;
Dadd = 4;
ConsIn = 0;
MB = 0;
FS = 3;
DataIn = 0;
MD = 0;
#40 Aadd = 1;
Badd = 0;
Write = 1;
Dadd = 2;
ConsIn = 0;
MB = 4;
FS = 4;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 7;
Write = 1;
Dadd = 5;
ConsIn = 0;
MB = 0;
FS = 5;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 7;
Write = 1;
Dadd = 5;
ConsIn = 0;
MB = 0;
FS = 6;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 6;
Write = 1;
Dadd = 7;
ConsIn = 0;
MB = 0;
FS = 8;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 2;
Write = 1;
Dadd = 2;
ConsIn = 0;
MB = 0;
FS = 9;

DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 6;
Write = 1;
Dadd = 5;
ConsIn = 0;
MB = 0;
FS = 4'ha;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 6;
Write = 1;
Dadd = 2;
ConsIn = 0;
MB = 0;
FS = 4'hb;
DataIn = 0;
MD = 0;
#40 Aadd = 1;
Badd = 5;
Write = 1;
Dadd = 5;
ConsIn = 0;
MB = 0;
FS = 4'hd;
DataIn = 0;
MD = 0;
#40 Aadd = 1;
Badd = 4;
Write = 1;
Dadd = 4;
ConsIn = 0;
MB = 0;
FS = 4'he;
DataIn = 0;
MD = 0;
#40 Aadd = 4;
Badd = 5;
Write = 1;
Dadd = 4;
ConsIn = 0;
MB = 0;
FS = 4'h2;
DataIn = 0;
MD = 0;
#40 Aadd = 5;
Badd = 0;
Write = 1;
Dadd = 5;
ConsIn = 16'h0ff1;
MB = 1;
FS = 4'h5;
DataIn = 0;
MD = 0;
#40 Aadd = 0;
Badd = 5;
Write = 1;
Dadd = 0;

ConsIn = 0;
MB = 0;
FS = 4'hc;
DataIn = 0;
MD = 0;
#80 $finish;
end
initial begin
$dumpfile("dataroute.vcd");
$dumpvars(V,C,N,Z,DataOut,AddOut,tb);
end
endmodule*/

//Function_Unit.v
//ALU_unit
//
//ALU_unit.v
module ALU_unit (G,V,C,N,Z,A,B,G_select);
output V,C,N,Z;
output [15:0] G;
input [15:0] A,B;
input [3:0] G_select;
//retardo anterior #20
assign #20 {C,G} = (G_select == 4'h0)?{1'b0, A}:
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
(G_select ==
{1'b0,~A};

4'h1)?A + 1:
4'h2)?A + B:
4'h3)?A + B +1:
4'h4)?A + {1'b0,~B}:
4'h5)?A + {1'b0,~B} + 1'b1:
4'h6)?A + {1'b0, 16'hFFFF}:
4'h7)?{1'b0, A}:
4'h8)?{1'b0, A & B}:
4'h9)?{1'b0, A | B}:
4'ha)?{1'b0, A ^ B}:
4'hb)?{1'b0,~A}:
4'hc)?{1'b0, A & B}:
4'hd)?{1'b0, A | B}:
4'he)?{1'b0, A ^ B}:

assign V = (G_select == 4'h0)?1'b0:

(G_select == 4'h7)?1'b0:
(G_select == 4'h8)?1'b0:
(G_select == 4'h9)?1'b0:
(G_select == 4'ha)?1'b0:
(G_select == 4'hb)?1'b0:
(A[15]&B[15]&~G[15])|(~A[15]&~B[15]&G[15]);
assign N = G[15];

//assign #2 Z = ~|G;
assign Z = (G == 4'h0)?1'b1:1'b0;
endmodule
//
//
//desplazador
//
module desplazador (H,B,S);
output [15:0] H;
input [15:0] B;
input [1:0] S;
assign #5 H =

(S == 2'b00)?B:
(S == 2'b01)?B>>1:
B<<1;

endmodule
//
//
//
//Function_Unit
//
module MUX_F (F,w1,w2,MF_select);
output [15:0] F;
input [15:0] w1, w2;
input MF_select;
assign F = (MF_select == 1'b0)?w1:w2;
endmodule
module fuction_unit(F,V,C,N,Z,FS,A,B);
output [15:0] F;
output V,C,N,Z;
input [15:0] A, B;
input [3:0] FS;
wire [15:0] w1, w2;
wire [3:0] G;
wire [1:0] H;
wire MF;
ALU_unit ALU (w1,V,C,N,Z,A,B,G);
desplazador SHIFTER (w2,B,H);
MUX_F MUX (F,w1,w2,MF);
assign
assign
assign
assign
assign
assign
assign

MF =
G[3]
G[2]
G[1]
G[0]
H[1]
H[0]

FS[3]&FS[2];
= FS[3];
= FS[2];
= FS[1];
= FS[0];
= FS[1];
= FS[0];

endmodule
`timescale 1ns/1ps
module MUX(A,B,MF,O);
input [15:0] A, B;
input MF;
output [15:0] O;
reg [15:0] O;
initial
O = 16'h0000;
always @ (A or B or MF)
begin
if (MF == 0)
O <= #2 A;
else
O <= #2 B;
end
endmodule

`timescale 1ns/1ps
module regbank (clk,D,Dadd,Write,Aadd,Badd,A,B);
input [15:0] D;
input [2:0] Dadd, Aadd, Badd;
input clk, Write;
output [15:0] A, B;
output [15:0] R0, R1, R2, R3, R4, R5, R6, R7;
reg [15:0] A,B,R0, R1, R2, R3, R4, R5, R6, R7;
//reg [15:0] R [7:0]; -> Banco de registros definidos como una memoria.
/*assign R0
assign R1 =
assign R2 =
assign R3 =
assign R4 =
assign R5 =
assign R6 =
assign R7 =

= R[0];
R[1];
R[2];
R[3];
R[4];
R[5];
R[6];
R[7];*/

reg [15:0] addr; // No haria falta si definimos los registros individualmente, h

aria falta si los definimos como una memoria.
/*initial
begin
addr = 0;
repeat (8)
begin
R[addr] = addr;
addr = addr + 1;

end
end*/
/*initial //
begin
R0 =
R1 =
R2 =
R3 =
R4 =
R5 =
R6 =
R7 =
end*/

Inicializamos todos los registros a 0.

3'd0;
3'd0;
3'd0;
3'd0;
3'd0;
3'd0;
3'd0;
3'd0;

always @ (posedge clk) // Se ejecuta el procedimiento en el flanco de subida de

reloj.
begin
if (Write == 1)
//R[Dadd] <= #3 D;
case (Dadd) // Si Write = 1, en el registro que apunte Daad (met
emos el dato D). Ej: si Daad = 2, en el registro R2 se comprueba si es menor o i
gual que el dato D.
3'd0: R0 <= #3 D;
3'd1: R1 <= #3 D;
3'd2: R2 <= #3 D;
3'd3: R3 <= #3 D;
3'd4: R4 <= #3 D;
3'd5: R5 <= #3 D;
3'd6: R6 <= #3 D;
3'd7: R7 <= #3 D;
endcase
end
always @ (Aadd or Badd or R0 or R1 or R2 or R3 or R4 or R5 or R6 or R7)
begin
/*A <= #2 R[Aadd];
B <= #2 R[Badd];*/
case (Aadd)
3'd0: A <=
3'd1: A <=
3'd2: A <=
3'd3: A <=
3'd4: A <=
3'd5: A <=
3'd6: A <=
3'd7: A <=
endcase
case (Badd)
3'd0: B <=
3'd1: B <=
3'd2: B <=
3'd3: B <=
3'd4: B <=
3'd5: B <=
3'd6: B <=
3'd7: B <=
endcase
end

#2
#2
#2
#2
#2
#2
#2
#2

R0;
R1;
R2;
R3;
R4;
R5;
R6;
R7;

#2
#2
#2
#2
#2
#2
#2
#2

R0;
R1;
R2;
R3;
R4;
R5;
R6;
R7;

endmodule