Escolar Documentos
Profissional Documentos
Cultura Documentos
Decodor
---------------------------------------------------------------------------------------------------------------------module Decodor( output reg [3:0] out,
input [1:0] in
);
always@(*) begin
case (in)
2'b00 : out <= 4'b0001;
2'b01 : out <= 4'b0010;
2'b10 : out <= 4'b0100;
2'b11 : out <= 4'b1000;
default : out <= 4'b0000;
endcase
end
endmodule
Transcodor
-------------------------------------------------------------------------------------------------------------------------module Trasncodor( output reg[7:0] out,
input [3:0] in
);
always@(*) begin
case(in)
4'd0: out[7:0] = 8'b10000001;
4'd1: out[7:0] = 8'b11001111;
4'd2: out[7:0] = 8'b10010010;
4'd3: out[7:0] = 8'b10000110;
4'd4: out[7:0] = 8'b11001100;
4'd5: out[7:0] = 8'b10100100;
4'd6: out[7:0] = 8'b10100000;
4'd7: out[7:0] = 8'b10001111;
4'd8: out[7:0] = 8'b10000000;
4'd9: out[7:0] = 8'b10000100;
4'hA: out[7:0] = 8'b10001000;
4'hB: out[7:0] = 8'b11100000;
4'hC: out[7:0] = 8'b10110001;
4'hD: out[7:0] = 8'b11000010;
4'hE: out[7:0] = 8'b10110000;
4'hF: out[7:0] = 8'b10111000;
endcase
end
endmodule
PMW_generator
Numarator
----------------------------------------------------------------------------------------------------------------module Numarator#(parameter NR_BITI = 8 // modul parametrizabil, pot sa
specific numarul de biti al numaratorului (daca nu specific, implicit pe 8 biti)
)
(output reg [NR_BITI-1:0] COUNTER,
input DIRECTION, // directia de numarare -> 0 - crescator
input RST,
input CLK
);
always@(posedge CLK) begin
if(RST)
COUNTER<= 0;
else
COUNTER<= DIRECTION == 0 ? COUNTER + 1 : COUNTER - 1; //
daca nu reset, numara in sus sau in jos
end
endmodule
decodor
----------------------------------------------------------------------------------------------------------------------`timescale 1ns / 1ps
module decodor(
input [1:0] selection,
output reg [3:0] out_sel
);
always @ (selection)
begin
case (selection)
0 : out_sel = 4'b1110;
1 : out_sel = 4'b1101;
2 : out_sel = 4'b1011;
3 : out_sel = 4'b0111;
endcase
end
endmodule
decodor
----------------------------------------------------------------------------------------------------------------------`timescale 1ns / 1ps
module top(
input [3:0] value,
input [1:0] selection,
output [3:0] out_sel,
output [7:0] out_seg
);
// Instantiate the module
transcodor inst_transcodor (
.value(value),
.out_seg(out_seg)
);
// Instantiate the module
decodor inst_decodor (
.selection(selection),
.out_sel(out_sel)
);
transcodor
----------------------------------------------------------------------------------------------------------------------module transcodor(
input [3:0] value,
output reg [7:0] out_seg
);
always @ (value)
begin
case(value)
0 : out_seg = 8'b11000000;
1 : out_seg = 8'b11111001;
2 : out_seg = 8'b10100100;
3 : out_seg = 8'b10110000;
4 : out_seg = 8'b10011001;<
5 : out_seg = 8'b10010010;
6 : out_seg = 8'b10000010;
7 : out_seg = 8'b11111000;
8 : out_seg = 8'b10000000;
9 : out_seg = 8'b10010000;
10 : out_seg = 8'b10001000;
11 : out_seg = 8'b10000011;
12 : out_seg = 8'b11000110;
13 : out_seg = 8'b10100001;
14 : out_seg = 8'b10000110;
15 : out_seg = 8'b10001110;
default : out_seg = 8'b00000000;
endcase
end
endmodule
counter-lab3
----------------------------------------------------------------------------------------------------------------------module counter(
input clock,
input reset,
output reg led
);
reg [24:0] count;
always @(posedge clock or posedge reset)
begin
if (reset) begin
led <= 0;
count <= 0;
end
else begin
if (count == 24999999) begin
count <= 0;
led <= ~led;
end
else
count <= count + 1;
end
end
endmodule
pwm
------------------------------------------------------input clk, rst,
input [7:0] lim,
output reg led
);
wire [7:0] cnt;
module pwm(
top
------------------------------------------------------input clk,
input rst,
output led
);
reg [7:0] lim;
reg direction;
reg [16:0] count;
wire clk1;
module top(
counter
-------------------------------------------------------module counter(
input clk,
input rst,
output reg [7:0] cnt
);
always @ (posedge clk)
begin
if (rst)
cnt <= 0;
else
cnt <= cnt + 1;
end
endmodule
rom
------------------------------------------------------input [3:0] in,
output reg [3:0] out
);
always @(in)
case(in)
0: out = 4'b1010;
1: out = 4'b0110;
2: out = 4'b0011;
3: out = 4'b1110;
4: out = 4'b1011;
5: out = 4'b1111;
6: out = 4'b0111;
7: out = 4'b1100;
&
8: out = 4'b0001;
9: out = 4'b0101;
10: out = 4'b1101;
11: out = 4'b0000;
12: out = 4'b0010;
13: out = 4'b0100;
14: out = 4'b1000;
15: out = 4'b1001;
endcase
module ROM(
endmodule
ram
------------------------------------------------------in
put clk,
input [3:0] wr_addr,
input [3:0] wr_data,
input wr_en,
input [3:0] rd_addr,
input rd_en,
output reg [3:0] rd_data
);
reg [3:0] mem [0:15];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
always @(posedge clk) begin
if (rd_en)
rd_data <= mem[rd_addr];
end
endmodule
module RAM(
counter
------------------------------------------------------input clk,
output reg [25:0] count
);
always @(posedge clk)
count <= count + 1;
endmodule
module counter(
top
------------------------------------------------------p; input CLK,
input [3:0] ADR,
input [3:0] DIN,
input WEN,
output [3:0] DOUT
);
wire [25:0] count;
wire [3:0] rd_data;
// Instantiate the module
RAM RAM_inst (
.
clk(CLK),
.wr_addr(ADR),
.wr_data(DIN),
.wr_en(WEN),
.rd_addr(count[25:22]),
.rd_en(1'b1),
.rd_data(rd_data)
);
// Instantiate the module
ROM ROM_inst (
.in(rd_data),
.out(DOUT)
);
// Instantiate the module
counter counter_inst (
.clk(CLK),
.count(count)
);
endmodule
module top(