waveform:

Adder_16bitcode:
module csa_16_str (x,y,cin,s,cout);
input [15:0] x;
input [15:0] y;
input cin;
output [15:0] s;
output cout;
wire [15:0]x_n,y_n,a,b;
wire [15:0]s1,s2,s3,s4;
wire [6:0]c;
//signal declaration
wire w1,w2,cout,c1,c2;
wire ov;
//wire [4:0] c;
//wire c1,c2,c3,c4;
comp_2s_16b a1 (x,x_n,w1);
comp_2s_16b a2 (y,y_n,w2);
mux_16 a3(x,x_n,x[15],a);
mux_16 a4(y,y_n,y[15],b);
//first four bits
adder_seg W2 ({1'b0,a[2:0]},{1'b0,b[2:0]},cin,{c2,s1[2],s1[1],s1[0]},c[0]);
adder_seg W3 ({1'b0,a[5:3]},{1'b0,b[5:3]},c2,{c3,s1[5],s1[4],s1[3]},c[1]);
adder_seg W4 ({1'b0,a[8:6]},{1'b0,b[8:6]},c3,{c4,s1[8],s1[7],s1[6]},c[2]);
adder_seg W5 ({1'b0,a[11:9]},{1'b0,b[11:9]},c4,{c5,s1[11],s1[10],s1[9]},c[3]);
full_adder A1(a[12],b[12],c5,s1[12],c[4]);
full_adder A2(a[13],b[13],c[4],s1[13],c[5]);
full_adder A3(a[14],b[14],c[5],s1[14],c[6]);
full_adder A4(a[15],b[15],c[6],s1[15],cout);
xor A5 (ov,c[6],cout);
overflow_16 A6(s1,s2,q1);
mux_16 A7(s1,s2,ov,s3);
comp_2s_16b B1 (s3,s4,w1);
mux_16 A8(s3,s4,s3[15],s);
endmodule
mux16:
module mux_16(a,b,sel,sel_out);
//configuration parameters
input [15:0]a,b;
input sel;
output [15:0]sel_out;
//signals

wire [15:0]w1,w2;
wire sel_bar;
//initializing gates
mux_4bit_2x1 a1(a[3:0],b[3:0],sel,sel_out[3:0]);
mux_4bit_2x1 a2(a[7:4],b[7:4],sel,sel_out[7:4]);
mux_4bit_2x1 a3(a[11:8],b[11:8],sel,sel_out[11:8]);
mux_4bit_2x1 a4(a[15:12],b[15:12],sel,sel_out[15:12]);
endmodule
mux_4bit_2x1:
module mux_4bit_2x1(a,b,sel,sel_out);
//configuration parameters
input [3:0]a,b;
input sel;
output [3:0]sel_out;
//signals
wire [3:0]w1,w2;
wire sel_bar;
//initializing gates
mux_2x1 a1(a[0],b[0],sel,sel_out[0]);
mux_2x1 a2(a[1],b[1],sel,sel_out[1]);
mux_2x1 a3(a[2],b[2],sel,sel_out[2]);
mux_2x1 a4(a[3],b[3],sel,sel_out[3]);
endmodule
mux2x1:
module mux_2x1(a,b,sel,sel_out);
//configuration parameters
input a,b,sel;
output sel_out;
//signals
wire w1,w2,sel_bar;
//initializing gates
and a1(w1,b,sel);
not a2(sel_bar,sel);
and a3(w2,sel_bar,a);
or a4(sel_out,w1,w2);
endmodule
comp_2s_16 code:
module comp_2s_16b(x,s,c);
input [15:0] x;
output [15:0] s;
wire [14:0]w1,w2;
output c;
not a1(w1[0],x[0]);
not a2(w1[1],x[1]);
not a3(w1[2],x[2]);
not a4(w1[3],x[3]);

not a5(w1[4],x[4]);
not a6(w1[5],x[5]);
not a7(w1[6],x[6]);
not a8(w1[7],x[7]);
not a9(w1[8],x[8]);
not a10(w1[9],x[9]);
not a11(w1[10],x[10]);
not a12(w1[11],x[11]);
not a13(w1[12],x[12]);
not a14(w1[13],x[13]);
not a15(w1[14],x[14]);
full_adder A0(w1[0],1'b1,1'b0,s[0],w2[0]);
full_adder A1(w1[1],1'b0,w2[0],s[1],w2[1]);
full_adder A2(w1[2],1'b0,w2[1],s[2],w2[2]);
full_adder A3(w1[3],1'b0,w2[2],s[3],w2[3]);
full_adder A4(w1[4],1'b0,w2[3],s[4],w2[4]);
full_adder A5(w1[5],1'b0,w2[4],s[5],w2[5]);
full_adder A6(w1[6],1'b0,w2[5],s[6],w2[6]);
full_adder A7(w1[7],1'b0,w2[6],s[7],w2[7]);
full_adder A8(w1[8],1'b0,w2[7],s[8],w2[8]);
full_adder A9(w1[9],1'b0,w2[8],s[9],w2[9]);
full_adder A10(w1[10],1'b0,w2[9],s[10],w2[10]);
full_adder A11(w1[11],1'b0,w2[10],s[11],w2[11]);
full_adder A12(w1[12],1'b0,w2[11],s[12],w2[12]);
full_adder A13(w1[13],1'b0,w2[12],s[13],w2[13]);
full_adder A14(w1[14],1'b0,w2[13],s[14],w2[14]);
full_adder A15(x[15],1'b0,w2[14],s[15],c);
endmodule
Complement_2s_4bits:
module comp_2s(x,s,c);
input [3:0] x;
output [3:0] s;
wire [3:0]w1,w2;
output c;
not a1(w1[0],x[0]);
not a2(w1[1],x[1]);
not a3(w1[2],x[2]);
full_adder A0(w1[0],1'b1,1'b0,s[0],w2[0]);
full_adder A1(w1[1],1'b0,w2[0],s[1],w2[1]);
full_adder A2(w1[2],1'b0,w2[1],s[2],w2[2]);
full_adder A3(x[3],1'b0,w2[2],s[3],c);
endmodule
adder_Seg
// Arizona state University
//CSE 598 Digital design and verification language
//Home work 1 Question 5.38 4-bit ripple carry adder
module adder_seg(a,b,cin,s,c);

input signed [3:0] a,b;

input cin;
output signed [3:0]s;
output c;
wire c1,c2;
//wire w1,w2,w3;
wire [3:0] s1,s2;
//wire [3:0]a_n,b_n,x,y;
rca_4str q1(a,b,1'b0,s1,c1);
rca_4str q2 (a,b,1'b1,s2,c2);
//rca_4_old_str
//comp_2s b1(a,a_n,c1);
////comp_2s b2(b,b_n,c2);
//mux_4bit_2x1 b3(a,a_n,a[3],x);
//mux_4bit_2x1 b4(b,b_n,b[3],y);
//Instantiation
// full_adder A0(x[0],y[0],1'b0,s1[0],w1);
// full_adder A1(x[1],y[1],w1,s1[1],w2);
// full_adder A2(x[2],y[2],w2,s1[2],w3);
// full_adder A3(x[3],y[3],w3,s1[3],c);
//
//
//
//

full_adder
full_adder
full_adder
full_adder

B0(x[0],y[0],1'b1,s2[0],w1);
B1(x[1],y[1],w1,s2[1],w2);
B2(x[2],y[2],w2,s2[2],w3);
B3(x[3],y[3],w3,s2[3],c);

mux_4bit_2x1 b5(s1,s2,cin,s);
endmodule
overflow:
module overflow(a,o,c);
input [3:0] a;
output [3:0]o;
output c;
wire a3_n;
wire[3:1] w;
not a1(a3_n,a[3]);
full_adder a2(a[0],1'b0,1'b0,o[0],w[1]);
full_adder a3(a[1],1'b0,w[1],o[1],w[2]);
full_adder a4(a[2],1'b0,w[2],o[2],w[3]);
full_adder a5(a3_n,1'b1,w[3],o[3],c);
endmodule
Testbench:
`timescale 1ns / 1ps
module csa_16_str_tb;
reg [15:0] a;
reg [15:0] b;

reg cin;
wire [15:0] sum;
wire c0;
csa_16_str a1(a,b,cin,sum,c0);
initial begin
// tesing vector to verify substract and addition
#10 a=16'b0000000000000000;b=16'b0000000000001111;cin=1'b0;
#10 a=16'b0000000000001111;b=16'b1111000000000000;cin=1'b0;
#10 a=16'b1111000000000000;b=16'b0011001100110011;cin=1'b0;
#10 a=16'b0011001100110011;b=16'b1100110011001100;cin=1'b0;
#10 a=16'b1100110011001100;b=16'b0101010101010101;cin=1'b0;
#10 a=16'b0101010101010101;b=16'b1010101010101010;cin=1'b0;
#10 a=16'b1010101010101010;b=16'b0000000000000001;cin=1'b0;
#10 a=16'b0000000000000001;b=16'b1000000000000000;cin=1'b0;
#10 a=16'b1000000000000000;b=16'b1111111111111111;cin=1'b0;
#10 a=16'b1111111111111111;b=16'b0000000000000000;cin=1'b0;
//
#10 a=16'b0000000000000000;b=16'b0000000000001111;cin=1'b1;
#10 a=16'b0000000000001111;b=16'b1111000000000000;cin=1'b1;
#10 a=16'b1111000000000000;b=16'b0011001100110011;cin=1'b1;
#10 a=16'b0011001100110011;b=16'b1100110011001100;cin=1'b1;
#10 a=16'b1100110011001100;b=16'b0101010101010101;cin=1'b1;
#10 a=16'b0101010101010101;b=16'b1010101010101010;cin=1'b1;
#10 a=16'b1010101010101010;b=16'b0000000000000001;cin=1'b1;
#10 a=16'b0000000000000001;b=16'b1000000000000000;cin=1'b1;
#10 a=16'b1000000000000000;b=16'b1111111111111111;cin=1'b1;
#10 a=16'b1111111111111111;b=16'b0000000000000000;cin=1'b1;
//#10 a=16'b1111000000000000;b=16'b0011001100110011;cin=1'b0;
//#10 a=16'b0011001100110011;b=16'b1100110011001100;cin=1'b0;
/*#10 a=8'b10000010;b=8'b10000011;cin=1'b0;
#10 a=8'b00110101;b=8'b11010011;cin=1'b0;
#10 a=8'b11111111;b=8'b11111111;cin=1'b0;
#10 a=8'b11111111;b=8'b00000001;cin=1'b0;
#10 a=8'b11111111;b=8'b00010000;cin=1'b0;
#10 a=8'b00000011;b=8'b00000011;cin=1'b0;
#10 a=8'b11111111;b=8'b11110000;cin=1'b0;
#10 a=8'b11111101;b=8'b11111110;cin=1'b0;
#10 a=8'b11111101;b=8'b11111110;cin=1'b0;
#10 a=8'b11111111;b=8'b11111111;cin=1'b1;
#10 a=8'b00000011;b=8'b11111110;cin=1'b1;
#10 a=8'b00000011;b=8'b11111110;cin=1'b1; */
#10 $stop;
end
endmodule