EE 4313 Homework 2 (Chapter 14)

Due 10JUN2015 by 1159pm (Due prior to the start of class). It must be uploaded as a single electronic
file (pdf) in BB. For all problems, assume room temperature VT=25mV.
100 Points
1. Design a CMOS inverter(65nm) with VDD=1.0V, L=65nm, Kn=2.5Kp=470A/V2, and VTN=VTP
=0..35V, (W/L)n=1.5
a. Find Wp that results in VM=VDD/2. What is the silicon area utilized by the inverter in this case?
b. For the matched case in (a), find the values of VOL, VOH, VIL, VIH, NMH, NML.
c. For the matched case in (a), find the output resistance of the inverter in each of its two states.
2. For the circuit below with a capacitor C connected between the output and ground, let the on-resistance
of PU be 2k and PD be 1k. If C=50fF, find tPHL, tPLH, and tP.

3. An IC inverter fabricated in a 0.18 um CMOS process is found to have a load capacitance of 10fF. If
the inverter is operated from a 1.8V power supply, find the energy needed to charge and discharge the
load capacitance. If the IC chip has 2 million of these inverters operating at an average switching
frequency of 1GHz, what is the power dissipated in the chip? What is the average current drawn from
the power supply?
__________
4. Give the CMOS realization for the Boolean function: Y=(A+B)(C+D)