Instrucciones:

Se requiere disear una ALU que cumpla con las caractersticas mostradas en las tablas 1 y 2.
Selector
0
1
2
3

Operacin
A * B (Lgica)
AB
A + B (Aritmtica)
A B (Aritmtica)
Tabla 1
Selector
0
1
2
3

X
1
1
1
1
Tabla 2

Cout
0
0
1
1

Cdigo:
A continuacin se presenta el cdigo a dos columnas.

Pgina 1 de 5

// Se comienza por crear los componentes que genera las partes de la ALU//
ARCHITECTURE BEH OF MUX1 IS
Compuerta AND
LIBRARY IEEEE;
BEGIN
USE IEEE.STD_LOGIC_1164.ALL;
WITH S SELECT
ENTITY GAND IS
X<= I(0) WHEN 00";
PORT ( A,B: IN STD_LOGIC;
X<= I(1) WHEN 01;
X: OUT STD_LOGIC);
X<= I(2) WHEN 10;
END GAND;
X<= I(3) WHEN 1;
ARCHITECTURE BEH OF GAND IS
BEGIN
0 WHEN OTHERS;
X<= A AND B;
END BEH;
END BEH;
Compuerta XOR
LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GXOR IS
PORT ( A,B: IN STD_LOGIC;
X: OUT STD_ LOGIC);
END GXOR;
ARCHITECTURE BEH OF GXOR IS
BEGIN
X<= A XOR B;
END BEH;

Compuerta NOT
LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GNOT IS
PORT ( A,B: IN STD_LOGIC;
X: OUT STD_LOGIC);
END GNOT;
ARCHITECTURE BEH OF GNOT IS
BEGIN
X<= NOT (B);
END BEH;

Multiplexor
LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX1 IS
PORT ( I: IN STD_LOGIC_VECTOR;
(3 DOWNTO 0);
S: IN STD_LOGIC_VECTOR;
(1 DOWNTO 0);
X: OUT STD_LOGIC);
END MUX1;

LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2 IS
PORT ( I: IN STD_LOGIC_VECTOR;
(3 DOWNTO 0);
S: IN STD_LOGIC_VECTOR;
(1 DOWNTO 0);
X: OUT STD_LOGIC);
END MUX1;
ARCHITECTURE BEH OF MUX1 IS
BEGIN
WITH S SELECT
X<= 0 WHEN 00";
X<= 0 WHEN 01;
X<= I(2) WHEN 10;
X<= I(3) WHEN 1;
0 WHEN OTHERS;
END BEH;

Sumador completo
LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MADDER IS
PORT (A,B: IN STD_LOGIC;
X,COUT: OUT STD_LOGIC);
END MADDER;
ARCHITECTURE STRL OF MADDER IS
COMPONENT GAND
PORT (A,B: IN STD_LOGIC;
X: OUT STD_LOGIC);
END COMPONENT
COMPONENT GXOR
PORT (A,B: IN STD_LOGIC;
X: OUT STD_LOGIC);
END COMPONENT
BEGIN
Pgina 2 de 5

U1: GXOR PORT MAP(A,B,S);

U2: GAND PORT MAP(A,B,COUT);
END STRL;

U2: GNOT PORT MAP(A,R);

U3: GAND PORT MAP(R,B,COUT);
END STRL;

LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULLADDER IS
PORT (A,B, CIN: IN STD_LOGIC;
X,COUT: OUT STD_LOGIC);
END FULLADDER;
ARCHITECTURE STRL OF FULLADDER IS
COMPONENT MADDER
PORT (A,B: IN STD_LOGIC;
S,OUT: OUT STD_LOGIC);
END COMPONENT
COMPONENT GOR
PORT (A,B: IN STD_LOGIC;
S: OUT STD_LOGIC);
END COMPONENT
SIGNAL N,O,P: STD_LOGIC
BEGIN
U1: MADDER PORT MAP(A,B,N,P);
U2: MADDER PORT MAP(N,CIN,S,O);
U3: GOR PORT MAP(P,O,COUT);
END STRL;

LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULLLESSIS
PORT (A,B, CIN: IN STD_LOGIC;
X,COUT: OUT STD_LOGIC);
END FULLLESS;
ARCHITECTURE STRL OF FULLADDER IS
COMPONENT MLESS
PORT (A,B: IN STD_LOGIC;
S,OUT: OUT STD_LOGIC);
END COMPONENT
COMPONENT GOR
PORT (A,B: IN STD_LOGIC;
S: OUT STD_LOGIC);
END COMPONENT
SIGNAL N,O,P: STD_LOGIC
BEGIN
U1: MLESS PORT MAP(A,B,N,P);
U2: MLESS PORT MAP(N,CIN,S,O);
U3: GOR PORT MAP(P,O,COUT);
END STRL;

Restador completo

ALU
LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ALU IS
PORT (A,B, CIN: IN STD_LOGIC;
S:IN STD_LOGIC_VECTOR;
(1 DOWNTO 0);
X,COUT: OUT STD_LOGIC);
END ALU;
ARCHITECTURE STRL OF ALU IS
COMPONENT GAND

LIBRARY IEEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MLESS IS
PORT (A,B: IN STD_LOGIC;
X,COUT: OUT STD_LOGIC);
END MADDER;
ARCHITECTURE STRL OF MADDER IS
COMPONENT GAND
PORT (A,B: IN STD_LOGIC;
X: OUT STD_LOGIC);
END COMPONENT
COMPONENT GNOT
PORT (A: IN STD_LOGIC;
X: OUT STD_LOGIC);
END COMPONENT
COMPONENT GXOR
PORT (A,B: IN STD_LOGIC;
X: OUT STD_LOGIC);
END COMPONENT
SIGNAL R: STD_LOGIC;
BEGIN
U1: GXOR PORT MAP(A,B,S);

PORT A,B: IN STD_LOGIC;

X:OUT STD_LOGIC);
END COMPONENT
COMPONENT GXOR
PORT (A,B: IN STD_LOGIC;
X:OUT STD_LOGIC);
END COMPONENT
COMPONENT FULLADDER
PORT(A,B,CIN: IN STD_LOGIC;
S,COUT:OUT STD_LOGIC);
Pgina 3 de 5

END COMPONENT
COMPONENT FULLLESS
PORT(A,B,CIN: IN STD_LOGIC;
S,COUT:OUT STD_LOGIC);
END COMPONENT
COMPONENT MUX1
PORT ( I: IN STD_LOGIC_VECTOR;
(3 DOWNTO 0);
S: IN STD_LOGIC_VECTOR;
(1 DOWNTO 0);
X: OUT STD_LOGIC);
END MUX1;
ARCHITECTURE STRL OF ALU IS
SIGNAL I: STD_LOGIC_VECTOR;

(3 DOWNTO 0);
BEGIN
U1: GAND PORT MAP(A,B,I(0));
U2: GOR PORT MAP(A,B,I(1);
U3: FULLADDER PORT
MAP(A,B,CIN,I(3),COUT1);
U4: FULLLESS PORT
MAP(A,B,CIN,I(4),COUT2);
U5: MUX1 PORT MAP(I,S,X);
END STRL;

Pgina 4 de 5

Diseo esquemtico:

Conclusiones:
La programacin de una ALU en la forma estructural es una manera ms fcil de poder
genera un cdigo reducido, ya que solo se define crea una vez cada componente, en
esta tarea el reto era poder generar la ALU partiendo de las tablas lo cual fue un poco
sencillo exceptuando la parte de restringir el cout.