AIE Processor

Concept

Sequential Processor Stages

Fetch

Deco
de

Execu
te

Mem

WB

Pipelining Processor Stages

Fetch

P
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Deco
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Execu
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P
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Mem

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WB

Transaction Table
Five Stages Pipeline

Pipelining Design
As Queue
Problems:
High Circuit Complexity
If Queue is Full in a stage the previous must
halt until the queue release item, so there is
no great benefit.

Implementation
Shift Register Circuit & Registers [Waste
Cycles]
Counter & Registers [Save Cycles]

Shift Register Circuit & Registers

Counter & Registers Pipeline

Pipeline Optimal Designs

Sync Pipeline
All Pipeline Modules Attached with Same
Cycle Controller
Cycle Time = Max Stage Clock
Problems
There is Waste in Clock but not to much
Every stage not aware of the status of
previous stage.

Pipeline Optimal Designs

A Sync Pipeline
Every Stage aware of the status of the previous
stage using internal handshaking signals
Ready Acknowledge Signals

Advantages
There is no clock waste thanks to handshaking signals
There is no Max Cycle Clock, every instruction take
the clocks need to perform its operation.

Disadvantages
In Control Unit you must specify every instruction
timing in every stage of the pipelined processor

Pipeline Optimal Designs

Sync Pipeline & A Sync Pipeline

Sync Pipeline Implementation

Key Feature of AIE Processor

32-bit Pipelined Processor
Processor Support 48 Instruction
Processor Interface with Interleaved
Memory
Interface with LCD Terminal using
Instructions
Processor have its Assembly
Interpreter

Instructions

Ir register
IR Register

8 bit

INSTRUCIONS
ROM

24 bit

Address Bus : 8 bit

Modes Select

Data Bus : 32 bit

32
bit

01-MOV reg,immediate
-8c005000
02-ADD d.reg,s1.reg,s2.reg
-20007000
03-ADC d.reg,s1.reg,s2.reg
-22007000
04-SUB d.reg,s1.reg,s2.reg
-24007000
05-SUW d.reg,s1.reg,s2.reg
-26007000
06-MUL d.reg,s1.reg,s2.reg
-28007000
07-DIV d.reg,s1.reg,s2.reg
-2a007000
08-TRSA d.reg,s1.reg
-2c007000
09-TRSB d.reg,s2.reg
-2e007000
0a-AND d.reg,s1.reg,s2.reg
-30007000
0b-OR d.reg,s1.reg,s2.reg
-32007000
0c-NAND d.reg,s1.reg,s2.reg
-34007000
0d-NOR d.reg,s1.reg,s2.reg

-4c022000
13-RPNT reg
-2c022000
14-STOWE address,reg
-4c102000
15-STOWO address,reg
-4c142000
16-STODW address,reg
-4c302000
17-LODWE reg,address
-4c195000
18-LODWO reg,address
-4c1d5000
19-LODDW reg,address
-4c395000
1a-JG address
-8c400000
1b-JE address
-8c800000
1c-JL address
-8cc00000
1d-JC address
-8d000000
1e-JNG address
-8c400800

ROM CONTROLS

Main Modes
IMMEDIATE MODE
REGISTER , REGISTER MODE
MEMORY MODE

IMMEDIATE MODE

IR Register :
ROM- address

8bit
3bit
Instructions :
*MOV reg,immediate
-8c005000
*JG address
-8c400000
*JE address
-8c800000
*JL address
-8cc00000
*JC address

REG-address

5 bit

IMMEDIATE

16 bit
*JNE address
-8c800800
*JNL address
-8cc00800
*JNC address
-8d000800
*JMP address
-8d400000

REGISTER REGISTER MODE

IR Register :
ROM- address

8bit

Destination_R
EG
3bit

5 bit

Instructions :
*ADD d.reg,s1.reg,s2.reg
-20007000
*ADC d.reg,s1.reg,s2.reg
-22007000
*SUB d.reg,s1.reg,s2.reg
-24007000
*SUW d.reg,s1.reg,s2.reg
-26007000
*MUL d.reg,s1.reg,s2.reg

Source_REG1

3bit

5 bit

Source_REG2

3bit

5 bit

*AND d.reg,s1.reg,s2.reg
-30007000
*OR d.reg,s1.reg,s2.reg
-32007000
*NAND d.reg,s1.reg,s2.reg
-34007000
*NOR d.reg,s1.reg,s2.reg
-36007000
*XOR d.reg,s1.reg,s2.reg

Indirect addressing MODE

IR Register :
ROM- address

8bit

Destination_R
EG
3bit

5 bit

Instructions :
*IDSTOWE address 2c102000
*IDSTOWO address 2c142000
*IDSTODW address 2c302000
*IDLODWE address -

Source_REG1

3bit

5 bit

Source_REG2

3bit

5 bit

MEMORY MODE

IR Register :
REG-address

ROM- address

8bit

3bit

Instructions :
*STOWE address,reg
-4c102000
*STOWO address,reg
-4c142000
*STODW address,reg
-4c302000
*LODWE reg,address
-4c195000
*LODWO reg,address

5 bit

IMMEDIATE

16 bit
*LODDW reg,address
-4c395000
*IPNT immediate
-4c022000
*PUSHWE reg
-4c102400
*PUSHWO reg
-4c142400
*PUSHDW reg
-4c302400

INSTRUCTION set
B31,B30,B2B28,B27,B26, B24,B23,
9
B25
B22

1)
2)
3)
4)
5)
6)
7)
8)
9)

B21,B20,B19, B17 B16 B15 B14,B13,

B18
B12

B11

(1)
(2)
(3)
(4
(5 (6 (7
(8
(9
)
)Mode
) , B29): Register)
Select Mode : {B31: Immediate mode , B)30: Memory
Register Mode}
Execution Control
Execution Conditional Control
Memory Control : {B21: BHE , B20:Select Memory , B19:Memory R/w ,
B18:Memory Even/Odd }
Select Write Back Block or TTY Block
Select The Input of the Write Back Block From Alu Result or Memory Output
No Operation
Register File Control { B14:Write Register , B13:OE Register ,B12:Enabel
Write Select Register }
Invert Condition

Tracing Some
Instructions

MIPS Architecture based

For Example
Executing These Two Instruction
Sequentially
I1:R1=R2+R3
I2:R4=R2 AND R1

l1

I1: Fetching
I2: Still in Memory

l2

l1

I1: Decoding & RegFetch

R2
R3

l2

I1: Execute
+
R3)

l1

(R2

l2

I1: MEM[no Operation]

+
R3)

l
1

(R2

l
2

Data Stored In
R1
I1: Write Back
+
R3)

l
1

R1=(R2

Solution

I1:R1=R2+R3
NOP
NOP
NOP
I2:R4=R2 AND R1

l
1

I1: Fetching
I2: Still in Memory

NO
P

L1

I1: Decoding & RegFetch

R3

R2

NO
P

NO
P

I1: Execute
+
R3)

L
1

(R2

NO
P

NO
P

NO
P

I1: MEM[no Operation]

+
R3)

L1

(R2

L
2

NO
P

NO
P

NO
P

L
1

Data Stored In

I1: Write Back

+
R3)

R1=(R2

L
2

NO
P

NO
P

NO
P

I1: Terminated
I2: Decoding & RegFetch

R2

L
2

NO
P

NO
P

I1: Terminated
I2:Execute

(R2

L
2

NO
P

I1: Terminated
I2:MEM[No Operation]

(R2

AND

I1: Terminated
I2: Terminated

Statistics & Comparisons

Cisc Vs Risc
Cisc:

-Richer instruction set but very complex circuit.

-Instructions generally take more than 1 clock to
execute.
-Instructions of a variable size.
Risc:
-Instructions execute in one clock cycle.
-Uniformed length instructions and fixed instruction
format.
-Simple instructions and circuit.

Speed:
With Pipelining:
Each stage takes 4 clock cycles
5 stages IF,ID,EX,MEM,WB
If clock rate 5 MHz then time for performing an
instruction per pipeline stage is 0.8 sec.
Without Pipelining:
If clock rate 5 MHz then time for performing an
instruction is 4 sec.

If

ID
If

ID
If

ID

EX

MEM

WB

If

NOP

NOP

NOP

Pipelining

ID

MOV r1,05h
MOV r2,04h
ADD r3,r1,r2
STODW r3,1234h

EX

MEM

Average no. of stall cycles per

instruction is 0.75
Speed up is 2.85

Thank you