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3/7/2010

Address Decoding

Memory/IO

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = FFFFF

 
                   

01111111111111111111

       

1M

 

locations

   
A 19 7FFFF CS A 0 – A 19 A 0 – A 18 8088
A 19
7FFFF
CS
A 0 – A 19
A 0 – A 18
8088
512 KB
memory
D 0 – D 7
D 0 – D 7
00000
A 19 7FFFF CS A 0 – A 19 A 0 – A 18 8088 512

FFFFF

7FFFF

00000

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = FFFFF

 
                   

11111111111111111111

       

1M

 

locations

   
A 0 – A 19 1 Mbyte memory 8088 D 0 – D 7 CS
A 0 – A 19
1 Mbyte
memory
8088
D 0 – D 7
CS
CS= Chip Select.
If CS = 0 then the memory will be ON
If CS = 1 then the memory will be sleeping and all its pins will be Z

FFFFF

00000

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

10000000000000000000

                 

End Address = FFFFF

 
                   

11111111111111111111

       

1M

 

locations

   
A 19 7FFFF CS A 0 – A 19 A 0 – A 18 8088
A 19
7FFFF
CS
A 0 – A 19
A 0 – A 18
8088
512 KB
memory
D 0 – D 7
D 0 – D 7
00000

FFFFF

80000

00000

3/7/2010

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = 0FFFF

 
                   

00001111111111111111

       

1M

 

locations

   
Address A 16 – A 19 Decoding A 0 – A 19 FFFF CS A
Address
A 16 – A 19
Decoding
A 0 – A 19
FFFF
CS
A 0 – A 15
64 KB
memory
D 0 – D 7
D 0 – D 7
0000
8088
8088
A 19 Decoding A 0 – A 19 FFFF CS A 0 – A 15 64

FFFFF

0FFFF

00000

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = 0FFFF

 
                   

00011111111111111111

       

1M

 

locations

   
This memory should be selected only when A16 = 1 A – A 16 19
This memory should be
selected only when
A16 = 1
A
– A
16
19
A17 = 0
A18 = 0
A19 = 0
FFFF CS A 0 – A 15 64 KB memory D 0 – D 7
FFFF
CS
A 0 – A 15
64 KB
memory
D 0 – D 7
0000
– A 16 19 A17 = 0 A18 = 0 A19 = 0 FFFF CS A

FFFFF

1FFFF

10000

00000

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = 0FFFF

 
                   

00001111111111111111

       

1M

 

locations

   
This memory should be selected only when A16 = 0 A – A 16 19
This memory should be
selected only when
A16 = 0
A
– A
16
19
A17 = 0
A18 = 0
A19 = 0
FFFF CS A 0 – A 15 64 KB memory D 0 – D 7
FFFF
CS
A 0 – A 15
64 KB
memory
D 0 – D 7
0000
0 A – A 16 19 A17 = 0 A18 = 0 A19 = 0 FFFF

FFFFF

0FFFF

00000

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = 0FFFF

 
                   

00101111111111111111

       

1M

 

locations

   
This memory should be selected only when A16 = 1 A – A 16 19
This memory should be
selected only when
A16 = 1
A
– A
16
19
A17 = 0
A18 = 0
A19 = 0
FFFF
CS
A 0 – A 15
64
KB
memory
D 0 – D 7
0000

FFFFF

2FFFF

20000

00000

3/7/2010

A

19

A

18

A

17

A

16

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Starting Address = 00000

 
                   

00000000000000000000

                 

End Address = 0FFFF

 
                   

00111111111111111111

       

1M

 

locations

   
This memory should be selected only when A16 = 1 A – A 16 19
This memory should be
selected only when
A16 = 1
A
– A
16
19
A17 = 0
A18 = 0
A19 = 0
FFFF
CS
A 0 – A 15
64 KB
memory
D 0 – D 7
0000

FFFFF

3FFFF

30000

00000

Timing Diagram of A Memory Operation

Example: 8088 sends address 70C12 to memory in a memory read operation assume that data 30H is read

Addr[15:0] D latch 8088 A[15:8] Buffer AD[7:0] D latch D[7:0] Trans DT/R ‐ceiver DEN IO/M
Addr[15:0]
D latch
8088 A[15:8]
Buffer
AD[7:0]
D latch
D[7:0]
Trans
DT/R
‐ceiver
DEN
IO/M
WR
RD
Memory
T3 T4 T1 T2 CLK ALE
T3
T4
T1
T2
CLK
ALE
A[19:16] 7H S3‐ S6 A[15:8] 0CH AD[7:0] 12H 30H Addr[19:16] 7H Addr[15:8] 0CH Addr[7:0] 12H
A[19:16]
7H
S3‐ S6
A[15:8]
0CH
AD[7:0] 12H
30H
Addr[19:16]
7H
Addr[15:8]
0CH
Addr[7:0]
12H
D[7:0]
30H

511

Connections Between CPU and Memory

 
 

Control signals

Memory 8088 Data Bus Address bus
Memory
8088
Data Bus
Address bus

What are the control signals from the microprocessor to memory? What are the control signal from memory to the microprocessor?

 

Address and data signals should be buffered

— The use of buffers on address bus increases driving capability

— Bidirectional buffers are used to control the data transferring directions on data bus

— D latches are used to de multiplex signals on AD[7:0] (and A[19:16])

510

 

Memory Chips

The number of address pins is related to the number of memory locations .

 

Common sizes today are 1K to 256M locations. ( 10 and 28 address pins

are present. )

The data pins are typically bi directional in readwrite memories.

The number of data pins is related to the size of the memory location .

For example, an 8 bit wide (byte wide) memory device has 8 data pins.

Catalog listing of 1K X 8 indicate a by te addressable 8K memory.

Each memory device has at least one chip select ( CS ) or chip enable ( CE ) or select ( S ) pin that enables the memory device.

Each memory device has at least one control pin.

For ROMs, an output enable ( OE ) or gate ( G ) is present.

 

The OE pin enables and disables a set of tristate buffers.

For RAMs, a readwrite ( R/W ) or write enable ( WE ) and read enable

 
 

(OE ) are present.

For dual control pin devices, it must be hold true that both are not 0 at the same time.

 

512

3/7/2010

Memory Address Decoding

The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.

In order to splice a memory device into the address space of the processor, decoding is necessary.

For example, the 8088 issues 20bit addresses for a total of 1MB of memory address space.

However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.

A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.

513

Decoding Circuits

NAND gate decoders are not often used.

3to8 Line Decoder (74LS138) is more common.

5‐15
5‐15

Memory Address Decoding

Memory Address Decoding 5 ‐ 14

514

Memory Address Decoding

Using Full memory addressing space

Addr[19:0]

FFFFF Highest address 0 0 1 1 0 1 1 1 1 1 1 1
FFFFF
Highest address
0
0 1 1
0
1
1 1
1 1 1 1
1 1 1 1
1 1 1 1
37FFF
32KB
Lowest address
0
0 1 1
0
0
0 0
0 0 0 0
0 0 0 0
0 0 0 0
30000
These 5 address lines
These 15 address lines select
00000
are not changed. They
set the base address
one of the 2 15 (32768) locations
inside the RAMs
Addr[14:0]
32KB
Addr[19]
CS
Addr[18]
Addr[17]
Addr[16]
Addr[15]
Can we design a decoder such that the first address
of the 32KB memory is 37124H?
IO/M
5‐16

3/7/2010

Memory Map ‐ All the address lines used by the decoder or memory chip =>
Memory Map ‐
All the address lines used by the decoder or memory chip =>
each byte is uniquely addressed = full address decoding
Full address
A14
CS2
16KB
A15
decoding
A16
EPROM
FFFFFFFFFF
FFFFF
FFFFF
FFFFF
A17
A0 A0 ‐ A13 ‐ A13
chip
FC000
FC000
FC000
A19=A18= =A14=1
select the EPROM
A18
OE
A19
A14
A CS10
A16, A15, A14 select
one EPROM chip
7
9FFFF
A15
B CS9
6
16KB
A16
C CS8
16KB
9C000
5
16KB
CS7
EPROM
16KB
16KB
EPROM
16KB
83FFF
83FFF
A19 = 1, A18 = 0, A17 = 0
activate the decoder
74LS138 4
EPROM
16KB
16KB
CS6
EPROM
chip
3
EPROM
chip
EPROM
80000
80000
A17
chip
EPROM
CS5
EPROM
E1
2
chip
chip
2 20 =
A18
CS4
c h p ip
hi c
E2
1
chip
1,048,576
A0
A19
CS3
E
0
OE
different
256KB
byte
MRDC
A17
RAM
addresses
A18
chip
CS1’
The same Memory‐ map
assignment
= 1Mbyte
3FFFF
3FFFF
3FFFF
3FFFF
A19
A0
MWTC
256KB
MRDC
A 256Kbyte = 2 18 RAM chip has
18 address lines, A0 ‐ A17
RAM
A17
chip
A18
A19, A18 assigned to 00 =>
CS active for every address
from 00000 to 3FFFF
CS1
WR RD
A18 = 0
A19 = 0
IO/M = 0
A19
00000
00000
00000
00000
00000
IO/M
WR
8088 Memory Map
RD
IO/M = 0 => Memory map
CS 1  A19  A18  IO / M  A19  A18  IO / M

Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips

Solution 2:

256KB 256KB 256KB 256KB CS CS CS CS Addr[19:2] Addr[1] 2‐ to ‐ 4 decoder
256KB
256KB
256KB
256KB
CS
CS
CS
CS
Addr[19:2]
Addr[1]
2‐ to ‐ 4
decoder
Addr[0]
CS
IO/M

519

Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips

Solution 1:

256KB 256KB 256KB 256KB CS CS CS CS Addr[17:0] Addr[18] 2‐ to ‐ 4 decoder
256KB
256KB
256KB
256KB
CS
CS
CS
CS
Addr[17:0]
Addr[18]
2‐ to ‐ 4
decoder
Addr[19]
CS
IO/M

518

Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips

Solution 3:

256KB 256KB 256KB 256KB Addr[19:18] CS CS CS CS Addr[16:7] Addr[5:0] Addr[17] 2‐ to ‐
256KB
256KB
256KB
256KB
Addr[19:18]
CS
CS
CS
CS
Addr[16:7]
Addr[5:0]
Addr[17]
2‐ to ‐ 4
decoder
Addr[6]
CS
IO/M
It is a bad design, but still works!

520

3/7/2010

Memory Address Decoding

Design a 1MB memory system consisting of multiple memory chips

Solution 4:

256KB 256KB CS CS
256KB
256KB
CS
CS

Addr[17:0]

Addr[18]

Addr[19]

IO/M

Addr[18] Addr[19]
Addr[18]
Addr[19]
512KB CS Addr[18] Addr[19]
512KB
CS
Addr[18]
Addr[19]

IO/M

IO/M

521

512KB CS Addr[18] Addr[19] IO/M IO/M 5 ‐ 21 Memory Address Decoding A[19] A[15:0] 64KB A[18]

Memory Address Decoding

A[19] A[15:0] 64KB A[18] A[17] A[16] IO/M CS A[15] A[14] A[13] A[12] A[11] A[10] A[8:0]

A[19]

A[15:0]

64KB

A[18]

A[17]

A[16]

IO/M

CS

A[15]

A[14]

A[13]

A[12]

A[11]

A[10]

A[8:0]

512B

CS

A[9]

523

 

Memory Address Decoding

 

Exercise Problem:

 

A 64KB memory chip is used to build a memory system with the starting address of 7000H. A block of memory locations in the memory chip are damaged.

FFFFH

FFFFH 7FFFFH  

7FFFFH

FFFFH 7FFFFH  
 

733FFH

3317H 3210H 0000H

3317H

3210H

0000H

73317H

Replace this block

73210H

73200H

70000H

64KB

64KB

Damaged block

1M addressing space

1M addressing space

 

522

 

Memory Address Decoding

 

Exercise Problem:

 

A 2MB memory chip with a damaged block (from 0DCF12H to 103745H) is used to build a 1MB memory system for an 8088based computer

1FFFFFH 1FFFFFH

1FFFFFH

1FFFFFH

512K

 

180000H

103745H

U se th ese two blocks
U
se
th
ese
two
blocks
U se th ese two blocks
 

0FFFFFH

0DCF12H

07FFFFH

512K

 

000000H

000000H

Damaged block

Damaged block

 

A[19]

A[20] A[19:0] CS
A[20]
A[19:0]
CS
 

A[19:0]

 

524

3/7/2010

Memory Address Decoding  Partial decoding — Example:  build a 32KB memory system by
Memory Address Decoding
 Partial decoding
— Example:
 build a 32KB memory system by using four 8KB memory chips
 The starting address of the 32KB memory system is 30000H
0
0 1 1 0
1 1
1
1 1 1 1
1 1 1 1
1 1 1 1
high addr. of chip #4
0
0 1 1 0
1 1 0
0 0 0 0 0 0 0 0 0 0 0 0
Low addr. o c ip #4
f
h
0
0 1 1 0
1 0
1
1 1 1 1
1 1 1 1
1 1 1 1
high addr. of chip #3
Chip #4
36000H
0
0 1 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Low addr. of chip #3
Chip #3
0
0 1 1 0
0 1
1
1 1 1 1
1 1 1 1
1 1 1 1
34000H
high addr. of chip #2
Chip #2
0
0 1 1 0
0 1
0 0 0 0 0 0 0 0 0 0 0 0 0
Low addr. of chip #2
32000H
Chip #1
30000H
0
0 1 1 0
0 0
1
1 1 1 1
1 1 1 1
1 1 1 1
high addr. of chip #1
0
0 1 1 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Low addr. of chip #1
5‐25
Memory Map ‐ Some address lines not used by the decoder or memory chip =>
Memory Map ‐
Some address lines not used by the decoder or memory
chip => mirror images = partial address decoding
Partial address
A14
CS2
16KB
A15
FFFFFFFFFFFFFFF
FFFFF
FFFFF
FFFFF
mirror
decoding
A16
EPROM
FC000
FC000
FC000
image
A17
A0 A0 ‐ A13 ‐ A13
chip
A18= =A14=1
select the EPROM
A18
DFFFF
OE
DC000
mirror
image
CF000
A14
A CS10
A16, A15, A14 select
one EPROM chip
7
CC000
A15
B CS9
6
16KB
A16
C CS8
16KB
5
16KB
CS7
EPROM
16KB
16KB
EPROM
9FFFF 9FFFF
A19 = 1, A17 = 0
activate the decoder
16KB
74LS138 4
EPROM
16KB
16KB
9C000
9C000
CS6
EPROM
chip
3
EPROM
base
chip
EPROM
A17
chip
EPROM
CS5
EPROM
image
E1
2
chip
83FFF
83FFF
chip
CS4
c h p ip
hi c
80000
80000
E2
1
chip
7FFFF
A0
A19
7FFFF
7FFFF
base
CS3
E
0
OE
7C000
7C000
7C000
image
64KB
MRDC
A15
RAM
A18
chip
CS1’
The same Memory‐ map
assignment
A0
3FFFF
3FFFF
3FFFF
3FFFF
3FFFF
A19
MWTC
64KB
30000
30000
30000
30000
A 64Kbyte = 2 16 RAM chip has
16 address lines, A0 ‐ A15
2FFFF
2FFFF
2FFFF
2FFFF
mirror
MRDC
RAM
20000
20000
20000
20000
images
A15
1FFFF
1FFFF
1FFFF
1FFFF
chip
10000
10000
10000
10000
A18
A19, A18 assigned to 00 =>
CS active for every address
from 00000 to 3FFFF
CS1
0FFFF
0FFFF
0FFFF
0FFFF
base
A19
WR RD
A18 = 0
A19 = 0
IO/M = 0
00000
00000
00000
00000
00000 image
00000
IO/M
WR
8088 Memory Map
RD
IO/M = 0 => Memory map
A16, A17 not used => four images for the same chip
Memory Address Decoding — Implementation of partial decoding 8KB 8KB 8KB 8KB CS CS CS
Memory Address Decoding
— Implementation of partial decoding
8KB
8KB
8KB
8KB
CS
CS
CS
CS
Addr[12:0]
Addr [ 13]
2
‐ to ‐ 4
decoder
Addr[14]
IO/M
 With the above decoding scheme, what happens if the processor accesses location
02117H, 32117H, and 9A117H?
 If two 16KB memory chips are used to implement the 32KB memory system, what
is the partial decoding circuit?
 What are the advantage and disadvantage of partial decoding circuits?
5‐26
Generating Wait States
 Wait states are inserted into memory read or write cycles if slow memories
are used in computer systems
 Ready signal is used to indicate if wait states are needed
data
Address
memory
8088
Delay
decoder
circuit
Ready
clr
Ready
clr
D
Q
D
Q
clk
5‐28

3/7/2010

Generating Wait States (Timing) clr Ready clr DD QQ DD QQ clk 5‐29
Generating Wait States (Timing)
clr
Ready
clr
DD
QQ
DD
QQ
clk
5‐29