CD4011BMS, CD4012BMS

CD4023BMS
CMOS NAND Gates

November 1994

Features

Pinouts

High-Voltage Types (20V Rating)

CD4011BMS
TOP VIEW

Propagation Delay Time = 60ns (typ.) at CL = 50pF,

VDD = 10V
A 1

14 VDD

B 2

13 H

J = AB 3

12 G

K = CD 4

11 M = GH

Buffered Inputs and Outputs

Standardized Symmetrical Output Characteristics
Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC
100% Tested for Maximum Quiescent Current at 20V

C 5

10 L = EF

D 6

9 E

VSS 7

8 F

5V, 10V and 15V Parametric Ratings

Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standards No. 13B, Standard Specifications for Description of B Series CMOS Devices

CD4012BMS
TOP VIEW

J = ABCD 1

Description
CD4011BMS - Quad 2 Input

14 VDD

A 2

13 K = EFGH

B 3

12 H

C 4

11 G

D 5

10 F

CD4012BMS - Dual 4 Input

NC 6

9 E

CD4023BMS - Triple 3 Input

VSS 7

CD4011BMS, CD4012BMS, and CD4023BMS NAND gates

provide the system designer with direct implementation of
the NAND function and supplement the existing family of
CMOS gates. All inputs and outputs are buffered.

8 NC
NC = NO CONNECTION

CD4023BMS
TOP VIEW

The CD4011BMS, CD4012BMS and the CD4023BMS is

supplied in these 14 lead outline packages:

A 1

14 VDD

B 2

13 G

CD4011B

CD4012B

CD4023B

D 3

12 H

Braze Seal DIP

H4Q

H4H

H4Q

E 4

11 I

Frit Seal DIP

H1B

H1B

H1B

F 5

10 L = GHI

Ceramic Flatpack

H3W

H3W

H3W

K = DEF 6
VSS 7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999

7-53

9 J = ABC
8 C

File Number

3079

CD4011BMS, CD4012BMS, CD4023BMS

Functional Diagrams

J = AB

VDD

13

12

11

K = CD

14

L = EF
C

10

VSS

M = GH

CD4011BMS

J = ABCD

14

VDD

13

12

11

10

NC

NC

VSS

K = EFGH

NC = NO CONNECTION

CD4012BMS

14

VDD

13

12

11

10

L = GHI
F

VSS

K = DEF
J = ABC

CD4023BMS

7-54

Specifications CD4011BMS, CD4012BMS, CD4023BMS

Absolute Maximum Ratings

Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for
10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER
Supply Current

SYMBOL
IDD

CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND

VDD = 18V, VIN = VDD or GND

Input Leakage Current

IIL

VIN = VDD or GND

VDD = 20

VDD = 18V
Input Leakage Current

IIH

VIN = VDD or GND

VDD = 20

GROUP A
SUBGROUPS

LIMITS
TEMPERATURE

MIN

MAX

+25

0.5

+125oC

50

-55oC

0.5

+25o

-100

nA

+125oC

-1000

nA

-55oC

-100

nA

+25oC

100

nA

+125oC

1000

nA

100

nA

50

mV

-55oC

Output Voltage

VOL15

VDD = 15V, No Load

1, 2, 3

+25oC, +125oC, -55oC

Output Voltage

VOH15

VDD = 15V, No Load (Note 3)

1, 2, 3

+25oC, +125oC, -55oC 14.95

VDD = 18V

Output Current (Sink)

IOL5

VDD = 5V, VOUT = 0.4V

UNITS

oC

+25oC

0.53

mA

Output Current (Sink)

IOL10

VDD = 10V, VOUT = 0.5V

+25oC

1.4

mA

Output Current (Sink)

IOL15

VDD = 15V, VOUT = 1.5V

+25oC

3.5

mA

+25oC

-0.53

mA

+25oC

-1.8

mA

Output Current (Source)

Output Current (Source)

IOH5A
IOH5B

VDD = 5V, VOUT = 4.6V

VDD = 5V, VOUT = 2.5V

Output Current (Source)

IOH10

VDD = 10V, VOUT = 9.5V

+25oC

-1.4

mA

Output Current (Source)

IOH15

VDD = 15V, VOUT = 13.5V

+25oC

-3.5

mA

+25oC

-2.8

-0.7

+25oC

0.7

2.8

N Threshold Voltage
P Threshold Voltage
Functional

VNTH
VPTH
F

VDD = 10V, ISS = -10A

VSS = 0V, IDD = 10A
VDD = 2.8V, VIN = VDD or GND

+25oC

VDD = 20V, VIN = VDD or GND

+25oC

VDD = 18V, VIN = VDD or GND

8A

+125oC

VDD = 3V, VIN = VDD or GND

8B

-55oC

VOH > VOL <

VDD/2 VDD/2

Input Voltage Low

(Note 2)

VIL

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

+25oC, +125oC, -55oC

1.5

Input Voltage High

(Note 2)

VIH

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

+25oC, +125oC, -55oC

3.5

Input Voltage Low

(Note 2)

VIL

VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3

+25oC, +125oC, -55oC

Input Voltage High

(Note 2)

VIH

VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3

+25oC, +125oC, -55oC

11

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.
2. Go/No Go test with limits applied to inputs

7-55

3. For accuracy, voltage is measured differentially to VDD. Limit

is 0.050V max.

Specifications CD4011BMS, CD4012BMS, CD4023BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER
Propagation Delay

Transition Time

SYMBOL
TPHL
TPLH

CONDITIONS (NOTE 1, 2)

GROUP A
SUBGROUPS TEMPERATURE

VDD = 5V, VIN = VDD or GND

9
10, 11

TTHL
TTLH

VDD = 5V, VIN = VDD or GND

9
10, 11

+25oC
+125oC,

-55oC

+25oC
+125oC,

-55oC

LIMITS
MIN

MAX

UNITS

250

ns

338

ns

200

ns

270

ns

NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

IDD

VDD = 5V, VIN = VDD or GND

1, 2

-55oC, +25oC

0.25

7.5

-55 C, +25 C

0.5

+125oC

15

0.5

+125 C
VDD = 10V, VIN = VDD or GND

VDD = 15V, VIN = VDD or GND

1, 2

1, 2

-55oC,

+25oC

30

Output Voltage

VOL

VDD = 5V, No Load

1, 2

+25oC, +125oC,
-55oC

50

mV

Output Voltage

VOL

VDD = 10V, No Load

1, 2

+25oC, +125oC,
-55oC

50

mV

Output Voltage

VOH

VDD = 5V, No Load

1, 2

+25oC, +125oC,
-55oC

4.95

Output Voltage

VOH

VDD = 10V, No Load

1, 2

+25oC, +125oC,
-55oC

9.95

Output Current (Sink)

IOL5

VDD = 5V, VOUT = 0.4V

1, 2

+125oC

0.36

mA

-55oC

0.64

mA

+125oC

0.9

mA

-55oC

1.6

mA

oC

+125

Output Current (Sink)

Output Current (Sink)

Output Current (Source)

Output Current (Source)

Output Current (Source)

Output Current (Source)

IOL10

IOL15

IOH5A

IOH5B

IOH10

IOH15

VDD = 10V, VOUT = 0.5V

1, 2

VDD = 15V, VOUT = 1.5V

1, 2

VDD = 5V, VOUT = 4.6V

1, 2

VDD = 5V, VOUT = 2.5V

1, 2

VDD = 10V, VOUT = 9.5V

1, 2

VDD =15V, VOUT = 13.5V

1, 2

+125oC

2.4

mA

-55oC

4.2

mA

+125oC

-0.36

mA

-55oC

-0.64

mA

+125oC

-1.15

mA

-55oC

-2.0

mA

+125oC

-0.9

mA

-55oC

-1.6

mA

+125oC

-2.4

mA

-55oC

-4.2

mA

Input Voltage Low

VIL

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

+25oC, +125oC,
-55oC

Input Voltage High

VIH

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

+25oC, +125oC,
-55oC

Propagation Delay

TPHL
TPLH

1, 2, 3

+25oC

120

ns

1, 2, 3

+25oC

90

ns

VDD = 10V
VDD = 15V

7-56

Specifications CD4011BMS, CD4012BMS, CD4023BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER

SYMBOL

Transition Time

TTHL
TTLH

Input Capacitance

CONDITIONS
VDD = 10V
VDD = 15V

CIN

Any Input

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 2, 3

+25oC

100

ns

1, 2, 3

+25 C

80

ns

1, 2

+25oC

7.5

pF

NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Supply Current

IDD

N Threshold Voltage

VNTH

N Threshold Voltage
Delta

VNTH

P Threshold Voltage

VPTH

P Threshold Voltage
Delta

VPTH

Functional

CONDITIONS

NOTES

TEMPERATURE

UNITS

+25 C

2.5

1, 4

+25oC

-2.8

-0.2

VDD = 10V, ISS = -10A

1, 4

+25oC

VSS = 0V, IDD = 10A

1, 4

+25oC

0.2

2.8

1, 4

+25oC

+25oC

VOH >
VDD/2

VOL <
VDD/2

1, 2, 3, 4

+25oC

1.35 x
+25oC
Limit

ns

VDD = 10V, ISS = -10A

VSS = 0V, IDD = 10A

VDD = 18V, VIN = VDD or GND

TPHL
TPLH

MAX

1, 4

VDD = 20V, VIN = VDD or GND

VDD = 3V, VIN = VDD or GND

Propagation Delay Time

MIN

VDD = 5V

3. See Table 2 for +25oC limit.

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER

SYMBOL

DELTA LIMIT

Supply Current - SSI

IDD

0.1A

Output Current (Sink)

IOL5

20% x Pre-Test Reading

IOH5A

20% x Pre-Test Reading

Output Current (Source)

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
METHOD

GROUP A SUBGROUPS

Initial Test (Pre Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

100% 5004

1, 7, 9, Deltas

100% 5004

1, 7, 9

100% 5004

1, 7, 9, Deltas

100% 5004

2, 3, 8A, 8B, 10, 11

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11

CONFORMANCE GROUP

PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A

7-57

READ AND RECORD

IDD, IOL5, IOH5A

Specifications CD4011BMS, CD4012BMS, CD4023BMS

TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
METHOD

GROUP A SUBGROUPS

Subgroup B-5

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

Subgroup B-6

Sample 5005

1, 7, 9

Sample 5005

1, 2, 3, 8A, 8B, 9

CONFORMANCE GROUP
Group B

Group D

READ AND RECORD

Subgroups 1, 2, 3, 9, 10, 11

Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS
Group E Subgroup 2

TEST

READ AND RECORD

MIL-STD-883
METHOD

PRE-IRRAD

POST-IRRAD

PRE-IRRAD

POST-IRRAD

5005

1, 7, 9

Table 4

1, 9

Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION

OPEN

GROUND

VDD

9V -0.5V

50kHz

3, 4, 10, 11

1, 2, 5, 6, 8, 9, 12,
13

1, 13

2 - 5, 9 - 12

6, 9, 10

1 - 5, 8, 11 - 13

25kHz

PART NUMBER CD4011B

Static Burn-In
1 Note 1

3, 4, 10, 11

1, 2, 5 - 9, 12, 13

14

Static Burn-In
2 Note 1

3, 4, 10, 11

1, 2, 5, 6, 8, 9,
12 - 14

Dynamic BurnIn Note 1

14

3, 4, 10, 11

1, 2, 5, 6, 8, 9,
12 - 14

Irradiation
Note 2

PART NUMBER CD4012B

Static Burn-In
1 Note 1

1, 6, 8, 13

2 - 5, 7, 9 - 12

14

Static Burn-In
2 Note 1

1, 6, 8, 13

2 - 5, 9 - 12, 14

Dynamic BurnIn Note 1

6, 8

14

1, 6, 8, 13

2 - 5, 9 - 12, 14

Irradiation
Note 2

PART NUMBER CD4023B

Static Burn-In
1 Note 1

6, 9, 10

1 - 5, 7, 8, 11 - 13

14

Static Burn-In
2 Note 1

6, 9, 10

1 - 5, 8, 11 - 14

Dynamic BurnIn Note 1

14

6, 9, 10

1 - 5, 8, 11 - 14

Irradiation
Note 2
NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V 0.5V

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

7-58

CD4011BMS, CD4012BMS, CD4023BMS

Schematic and Logic Diagrams
14

p
1*

(9, 5, 12)

p
p

2*

14

3*(1, 11)

n
(8, 6, 13)

VDD
p

VDD

4*(2, 12)

n
p

3 (10, 4, 11)
n

5*(8, 13)

VDD

n 6(9, 10)
VDD
7

VSS

VSS

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION NETWORK

VSS
VSS

1 OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION NETWORK

7
1 OF 3 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)

3(1, 11)

1(8, 6,13)
3
2(9, 5, 12)

4(2, 12)

(10, 4, 11)

(9, 10)

LOGIC DIAGRAM

LOGIC DIAGRAM

5(8, 13)

CD4011BMS

CD4023BMS

14

2(12)

VDD

2*(12)

3(11)

p
n

1
(13)

4(10)

3*(11)

5(9)

LOGIC DIAGRAM

p
VDD

4*(10)

p
n
p

5*(9)

VSS

n
1
1 OF 2 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)

n
n

VSS

CD4012BMS

7-59

(13)

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION
NETWORK

CD4011BMS, CD4012BMS, CD4023BMS

Typical Performance Characteristics
105
POWER DISSIPATION PER GATE (PD) (W)

OUTPUT VOLTAGE (VO) (V)

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 15V

15

10V
10

5V
5

o
8 AMBIENT TEMPERATURE (TA) = +25 C
6
4

SUPPLY VOLTAGE (VDD) = 15V

104 8

10V

6
4

10V
5V

103

8
6
4
2

102

8
6
4

CL = 50pF

CL = 15pF

10
2

10
15
INPUT VOLTAGE (VI) (V)

20

25

AMBIENT TEMPERATURE (TA) = +25oC

30

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

25
20
15

10V

10
5

5V
0

4 6 8

4 6 8

4 6 8

103
10
102
INPUT FREQUENCY (fI) (kHz)

104

FIGURE 2. TYPICAL POWER DISSIPATION CHARACTERISTICS

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

FIGURE 1. TYPICAL VOLTAGE TRANSFER

CHARACTERISTICS

4 68

5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V

7.5
5.0
2.5

5V
0

5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15
-10
-5

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15
-10
-5

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0
-5
-10
-15

-10V

-20
-25

-15V

-30

AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-5

-10V

-15V

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

-10

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

7-60

CD4011BMS, CD4012BMS, CD4023BMS

Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC

AMBIENT TEMPERATURE (TA) = +25oC

175
150

TRANSITION TIME (tTHL, tTLH) (ns)

PROPAGATION DELAY TIME PER GATE

(tPHL, tPLH) (ns)

200

(Continued)

SUPPLY VOLTAGE (VDD) = 5V

125
100
10V
75
50

15V

25
0
10

20

30

40

50

60

70

80

90

200

100
10V
15V

50

0
0

100

SUPPLY VOLTAGE (VDD) = 5V

150

20

40
60
80
100
LOAD CAPACITANCE (CL) (pF)

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME PER GATE

AS A FUNCTION OF LOAD CAPACITANCE

FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

Chip Dimensions and Pad Layouts

CD4011BMSH

CD4012BMSH

METALLIZATION:
PASSIVATION:

Thickness: 11k 14k,

AL.

10.4k - 15.6k, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS:

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

CD4023BMSH

7-61

0.0198 inches - 0.0218 inches

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