POLITEKNIK SULTAN HAJI AHMAD SHAH KUANTAN

DEPARTMENT OF ELECTRICAL ENGINEERING

DEE6113 CMOS IC DESIGN

Practical Work 4

Layout Design and Simulation of Basic

Logic Gates
Registration
No.

No

Name

Practical
Work Report
(Cognitive)

Practical Skill
Marks
(Psychomotor)

Total
Marks

1.

/ 30

/ 70

/ 100

2.

/ 30

/ 70

/ 100

CLASS

LECTURER NAME

: PN. NOORFOZILA BINTI BAHARI

DATE SUBMITTED

(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)

Practical Work Report Marks Distribution

Report format :
1.

Title and Outcomes

/4

2.

Result

/ 15

3.

Discussion

/7

4.

Conclusion

/4
TOTAL :

/ 30

DEE6113 CMOS IC Design

PRACTICAL WORK 4
4.1 TITLE: Layout Design and Simulation of Basic Logic Gates.
4.2 LEARNING OUTCOMES
At the end of this practical work session, the student should be able to:
a. to design the layout of the following logic gates:
i. 2-input NAND gate and 2-input AND gate
ii. 2-input NOR gate and 2-input OR gate
b. to simulate the layout of each gate in (1)
c. to design the layout of IC 4011/ IC 4081/ IC 4001 / IC 4071
4.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software.
4.4 PROCEDURE
Part A : Designing and simulating the layout of 2 input NAND gate .

Figure 4.1 : Symbol of 2-input NAND

gate

Figure 4.2 : CMOS static logic diagram of

2-input NAND gate

1. Based on figure 4.2, draw the stick diagram of 2 input NAND gate using Eulers path
method.

Figure 4.3 : Stick diagram of

2-input NAND gate

2. Open the Microwind Editor window.

3. Select the Foundry file from File menu. Select cmos012.rul file.
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DEE6113 CMOS IC Design

4. Draw the layout of 2-input NAND gate based on the stick diagram in Figure 4.3.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2

Figure 4.4 : Layout of 2 input NAND gate

5. Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
6. Add clock to input A and input B of the layout. To observe the output, place a Visible Node
icon at the output.
7. Lets set the value for of the pulse at input A as the following:
Time low = 0.2 ns
Time high = 0.2 ns
Rise time = Fall time = 0.001 ns
8. Click OK.
9. Lets set the value for of the pulse at input B as the following:
Time low = 0.4 ns
Time high = 0.4 ns
Rise time = Fall time = 0.001 ns
10. Click OK.
11. Save your layout.
12. Simulate the inverter layout by selecting:

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DEE6113 CMOS IC Design

>Simulate> Run Simulation>Voltage vs Time (default) on the main menu. The timing
diagram of the 2 input NAND gate appear, as shown in figure 4.5.

Figure 4.5 : Timing diagram

of 2-input NAND gate

13. Produce the truth table for 2-input NAND gate based on the timing diagram produced in
step 8. The truth table for 2-input NAND gate is shown in figure 4.6.

Figure 4.6 : Truth table of 2-input NAND gate

14. Measure the optimized area of the layout (the unit is 2).

Part B : Designing and simulating the layout of 2-input AND gate .

Figure 4.7 : Symbol of 2-input AND gate

1.

Figure 4.8 : CMOS static logic diagram

of 2-input AND gate
Based on figure 4.8, draw the stick diagram for 2-input AND gate using Eulers path
method.

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DEE6113 CMOS IC Design

Figure 4.9: Stick diagram of 2-input AND gate

2. Open the Microwind Editor window.
3. Select the Foundry file from File menu. Select cmos012.rul file.
4. Draw the layout of 2-input AND gate based on the stick diagram in figure 4.9.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2

Figure 4.10: Layout of 2-input AND gate

5. Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
6. Add clock to input A and input B of the layout. To observe the output, add Visible Node icon
at the output. (The settings of the clock pulses are the same as in Part A)
7. Save your layout.
8. Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu. The timing
diagram of the 2-input AND gate appear, as shown in figure 4.11.

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DEE6113 CMOS IC Design

Figure 4.11 : Timing diagram of 2-input AND gate

9. Produce the truth table for 2-input AND gate based on the timing diagram produced in step
8. The truth table for 2-input AND gate is shown in figure 4.12.

Figure 4.12 : Truth table of 2 input AND gate

10. Measure the optimized area of the layout (the unit is 2).

Part C : Designing and simulating the layout of 2 input NOR gate .

1. Draw the CMOS static logic diagram of 2-input NOR gate.
2. From the static logic diagram, draw the stick diagram of 2-input NOR gate using Eulers path
method.
3. Repeat Step 2 until Step 10 in Part B for 2-input NOR gate.

Part D : Designing and simulating the layout of 2 input OR gate .

1. Draw the CMOS static logic diagram of 2-input OR gate.
2. From the static logic diagram, draw the stick diagram of 2-input OR gate using Eulers path
method.
3. Repeat Step 2 until Step 10 in Part B for 2-input OR gate.

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DEE6113 CMOS IC Design

Part E : Designing the layout of IC 4011/ IC 4081/ IC 4001 / IC 4071

1. Each group is assigned to design only one IC layout.
Assigned IC Layout : ___________________
2. Design the layout of the assigned IC based on the CMOS IC logic gates internal diagrams
shown in Appendix B.
3. Do the DRC to ensure that your design follows all the design rules.
4. Measure the optimized area of the layout (the unit is 2).

Figure 4.13 : Layout example of IC 4011 (NAND gate IC)

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DEE6113 CMOS IC Design

4.5 RESULT
In your report, include the results of the following:
1. 2-input NAND gate and 2-input AND gate :
a) CMOS static logic diagram
b) Stick diagram
c) Layout
d) Timing diagram
e) Truth table
f) Optimized layout area

(6 marks)

2. 2-input NOR gate and 2-input OR gate:

a) CMOS static logic diagram
b) Stick diagram
c) Layout
d) Timing diagram
e) Truth table
f) Optimized layout area

(6 marks)

3. IC Layout and the optimized layout area of the IC that has been assigned to you.
(3 marks)

4.6 DISCUSSION
1. What is the function of stick diagram in integrated circuit layout design?
(2 marks)
2. State the colour codes for stick diagram.
(2 marks)
3. Explain the use of metal2 layer in designing the layout of logic gates IC in Part E.
(3 marks)

4.7 CONCLUSION
Write TWO (2) conclusions for the practical work that you have done.
(4 marks)

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DEE6113 CMOS IC Design

APPENDIX B

CMOS LOGIC GATES INTERNAL DIAGRAM

IC 4011 2 input NAND gate

IC 4001 2 input NOR gate

IC 4081 2 input AND gate

IC 4071 2 input OR gate

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DEE6113 CMOS IC Design

PRACTICAL SKILL ASSESSMENT RUBRIC

DEE6113 CMOS IC DESIGN
PRACTICAL WORK 4
Student Name :

Class :

Student ID# :

Date :

ASPECTS

A.

Technology feature

B.

Design rule

C.

Transistor size

D.

Metal layers

E.
F.

No DRC error
display
Layout Design
input / output /
floorplan

EXCELLENT
4-5
Use correct technology feature
for ALL parts of the layout.
Follow lambda design rule for
minimum width and spacing for
ALL polygons.
Use correct PMOS and NMOS
transistor size.
Use correct number of metal
layers and width.
Able to produce No DRC error
display for ALL layouts.

SCORE DESCRIPTION
MODERATE
2-3
Use correct technology feature
for parts of the layout.

POOR
1

SCALE

Use other technology feature.

x1

Follow lambda design rule for

MANY of the polygons.

Follow lambda design rule for

ONLY a few of the polygons.

x1

Use acceptable PMOS and NMOS

transistor size.
Use correct metal layers but
incorrect width.
Able to produce No DRC error
display for some of the layouts.

Use incorrect PMOS and

NMOS transistor size.
Use incorrect metal layers and
width.
Not able to produce No DRC
error display at ALL.
Produce acceptable floorplan
and input / output layout
design.
Not able to produce any
simulation for ALL of the
layouts.
Produce large layout size (end
product).

Produce good floorplan and

input / output layout design.

Produce appropriate floorplan

and input / output layout design.

Layout simulation

Able to produce the simulation

of ALL layouts correctly.

Able to produce the simulation

for some of the layouts correctly.

H.

Layout size (end

product)

Produce small layout size (end

product).

Produce acceptable layout size

(end product).

TOTAL

SCORE

x2
x2
x2
x2

x2
x2
/ 70

...
Supervisor Name and Signature