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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

An MRAS-Based Diagnosis of Open-Circuit Fault in

PWM Voltage-Source Inverters for PM Synchronous
Motor Drive Systems
Shin-Myung Jung, Student Member, IEEE, Jin-Sik Park, Member, IEEE, Hag-Wone Kim, Associate Member, IEEE,
Kwan-Yuhl Cho, Student Member, IEEE, and Myung-Joong Youn, Senior Member, IEEE

AbstractIn this paper, a simple and low-cost open-circuit fault

detection and identification method for a pulse-width modulated
(PWM) voltage-source inverter (VSI) employing a permanent magnet synchronous motor is proposed. An open-circuit fault of a
power switch in the PWM VSI changes the corresponding terminal
voltage and introduces the voltage distortions to each phase voltage. The proposed open-circuit fault diagnosis method employs the
model reference adaptive system techniques and requires no additional sensors or electrical devices to detect the fault condition and
identify the faulty switch. The proposed method has the features
of fast diagnosis time, simple structure, and being easily inserted
to the existing control algorithms as a subroutine without major
modifications. The simulations and experiments are carried out
and the results show the effectiveness of the proposed method.
Index TermsFault detection, fault diagnosis, fault identification, model reference adaptive system (MRAS), open-circuit fault,
pulse-width modulated voltage-source inverter (PWM VSI).

I. INTRODUCTION
HE permanent magnet synchronous motor (PMSM) is increasingly used in powered wheelchairs, electric vehicles,
aerospace, medical and military applications, and nuclear power
plants due to its advantages such as high power density, torque
to inertia ratio, efficiency, and simple control [1]. In these applications, because an accident or fault can result in huge damages
to the human life and environments, the reliability of the machine drives is one of the most important factors to guarantee
the safe, continuous and high performance operation under even
some accidents or faults. Generally, when an accident or fault
occurs, the drive system has to be stopped for emergency or
nonprogrammed maintenance schedule. Due to the high cost of

Manuscript received April 1, 2012; revised June 5, 2012; accepted July 26,
2012. Date of current version November 22, 2012. This work was supported
by a Human Resources Development grant of the Korea Institute of Energy
Technology Evaluation and Planning funded by the Ministry of Knowledge
Economy, Republic of Korea (2011H100100110). Recommended for publication by Associate Editor J. O. Ojo.
S.-M. Jung and M.-J. Youn are with the Department of Electrical Engineering,
KAIST, Yuseong-gu, Daejeon 305-701, Korea (e-mail: caesarju@kaist.ac.kr;
mmyoun@ee.kaist.ac.kr).
J.-S. Park is with the CDS Circuit Technology Group, Samsung ElectroMechanics Company, Yeongtong-gu, Suwon, Gyeonggi-do 443-743, Korea
(e-mail: Park.jinsik0@gmail.com).
H.-W. Kim and K.-Y. Cho are with the Department of Control and Instrumentation Engineering, Korea National University of Transportation, Chungju,
Chungbuk 380-702, Korea (e-mail: khw@ut.ac.kr; kycho@ut.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2212916

Fig. 1.

General configuration of a PMSM drive system.

unexpected maintenance, the development of a reliable system

is the area of interest. A control system with minimum or zero
effects from the faults is called a fault-tolerant control system,
and it performs the following three tasks [2]: 1) fault detection;
2) fault identification; and 3) remedial actions. The fault detection is the process to determine whether the system is healthy or
not. The fault identification is performed after the fault detection
to identify the location, type, and nature of the fault. Finally, the
remedial actions, also known as fault isolation, are the process
to remove the faulty devices and reconfigure the system for a
safe and continuous operation. Among these three tasks, the
fault detection and fault identification are considered as a prime
process for the practical implementation and are often called as
a fault diagnosis.
Typically, the motor drive systems consist of a microcontroller unit (MCU) for implementing the control algorithms, a
power electronic converter, i.e., pulse-width modulated voltagesource inverter (PWM VSI), and a motor as shown in Fig. 1.
In this figure, various types of faults can occur in the following
components or subsystems such as:
1) microcontroller unit (MCU);
2) motor (PMSM);
3) power converter (PWM VSI);
4) sensorsvoltage and current/position encoder;
5) connectors and wires.
The MCU, connectors, and wires have very low failure rates
compared to the remaining of the system. This is because the
MCU is very reliable and does not involve high voltages or currents. The connectors and wires are static and have low failure
rates if selected and installed properly. Some of the machine

0885-8993/$31.00 2012 IEEE

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

faults caused by the winding insulation failure due to the excessive voltage or current stress can practically be removed because
the line voltage surges are absorbed at the input side of the power
converter and the current stresses are limited by the overcurrent
protection of the power converter [3]. In recent years, the sensor faults have been increasingly concerned in the literature
works [4][7]. The sensor faults including biased signal, loss of
signal, incorrect gain, and unresponsive signal are mainly due
to the broken or bad connections, bad communications, or some
hardware or software malfunction. Therefore, if the connectors
and wires are installed correctly, the failure rates of the sensor
faults can be lowered. For these reasons, those faults are not
considered in this paper.
On the other hand, the power converter failures can be a
critical factor to the overall drive system and cause system shutdowns; therefore, these require a high cost of unexpected maintenance. It is estimated that about 38% of all the failures are
found in the power converter [8] and the most of faults are
occurred to the power switches [9]. In response to a control
algorithm, a voltage command is generated, and the VSI synthesizes this voltage command using the power switches, i.e.,
insulated-gate bipolar transistor (IGBT) and MOSFET, with the
techniques such as the sinusoidal PWM (SPWM) or spacevector PWM (SVPWM). There could be a quite high chance of
failure in the switching devices due to the high electrical and
thermal stresses [10]. The failure of switching devices can take
place in the form of short circuit or open circuit. The shortcircuit fault may occur due to an improper gate signal so that
both power switches in a leg of the VSI are turned ON. This
results in a short circuit of the capacitor in the dc link that blows
out the other components particularly switching devices. Therefore, the short-circuit fault is one of the most fatal accidents and
the most important thing in the drive system is to minimize the
time between short-circuit fault initiation and appropriate reaction. Consequently, the control circuits of the switching devices
are designed to have a fast fault diagnosis characteristic to prevent the abnormal overcurrent and mostly the hardware-based
protection schemes are employed. The open-circuit fault, on the
other hand, is often overlooked since it has the characteristic
of slow response and less danger to the whole drive system
compared with the short-circuit fault. The open-circuit fault
may result from the disconnection of a wire from the switching devices due to a thermic cycling or a gate driver failure.
The open-circuit fault leads to the current imbalance in both the
faulty and healthy phases and results in the pulsating currents
and torques, which highly degrades the driving performances.
The open-circuit fault is not generally harmful to the machine
drives and does not cause system shutdowns, but could lead
to the secondary faults at the other components [3]. The opencircuit fault is one of the general faults and can be frequently
taken place in the drive system, though, and the literature has
much concerned about the fault.
Several pieces of research have been developed and published to diagnose the open-circuit fault in motor drive systems [2], [10], [11][23], [32][38]. The comparison between
the actual and voltage command methods [2], [10], [11] is made,
which is based on an analytical model of the PWM VSI and

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requires the voltage measurements or sensors at the specific

points of the drive system. In [12], the diagnosis is based on the
fact that during the fault condition the voltage across the lower
switch is about one half of the dc-link voltage. These methods [2], [10][12] have shown the characteristic of the fast fault
diagnosis performance and thus reduced the time between the
fault occurrence and its diagnosis. The major problem of these
methods, however, is the increase in system cost due to the additional hardware equipment such as voltage sensors and electric
circuits. In [13], the authors proposed two techniques, the slope
method and instantaneous frequency method. The first one uses
the analysis of the currentvector trajectory to detect the fault
condition and identify the faulty switch. The second one, however, can only determine the fault condition of the PWM VSI
from the instantaneous frequency of the current vector but cannot identify the faulty switch. Parks vector method [14] and the
normalized dc current method [15][18] detect the fault condition and identify the faulty switch by calculating the midpoint
position of the current trajectory, which is the mean value of
the ac current space vector over one period. All these suggested
methods have shown acceptable performances but take at least
one fundamental period between the fault occurrence and its diagnosis. Recently, in [19], a fault diagnosis method in the case of
the trapezoidal back electromotive force (EMF) is proposed. The
proposed scheme uses the observed phase current information
and detects the fault condition based on the operating characteristic of the brushless dc motors. This method, however, is only
suitable for the trapezoidal back-EMF type motors. The artificial intelligence methods, such as wavelet fuzzy network [20]
and wavelet neural network [21][23], have also been proposed.
However, these digital-control-based algorithms have a major
drawback of the complicated and excessive computing process.
This paper proposes a simple and low-cost open-circuit fault
diagnosis algorithm in the PWM VSI for PMSM. Such technique requires no additional sensors and is based on the analytical model of the PWM VSI. The proposed fault diagnosis
method has the fast, simple and low-cost characteristics and can
be easily embedded in the existing PMSM drive system as a subroutine without major modifications. This proposed method is
implemented in a digital manner using a MCU TMS320F28335
from Texas Instruments, Incorporated. The simulation and experimental results show the validity of the proposed diagnosis
method.
II. ANALYSIS OF THE OPEN-CIRCUIT FAULT IN THE PWM VSI
Fig. 2 shows the basic configuration of phase A leg of a threephase PWM VSI. When the system is under the normal condition
as can be seen in Fig. 2(a), the terminal voltage of phase A,
va0 , is determined by the phase current ias and the switching
function Sa of QaU and QaL . If the switching function is 1,
which means that QaU is turned ON and QaL is turned OFF, the
terminal voltage of phase A is equal to Vdc /2, where Vdc is the
dc-link voltage. If the switching function is 0, which means that
QaU is turned OFF and QaL is turned ON, va0 = Vdc /2. The
possible terminal voltages according to the switching function
and the direction of phase current under the normal condition are

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Fig. 2. Basic configuration of phase A leg of a three-phase PWM VSI.

(a) Normal condition. (b) Open-circuit fault in the upper switch Q a U .
TABLE I
TERMINAL VOLTAGES OF PHASE A UNDER THE NORMAL CONDITION

Fig. 3.

Relationship between terminal voltages and phase voltages.

satisfied as
ias + ibs + ics = 0.

TABLE II
TERMINAL VOLTAGES OF PHASE A UNDER THE OPEN-CIRCUIT
FAULT CONDITION

(2)

Also, the sum of each phase back EMF is equal to zero at

any instant under the assumption that the air-gap magnetic flux
distribution is a sinusoid. From (2) and this assumption, the
following condition is satisfied for the PMSM as
d
(ias +ibs +ics )
dt
+ ecs ) = 0
(3)

vas + vbs + vcs = Rs (ias + ibs + ics ) + Ls

+ (eas + ebs

represented in Table I. Unlike the normal condition, however, an

open-circuit fault in the upper switch QaU results in changing
the corresponding terminal voltage when the phase current ias
is positive and the switching function Sa is 1, since the upper
switch QaU is not working properly. In this case, the terminal
voltage of phase A is not equal to Vdc /2, but equal to Vdc /2. The
equivalent circuit after the open-circuit fault occurrence to the
upper switch QaU is shown in Fig. 2(b), and the corresponding
terminal voltages are represented in Table II.
From the aforementioned analysis, it is obvious that the phase
voltages may have the voltage deviations in the steady state after
the fault occurrence from the normal condition. Based on this
fact, the proposed fault diagnosis method indirectly observes
these voltage deviations using the analytical model of the PWM
VSI and the fault diagnosis can be achieved.
To take a close look at the effect of the open-circuit fault of a
switch on the phase voltages, the knowledge of the relationship
between the terminal voltages and the phase voltages is required.
This relationship can be represented as follows [1]:

vas
va0
vb0 = vbs + vs0
(1)
vc0
vcs
where vas , vbs , and vcs are the phase voltages and vs0 is the
neutral to center voltage, as shown in Fig. 3. In a three-phase
three-wire system, the following condition by Kirchoffs law is

where Rs is a stator resistance, Ls is a stator inductance, and

eas , ebs , and ecs represent the corresponding phase back EMFs,
respectively. From (1) to (3), the neutral to center voltage vs0
becomes
1
vs0 = (va0 + vb0 + vc0 ).
(4)
3
Therefore, the relationship between the terminal voltages and
the phase voltages can be represented as follows:

vas
2 1 1
va0
1
vbs = 1 2 1 vb0 .
(5)
3
1 1 2
vcs
vc0
On the other hand, the effect of an open-circuit fault on one
of the switches can be represented by a deviation value from
the terminal voltages of the PWM VSI. If va0 is considered as
representing the voltage deviation due to an open-circuit fault in
the upper switch QaU , the phase voltages after the open-circuit
fault occurrence are represented as follows:

2 1 1
va0 va0
vas f
vbs f = 1 1 2 1
(6)
vb0
3
1 1 2
vcs f
vc0
where vas f , vbs f , and vcs f are the phase voltages after the
open-circuit fault occurs to the upper switch QaU . After some
calculations, (6) can be expressed as

2va0
vas f
vas
vas
vas dist
vbs f = vbs + 1 va0 = vbs + vbs dist
3
vcs f
vcs
va0
vcs
vcs dist
(7)

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

where vas dist , vbs dist , and vcs dist are the phase voltage
deviations introduced by the open-circuit fault occurred to the
upper switch QaU . As can be seen in (7), the phase voltage after
the open-circuit fault occurrence can be divided into two parts.
The first term of (7), vk s (k = {a, b, c}), are the normal phase
voltages and the second term of (7), vk s dist (k = {a, b, c}), are
the voltage deviations due to the open-circuit fault in the upper
switch QaU . These phase voltage deviations can be considered
as voltage distortions induced by the open-circuit fault and
observed from the machine parameters, which is discussed in
the following.
The voltage distortions in the abc frame can be transformed
to the rotor reference frame by using the relationship [1] as



vas f
vq f
(8)
= T(e ) vbs f
vd f
vcs f

2
2
cos e cos e
cos e +
3
3
2

(9)
T(e ) =

3
2
2
sin e sin e
sin e +
3
3
where e is the electrical angular position of the rotor. Using (7)
through (9), the voltage distortions in the rotor reference frame
in (8) can be represented as

  



vas + vas dist
vq
vq dist
vq f

= T(e ) vbs + vbs dist =

+
vd f
vd
vd dist
vcs + vcs dist
(10)
where vq f and vd f are the q- and d-axis voltages after the fault
occurrence, vq and vd are the normal q- and d-axis voltages, and
vq dist and vd dist are the q- and d-axis voltage deviations
or distortions due to the open-circuit fault. The stator voltages
in the rotor reference frame after the fault occurrence can also
be represented as two parts. One is the normal q- and d-axis
voltages and the other is the voltage deviations caused by the
open-circuit fault. The analysis for the open-circuit fault in the
other switches can be made in a similar manner.
III. PROPOSED OPEN-CIRCUIT FAULT DIAGNOSIS ALGORITHM
An open-circuit fault in the PWM VSI makes the current in
that phase be zero for either the positive or negative half-cycle
depending on whether it occurs to the upper or lower switch.
If the open-circuit fault occurs to the upper switch QaU , for
example, the positive half-cycle of phase A current is always
zero. As a result, it causes a dc current offset in the faulty phase
and this offset current is equally divided into the healthy phases.
Therefore, the offset current gives the uneven current stress on
the remaining switches of the PWM VSI, which may cause
thermal defects [3].
To detect the open-circuit fault condition and identify the
faulty switch, a simple and low-cost fault diagnosis algorithm is
proposed. This proposed method is employing the model reference adaptive system (MRAS) techniques and does not require
any additional hardware circuits such as voltage sensors. The
voltage distortions caused by the open-circuit fault in the rotor

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reference frame are estimated by a voltage distortion observer

which is based on the electrical model of the PMSM. And the
estimated voltage distortions in the rotor reference frame are
transformed to the abc frame for the error detection. By examining the error, the fault condition is determined by the time-based
analysis and the faulty switch is also identified immediately according to the observed voltage distortions in the abc frame.
A. MRAS-Based Voltage Distortion Observer
The current dynamics of a PMSM including the voltage distortions caused by the open-circuit fault can be represented as
follows [1]:

di Rs
q


e  

1 vq + vq dist
iq
dt Ls
+

Rs
did
Ls vd + vd dist
id
e

Ls
dt

m e

Ls
+
(11)
0
where iq and id are the q- and d-axis currents, e is the electrical
rotor angular speed, and m is the flux linkage established by
the permanent magnet, respectively. As can be seen in (11), the
motor currents are affected by the voltage distortions caused by
the open-circuit fault.
For the reference model of the MRAS, it is assumed that the
voltage distortions due to the open-circuit fault are zero and
the system is in the healthy mode. Under this condition, the
calculated current dynamics using the nominal parameters can
also be represented as follows:

diq m
Rs0
 
e  

1 vq
iq
dt
Ls0
+

Rs0
Ls0 vd
id
didm
e

Ls0
dt

m 0 e

Ls0
+
(12)
0
where vq and vd are the q- and d-axis stator voltage commands,
iq m and idm are the q- and d-axis currents of the model, respectively, and the subscript 0 represents the nominal value.
From (11) and (12), the voltage distortions in the rotor reference frame caused by the open-circuit fault can be obtained as
follows:

diq
diq m

vq dist = Ls
dt
dt

did
didm

(13)
vd dist = Ls
dt
dt
where it is assumed that the nominal parameters Rs0 , Ls0 , and
m 0 are identical to the real values Rs , Ls , and m , respectively.
Also, on the assumption that the switches in the PWM VSI
are ideal, the voltage commands vq and vd are identical to the
corresponding q- and d-axis voltages vq and vd . The average
voltage distortions over the kth PWM step can be derived from

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Fig. 4.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Configuration of the proposed voltage distortion observer.

(13) as follows:
vq

dist

(k) = Ls

vd

dist

(k) = Ls

iq (k) iq m (k)
Ts
id (k) idm (k)
Ts

(14)

The model currents iq m (k) and idm (k) in (14) can be obtained
from the discrete form of (12) and these become as follows:
iq m (k) = iq (k 1) +

Ts
[v (k 1) Rs0 iq (k 1)
Ls0 q

e Ls0 id (k 1) e m 0 ]
idm (k) = id (k 1) +

Ts
[v (k 1) Rs0 id (k 1)
Ls0 d

+ e Ls0 iq (k 1)].

(15)

Fig. 4 shows the block diagram of the proposed voltage distortion observer. The observed voltage distortions from the plant
and model currents are used for the fault diagnosis algorithm of
the open-circuit fault in the PWM VSI. In this proposed fault
diagnosis algorithm, two schemes, the error detection and fault
detection time, are used for the robustness against the false fault
diagnosis.
B. Error Detection and Fault Detection Time
Under the normal operation, the voltage distortions in (14) are
zero. However, under the fault condition, the voltage distortions
have either the positive or negative values according to the faulty
switch in the PWM VSI and are repetitively appeared while the
current of faulty leg is zero. Therefore, the threshold value is
employed to determine the error occurrence and given by
Vth = K

(16)

where K is a positive number and carefully selected to minimize

the possibility of the false alarms mainly caused by the noises
and the nonideal characteristics of the power switches. In the
aforementioned open-circuit fault analysis, it has been assumed
that the switches are ideal; thus, the voltage commands are
the same as the corresponding voltages applied to the PMSM.
However, in a real situation, since the voltage commands are
not identical to the corresponding real applied voltages, there

Fig. 5. Ideal and practical switching pattern considering the dead-time and
turn-on/off times of the switches. (a) Practical gate signal including the deadtime. (b) Actual gate signal including turn-on delay, turn-on transition time,
turn-off delay, and turn-off transition time of the switches when ia s 0.
(c) Actual gate signal when ia s < 0.

exist voltage differences between them. This is well known

as the dead-time effect, and caused by the intended blanking
time to prevent the arm-short of a switch leg and the nonideal
characteristics of the switching devices [24], [25]. The voltage
differences due to the dead-time effect can be represented in the
abc frame as follows [25]:
dead

= vas
vas (2 sgn (ias ) sgn (ibs ) sgn (ics )) Ap
vas
dead

vbs
= vbs
vbs (2 sgn (ibs ) sgn (ics ) sgn (ias )) Ap
dead

vcs
= vcs
vcs (2 sgn (ics ) sgn (ias ) sgn (ibs )) Ap

(17)

Ap =

1
(tdead + ton tof f )
2 (Vdc Vce + Vd )
6
Ts

+ (Vce + Vd )

(18)

where sgn() is a sign function of each phase current, Vdc is

the dc-link voltage, Vce is the saturation voltage of the active
switch, Vd is the forward voltage of the antiparallel diode, Ts is
the sample period, tdead is the intended blanking time to prevent
the short-circuit phenomenon, ton is the sum of the turn-on delay
and transition time, and tof f is the sum of the turn-off delay and
transition time. Fig. 5 shows the ideal and practical switching
pattern considering the dead-time and turn-on/off time of the
power switches. The voltage distortions due to the dead-time
effect in the abc frame are summarized as shown in Table III
and Fig. 6. Therefore, the threshold value K in (16) can be
selected by considering the dead-time effect as
K = m Vm ax

(19)

where Vm ax is the maximum value of (17) and m is a positive

number, and carefully selected to minimize the possibility of
false error detection due to the noise and dead-time effect. If m

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

TABLE III
VOLTAGE DIFFERENCES BETWEEN VOLTAGE COMMANDS AND REAL APPLIED
VOLTAGES TO THE PMSM ACCORDING TO THE ROTOR POSITION

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TABLE IV
BOOLEAN ERRORS AND VOLTAGE DISTORTIONS ACCORDING
TO THE FAULTY SWITCH

either the positive or the negative value repetitively according

to the faulty switch, the generated Boolean errors also show the
repetitive square waveforms under the fault condition. Therefore, the fault condition can be roughly observed by checking
the generated Boolean errors. Table IV indicates the generated
Boolean errors and observed voltage distortions according to
the faulty switch. As can be seen in Table IV, the fault condition
can be determined by inspecting the generated Boolean errors
and the faulty switch can also be identified.
The error detection in (20) is a simple and frequently used
method, but has the possibility of false detection due to the
noise and operating point change [26]. To guarantee the robustness against the false error detection, the proposed method
employs the time-based analysis introduced in [11]. The fault
detection time Tf au lt is defined as how long the Boolean errors
are continuously generated and given by
Fig. 6. Voltage differences between voltage commands and real applied voltages to the PMSM under the normal condition in the abc frame.

is selected too high, the errors may not be detected. Moreover, if

m is too small, the probability of false error detection increases.
After an open-circuit fault occurs, the voltage distortions in
(14) are observed and the following simple logic [11], [19], [26],
[27] for each phase is used to generate the Boolean errors k s
(k = {a, b, c}) as

vk s dist > Vth

: error

1,
k s =

0,
1,

|vk s dist | < Vth

vk s dist < Vth

:
:

normal
error

(20)

where vk s dist (k = {a, b, c}) are the observed voltage distortions in the abc frame, Vth is the selected threshold value
in (16) through (19), and k s (k = {a, b, c}) are the generated
Boolean errors for each phase. In (20), if the Boolean errors
have the value either 1 or 1, it means that there is an error
and the system may be under the fault condition. If the Boolean
errors have the value of zero, it means that the system may be
under the normal condition. Since the voltage distortions have

Tf au lt = kf Ts

(21)

where kf is the sensitivity factor for the fault detection and

Ts is the sampling time. If kf is too large, the open-circuit
fault may not be detected. If kf is too small, the possibility of
false detection increases. Therefore, the sensitivity factor kf is
carefully selected considering the detection time and reliability
of the fault detection.
C. Fault Diagnosis Algorithm
By using the concept of the error detection and fault detection
time from (20) and (21), the algorithm for the fault detection is
given by

1, te Tf au lt : fault
(22)
F lagD =
0, te < Tf au lt : normal
where te is the elapsed time from the beginning of error detection
in (20) to the arriving at the fault detection time Tf au lt and
F lagD is the fault detection flag indicating the fault condition.
The error detection time te is reset to zero when the Boolean
errors have the value of zero. For the fault detection, the error
detection time te is compared with the fault detection time Tf au lt

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

TABLE V
FAULT IDENTIFICATION FLAG ACCORDING TO THE GENERATED
BOOLEAN ERRORS

Fig. 8. Process of the proposed fault diagnosis algorithm when the open-circuit
fault occurs to the upper switch Q a U .

Fig. 7.

Block diagram of the proposed fault diagnosis system.

defined in (21), and if te Tf au lt , the fault detection flag F lagD

is set from low to high and the open-circuit fault is detected.
The identification of the faulty switch is obtained just after
the fault detection by the generated Boolean errors k s (k =
{a, b, c}) from Table IV. According to the Boolean errors, the
fault identification flag F lagI composed of three flags F lagA ,
F lagB , and F lagC is defined as given in Table V and used to
identify the faulty switch.
Fig. 7 shows the block diagram of the proposed fault diagnosis algorithm. The fault diagnosis is accomplished in the
following procedures: 1) observation of the voltage distortions;
2) generation of the Boolean errors by the error detection; 3)
determination of the fault condition by the fault detection time;
and 4) identification of the faulty switch. Fig. 8 shows the process of the proposed fault diagnosis algorithm in the case of the
fault occurrence to the upper switch QaU . When the open-circuit
fault occurs to the upper switch QaU , the voltage distortion of
phase A has a negative value and is compared with the selected
threshold value in (16) as shown in (20). Also, the error detection time te is triggered to measure the time until the errors
are detected by (20). If the error detection time te continuously
elapses, and exceeds beyond the fault detection time Tf au lt defined in (21), the fault detection flag F lagD is set from low to
high. After the fault detection flag F lagD is set to high, the
fault identification is obtained from Table V and the fault identification flag F lagI is set according to the faulty switch. Fig. 9
shows the overall block diagram of the proposed open-circuit
fault diagnosis system.

Fig. 9.

Overall structure of the proposed open-circuit fault diagnosis.

D. Extension to the Open-Phase Fault

The open-phase fault is occurred when two switches in one
of three legs are open-circuited. The analysis can be made in a
similar manner in Section II except that the effect of the faulty
switch on the voltage distortions is appeared alternately. For
example, when two switches in phase A, QaU and QaL , have
the open-circuit faults, the voltage distortions have positive to
negative or negative to positive values by turns according to
the faulty switch. If the lower switch QaL has an open-circuit
fault first, then the phase voltages after the open-circuit fault
occurrence are represented as follows:
vas
vbs
vcs

2 1 1
va0 + va0
= 1 1 2 1

vb0
3
1 1 2
vc0

f1
f1
f1

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

2521

Fig. 10. Process of the open-circuit fault diagnosis when the open-circuit
faults occur to the lower switch Q a L and the upper switch Q a U .

2va0
vas
1
= vbs + va0 .
3
vcs
va0

(23)

After the open-circuit fault occurrence to the lower switch

QaL , the upper switch QaU has an open-circuit fault and the
phase voltages are represented as follows:

2 1 1
va0 va0
vas f 2
vbs f 2 = 1 1 2 1

vb0
3
1 1 2
vcs f 2
vc0

2va0
vas
1
(24)
= vbs + va0 .
3
vcs
va0
As can be seen in (23) and (24), the voltage distortions have
the positive to negative or negative to positive values according
to the faulty switch, and the faulty switch or faulty leg can be
identified in a similar manner introduced previously. Fig. 10
shows the process of the open-phase fault diagnosis in the case
of the open-phase fault occurrence to phase A. As can be seen
in Fig. 10, the identification flag FlagI shows 011 and 100
alternately, which means that QaL and QaU have the opencircuit faults.
E. Influence of the System Parameter Error
Generally, the accuracy of the model parameters affects the
observation of the voltage distortions in (14). In the proposed
method, the model currents in (15) are affected by the model
parameter errors. If the errors of the machine parameter are
large, the model currents can converge to the wrong values and
the observation of the voltage distortions also has wrong values.
As can be seen in (15), the model currents are affected by the
resistance, inductance, and flux linkage. In a low-speed region,
the model currents in (15) are less affected by the variations of
the machine parameters, because the currents and the electrical

Fig. 11. Simulation results of the fault diagnosis when the open-circuit fault
occurs to the upper switch Q a U . (a) Phase currents. (b) Process of the proposed
fault diagnosis algorithm.

angular speed are small and the voltage commands are large.
Thus, the resistance loss, inductance loss, and flux linkage loss
in (15) can be ignored. On the other hand, in a high-speed region,
the model currents are severely affected by the variations of
the machine parameters, because the electrical angular speed
is quite large compared to the voltage commands. Therefore,
to avoid the false fault detection due to the variations in the
machine parameter errors, the threshold value K in (16) should
be selected within a safe limit so that no false Boolean errors are
generated. In addition, to get a better performance, the online
observation algorithms of the machine parameter values could
be added in the proposed method. However, it is beyond the
scope.
IV. SIMULATION AND EXPERIMENTAL RESULTS
In this section, the simulation and experimental results are
presented to prove the effectiveness of the proposed fault diagnosis algorithm.
A. Simulation Result
Fig. 11(a) shows the simulation results for the phase currents
ias , ibs , and ics , and the fault signal when the open-circuit fault
occurs to the upper switch QaU . As can be seen in this figure,
the negative phase current ias rapidly approaches to zero and
does not appear during the positive half-cycle after the fault

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Fig. 12. Simulation results of the fault diagnosis when the open-circuit fault
occurs to phase A. (a) Phase currents. (b) Process of the proposed fault diagnosis
algorithm.
TABLE VI
SPECIFICATIONS OF THE TEST PMSM

TABLE VII
SPECIFICATIONS OF THE PWM VSI

occurrence as indicated by the dotted circle in the upper trace of

Fig. 11(a). Only the negative current flows through the switch
QaL or diode DaU . The other phase currents, ibs and ics , show
the similar shapes as the normal condition, but increase a little bit
due to the dc offset current caused by the open-circuit fault. Since
the phase currents are distorted due to the open-circuit fault, the
pulsating torque may be generated and the performance of the
system is deteriorated. Fig. 11(b) shows the simulation results

Fig. 13. Experimental results of the fault diagnosis when the open-circuit fault
occurs to the upper switch Q a U (500 r/min). (a) Process of the proposed fault
diagnosis algorithm. (b) Fault identification.

for the process of the proposed fault diagnosis algorithm. It

compares the observed voltage distortions in the abc frame with
the threshold value in (16) and generates the Boolean errors. The
generated Boolean errors trigger the timer to measure the error
detection time te until the errors are detected. If te Tf au lt , the
open-circuit fault is detected and the fault detection flag F lagD
is set from low to high and the fault identification flag F lagI
is also set to identify the faulty switch. The fault identification
is obtained from Table V and the identification flag, F lagI ,
composed of three flags F lagA , FlagB , and F lagC is set the
digital word 100 which means that the open-circuit fault has
been occurred to the upper switch QaU .
The proposed method is also applicable when the open-circuit
fault occurs simultaneously to both the upper and lower switches
in one phase leg. The simulation results are given in Fig. 12 in
the case of the fault occurs to the upper and lower switches in
phase A. The results indicate that the phase current ias does
not flow through the upper and lower switches, QaU and QaL ,
which remains zero as indicated in Fig. 12(a). The observed
voltage distortion in phase A, vas dist , has both positive and
negative values by turns according to the faulty switch as shown
in Fig. 12(b). The fault condition can be detected in a similar

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

Fig. 14. Experimental results of the fault diagnosis when the open-circuit fault
occurs to the upper switch Q a U (3000 r/min). (a) Process of the proposed fault
diagnosis algorithm. (b) Fault identification.

TABLE VIII
FAULT DETECTION TIME BETWEEN PREVIOUS METHODS
AND THE PROPOSED METHOD

manner to an open-circuit fault and the faulty switches can be

identified by the identification flag F lagI showing 011 and
100 by turns which means that the switches QaL and QaU are
in trouble.

2523

Fig. 15. Experimental results of the fault diagnosis when the open-circuit
fault occurs to phase A (500 r/min). (a) Process of the proposed fault diagnosis
algorithm. (b) Fault identification.

B. Experimental Result
In order to confirm the feasibility of the fault diagnosis algorithm, the experiments have been realized under the same
conditions as the simulations. The parameters related to the test
motor and PWM VSI are represented in Tables VI and VII,
respectively. The three-phase PWM VSI is composed of six
IGBTs, FGH40N60SFD from Fairchild, Corp. The switching
frequency of the PWM VSI is 11 kHz. All the control laws
proposed in this paper have been realized by using a single
MCU TMS320F28335 from Texas Instruments, Incorporated.
The sampling rate of phase currents is identical to the switching
frequency. The open-circuit fault condition is made by introducing no gate drive signal to the IGBT.
Fig. 13(a) shows the experimental results for the process of
the fault diagnosis algorithm. As can be seen in this figure, when
all of the switching devices are under the normal condition, the
observed voltage distortion is nearly zero. However, there is
a significant difference after the fault occurrence to the upper
switch QaU , and the error signal is generated. When the error
detection time te continuously elapses and exceeds beyond the
fault detection time Tf au lt defined as in (21), the fault detection
flag F lagD changes from low to high. Fig. 13(b) shows the

2524

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Fig. 16. Effects of machine parameter variations (3000 r/min). (a) R s 0 = 0.5R s . (b) R s 0 = 1.5R s . (c) L s 0 = 0.5L s . (d) L s 0 = 1.5L s . (e) m 0 = 0.8m .
(f) m 0 = 1.2m .

fault identification flag F lagI composed of three flags F lagA ,

F lagB , and F lagC that identify the faulty switch. In this case,
100 means that the open-circuit fault has been occurred to
the upper switch QaU . Fig. 14 shows the similar experimental
results in the case of the rated speed, 3000 r/min.
Fig. 15 shows the experimental results for the open-phase
fault diagnosis when the fault occurs to phase A. The current of phase A remains zero after the open-phase fault occurrence and the observed voltage distortion has both positive
and negative values by turns as shown in Fig. 15(a). The iden-

tification flag F lagI for the open-phase fault shows two values according to the faulty switches, and in this case, the flag
shows 011 and 100, which means that the lower and upper switches, QaL and QaU , in phase A have the open-circuit
fault.
The comparison of the fault diagnosis time between proposed
method and previous methods is summarized in Table VIII. As
can be seen in this table, the proposed method can detect the
fault in less than 1 msec, while the previous methods take more
than 2.7 msec.

JUNG et al.: MRAS-BASED DIAGNOSIS OF OPEN-CIRCUIT FAULT IN PWM VOLTAGE-SOURCE INVERTERS

Fig. 16 shows the effect of the machine parameter variations

on the process of the proposed method at 3000 r/min. The parameter variations affect the observation of the voltage distortions
in a high-speed region. Even under the healthy condition, since
RHS terms of (15) which are related to the machine parameters
are large due to the high electrical angular speed, the observed
voltage distortions are highly affected by the machine parameter
errors. The voltage distortions are less affected by the resistance
and inductance variation, but are severely affected by the flux
linkage variation. Fig. 16(e) and (f) show the chances of the false
alarm under 20% flux linkage variations. To avoid the false
fault detection, the threshold value K in (16) should be selected
under the consideration of the variations in the machine parameter values. In this system, the threshold value K is selected as
15. Otherwise, the online observation and compensation algorithms of the machine parameter values should be added for a
better performance.
V. CONCLUSION
The fault detection and identification is becoming more and
more important for industrial applications. Therefore, it is increasingly required to improve the fault diagnosis capabilities.
In this paper, a simple and low-cost open-circuit fault detection
and identification method is presented. The proposed fault diagnosis is achieved by the simple voltage distortion observer. Once
the voltage distortions are estimated, these are compared with
the threshold value to determine the fault condition. When the
open-circuit fault occurs, the observed voltage distortions are
bigger than the threshold value. By comparing these two values,
the fault condition is decided. Also, the fault identification is
achieved by using the observed voltage distortions, since the
voltage distortions are different according to the faulty switch.
The proposed method can be well combined with the postfault
actions which are the reconfigurations of the whole drive system
to operate safely and continuously. Two major postfault actions
are also introduced in the literature works [28][30]. However,
the postfault actions are beyond the scope of this paper. In comparison with the previous existing fault diagnosis [31], the proposed method has simple structure and fast fault detection time.
Also, it can be implemented without any extra devices such as
voltage sensors and the computing effort is very small. The execution of the algorithm can be easily embedded in the existing
systems without major modifications. To show the effectiveness
of the proposed method, the simulations and experiments are
carried out for the digitally controlled PMSM drive system. The
simulation and experimental results verify the validity of the
proposed method and show that the proposed method gives the
good performance and practical value.
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Shin-Myung Jung (S08) was born in Korea, in

1981. He received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute
of Science and Technology, Daejeon, Korea, in 2004
and 2006, respectively, where he is currently working
toward the Ph.D. degree.
His research interests include power electronics
and control, which include motor drives, fault tolerant
control, and high-performance switching regulators.
Mr. Jung is a Member of the Korean Institute of
Power Electronics.

Jin-Sik Park (S08M12) was born in Korea, in

1981. He received the B.S., M.S., and Ph.D. degrees
in electrical engineering from the Korea Advanced
Institute of Science and Technology, Daejeon, Korea,
in 2003, 2005, and 2012, respectively.
He is currently with Samsung Electro-Mechanics
Company, Gyeonggi-do, Korea. His research interests include the design of motor drive systems, sensorless drive of ac motor, and dc/dc power converter
topology.
Dr. Park is a Member of the Korean Institute of
Power Electronics.

Hag-Wone Kim (A05) received the B.S. degree in

electrical engineering from Korea University, Seoul,
Korea, in 1989, and the M.S. and Ph.D. degrees in
electrical and electronic engineering from the Korea
Advanced Institute of Science and Technology,
Daejeon, Korea, in 1991 and 2004, respectively.
He was with LG Electronics, Digital Appliance
Research Lab., from 1991 to 2008. Since 2005, he
has been an Associate Professor and since 2008, he
has been a Professor at Korea National University of
Transportation, Chungju, Korea. His research interests include the areas of variable speed motor drives and power converters.
Dr. Kim is a Member of the Korean Institute of Power Electronics.

Kwan-Yuhl Cho (S88) received the B.S. degree in

electrical engineering from Seoul National University, Seoul, Korea, in 1986, and the M.S. and Ph.D.
degrees in electrical and electronics engineering from
the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1988 and 1993, respectively.
He was with the LG Electronics, Digital Appliance
Research Lab., from 1993 to 2004. Since 2004, he
has been with the Department of Control and Instrumentation Engineering, Korea National University of
Transportation, Chungbuk, Korea. He was a Visiting
Scholar at Virginia Tech., from 2010 to 2011. He is a Planning Activities Director of the Korean Institute of Power Electronics. His research interests include
variable speed motor drives and power converters.

Myung-Joong Youn (S74M78SM98) was born

in Seoul, Korea, in 1946. He received the B.S. degree
from Seoul National University, Seoul, in 1970, and
the M.S. and Ph.D. degrees in electrical engineering
from the University of Missouri, Columbia, in 1974
and 1978, respectively.
In 1978, he joined the Air-Craft Equipment Division, General Electric Company, Erie, PA, where he
was an Individual Contributor on Aerospace Electrical System Engineering. Since 1983, he has been a
Professor at the Korea Advanced Institute of Science
and Technology, Daejeon, Korea. His research activities are in the areas of
power electronics and control, which include drive systems, rotating electrical
machine design, and high-performance switching regulators.
Dr. Youn is a Member of the Institution of Electrical Engineers, U.K., the
Korean Institute of Power Electronics, the Korean Institute of Electrical Engineers, and the Korea Institute of Telematics and Electronics.