`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date: 04:45:26 01/27/2010
// Design Name:
// Module Name: countercomp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module petrol(reset, enable, clk, counter, c_in, b1, b2, b3, b4, out1, out2, out
3, out4);
input reset, enable;
input clk;
input [3:0]c_in;
output counter;
output reg [3:0] b1,b2;
output reg [3:0] b3,b4;
output reg [6:0] out1,out2;
output reg [6:0] out3,out4;
reg state, next_state;
parameter s_initial = 1'b0;
parameter s_go = 1'b1;
reg [3:0] counter;
always @ (posedge reset)
begin
state <= s_initial;
next_state <= s_initial;
end

initial
begin
next_state = s_initial;
state = s_initial;
end
always @ (posedge clk)
begin
state <= next_state;
case(state)
s_initial:
begin
 counter <= 4'b0000;
b1<=0;
b2<=0;
next_state <= s_go;
end
s_go:
begin
if (enable == 1'b1)
begin
if ( counter != c_in)
begin
counter <= counter + 1;
if(counter>4'b1000)
{b1,b2}=counter+4'b0111;
else if (counter<=4'b1000)
{b1,b2}=counter+1;
else
{b1,b2}={b1,b2};
end
end
end
endcase
end
always @ (c_in)
begin
if(c_in>4'b1001)
{b3,b4}=c_in+4'b0110;
else
{b3,b4}=c_in;
end

always @ (counter)
begin
case (b1)
4'b0000: out1=7'b1111110;
4'b0001: out1=7'b0110000;
4'b0010: out1=7'b1101101;
4'b0011: out1=7'b1111001;
4'b0100: out1=7'b0110011;
4'b0101: out1=7'b1011011;
4'b0110: out1=7'b1011111;
4'b0111: out1=7'b1110000;
4'b1000: out1=7'b1111111;
4'b1001: out1=7'b1111011;
default: out1=7'b0000000;
endcase
end
always @ (counter)
begin
case (b2)
4'b0000: out2=7'b1111110;
4'b0001: out2=7'b0110000;
4'b0010: out2=7'b1101101;
4'b0011: out2=7'b1111001;
4'b0100: out2=7'b0110011;
4'b0101: out2=7'b1011011;
 4'b0110: out2=7'b1011111;
4'b0111: out2=7'b1110000;
4'b1000: out2=7'b1111111;
4'b1001: out2=7'b1111011;
default: out2=7'b0000000;
endcase
end
always @ (counter)
begin
case (b3)
4'b0000: out3=7'b1111110;
4'b0001: out3=7'b0110000;
4'b0010: out3=7'b1101101;
4'b0011: out3=7'b1111001;
4'b0100: out3=7'b0110011;
4'b0101: out3=7'b1011011;
4'b0110: out3=7'b1011111;
4'b0111: out3=7'b1110000;
4'b1000: out3=7'b1111111;
4'b1001: out3=7'b1111011;
default: out3=7'b0000000;
endcase
end
always @ (counter)
begin
case (b4)
4'b0000: out4=7'b1111110;
4'b0001: out4=7'b0110000;
4'b0010: out4=7'b1101101;
4'b0011: out4=7'b1111001;
4'b0100: out4=7'b0110011;
4'b0101: out4=7'b1011011;
4'b0110: out4=7'b1011111;
4'b0111: out4=7'b1110000;
4'b1000: out4=7'b1111111;
4'b1001: out4=7'b1111011;
default: out4=7'b0000000;
endcase
end
endmodule