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library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------
architecture TB of dff_TB is
component dff
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end component;
begin
process
begin
-- case 1
T_data_in <= '1';
wait for 12 ns;
assert (T_data_out='1') report "Error1!" severity error;
if (T_data_out/='1') then
err_cnt := err_cnt + 1;
end if;
-- case 2
T_data_in <= '0';
wait for 28 ns;
assert (T_data_out='0') report "Error2!" severity error;
if (T_data_out/='0') then
err_cnt := err_cnt + 1;
end if;
-- case 3
T_data_in <= '1';
wait for 2 ns;
assert (T_data_out='0') report "Error3!" severity error;
if (T_data_out/='0') then
err_cnt := err_cnt + 1;
end if;
-- case 4
T_data_in <= '0';
wait for 10 ns;
assert (T_data_out='0') report "Error4!" severity error;
if (T_data_out/='0') then
err_cnt := err_cnt + 1;
end if;
-- case 5
T_data_in <= '1';
wait for 20 ns;
assert (T_data_out='1') report "Error5!" severity error;
if (T_data_out/='0') then
err_cnt := err_cnt + 1;
end if;
wait;
end process;
end TB;
-----------------------------------------------------------------
configuration CFG_TB of dff_TB is
for TB
end for;
end CFG_TB;
-----------------------------------------------------------------