library ieee;

use ieee.std_logic_1164.all;
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entity test_dff is
end test_dff;
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architecture tb of test_dff is
component dff is
port (
d,clk,rst :in std_logic;
q : out std_logic
);
end component;
signal d,clk,rst : std_logic;
signal q : std_logic;
signal clk_cont : boolean := true;
begin
state : dff port map (d=>d,clk=>clk,rst=>rst,q=>q);
process
begin
while clk_cont = true loop
clk<='0';
wait for 10 ns;
clk<='1';
wait for 10 ns;
end loop;
wait;
end process;
process
begin
clk_cont <=false after 1000 ns;
wait;
end process;
process
begin
rst<='0';
d<='0';
wait for 20 ns;
rst<='0';
d<='1';
wait for 20 ns;
rst<='1';
wait for 20 ns;
wait;
end process;
end tb;
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