VHDL Codes For 32-Bit Processor: AARON T IMMANUEL (217-74-907)

AARON T IMMANUEL (217-74-907)
VHDL CODES FOR 32-BIT PROCESSOR
1. VHDL CODE FOR REGISTER FILE:

-- VHDL FOR REGISTER FILE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
-- REGISTER FILE ENTITY DECLARATION

ENTITY REGISTER_FILE IS
PORT (INSTRUCTION: IN STD_ULOGIC_VECTOR(31 DOWNTO 0));
END ENTITY REGISTER_FILE;
-- REGISTER FILE ARCHITECTURE BODY

ARCHITECTURE BASIC_REGISTER_FILE OF REGISTER_FILE IS
TYPE REG IS (R1,R2,R3,R4,R5,R6,R7,R8);

SIGNAL RS, RT, RD: REG :=R1;
SIGNAL OPCODE: STD_ULOGIC_VECTOR(5 DOWNTO 0);
BEGIN
OPCODE <= (INSTRUCTION(31 DOWNTO 26));
P1: PROCESS (INSTRUCTION) IS

VARIABLE OPCODE1: STD_ULOGIC_VECTOR(5 DOWNTO 0);
BEGIN
OPCODE1 := (INSTRUCTION(31 DOWNTO 26));
C1: CASE (INSTRUCTION(25 DOWNTO 21)) IS
WHEN "00000" => RS <= R1;
WHEN "00001" => RS <= R2;
WHEN "00010" => RS <= R3;
WHEN "00011" => RS <= R4;
WHEN "00100" => RS <= R5;
WHEN "00101" => RS <= R6;
WHEN "00110" => RS <= R7;
WHEN "00111" => RS <= R8;
WHEN OTHERS => NULL;
END CASE C1;
C2: CASE (INSTRUCTION(20 DOWNTO 16)) IS
WHEN "00000" => RT <= R1;
WHEN "00001" => RT <= R2;
WHEN "00010" => RT <= R3;
WHEN "00011" => RT <= R4;
WHEN "00100" => RT <= R5;
WHEN "00101" => RT <= R6;
WHEN "00110" => RT <= R7;
WHEN "00111" => RT <= R8;
END CASE C2;
C3: CASE (OPCODE1) IS
WHEN "000001" | "000010" | "000011" | "000100" | "000111" | "001000" | "001001" | "001010" |
"001011" | "001100" | "001101" =>
IF (INSTRUCTION(15 DOWNTO 11) = "00000") THEN
1
RD <= R1;
ELSIF (INSTRUCTION(15 DOWNTO 11) = "00001") THEN
RD <= R2;
RD <= R3;
RD <= R4;
RD <= R5;
RD <= R6;
RD <= R7;
RD <= R8;
END IF;
END CASE C3;
END PROCESS P1;
END ARCHITECTURE BASIC_REGISTER_FILE;
2
2. VHDL CODE FOR ALU:
-- VHDL FOR ALU

LIBRARY IEEE;
-- ALU ENTITY DECLARATION

ENTITY ALU IS
PORT (INSTRUCTION: IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
ALU_OP: IN STD_ULOGIC_VECTOR(1 DOWNTO 0));
END ENTITY ALU;
-- ALU ARCHITECTURE BODY

ARCHITECTURE BASIC_ALU OF ALU IS
SIGNAL OPCODE: STD_ULOGIC_VECTOR(5 DOWNTO 0) :="000000";

SIGNAL ALU_CONTROL: STD_ULOGIC_VECTOR(2 DOWNTO 0) :="000";
TYPE OPERATE IS (NOP_OP, ADD_OP, SUB_OP, SLT_OP, SRA_OP, SRL_OP, AND_OP, OR_OP);
SIGNAL OPERATION: OPERATE :=NOP_OP;
BEGIN
OPCODE <= INSTRUCTION(31 DOWNTO 26);
P1: PROCESS (OPCODE, ALU_OP) IS

BEGIN
C1: CASE ALU_OP IS
WHEN "00" => F1: IF (OPCODE = "000101") THEN

ALU_CONTROL <= "001";
ELSE
ALU_CONTROL <= "UUU";
END IF F1;

ELSE
END IF F2;

ELSIF (OPCODE = "001111") THEN
ELSE
END IF F3;

3

ELSE
END IF F4;
WHEN OTHERS => ALU_CONTROL <= "UUU";
END CASE C1;

END PROCESS P1;
P2: PROCESS (ALU_CONTROL, OPCODE) IS

BEGIN
C1: CASE (ALU_CONTROL) IS
WHEN "001" => OPERATION <= ADD_OP;
WHEN "010" => OPERATION <= SUB_OP;
WHEN "011" => OPERATION <= SLT_OP;
WHEN "100" => OPERATION <= SRA_OP;
WHEN "101" => OPERATION <= SRL_OP;
WHEN "110" => OPERATION <= AND_OP;
WHEN "111" => OPERATION <= OR_OP;
WHEN OTHERS => OPERATION <= NOP_OP;
END CASE C1;
END PROCESS P2;
END ARCHITECTURE BASIC_ALU;
4
3. VHDL CODE FOR CONTROL UNIT:

-- VHDL FOR CONTROL UNIT WITH 9 CONTROL SIGNALS
LIBRARY IEEE;
-- CONTROL UNIT ENTITY DECLARATION

ENTITY CONTROL_UNIT IS
PORT (CLOCK: IN STD_ULOGIC;
OPCODE: IN STD_ULOGIC_VECTOR(5 DOWNTO 0);
REG_DST, REG_WRITE, BRANCH: OUT STD_ULOGIC :='0';
MEM_READ, MEM_WRITE, MEMTOREG: OUT STD_ULOGIC :='0';
ALU_OP: OUT STD_ULOGIC_VECTOR(1 DOWNTO 0) :="00";
ALU_SRC, PC_SRC: OUT STD_ULOGIC :='0');
END ENTITY CONTROL_UNIT;
-- CONTROL UNIT ARCHITECTURE BODY

ARCHITECTURE BASIC_CONTROL OF CONTROL_UNIT IS
TYPE STATES IS (FETCH, DECODE, LOAD_STORE, BRANCH_S, LOAD_S, STORE_S, REGISTER_S);
SIGNAL PRESENT_STATE: STATES :=FETCH;
BEGIN
P1: PROCESS (CLOCK) IS

BEGIN
F1: IF(CLOCK'EVENT AND CLOCK = '1') THEN -- RISING EDGE OF THE CLOCK
C1: CASE PRESENT_STATE IS
WHEN FETCH => PC_SRC <= '0';

BRANCH <= '0';
MEM_READ <= '1';
ALU_OP <= "00";
ALU_SRC <= '0';
PRESENT_STATE <= DECODE;
WHEN DECODE => ALU_OP <= "00";

ALU_SRC <= '0';
C2: CASE OPCODE IS
WHEN "001110" | "001111" => PRESENT_STATE <= BRANCH_S;
WHEN "000101" | "000110" => PRESENT_STATE <= LOAD_STORE;
WHEN "000001" | "000010" | "000011" | "000100" => PRESENT_STATE <= REGISTER_S;
WHEN "000111" | "001000" | "001001" | "001010" => PRESENT_STATE <= REGISTER_S;
WHEN "001011" | "001100" | "001101" => PRESENT_STATE <= REGISTER_S;
WHEN OTHERS => PRESENT_STATE <= FETCH;
END CASE C2;
WHEN LOAD_STORE => ALU_OP <= "00";

ALU_SRC <= '0';
C3: CASE OPCODE IS
WHEN "000101" => PRESENT_STATE <= LOAD_S;
WHEN "000110" => PRESENT_STATE <= STORE_S;
END CASE C3;
WHEN BRANCH_S => ALU_OP <= "10";

5
C4: CASE OPCODE IS

WHEN "001110" => ALU_SRC <= '1';
WHEN "001111" => ALU_SRC <= '0';
WHEN OTHERS => ALU_SRC <= 'U';
END CASE C4;
PRESENT_STATE <= FETCH;
BRANCH <= '1';
PC_SRC <= '1';
WHEN REGISTER_S => ALU_SRC <= '0';

ALU_OP <= "11";
REG_DST <= '1';
MEMTOREG <= '1';
REG_WRITE <= '1';
WHEN LOAD_S => ALU_OP <= "00";

MEM_READ <= '1';
MEM_WRITE <= '0';
REG_DST <= '0';
MEMTOREG <= '0';
REG_WRITE <= '1';
WHEN STORE_S => ALU_OP <= "01";

MEM_WRITE <= '1';
MEM_READ <= '0';
END CASE C1;

END IF F1;
END PROCESS P1;
END ARCHITECTURE BASIC_CONTROL;
6
4. VHDL CODE FOR TEST CODE:
-- VHDL FOR SAMPLE TEST CODE USING 8 GENERAL PURPOSE REGISTERS

LIBRARY IEEE;
-- ENTITY DECLARATION
ENTITY PROGRAM IS
PORT ( R1, R2, R3, R4, R5, R6, R7, R8: INOUT INTEGER :=0;
CLOCK: IN STD_ULOGIC);
END ENTITY PROGRAM;
-- ARCHITECTURE BODY
ARCHITECTURE OPERATION OF PROGRAM IS
-- FUNCTION TO CONVERT INTEGER INTO BIT

FUNCTION CONVERSION (SIGNAL A: IN INTEGER)
RETURN BIT IS
BEGIN
IF (A > 0) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END FUNCTION CONVERSION;
SIGNAL X: BIT;
BEGIN
P1: PROCESS (CLOCK, R7) IS

BEGIN
F1: IF (CLOCK'EVENT AND CLOCK ='1') THEN
R4 <= R2 + R3;
R7 <= R5 + R6;
R2 <= 0;
X <= CONVERSION(R7);
F2: IF (R2 < R7) THEN
F3: IF (X = '1') THEN
R8 <= R8 + R5;
END IF F3;
ELSE
R7 <= R3 + R4;
R8 <= R3 + R5;
END IF F2;
END IF F1;
END PROCESS P1;
END ARCHITECTURE OPERATION;

VHDL Codes For 32-Bit Processor: AARON T IMMANUEL (217-74-907)

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

VHDL Codes For 32-Bit Processor: AARON T IMMANUEL (217-74-907)

Enviado por

Direitos autorais:

Formatos disponíveis

AARON T IMMANUEL (217-74-907)

VHDL CODES FOR 32-BIT PROCESSOR

1. VHDL CODE FOR REGISTER FILE:

-- REGISTER FILE ENTITY DECLARATION

-- REGISTER FILE ARCHITECTURE BODY

TYPE REG IS (R1,R2,R3,R4,R5,R6,R7,R8);

OPCODE <= (INSTRUCTION(31 DOWNTO 26));

P1: PROCESS (INSTRUCTION) IS

END ARCHITECTURE BASIC_REGISTER_FILE;

2. VHDL CODE FOR ALU:

-- VHDL FOR ALU

-- ALU ENTITY DECLARATION

-- ALU ARCHITECTURE BODY

SIGNAL OPCODE: STD_ULOGIC_VECTOR(5 DOWNTO 0) :="000000";

OPCODE <= INSTRUCTION(31 DOWNTO 26);

P1: PROCESS (OPCODE, ALU_OP) IS

WHEN "00" => F1: IF (OPCODE = "000101") THEN

WHEN "01" => F2: IF (OPCODE = "000110") THEN

WHEN "10" => F3: IF (OPCODE = "001110") THEN

WHEN "11" => F4: IF (OPCODE = "000001") THEN

ALU_CONTROL <= "010";

WHEN OTHERS => ALU_CONTROL <= "UUU";

END CASE C1;

P2: PROCESS (ALU_CONTROL, OPCODE) IS

END ARCHITECTURE BASIC_ALU;

3. VHDL CODE FOR CONTROL UNIT:

-- CONTROL UNIT ENTITY DECLARATION

-- CONTROL UNIT ARCHITECTURE BODY

P1: PROCESS (CLOCK) IS

C1: CASE PRESENT_STATE IS

WHEN FETCH => PC_SRC <= '0';

WHEN DECODE => ALU_OP <= "00";

WHEN LOAD_STORE => ALU_OP <= "00";

WHEN BRANCH_S => ALU_OP <= "10";

C4: CASE OPCODE IS

WHEN REGISTER_S => ALU_SRC <= '0';

WHEN LOAD_S => ALU_OP <= "00";

WHEN STORE_S => ALU_OP <= "01";

WHEN OTHERS => PRESENT_STATE <= FETCH;

END CASE C1;

4. VHDL CODE FOR TEST CODE:

-- VHDL FOR SAMPLE TEST CODE USING 8 GENERAL PURPOSE REGISTERS

-- FUNCTION TO CONVERT INTEGER INTO BIT

P1: PROCESS (CLOCK, R7) IS

END ARCHITECTURE OPERATION;

Você também pode gostar